WO2016179952A1 - 薄膜晶体管、阵列基板及其制备方法、显示装置 - Google Patents

薄膜晶体管、阵列基板及其制备方法、显示装置 Download PDF

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WO2016179952A1
WO2016179952A1 PCT/CN2015/091545 CN2015091545W WO2016179952A1 WO 2016179952 A1 WO2016179952 A1 WO 2016179952A1 CN 2015091545 W CN2015091545 W CN 2015091545W WO 2016179952 A1 WO2016179952 A1 WO 2016179952A1
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thin film
pattern
lanthanum boride
film transistor
layer
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PCT/CN2015/091545
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English (en)
French (fr)
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袁广才
闫梁臣
徐晓光
王磊
彭俊彪
兰林锋
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京东方科技集团股份有限公司
华南理工大学
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Priority to EP15885767.2A priority Critical patent/EP3297031B1/en
Priority to US15/303,231 priority patent/US9917157B2/en
Publication of WO2016179952A1 publication Critical patent/WO2016179952A1/zh

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Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a thin film transistor, an array substrate, a method for fabricating the same, and a display device.
  • TFT Thin Film Transistor
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Diode
  • thin film transistor technology has evolved from the original amorphous silicon (a-Si) thin film transistor to the current low temperature poly-silicon (LTPS) thin film transistor, metal induced lateral crystallization (Metal- Induced Lateral Crystallization (MILC) thin film transistor, oxide (Oxide) thin film transistor, and the like.
  • a-Si amorphous silicon
  • LTPS low temperature poly-silicon
  • MILC metal induced lateral crystallization
  • MILC Metal- Induced Lateral Crystallization
  • oxide (Oxide) thin film transistor oxide
  • Oxide thin film transistors use an oxide semiconductor as an active layer, which has the characteristics of large mobility, high on-state current, better switching characteristics, and better uniformity, and can be applied to applications requiring fast response and large current.
  • the above oxide semiconductor material mostly contains some rare metal elements such as metal elements such as indium and antimony.
  • the abundance of indium in the earth's crust is only about 0.049ppm. Therefore, with the large consumption of indium by industrial demand, the indium of the metal element is less and less, resulting in an increase in the price of the metal elemental indium, thereby increasing the manufacturing cost of the display device, which is disadvantageous for mass production of the product.
  • Embodiments of the present disclosure provide a thin film transistor, an array substrate, a method for fabricating the same, and a display device, which can reduce the use of indium elements in a semiconductor active layer, thereby solving the problem that the indium element is increasingly thin Lack of production costs caused by the lack of production costs.
  • An aspect of an embodiment of the present disclosure provides a method of fabricating a thin film transistor, including:
  • a pattern of the semiconductor active layer is formed on the transparent substrate by a patterning process; wherein the pattern of the semiconductor active layer includes a hafnium boride pattern.
  • a method of fabricating an array substrate including the method of fabricating any of the thin film transistors described above, is provided.
  • a thin film transistor including a pattern of a semiconductor active layer, the pattern of the semiconductor active layer including a lanthanum boride pattern is provided.
  • an array substrate including any one of the thin film transistors described above.
  • a display device including the array substrate as described above is provided.
  • Embodiments of the present disclosure provide a thin film transistor, an array substrate, a method of fabricating the same, and a display device.
  • the method for preparing a thin film transistor includes: forming a pattern of a semiconductor active layer by a patterning process on a transparent substrate; wherein the pattern of the semiconductor active layer includes a lanthanum boride pattern.
  • the main component constituting the semiconductor active layer may be lanthanum boride.
  • the strontium element is a rare earth element
  • the abundance in the earth's crust is 30ppm, which is much larger than the abundance of indium element in the earth's crust, and the annual consumption of strontium element is much smaller than that of indium.
  • the semiconductor active layer composed of lanthanum boride has an obvious cost and sustainable use advantage compared to the semiconductor active layer containing indium.
  • the lanthanum element of lanthanum boride is located in the center of the cube, and each of the six boron elements constitutes a regular octahedron.
  • the body of each regular octahedron is located at the apex of the cube, and the yttrium element in the adjacent lattice has a certain electron orbit. Overlap to form an electronic channel.
  • lanthanum boride has high mobility and conductivity, so that the semiconductor active layer composed of lanthanum boride has high electron mobility, so that the thin film transistor has a high switching current ratio, which is advantageous for controlling the device. Leakage; at the same time, it can effectively increase the charging rate of the device, thereby improving the display effect of the display device.
  • FIG. 1 is a flowchart of a method for fabricating a thin film transistor according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a bottom gate type thin film transistor according to an embodiment of the present disclosure
  • FIG. 2b is a schematic structural diagram of a top gate type thin film transistor according to an embodiment of the present disclosure
  • 2c is a schematic structural diagram of another bottom gate type thin film transistor according to an embodiment of the present disclosure.
  • FIG. 3 is a flow chart of a method for fabricating the thin film transistor shown in FIG. 2a;
  • FIG. 4 is a graph showing a TFT transfer characteristic of the thin film transistor shown in FIG. 2a;
  • FIG. 5 is a graph showing a transfer characteristic of a TFT of the thin film transistor shown in FIG. 2c;
  • Fig. 6 is a graph showing another TFT transfer characteristic of the thin film transistor shown in Fig. 2a.
  • the embodiment of the present disclosure provides a method for fabricating a thin film transistor, as shown in FIG. 1 , which may include:
  • the gate pattern 11 is formed by a patterning process.
  • a gate insulating layer 12 is formed by a patterning process.
  • a pattern of the semiconductor active layer 13 is formed by a patterning process; wherein the pattern of the semiconductor active layer 13 includes a lanthanum boride pattern.
  • the present disclosure does not limit the sequence of the above steps S101 to S104.
  • the above method may be performed by performing step S101 to form a pattern of the gate electrode 11 on the transparent substrate 10, and then on the substrate on which the gate pattern 11 is formed.
  • the method may be performed by performing step S103 to form a pattern of the semiconductor active layer 13 including the hafnium boride pattern on the transparent substrate 10; a pattern in which the source electrode 14 and the drain electrode 15 are formed on the substrate on which the semiconductor active layer 13 pattern is formed; and a pattern in which the gate insulating layer 12 and the gate electrode 11 are sequentially formed on the substrate on which the source electrode 14 and the drain 15 pattern are formed .
  • the bottom gate type TFT and the top gate type TFT are determined relative to the positions of the gate electrode 11 and the gate insulating layer 12, that is, when the gate electrode 11 is opposite to the transparent substrate 10 As shown in FIG. 2a, near the transparent substrate 10, when the gate insulating layer 12 is away from the transparent substrate 10, it is a bottom gate type TFT; when the gate electrode 11 is away from the transparent substrate 10, the gate insulating layer 12 is close to the transparent In the case of the substrate 10, it is a top gate type TFT.
  • the patterning process in the embodiments of the present disclosure may include a photolithography process, or may include a photolithography process and an etching process, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, etc.;
  • the engraving process includes a process of forming a film, exposing, developing, etc., and specifically, a process of forming a pattern by using a photoresist, a mask, an exposure machine, or the like.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present disclosure.
  • the transparent substrate 10 may be made of a hard material such as a glass substrate, a hard resin substrate, or a transparent substrate made of a flexible material. Moreover, in the above steps, various film layers are prepared on the transparent substrate 10, which may be directly prepared on the surface of the transparent substrate 10, or may be performed on the transparent substrate 10 on which some film layers or film layer patterns have been formed. preparation.
  • the semiconductor active layer 13 is mainly composed of a lanthanum boride film layer.
  • the chemical formula of lanthanum boride is La x B y .
  • y 1, the value of x can range from 0.05 to 1.
  • Those skilled in the art can adjust the above values of y and x according to actual conditions. Among them, the higher the content of boron element, the lower the concentration and conductivity of the carrier, which in turn facilitates the conversion of the lanthanum boride from the conductor to the semiconductor.
  • the single film layer may be a hafnium boride film layer.
  • the semiconductor active layer 13 is formed by stacking a plurality of thin film layers, the lanthanum boride thin film layer is located in an intermediate layer of the multilayer thin film layer stack structure, and the lanthanum boride thin film layer is opposite to the multilayer thin film layer stack structure.
  • the thickness is the largest.
  • the other thin film layers in the multilayer thin film layer stack structure may be metal oxide semiconductors such as Indium Gallium Zinc Oxide (IGZO). Since the film layer composed of indium element occupies less in the entire semiconductor active layer 13 than the lanthanum boride, the use of indium element can be reduced, thereby solving the problem that the indium element is increasingly scarce. The problem of rising production costs.
  • IGZO Indium Gallium Zinc Oxide
  • lanthanum boride also has the advantages of high melting point, resistance to ion bombardment, oxidation resistance, thermal conductivity, and good chemical stability, and its mobility is higher than that of amorphous silicon.
  • An embodiment of the present disclosure provides a method of fabricating a thin film transistor, comprising: forming a pattern of a semiconductor active layer by a patterning process on a transparent substrate; wherein the pattern of the semiconductor active layer includes a hafnium boride pattern.
  • the main component constituting the semiconductor active layer may be lanthanum boride.
  • the strontium element is a rare earth element
  • the abundance in the earth's crust is 30ppm, which is much larger than the abundance of indium element in the earth's crust, and the annual consumption of strontium element is much smaller than that of indium. Therefore, the semiconductor active layer composed of lanthanum boride has an obvious cost and sustainable use advantage compared to the semiconductor active layer containing indium.
  • the lanthanum element of lanthanum boride is located in the center of the cube, and each of the six boron elements constitutes a regular octahedron.
  • the body of each regular octahedron is located at the apex of the cube, and the yttrium element in the adjacent lattice has a certain electron orbit. Overlap to form an electronic channel.
  • lanthanum boride has high mobility and conductivity, so that the semiconductor active layer composed of lanthanum boride has high electron mobility, so that the thin film transistor has The high switching current ratio is high, which is beneficial to control the leakage of the device; at the same time, the charging rate of the device can be effectively improved, thereby improving the display effect of the display device.
  • the preparation method provided in this embodiment is used for preparing the TFT shown in FIG. 2a.
  • the semiconductor active layer 13 mainly composed of lanthanum boride is prepared by physical vapor deposition, as shown in FIG.
  • the TFT method can include:
  • a gate metal layer having a thickness of 100 nm to 2000 nm is prepared by a physical vapor deposition method.
  • the gate metal layer may be composed of a metal, a metal alloy or a conductive metal oxide. It is also possible to use two or more layers of conductive materials, such as two layers of molybdenum metal and an aluminum metal layer between the two layers of molybdenum metal, namely Mo/Al/Mo (molybdenum/aluminum/molybdenum).
  • a photoresist is coated on the surface of the gate metal layer, and the gate metal layer is exposed, developed, and etched by a common mask to expose a portion of the surface of the gate metal layer; The uncovered gate metal layer is etched to form a pattern of the gate 11.
  • the gate insulating layer 12 can be prepared by physical vapor deposition, chemical vapor deposition, electrochemical oxidation or thermal oxidation, and the thickness of the gate insulating layer 12 is 50 nm to 1000 nm.
  • the material constituting the gate insulating layer 12 may be silicon dioxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (Si-ON), aluminum oxide (Al 2 O 3 ), or five. At least one of tantalum oxide (Ta 2 O 5 ), antimony trioxide (Y 2 O 3 ) or barium hydroxide (HfO 2 ).
  • the preparation gas pressure can be 0.02pa to 0.5pa. When the preparation gas pressure is less than 0.02 Pa and more than 0.5 Pa, the formed barium boride performance is degraded. In order to improve the stability of the lanthanum boride film layer, optionally, the above-mentioned preparation gas pressure may be 0.05 Pa to 0.3 Pa.
  • the growth rate of the lanthanum boride film layer may be 10 nm/min to 100 nm/min.
  • the growth rate of the film is less than 10 nm/min, the production efficiency is lowered.
  • the growth rate of the film is more than 100 nm/min, the film formation speed is too fast to cause a decrease in film properties.
  • the higher the content of boron element in the lanthanum boride film the more favorable the carrier concentration and conductivity are, thereby facilitating the conversion of lanthanum boride from the conductor to the semiconductor.
  • the boron element in the lanthanum boride is lighter than the lanthanum element, and is greatly affected by the growth rate of the film. Therefore, the growth rate of the film is faster in the range of 10 nm/min to 100 nm/min, and the boron element is more The substrate is easily reached, and thus the content of boron element in the formed lanthanum boride thin film layer is higher.
  • the growth rate of the above film may alternatively be from 20 nm/min to 100 nm/min.
  • the preparation gas pressure is the gas pressure of the physical vapor deposition chamber.
  • the preparation gas pressure is the sputtering pressure of the target.
  • the formed hafnium boride thin film layer may have a thickness of 10 nm to 500 nm. Since the performance of the TFT is affected by the respective film layers constituting the TFT. Among them, the semiconductor active layer is one of the most serious parts.
  • the thickness of the above-mentioned lanthanum boride thin film layer is less than 10 nm or more than 500 nm, the stability of the TFT performance is lowered, thereby lowering the yield of the product.
  • the above-mentioned lanthanum boride thin film layer may have a thickness of 20 nm to 200 nm.
  • the semiconductor active layer 13 is composed of a plurality of thin film layers
  • the above-mentioned lanthanum boride thin film layer is located in the intermediate layer of the multilayer thin film layer stack structure, and the lanthanum boride thin film layer is opposite to the multilayer thin film layer
  • the other thin film layers in the stacked structure have the largest thickness, for example, 10 nm to 500 nm.
  • the other thin film layers in the multilayer thin film layer stack structure may have a thickness of 10 nm to 50 nm, and a metal oxide semiconductor such as IGZO (indium gallium zinc oxide) may be used.
  • IGZO indium gallium zinc oxide
  • the film layer composed of the indium element occupies less in the entire semiconductor active layer 13 than the lanthanum boride, the use of the indium element can be reduced, thereby solving the problem that the indium element is increasingly scarce. And caused the problem of rising production costs.
  • the carrier concentration of the lanthanum boride film layer can be controlled to be 10 15 cm -3 -10 18 cm -3 , thereby achieving the purpose of converting the lanthanum boride film layer into a semiconductor.
  • the carrier concentration is less than 10 15 cm -3
  • the electron mobility is too low.
  • the carrier concentration is greater than 10 18 cm -3
  • the leakage current of the TFT is increased, which affects the switching characteristics of the device. . If further increased, the semiconductor active layer is conductorized, resulting in failure of the TFT. It should be noted that since the lanthanum element is less affected by the pressure than the boron element.
  • the pressure of an inert gas such as argon gas or nitrogen gas can be appropriately reduced.
  • an inert gas such as argon gas or nitrogen gas
  • the content of boron element in the formed lanthanum boride film is increased, thereby facilitating the reduction of the carrier concentration and the conductivity, thereby facilitating the conversion of the lanthanum boride from the conductor to the semiconductor.
  • a photoresist may be coated on the surface of the lanthanum boride film layer, and then the photoresist is masked and exposed by a common mask. And a developing process to expose a surface of the portion of the lanthanum boride film layer; thereafter, the lanthanum boride film layer not covered by the photoresist is etched to form a pattern of the semiconductor active layer 13.
  • a data metal layer having a thickness of 100 nm to 1000 nm is formed by physical vapor deposition.
  • the data metal layer may be composed of a metal, a metal alloy or a conductive metal oxide. It may also be composed of two or more layers of conductive materials, such as two layers of molybdenum metal and an aluminum metal layer between the two layers of molybdenum metal, namely Mo/Al/Mo (molybdenum/aluminum/molybdenum).
  • a photoresist is coated on the surface of the data metal layer, and the photoresist is masked, exposed, and developed to expose a surface of a portion of the data metal layer; and thereafter, the data not covered by the photoresist is exposed.
  • the metal layer is etched to form a pattern of the source 14 and the drain 15.
  • the above embodiment employs a physical vapor deposition method to prepare a semiconductor active layer 13 mainly composed of lanthanum boride.
  • a semiconductor active layer 13 mainly composed of lanthanum boride is prepared by a sputtering method, and a method of preparing a thin film transistor will be described in detail.
  • the preparation method provided in this embodiment is used to prepare the TFT shown in FIG. 2a, and the method specifically includes:
  • an Al thin film having a thickness of 300 nm is formed on the transparent substrate 10, and a pattern of the gate electrode 11 is formed by masking, exposure, etching, and development processes.
  • a gate insulating layer 12 having a thickness of 200 nm was formed on the substrate on which the pattern of the gate electrode 11 was formed by anodization.
  • a hafnium boride film is prepared by a sputtering method. Floor.
  • the lanthanum boride target is first mounted on a sputtering apparatus, and a thin film is prepared by direct sputtering.
  • the sputtering pressure is controlled to be 0.3 Pa, and the growth rate of the film is 10 nm/min to form a thickness. It is a 20 nm lanthanum boride film layer.
  • the pattern of the semiconductor active layer 13 is then formed by masking, exposure, development, and etching processes. Among them, the semiconductor active layer 13 has a carrier concentration of about 10 18 cm -3 and a mobility of about 3 cm 2 /Vs.
  • ITO Indium Tin Oxides
  • the transfer characteristic curve of the TFT device obtained by the above method is as shown in Fig. 4. It can be seen that when the gate voltage of the TFT device is 0 V, the drain current is about 10 - 9.5 A.
  • the preparation method provided in this embodiment is used to prepare the TFT shown in FIG. 2c.
  • the semiconductor active layer 13 of the TFT in this embodiment is located at the source 14 and Above the drain 15, the preparation steps of the semiconductor active layer 13 are located after the preparation steps of the source 14 and the drain 15.
  • the method provided in this embodiment is the same as the second embodiment except for the preparation method of the semiconductor active layer 13.
  • the method of preparing the semiconductor active layer 13 includes first preparing a lanthanum boride thin film layer by a sputtering method on a substrate on which the source electrode 14 and the drain electrode 15 are formed.
  • the lanthanum boride target is first mounted on a sputtering apparatus, and then formed into a film by direct sputtering.
  • the working pressure is controlled to 0.1 Pa during the sputtering process, and the growth rate of the film is 20 nm/min to form A lanthanum boride film layer having a thickness of 40 nm.
  • the pattern of the semiconductor active layer 13 is then formed by masking, exposure, etching, and development processes. Among them, the semiconductor active layer 13 has a carrier concentration of about 10 17 cm -3 and a mobility of about 1.5 cm 2 /Vs.
  • the transfer characteristic curve of the TFT device obtained by the above method is as shown in FIG. 5. It can be seen that when the gate voltage of the TFT device is 0 V, the drain current is about 10 -9 A.
  • the preparation method provided in this embodiment is used to prepare a TFT as shown in FIG. 2a.
  • the method provided in this embodiment is the same as the second embodiment except for the method for preparing the semiconductor active layer 13.
  • the method for preparing the semiconductor active layer 13 includes first preparing a lanthanum boride thin film layer by a sputtering method on a substrate on which the gate insulating layer 12 is formed.
  • the lanthanum boride target is first mounted on a sputtering apparatus, and a film is prepared by direct sputtering.
  • the working pressure is controlled to 0.05 Pa during the sputtering process, and the growth rate of the film is 30 nm/min to form a thickness. It is a 100 nm lanthanum boride film layer.
  • the pattern of the semiconductor active layer 13 is then formed by masking, exposure, etching, and development processes. Among them, the semiconductor active layer 13 has a carrier concentration of about 10 15 cm -3 and a mobility of about 2.8 cm 2 /Vs.
  • the transfer characteristic curve of the TFT device obtained by the above method is as shown in Fig. 6. It can be seen that when the gate voltage of the TFT device is 0 V, the drain current is about 10 -10.5 A.
  • the drain current of the TFT device fabricated in the fourth embodiment is the smallest, that is, the off-state current of the TFT is the smallest.
  • the gate voltage of the TFT device is between 0V and 10V, the slope of the curve shown in FIG. 6 is the largest. Therefore, the TFT device fabricated in the fourth embodiment has the fastest rising current of the drain current, so the TFT fabricated in the fourth embodiment is used. The device has the fastest switching response and the best switching characteristics.
  • Embodiments of the present disclosure provide a method for fabricating an array substrate, including a method for fabricating any of the above-described thin film transistors, having the same steps and advantageous effects as the method for fabricating the thin film transistor provided by the foregoing embodiments.
  • the steps and beneficial effects of the thin film transistor fabrication method have been described in detail since the foregoing embodiments, and are not described herein again.
  • the method for preparing the array substrate may include:
  • a gate metal layer having a thickness of 100 nm to 2000 nm is formed on the transparent substrate 10 by physical vapor deposition. Then, a photoresist is coated on the surface of the gate metal layer, and the gate metal layer is exposed, developed, and etched by a common mask to expose a portion of the surface of the gate metal layer; The uncovered gate metal layer is etched to form a pattern of the gate electrode 11 and the gate line.
  • the gate insulating layer 12 is prepared by a chemical vapor deposition method, an electrochemical oxidation method, or a thermal oxidation method, and the gate insulating layer 12 has a thickness of 50 nm to 1000 nm.
  • a semiconductorized hafnium boride thin film layer is prepared by a physical vapor deposition method.
  • a photoresist may be coated on the surface of the lanthanum boride film layer, and then the photoresist is masked and exposed by a common mask. And a developing process to expose a surface of the portion of the lanthanum boride film layer; thereafter, the lanthanum boride film layer not covered by the photoresist is etched to form a pattern of the semiconductor active layer 13.
  • a data metal layer having a thickness of 100 nm to 1000 nm is formed by physical vapor deposition. Then, a photoresist is coated on the surface of the data metal layer, and the photoresist is masked, exposed, and developed to expose a surface of a portion of the data metal layer; and thereafter, the data not covered by the photoresist is exposed.
  • the metal layer is etched to form a pattern of source 14, drain 15, and data lines.
  • a passivation layer can be formed on the substrate on which the patterns of the source 14, the drain 15, and the data lines are formed.
  • a via hole is formed by a patterning process for exposing a portion of the drain electrode 15.
  • the pixel electrodes are formed by a patterning process so that the pixel electrodes are connected to the drain electrodes 15 through the via holes.
  • FIG. 2a is merely an illustration of a method of fabricating an array substrate provided with the TFT shown in FIG. 2a.
  • Other types of array substrates such as an array substrate provided with TFTs as shown in FIG. 2b or 2c, or an array substrate provided with pixel electrodes and common electrodes at the same time, etc., will not be further described herein, but all should belong to the present disclosure. protected range.
  • An embodiment of the present disclosure provides a thin film transistor, as shown in FIG. 2a, FIG. 2b or FIG. 2c, which may include a gate electrode 11, a gate insulating layer 12, a semiconductor active layer 13, and a source electrode 14 and a drain electrode 15.
  • the semiconductor active layer 13 is mainly composed of lanthanum boride.
  • the semiconductor active layer 13 may have a thickness of 10 nm to 500 nm. Since the performance of the TFT is affected by the respective film layers constituting the TFT. Among them, the semiconductor active layer is one of the most serious parts. When the thickness of the above-mentioned lanthanum boride thin film layer is less than 10 nm or more than 500 nm, It will reduce the stability of TFT performance and thus reduce the yield of the product.
  • the active layer can be formed using a semiconductor material composed of lanthanum boride.
  • the strontium element is a rare earth element
  • the abundance in the earth's crust is 30ppm, which is much larger than the abundance of indium in the earth's crust, and the annual consumption of strontium is much smaller than that of indium. Therefore, the semiconductor active layer composed of lanthanum boride has an obvious cost and sustainable use advantage compared to the semiconductor active layer containing indium.
  • the lanthanum element of lanthanum boride is located in the center of the cube, and each of the six boron elements constitutes a regular octahedron.
  • each regular octahedron is located at the apex of the cube, and the yttrium element in the adjacent lattice has a certain electron orbit. Overlap to form an electronic channel. Therefore, lanthanum boride has high mobility and conductivity, so that the semiconductor active layer composed of lanthanum boride has high electron mobility, so that the thin film transistor has a high switching current ratio, which is advantageous for controlling the device. Leakage; at the same time, it can effectively increase the charging rate of the device, thereby improving the display effect of the display device.
  • An embodiment of the present disclosure provides an array substrate including any one of the thin film transistors described above, which has the same structure and advantageous effects as the thin film transistor provided by the foregoing embodiments, and the structure and the beneficial effects of the thin film transistor have been achieved by the foregoing embodiments. A detailed description is given and will not be described here.
  • Embodiments of the present disclosure provide a display device including the array substrate as described above.
  • the display device may be a liquid crystal display device, for example, the display device may be any product or component having a display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone or a tablet computer.
  • a display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone or a tablet computer.

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Abstract

提供一种薄膜晶体管、阵列基板及其制备方法、显示装置。其中，薄膜晶体管的制备方法包括：在透明基板（10）上，通过构图工艺形成半导体有源层（13）的图案；其中半导体有源层（13）的图案包括硼化镧图案。

Description

薄膜晶体管、阵列基板及其制备方法、显示装置
相关申请的交叉引用
本申请主张在2015年5月11日在中国提交的中国专利申请号No.201510236824.3的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种薄膜晶体管、阵列基板及其制备方法、显示装置。
背景技术
薄膜晶体管(Thin Film Transistor，简称TFT)作为显示技术领域中最重要的电子器件之一，用于控制和驱动液晶显示器(Liquid Crystal Display，简称LCD)以及有机发光二极管(Organic Light Emitting Diode，简称OLED)显示器的子像素。
随着显示技术的快速发展，薄膜晶体管技术由原来的非晶硅(a-Si)薄膜晶体管发展到现在的低温多晶硅(Low Temperature Poly-silicon，LTPS)薄膜晶体管、金属诱导横向晶化(Metal-Induced Lateral Crystallization，MILC)薄膜晶体管、氧化物(Oxide)薄膜晶体管等。
目前广泛应用的Oxide薄膜晶体管采用氧化物半导体作为有源层，具有迁移率大、开态电流高、开关特性更优、均匀性更好的特点，可以适用于需要快速响应和较大电流的应用，如高频、高分辨率、大尺寸的显示器以及有机发光显示器等。
然而，现有技术中，上述氧化物半导体材料大多包含有一些稀有金属元素，例如铟、锶等金属单质。其中，铟元素在地壳中的丰度只有0.049ppm左右。因此，随着工业需求对铟的大量消耗，使得金属单质铟越来越少，导致金属单质铟的价格升高，从而增加了显示设备的制作成本，不利于产品的量产。
发明内容
本公开的实施例提供一种薄膜晶体管、阵列基板及其制备方法、显示装置，能够减少半导体有源层中铟元素的使用，从而解决由于铟元素越来越稀 缺，而导致的制作成本上升的问题。
为达到上述目的，本公开的实施例采用如下技术方案：
本公开实施例的一方面，提供一种薄膜晶体管的制备方法，包括：
在透明基板上，通过构图工艺形成半导体有源层的图案；其中所述半导体有源层的图案包括硼化镧图案。
本公开实施例的另一方面，提供一种阵列基板的制备方法，包括如上所述的任意一种薄膜晶体管的制备方法。
本公开实施例的又一方面，提供一种薄膜晶体管，包括半导体有源层的图案，所述半导体有源层的图案包括有硼化镧图案。
本公开实施例的又一方面，提供一种阵列基板，包括如上所述的任意一种薄膜晶体管。
本公开实施例的又一方面，提供一种显示装置，包括如上所述的阵列基板。
本公开实施例提供一种薄膜晶体管、阵列基板及其制备方法、显示装置。其中，薄膜晶体管的制备方法包括：在透明基板上，通过构图工艺形成半导体有源层的图案；其中半导体有源层的图案包括硼化镧图案。这样一来，构成半导体有源层的主要成分可以为硼化镧。其中，镧元素虽然是稀土元素，但在地壳中的丰度30ppm，远大于铟元素在地壳中的丰度，而且镧元素的年均消耗量也远小于铟元素。因此，由硼化镧构成的半导体有源层相比于含铟的半导体有源层具有明显的成本和可持续使用的优势。此外，硼化镧的镧元素位于立方体体心，每六个硼元素组成一个正八面体，每个正八面体的体心位于立方体的顶点上，相邻的晶格中的镧元素具有一定的电子轨道交叠，形成电子通道。因此，硼化镧具有很高的迁移率和导电性，从而使得由硼化镧构成的半导体有源层的电子迁移率高，使得薄膜晶体管具有较高的开关电流比高，有利于控制器件的漏电；同时，可以有效地提高器件的充电率，进而提高显示器件的显示效果。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面 描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种薄膜晶体管的制备方法的流程图；
图2a为本公开实施例提供的一种底栅型的薄膜晶体管结构示意图；
图2b为本公开实施例提供的一种顶栅型的薄膜晶体管结构示意图；
图2c为本公开实施例提供的另一种底栅型的薄膜晶体管结构示意图；
图3为图2a所示的薄膜晶体管的制备方法流程图；
图4为图2a所示的薄膜晶体管的一种TFT转移特性曲线图；
图5为图2c所示的薄膜晶体管的一种TFT转移特性曲线图；
图6为图2a所示的薄膜晶体管的另一种TFT转移特性曲线图。
附图说明：
10-透明基板；11-栅极；12-栅极绝缘层；13-半导体有源层；14源极；15-漏极。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
本公开实施例提供一种薄膜晶体管的制备方法，如图1所示，可以包括：
S101、如图2a所示，在透明基板10上，通过构图工艺形成栅极图案11。
S102、在透明基板10上，通过构图工艺形成栅极绝缘层12。
S103、在透明基板10上，通过构图工艺形成半导体有源层13的图案；其中，该半导体有源层13的图案包括硼化镧图案。
S104、在透明基板10上，通过构图工艺形成源极14、漏极15的图案。
需要说明的是，第一、本公开对上述步骤S101至S104的先后顺序不做限定。例如当TFT如图2a所示为底栅型薄膜晶体管时，上述方法可以为，先进行步骤S101，以在透明基板10上形成栅极11的图案，然后在形成有栅极图案11的基板上形成栅极绝缘层12；之后再形成有栅极绝缘层12的基板上形成包括硼化镧图案的半导体有源层13的图案，最后在形成有半导体有源层13图案的基板上形成源极14和漏极15的图案。
而当TFT如图2b所示为顶栅型薄膜晶体管时，上述方法可以为，先进行步骤S103，以在透明基板10上形成包括硼化镧图案的半导体有源层13的图案；然后，在形成有半导体有源层13图案的基板上形成源极14和漏极15的图案；之后再形成有源极14和漏极15图案的基板上依次形成栅极绝缘层12以及栅极11的图案。
综上所述，底栅型TFT和顶栅型TFT是相对所述栅极11和栅极绝缘层12的位置而定的，即：相对所述透明基板10而言，当栅极11如图2a所示，靠近所述透明基板10，栅极绝缘层12远离所述透明基板10时，为底栅型TFT；当栅极11远离所述透明基板10，栅极绝缘层12靠近所述透明基板10时，为顶栅型TFT。
本公开以下实施例均是以底栅型TFT为例进行的说明，当然对于顶栅型TFT而言同样适用。由于原理相同，因此不再对顶栅型TFT进行赘述，但都应当属于本公开的保护范围。
此外，上述步骤S101、S102以及S104的具体实施方式可以参见现有技术。
第二、在本公开实施例中的构图工艺，可指包括光刻工艺，或，包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺包括成膜、曝光、显影等工艺，具体可以利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本公开中所形成的结构选择相应的构图工艺。
第三、上述透明基板10可以由硬质材料构成，例如玻璃基板、硬质树脂基板，或者是由柔性材料构成的透明基板。并且，上述步骤中在透明基板10上制备各种薄膜层，可以是直接在透明基板10的表面上进行制备，或者，可以是在已经形成有一些薄膜层或薄膜层图案的透明基板10上进行制备。
第四、本公开实施例中，半导体有源层13主要由硼化镧薄膜层构成。硼化镧的化学式为LaxBy，当y为1时，x的取值范围可以为0.05-1之间。本领域技术人员可以根据实际情况对上述y和x的数值进行调节。其中，硼元素的含量越高，载流子的浓度和导电率越低，进而利于实现硼化镧从导体到半导体的转换。
具体地，当半导体有源层13的图案由单层薄膜层构成时，该单层薄膜层可以为硼化镧薄膜层。或者，当半导体有源层13为多层薄膜层堆叠而成时，硼化镧薄膜层位于多层薄膜层堆叠结构的中间层，且硼化镧薄膜层相对于多层薄膜层堆叠结构中的其他薄膜层而言，厚度最大。其中，多层薄膜层堆叠结构中的其他薄膜层可以采用金属氧化物半导体，例如铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)。由于铟元素构成的薄膜层在整个半导体有源层13中占有的份额相对于硼化镧而言较少，因此可以减小铟元素的使用，从而解决由于铟元素越来越稀缺，而导致的制作成本上升的问题。
此外，硼化镧还具有高熔点、耐离子轰击、抗氧化、导热、化学稳定性好的优点，同时其迁移率相对于非晶硅而言较高。
本公开实施例提供一种薄膜晶体管的制备方法，包括：在透明基板上，通过构图工艺形成半导体有源层的图案；其中半导体有源层的图案包括硼化镧图案。这样一来，构成半导体有源层的主要成分可以为硼化镧。其中，镧元素虽然是稀土元素，但在地壳中的丰度30ppm，远大于铟元素在地壳中的丰度，而且镧元素的年均消耗量也远小于铟元素。因此，由硼化镧构成的半导体有源层相比于含铟的半导体有源层具有明显的成本和可持续使用的优势。此外，硼化镧的镧元素位于立方体体心，每六个硼元素组成一个正八面体，每个正八面体的体心位于立方体的顶点上，相邻的晶格中的镧元素具有一定的电子轨道交叠，形成电子通道。因此，硼化镧具有很高的迁移率和导电性，从而使得由硼化镧构成的半导体有源层的电子迁移率高，使得薄膜晶体管具 有较高的开关电流比高，有利于控制器件的漏电；同时，可以有效地提高器件的充电率，进而提高显示器件的显示效果。
以下通过具体的实施例对上述薄膜晶体管的制备方法进行详细的举例说明。
实施例一
本实施例提供的制备方法，用于制备如图2a所示的TFT，尤其是本实施例采用物理气相沉积法制备主要由硼化镧构成的半导体有源层13，如图3所示，制备TFT的方法可以包括：
S201、在透明基板10上，形成栅极11的图案。
具体的，在透明基板10上，通过物理气相沉积法制备厚度为100nm～2000nm的栅极金属层。其中，该栅极金属层可以采用金属、金属合金或导电金属氧化物构成。还可以采用由两层以上的导电材料构成，例如两层钼金属层和位于所述两层钼金属层之间的铝金属层，即Mo/Al/Mo(钼/铝/钼)等。然后，在栅极金属层的表面涂覆光刻胶，并采用普通掩膜版对栅极金属层进行曝光、显影、刻蚀工艺，露出部分栅极金属层的表面；之后，对光刻胶未覆盖的栅极金属层进行刻蚀，从而形成栅极11的图案。
S202、在形成有栅极11图案的基板上，形成栅极绝缘层12。
具体的，在形成有栅极11图案的基板上，可以通过物理气相沉积法、化学气相沉积法、电化学氧化法或热氧化法制备栅极绝缘层12，该栅极绝缘层12的厚度为50nm～1000nm。其中，构成该栅极绝缘层12的材料可以为二氧化硅(SiO2)、氮化硅(SiNx)、氮氧化硅(Si-O-N)、三氧化二铝(Al2O3)、五氧化二钽(Ta2O5)、三氧化二钇(Y2O3)或氢氧化铪(HfO2)中的至少一种。
S203、在形成有栅极绝缘层12的基板上，通过物理气相沉积法制备半导体化的硼化镧薄膜层。
其中制备气压可以为0.02pa～0.5pa。当制备气压小于0.02pa和大于0.5pa，形成的硼化镧性能会下降。为了提高硼化镧薄膜层的稳定性，可选地，上述制备气压可以为0.05pa～0.3Pa。
并且，当制备气压为0.05pa～0.3Pa时，硼化镧薄膜层的生长速率可以为 10nm/min～100nm/min。当薄膜的生长速率小于10nm/min时，会导致生产效率下降。当薄膜的生长速率大于100nm/min时，成膜速度太快从而导致薄膜性能下降。需要说明的是，由于硼化镧薄膜中，硼元素的含量越高，越有利于降低载流子的浓度和导电率，进而有利于实现硼化镧从导体到半导体的转换。而硼化镧中的硼元素相对于镧元素而言较轻，受到薄膜的生长速率的影响较大，因此在10nm/min～100nm/min的范围内，薄膜的生长速率越快，硼元素越容易到达基板，因此形成的硼化镧薄膜层中硼元素的含量越高。为了提高硼化镧薄膜层的稳定性，可选地，上述薄膜的生长速率可以为20nm/min～100nm/min。
需要说明的是，上述在制备硼化镧薄膜层的过程中，当采用物理气相沉积法时，所述制备气压为物理气相沉积腔室的气压。当采用溅射法制备硼化镧薄膜层时，所述制备气压为靶材的溅射压强。
此外，形成的硼化镧薄膜层的厚度可以为10nm～500nm。由于TFT的性能会受到组成该TFT的各个薄膜层的影响。其中半导体有源层又是对其影响最为严重的部分之一。当上述硼化镧薄膜层的厚度小于10nm或大于500nm时，会降低TFT性能的稳定性，从而降低了产品的良率。为了进一步提高TFT性能的稳定性，上述硼化镧薄膜层的厚度可以为20nm～200nm。
需要说明的是，当半导体有源层13由多层薄膜层构成时，当上述硼化镧薄膜层位于多层薄膜层堆叠结构的中间层时，且硼化镧薄膜层相对于多层薄膜层堆叠结构中的其他薄膜层而言，厚度最大，例如为10nm～500nm。多层薄膜层堆叠结构中的其他薄膜层的厚度可以为10nm-50nm，并且可以采用金属氧化物半导体，例如IGZO(indium gallium zinc oxide，铟镓锌氧化物)。这样一来，由于铟元素构成的薄膜层在整个半导体有源层13中占有的份额相对于硼化镧而言较少，因此可以减小铟元素的使用，从而解决由于铟元素越来越稀缺，而导致的制作成本上升的问题。
此外，在制备过程中，可以控制硼化镧薄膜层的载流子浓度为1015cm-3-1018cm-3，从而达到了将硼化镧薄膜层转化成半导体的目的。其中，当载流子浓度小于1015cm-3时，导致电子迁移率过低，当载流子浓度大于1018cm-3时，会导致TFT的漏电流增大，从而影响器件的开关特性。如果进 一步增大会使半导体有源层导体化，从而导致TFT失效。需要说明的是，由于镧元素相对于硼元素而言，受压强影响较小。因此，在采用物理气相沉积法制备硼化镧薄膜层时，可以适当的降低氩气或氮气等惰性气体的压强。这样一来，可以有利于硼元素达到基板。从而使得形成的硼化镧薄膜中硼元素的含量增加，从而有利于降低载流子的浓度和导电率，进而利于实现硼化镧从导体到半导体的转换。
当形成具有半导体特性的硼化镧薄膜层后，可以在该硼化镧薄膜层的表面涂覆一层光刻胶，然后，采用普通掩膜版对所述光刻胶进行通过掩膜、曝光、显影工艺，露出部分硼化镧薄膜层的表面；之后，对光刻胶未覆盖的所述硼化镧薄膜层进行刻蚀，从而形成半导体有源层13的图案。
S204、在形成半导体有源层13的基板上，形成源极14、漏极15的图案。
具体的，在形成半导体有源层13的基板上，通过物理气相沉积法形成厚度为100nm～1000nm的数据金属层。其中，该数据金属层可以采用金属、金属合金或导电金属氧化物构成。还可以由两层以上的导电材料构成，例如两层钼金属层和位于所述两层钼金属层之间的铝金属层，即Mo/Al/Mo(钼/铝/钼)等。然后，在所述数据金属层的表面涂覆光刻胶，并对光刻胶进行掩膜、曝光以及显影工艺，露出部分数据金属层的表面；之后，对光刻胶未覆盖的所述数据金属层进行刻蚀，从而形成源极14、漏极15的图案。
上述实施例采用物理气相沉积法制备主要由硼化镧构成的半导体有源层13。以下实施例以采用溅射法制备主要由硼化镧构成的半导体有源层13为例，对薄膜晶体管的制备方法进行详细的描述。
实施例二
本实施例提供的制备方法，用于制备如图2a所示的TFT，所述方法具体包括：
首先，在透明基板10上形成厚度为300nm的Al薄膜，通过掩膜、曝光、刻蚀以及显影工艺，形成栅极11的图案。
接下来，在形成有栅极11图案的基板上，采用阳极氧化的方法制备厚度为200nm的栅极绝缘层12。
接下来，在形成有栅极绝缘层12的基板上，采用溅射法制备硼化镧薄膜 层。
具体的，先将硼化镧靶材安装在溅射仪上，通过直接溅射的方法制备成薄膜，溅射过程中控制制备气压为0.3Pa，薄膜的生长速率为10nm/min，以形成厚度为20nm的硼化镧薄膜层。然后通过掩膜、曝光、显影以及刻蚀工艺，形成半导体有源层13的图案。其中，半导体有源层13的载流子浓度约为1018cm-3，迁移率约为3cm2/Vs。
最后，在形成有半导体有源层13的基板上，采用溅射的方法形成一层氧化铟锡金属氧化物(Indium Tin Oxides，简称ITO)薄膜，厚度380nm，并采用掩膜、曝光、显影以及刻蚀工艺进行图形化，以同时得到源极14和漏极15的图案。
通过上述方法得到的TFT器件的转移特性曲线如图4所示，可以看出，当TFT器件的栅极电压为0V时，漏极电流在10-9.5A左右。
实施例三
本实施例提供的制备方法，用于制备如图2c所示的TFT，与实施例二提供的底栅型TFT不同的是，本实施例中的TFT的半导体有源层13位于源极14和漏极15的上方，因此半导体有源层13的制备步骤位于源极14和漏极15的制备步骤之后。
此外，本实施例提供的方法除了半导体有源层13的制备方法之外，其它各个薄膜层的制备方法与实施例二相同。
半导体有源层13的制备方法包括：首先，在形成有源极14和漏极15的基板上，采用溅射法制备硼化镧薄膜层。
具体的，先将硼化镧靶材安装在溅射仪上，然后通过直接溅射的方法制备成薄膜，溅射过程中控制工作气压为0.1Pa，薄膜的生长速率为20nm/min，以形成厚度为40nm的硼化镧薄膜层。然后通过掩膜、曝光、刻蚀以及显影工艺，形成半导体有源层13的图案。其中，半导体有源层13的载流子浓度约为1017cm-3，迁移率约为1.5cm2/Vs。
通过上述方法得到的TFT器件的转移特性曲线如图5所示，可以看出，当TFT器件的栅极电压为0V时，漏极电流在10-9A左右。
实施例四
本实施例提供的制备方法，用于制备如图2a所示的TFT。其中，本实施例提供的方法除了半导体有源层13的制备方法之外，其它各个薄膜层的制备方法与实施例二相同。
半导体有源层13的制备方法包括：首先，在形成有栅极绝缘层12的基板上，采用溅射法制备硼化镧薄膜层。
具体的，先将硼化镧靶材安装在溅射仪上，通过直接溅射的方法制备成薄膜，溅射过程中控制工作气压为0.05Pa，薄膜的生长速率为30nm/min，以形成厚度为100nm的硼化镧薄膜层。然后通过掩膜、曝光、刻蚀以及显影工艺，形成半导体有源层13的图案。其中，半导体有源层13的载流子浓度约为1015cm-3，迁移率约为2.8cm2/Vs。
通过上述方法得到的TFT器件的转移特性曲线如图6所示，可以看出，当TFT器件的栅极电压为0V时，漏极电流在10-10.5A左右。
综上所述，对比图4、图5以及图6可知，当TFT器件的栅极电压为0V时，采用实施例四制作的TFT器件的漏极电流最小，即TFT的关态电流最小。当TFT器件的栅极电压在0V到10V之间时，图6所示的曲线的斜率最大，因此，实施例四制作的TFT器件的漏极电流上升速度最快，所以实施例四制作的TFT器件的开关响应速度最快，开关特性最好。
本公开实施例提供一种阵列基板的制备方法，包括上述任意一种薄膜晶体管的制备方法，具有与前述实施例提供的薄膜晶体管的制备方法相同的步骤和有益效果。由于前述实施例已经对薄膜晶体管制备方的步骤和有益效果进行了详细的描述，此处不再赘述。
例如，当上述阵列基板包括如图2a所示的底栅型TFT时，所述阵列基板的制备方法可以包括：
首先，在透明基板10上，通过物理气相沉积法制备厚度为100nm～2000nm的栅极金属层。然后，在栅极金属层的表面涂覆光刻胶，并采用普通掩膜版对栅极金属层进行曝光、显影、刻蚀工艺，露出部分栅极金属层的表面；之后，对光刻胶未覆盖的栅极金属层进行刻蚀，从而形成栅极11以及栅线的图案。
然后，在形成有栅极11和栅线图案的基板上，可以通过物理气相沉积法、 化学气相沉积法、电化学氧化法或热氧化法制备栅极绝缘层12，该栅极绝缘层12的厚度为50nm～1000nm。
接下来，在形成有栅极绝缘层12的基板上，通过物理气相沉积法制备半导体化的硼化镧薄膜层。具体制备过程可以参照上述实施例一。当形成具有半导体特性的硼化镧薄膜层后，可以在该硼化镧薄膜层的表面涂覆一层光刻胶，然后，采用普通掩膜版对所述光刻胶进行通过掩膜、曝光、显影工艺，露出部分硼化镧薄膜层的表面；之后，对光刻胶未覆盖的所述硼化镧薄膜层进行刻蚀，从而形成半导体有源层13的图案。
接下来，在形成半导体有源层13的基板上，通过物理气相沉积法形成厚度为100nm～1000nm的数据金属层。然后，在所述数据金属层的表面涂覆光刻胶，并对光刻胶进行掩膜、曝光以及显影工艺，露出部分数据金属层的表面；之后，对光刻胶未覆盖的所述数据金属层进行刻蚀，从而形成源极14、漏极15以及数据线的图案。
接下来，在形成源极14、漏极15以及数据线的图案的基板上，可以通过形成一层钝化层。
接下来，在形成有钝化层上，通过构图工艺制作过孔，用于露出部分漏极15。
最后，在形成有过孔的基板上，通过构图工艺形成像素电极，使得像素电极通过上述过孔与漏极15相连接。
当然，上述仅仅是对设置有如图2a所示的TFT的一种阵列基板制作方法的举例说明。其他类型的阵列基板，例如设置如图2b或2c所示的TFT的阵列基板，或者同时设置有像素电极和公共电极的阵列基板等，在此不再一一赘述，但都应当属于本公开的保护范围。
本公开实施例提供一种薄膜晶体管，如图2a、图2b或图2c所示，可以包括栅极11、栅极绝缘层12、半导体有源层13、以及源极14和漏极15。其中，半导体有源层13主要有硼化镧构成。
可选地，半导体有源层13的厚度可以为10nm～500nm。由于TFT的性能会受到组成该TFT的各个薄膜层的影响。其中半导体有源层又是对其影响最为严重的部分之一。当上述硼化镧薄膜层的厚度小于10nm或大于500nm时， 会降低TFT性能的稳定性，从而降低了产品的良率。
这样一来，可以采用硼化镧构成的半导体材料构成有源层。镧元素虽然是稀土元素，但在地壳中的丰度30ppm，远大于铟元素在地壳中的丰度，而且镧元素的年均消耗量也远小于铟元素。因此，由硼化镧构成的半导体有源层相比于含铟的半导体有源层具有明显的成本和可持续使用的优势。此外，硼化镧的镧元素位于立方体体心，每六个硼元素组成一个正八面体，每个正八面体的体心位于立方体的顶点上，相邻的晶格中的镧元素具有一定的电子轨道交叠，形成电子通道。因此，硼化镧具有很高的迁移率和导电性，从而使得由硼化镧构成的半导体有源层的电子迁移率高，使得薄膜晶体管具有较高的开关电流比高，有利于控制器件的漏电；同时，可以有效地提高器件的充电率，进而提高显示器件的显示效果。
本公开实施例提供一种阵列基板，包括如上所述的任意一种薄膜晶体管，具有与前述实施例提供的薄膜晶体管相同的结构和有益效果，由于前述实施例已经对薄膜晶体管的结构和有益效果进行了详细的描述，此处不再赘述。
本公开实施例提供一种显示装置，包括如上所述的阵列基板。该显示装置可以是液晶显示装置，例如该显示装置可以为液晶显示器、液晶电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件。具有与前述实施例提供的阵列基板相同的结构和有益效果，由于前述实施例已经对阵列基板的结构和有益效果进行了详细的描述，此处不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种薄膜晶体管的制备方法，包括：
    在透明基板上，通过构图工艺形成半导体有源层的图案；其中所述半导体有源层的图案包括硼化镧图案。
  2. 根据权利要求1所述的薄膜晶体管的制备方法，其中，所述通过构图工艺形成半导体有源层的图案的方法包括：
    采用物理气相沉积法或溅射法的成膜工艺，在所述透明基板上制备硼化镧薄膜层；所述成膜工艺中的制备压强为0.02pa～0.5pa；
    在所述硼化镧薄膜层的表面涂覆一层光刻胶；
    对所述光刻胶进行通过掩膜、曝光、显影工艺，露出部分硼化镧薄膜层的表面；
    对所述光刻胶未覆盖的所述硼化镧薄膜层进行刻蚀，从而形成所述半导体有源层的图案。
  3. 根据权利要求2所述的薄膜晶体管的制备方法，其中，
    所述制备压强为0.05pa～0.3Pa，并且
    所述硼化镧薄膜层的生长速率为10nm/min～100nm/min。
  4. 根据权利要求3所述的薄膜晶体管的制备方法，其中，
    所述硼化镧薄膜层的生长速率为20nm/min～100nm/min。
  5. 根据权利要求2所述的薄膜晶体管的制备方法，其中，
    在采用物理气相沉积法制备硼化镧薄膜层时，降低惰性气体的压强以有利于硼元素达到基板。
  6. 根据权利要求1所述的薄膜晶体管的制备方法，其中，所述硼化镧图案的厚度为10nm～500nm。
  7. 根据权利要求1所述的薄膜晶体管的制备方法，其中，所述硼化镧图案的载流子浓度为1015cm-3-1018cm-3。
  8. 根据权利要求1所述的薄膜晶体管的制备方法，其中，所述通过构图工艺形成半导体有源层的图案的方法包括：
    通过直接溅射的方法制备硼化镧薄膜层，溅射过程中控制工作气压为 0.05Pa，薄膜的生长速率为30nm/min，并形成厚度为100nm的硼化镧薄膜层；
    通过掩膜、曝光、刻蚀以及显影工艺，形成半导体有源层的图案。
  9. 一种阵列基板的制备方法，包括如权利要求1-8任一项所述的薄膜晶体管的制备方法。
  10. 一种薄膜晶体管，包括半导体有源层的图案，其中，所述半导体有源层的图案包括硼化镧图案。
  11. 根据权利要求10所述的薄膜晶体管，其中，所述硼化镧图案的厚度为10nm～500nm。
  12. 根据权利要求10所述的薄膜晶体管，其中，所述硼化镧图案的载流子浓度为1015cm-3-1018cm-3。
  13. 根据权利要求10所述的薄膜晶体管，，其中，
    当半导体有源层的图案由单层薄膜层构成时，该单层薄膜层为硼化镧薄膜层。
  14. 根据权利要求10所述的薄膜晶体管，其中，
    当半导体有源层为多层薄膜层堆叠而成时，硼化镧薄膜层位于多层薄膜层堆叠结构的中间层，且硼化镧薄膜层相对于多层薄膜层堆叠结构中的其他薄膜层而言，厚度最大。
  15. 根据权利要求14所述的薄膜晶体管，其中，
    多层薄膜层堆叠结构中的其他薄膜层为金属氧化物半导体。
  16. 一种阵列基板，包括如权利要求10-15任一项所述的薄膜晶体管。
  17. 一种显示装置，包括如权利要求16所述的阵列基板。
PCT/CN2015/091545 2015-05-11 2015-10-09 薄膜晶体管、阵列基板及其制备方法、显示装置 WO2016179952A1 (zh)

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