WO2016179882A1 - Esl型tft基板结构及其制作方法 - Google Patents

Esl型tft基板结构及其制作方法 Download PDF

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WO2016179882A1
WO2016179882A1 PCT/CN2015/082012 CN2015082012W WO2016179882A1 WO 2016179882 A1 WO2016179882 A1 WO 2016179882A1 CN 2015082012 W CN2015082012 W CN 2015082012W WO 2016179882 A1 WO2016179882 A1 WO 2016179882A1
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layer
oxide semiconductor
drain
semiconductor layer
electrode
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French (fr)
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李文辉
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an ESL type TFT substrate structure and a method of fabricating the same.
  • LCDs liquid crystal displays
  • OLEDs organic light emitting diodes
  • the display panel is an important part of LCD and OLED. Both the display panel of the LCD and the display panel of the OLED usually have a Thin Film Transistor (TFT) substrate.
  • TFT Thin Film Transistor
  • the display panel of the LCD mainly consists of a TFT substrate, a color filter substrate (Color Filter, CF), and a liquid crystal layer (Liquid Crystal Layer) disposed between the two substrates.
  • the working principle is By applying a driving voltage to the TFT substrate and the CF substrate, the rotation of the liquid crystal molecules in the liquid crystal layer is controlled, and the light of the backlight module is refracted to generate a picture.
  • the existing TFT substrates mainly include a Coplanar type, an Etch Stop Layer (ESL) type, and a Back Channel Etch (BCE) type.
  • ESL Etch Stop Layer
  • BCE Back Channel Etch
  • a conventional ESL-type TFT substrate includes a substrate 10 , a gate electrode 20 sequentially disposed on the substrate 10 , a gate insulating layer 30 , an oxide semiconductor layer 40 , an etch stop layer 50 , a source 61 , and a drain. 62.
  • the ESL-type TFT substrate shown in Figure 1 uses an etch stop layer ESL to avoid back channel damage, but there are variations in process accuracy (such as alignment deviation of the exposure process, line width deviation of the etching process, etc.), source 61 and drain
  • the pole 62 must have a certain overlap length L1 and L3 with the etch stop layer 50, plus the minimum slit length L2 between the source 61 and the drain 62 under the existing process capability, and the actual channel length L is L1.
  • the larger channel length L is likely to cause a decrease in the conductivity of the TFT on the one hand, and an increase in the size of the TFT on the other hand, thereby causing a decrease in the aperture ratio of the pixel and increasing the difficulty in pixel design.
  • An object of the present invention is to provide an ESL type TFT substrate structure having a small channel length, on the one hand, the TFT has good electrical conductivity, and on the other hand, the TFT size is small, thereby increasing the pixel aperture ratio and reducing the pixel. Design difficulty.
  • Another object of the present invention is to provide a method for fabricating an ESL-type TFT substrate, which can reduce the channel length, improve the conductivity of the TFT, and reduce the size of the TFT, thereby improving the pixel aperture ratio and reducing the pixel design difficulty.
  • an ESL type TFT substrate structure including:
  • a gate disposed on the substrate
  • a gate insulating layer disposed on the gate and the substrate;
  • An oxide semiconductor layer disposed on the gate insulating layer above the gate;
  • An etch barrier layer disposed on the oxide semiconductor layer, wherein the etch barrier layer is respectively provided with a first via hole and a second via hole on opposite sides of the oxide semiconductor layer;
  • a passivation protection layer disposed on the drain and the etch barrier layer, the passivation protection layer is provided with a through hole penetrating through the second via hole;
  • the source and the drain do not overlap in a space above the gate.
  • the source and the drain overlap in a space above the gate.
  • the material of the oxide semiconductor layer is indium gallium zinc oxide.
  • the material of the electrode layer is indium tin oxide.
  • the invention also provides an ESL type TFT substrate structure, comprising:
  • a gate disposed on the substrate
  • a gate insulating layer disposed on the gate and the substrate;
  • An oxide semiconductor layer disposed on the gate insulating layer above the gate;
  • An etch barrier layer disposed on the oxide semiconductor layer, wherein the etch barrier layer is respectively provided with a first via hole and a second via hole on opposite sides of the oxide semiconductor layer;
  • a passivation protective layer disposed on the drain and the etch stop layer, wherein the passivation protective layer is provided with a through hole penetrating through the second via hole;
  • the material of the oxide semiconductor layer is indium gallium zinc oxide
  • the material of the electrode layer is indium tin oxide.
  • the invention also provides a method for fabricating an ESL type TFT substrate, comprising the following steps:
  • Step 1 providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer to obtain a gate;
  • Step 2 depositing a gate insulating layer on the gate and the substrate; depositing and patterning an oxide semiconductor layer on the gate insulating layer;
  • Step 3 depositing an etch barrier layer on the oxide semiconductor layer, and patterning the etch barrier layer by using a gray scale reticle to completely etch the etch barrier layer corresponding to one side of the oxide semiconductor layer Etching away, exposing a side region of the oxide semiconductor layer, forming a transparent first via hole, etching away an etch barrier layer portion corresponding to the other side of the oxide semiconductor layer, without exposing The other side region of the oxide semiconductor layer forms a second via in the form of a blind via;
  • the spacing distance between the first and second vias defines a channel length
  • Step 4 depositing a second metal layer on the etch barrier layer, and patterning the second metal layer to obtain a drain; the drain passing through the first via and the oxide semiconductor Layer contact;
  • Step 5 depositing a passivation protective layer on the drain and the etch barrier layer, and patterning the passivation protective layer to form a via hole penetrating through the second via hole in the form of the blind via hole, and simultaneously The second via hole in the form of a blind hole is completely dug, forming a transparent second via hole to keep the channel length unchanged;
  • Step 6 Depositing and patterning an electrode layer on the passivation protective layer, one side of the electrode layer being relatively close to the drain and contacting the oxide semiconductor layer via the via hole and the second via hole to form a source
  • the other side of the electrode layer extends in a direction away from the drain to constitute a pixel electrode.
  • the step 3 specifically includes the following steps:
  • Step 31 coating a photoresist layer on the etch barrier layer, exposing and developing the photoresist layer by using a gray scale reticle, respectively obtaining a full exposure region corresponding to a side of the oxide semiconductor layer. And corresponding to a half-exposure region located on the other side of the oxide semiconductor layer;
  • Step 32 using the photoresist layer as a shielding layer, etching the etching barrier layer, and The etch stop layer under the fully exposed area is completely etched away to obtain a transparent first via hole, and the etch stop layer portion corresponding to the underside of the half exposure region is etched away to form a second pass in the form of a blind via. hole;
  • Step 33 peeling off the photoresist layer.
  • the etching is performed by a dry etching process.
  • the source and the drain do not overlap in a space above the gate.
  • the source and the drain overlap in a space above the gate.
  • the present invention provides an ESL-type TFT substrate structure in which the same electrode layer is provided as both a source and a pixel electrode, and the drain and the source are respectively located in different layers, so that the channel length of the TFT Smaller, on the one hand, can make the TFT have good electrical conductivity, on the one hand, the TFT can be made smaller in size, thereby improving the pixel aperture ratio and reducing the pixel design difficulty.
  • the method for fabricating an ESL type TFT substrate provided by the present invention firstly performs patterning treatment on the etching barrier layer by using a gray scale mask to obtain a first via hole in the form of a transparent first via hole and a blind via hole, and passes through the first
  • the spacing distance between the second vias defines the channel length, and then the drain is formed, and then the passivation protective layer is deposited and patterned while the second via in the form of the blind via is completely dig open to maintain the channel.
  • the length is constant, and finally an electrode layer serving as a source and a pixel electrode is formed, which can reduce the channel length, improve the conductivity of the TFT, and reduce the size of the TFT, thereby improving the pixel aperture ratio and reducing the pixel design difficulty.
  • FIG. 1 is a schematic cross-sectional structural view of a conventional ESL type TFT substrate
  • FIG. 2 is a cross-sectional view showing a first embodiment of an ESL type TFT substrate structure according to the present invention
  • FIG. 3 is a cross-sectional view showing a second embodiment of an ESL type TFT substrate structure according to the present invention.
  • FIG. 4 is a flow chart showing a method of fabricating an ESL type TFT substrate according to the present invention.
  • step 1 is a schematic diagram of step 1 of a method for fabricating an ESL type TFT substrate according to the present invention
  • step 2 is a schematic diagram of step 2 of a method for fabricating an ESL type TFT substrate according to the present invention
  • FIG. 7 to FIG. 9 are schematic diagrams showing the third step of the method for fabricating an ESL type TFT substrate according to the present invention.
  • step 4 is a schematic diagram of step 4 of a method for fabricating an ESL type TFT substrate according to the present invention.
  • FIG. 11 is a schematic view showing a step 5 of a method for fabricating an ESL type TFT substrate according to the present invention.
  • Figure 12 is a schematic view showing the sixth step of the method for fabricating an ESL type TFT substrate of the present invention.
  • the present invention first provides an ESL type TFT substrate structure.
  • 2 is a schematic view showing a first embodiment of an ESL type TFT substrate structure according to the present invention.
  • the ESL type TFT substrate structure includes:
  • a gate insulating layer 3 disposed on the gate 2 and the substrate 1;
  • An etch stop layer 5 is disposed on the oxide semiconductor layer 4, and the etch stop layer 5 is respectively provided with a first via 51 and a second via 52 on both sides of the oxide semiconductor layer 4;
  • the spacing distance L4 between the first and second via holes 51, 52 defines the channel length;
  • the passivation protective layer 7 disposed on the drain 6 and the etch stop layer 5, the passivation protective layer 7 is provided with a through hole 72 penetrating through the second via 52;
  • the source electrode 81 is formed; the other side of the electrode layer 8 extends in a direction away from the drain electrode 6, and constitutes a pixel electrode 82.
  • the material of the oxide semiconductor layer 4 is Indium Gallium Zinc Oxide (IGZO).
  • the material of the electrode layer 8 is Indium Tin Oxide (ITO).
  • the source 81 and the drain 6 do not overlap in the space above the gate 2.
  • FIG 3 is a schematic view showing a second embodiment of an ESL type TFT substrate structure according to the present invention, and the second embodiment is different from the first embodiment in that the source electrode 81 and the drain electrode 6 are at the gate electrode 2 There is overlap in the upper space, and the process precision of the electrode layer 8 is relatively lower. The rest are the same as the first embodiment, and will not be described again here.
  • the same electrode layer 8 is provided as both the source 81 and the pixel electrode 82, and the drain 6 and the source 81 are respectively located at different layers, so that the trench of the TFT
  • the track length is the distance L4 between the first and second via holes 51, 52, which is smaller than the channel length of the existing ESL type TFT substrate.
  • the TFT can have good electrical conductivity, and on the other hand, can The TFT size is small, which can increase the pixel aperture ratio and reduce the pixel design difficulty.
  • the present invention further provides a method for fabricating an ESL type TFT substrate, comprising the following steps:
  • Step 1 as shown in FIG. 5, a substrate 1 is provided, a first metal layer is deposited on the substrate 1, and the first metal layer is patterned to obtain a gate 2.
  • Step 2 As shown in FIG. 6, a gate insulating layer 3 is deposited on the gate electrode 2 and the substrate 1, and an oxide semiconductor layer 4 is deposited and patterned on the gate insulating layer 3.
  • the material of the oxide semiconductor layer 4 is IGZO.
  • Step 3 depositing an etch barrier layer 5 on the oxide semiconductor layer 4, and patterning the etch barrier layer 5 with a gray scale mask, which corresponds to the oxidation
  • the etching stopper layer 5 on the side of the semiconductor layer 4 is completely etched away, and a side region of the oxide semiconductor layer 4 is exposed to form a transparent first via 51 corresponding to the oxide semiconductor layer 4.
  • the etching stopper layer 5 on the other side is partially etched away, and the other side region of the oxide semiconductor layer 4 is not exposed, forming the second via hole 52 in the form of a blind via.
  • the spacing distance L4 between the first and second vias 51, 52 defines the channel length.
  • the step 3 specifically includes the following steps:
  • Step 31 as shown in FIG. 7, the photoresist layer 30 is coated on the etch stop layer 5, and the photoresist layer 30 is exposed and developed by using a gray scale mask to obtain corresponding oxide semiconductors respectively.
  • the fully exposed region 301 above the layer 4 side and the half exposed region 302 above the other side of the oxide semiconductor layer 4 are provided.
  • Step 32 as shown in FIG. 8, the etch stop layer 5 is etched by using the photoresist layer 30 as a shielding layer, and the etch stop layer 5 corresponding to the under-exposed area 301 is completely etched away.
  • the first through via 51 is etched away from the etch stop layer 5 located under the half-exposure region 302 to form a second via 52 in the form of a blind via.
  • Step 33 as shown in FIG. 9, the photoresist layer 30 is peeled off.
  • Step 4 as shown in FIG. 10, depositing a second metal layer on the etch stop layer 5, and patterning the second metal layer to obtain a drain electrode 6; A via 51 is in contact with the oxide semiconductor layer 4.
  • Step 5 depositing a passivation protective layer 7 on the drain 6 and the etch barrier layer 5, and patterning the passivation protective layer 7 to form a second form in the form of the blind via
  • the through hole 72 penetrates through the through hole 52, and at the same time, the second through hole 52 in the form of the blind hole is completely excavated to form a transparent second through hole 52, and the channel length is kept constant.
  • Step 6 depositing and patterning an electrode layer 8 on the passivation protective layer 7, one side of the electrode layer 8 being relatively close to the drain electrode 6 and passing through the through hole 72 and The two via holes 52 contact the oxide semiconductor layer 4 to constitute a source electrode 81; the other side of the electrode layer 8 extends in a direction away from the drain electrode 6, thereby constituting the pixel electrode 82.
  • the material of the electrode layer 8 is ITO.
  • FIG. 12 illustrates that the source 81 and the drain 6 do not overlap in the space above the gate 2, of course, the source 81 and the drain 6 are also limited by process precision. There may be overlaps in the space above the gate 2 as shown in FIG.
  • the etching barrier layer 5 is first patterned by using a gray-scale mask to obtain a first via 51 and a second via 52 in the form of a blind via, through the first and the first
  • the spacing distance L4 between the two vias 51, 52 defines the channel length, and the drain 6 is formed, and then the passivation protective layer 7 is deposited and patterned while the second via 52 in the form of the blind via is completely dug.
  • Opening, keeping the channel length constant, and finally forming an electrode layer simultaneously serving as the source electrode 81 and the pixel electrode 82, can reduce the channel length, improve the conductivity of the TFT, and reduce the size of the TFT, thereby improving the pixel aperture ratio. Reduce the difficulty of pixel design.
  • the ESL type TFT substrate structure of the present invention has the same electrode layer as both a source and a pixel electrode, and the drain and the source are respectively located in different layers, so that the channel length of the TFT is small,
  • the aspect can make the TFT have good electrical conductivity, on the one hand, the TFT can be made small in size, thereby improving the pixel aperture ratio and reducing the pixel design difficulty.
  • the etching barrier layer is first patterned by using a gray scale mask to obtain a first via hole and a second via hole in the form of a blind via, through the first and second
  • the spacing distance between the vias defines the channel length
  • the drain is formed
  • the passivation protective layer is deposited and patterned while the second via in the form of the blind via is completely diced to keep the channel length constant.
  • an electrode layer simultaneously serving as a source and a pixel electrode can be formed, which can reduce the channel length, improve the conductivity of the TFT, and reduce the size of the TFT, thereby improving the pixel aperture ratio and reducing the pixel design difficulty.

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Abstract

一种ESL型TFT基板结构及其制作方法。该ESL型TFT基板结构中，蚀刻阻挡层（5）对应氧化物半导体层（4）的两侧分别设有第一过孔（51）与第二过孔（52）；漏极（6）经由第一过孔（51）接触氧化物半导体层（4）；钝化保护层（7）设有与第二过孔（52）贯通的通孔（72）；电极层（8）设于钝化保护层（7）上，其一侧相对靠近漏极（6）并经由通孔（72）与第二过孔（52）接触氧化物半导体层（4），构成源极（81），另一侧沿相对远离漏极（6）的方向延伸，构成像素电极（82）。该ESL型TFT基板结构具有较小的沟道长度，一方面使得TFT具有良好的导电能力，一方面使TFT尺寸较小，从而可以提高像素开口率，降低像素设计难度。

Description

ESL型TFT基板结构及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种ESL型TFT基板结构及其制作方法。
背景技术
在显示技术领域，液晶显示器(Liquid Crystal Display，LCD)与有机发光二极管显示器(Organic Light Emitting Diode，OLED)等平板显示器已经逐步取代CRT显示器，广泛的应用于液晶电视、手机、个人数字助理、数字相机、计算机屏幕或笔记本电脑屏幕等。
显示面板是LCD、OLED的重要组成部分。不论是LCD的显示面板，还是OLED的显示面板，通常都具有一薄膜晶体管(Thin Film Transistor，TFT)基板。以LCD的显示面板为例，其主要是由一TFT基板、一彩色滤光片基板(Color Filter，CF)、以及配置于两基板间的液晶层(Liquid Crystal Layer)所构成，其工作原理是通过在TFT基板与CF基板上施加驱动电压来控制液晶层中液晶分子的旋转，将背光模组的光线折射出来产生画面。
目前，现有的TFT基板主要有：共平面(Coplanar)型、具有蚀刻阻挡层(Etch Stop Layer，ESL)型、背沟道蚀刻(Back Channel Etch，BCE)型等多种类型。
请参阅图1，现有的ESL型TFT基板包括基板10、依次设于基板10上的栅极20、栅极绝缘层30、氧化物半导体层40、蚀刻阻挡层50、源极61、漏极62、钝化保护层70、及像素电极80。
图1所示的ESL型TFT基板采用蚀刻阻挡层ESL来避免背沟道损伤，但由于制程精度存在偏差(如曝光制程的对位偏差，蚀刻制程的线宽偏差等)，源极61与漏极62必须与蚀刻阻挡层50存在一定的重叠长度L1和L3，加上在现有的制程能力下源极61与漏极62之间的最小狭缝长度L2，实际的沟道长度L为L1、L2、L3之和，即L＝L1+L2+L3，大于同样设计的BCE型TFT基板内背沟道的长度，BCE型TFT基板内背沟道的长度即为源极与漏极之间的最小狭缝长度L2。
较大的沟道长度L，一方面容易造成TFT的导电性能下降，另一方面使TFT尺寸增大，从而造成像素的开口率下降，增加了像素设计的难度。
发明内容
本发明的目的在于提供一种ESL型TFT基板结构，其具有较小的沟道长度，一方面使得TFT具有良好的导电能力，一方面使TFT尺寸较小，从而可以提高像素开口率，降低像素设计难度。
本发明的目的还在于提供一种ESL型TFT基板的制作方法，能够减小沟道长度，提高TFT的导电能力，同时减小TFT尺寸，从而可以提高像素开口率，降低像素设计难度。
为实现上述目的，本发明提供一种ESL型TFT基板结构，包括：
基板；
设于所述基板上的栅极；
设于所述栅极及基板上的栅极绝缘层；
位于所述栅极上方设于所述栅极绝缘层上的氧化物半导体层；
设于所述氧化物半导体层上的蚀刻阻挡层，所述蚀刻阻挡层对应所述氧化物半导体层的两侧分别设有第一过孔、与第二过孔；
设于所述蚀刻阻挡层上经由第一过孔接触氧化物半导体层的漏极；
设于所述漏极与蚀刻阻挡层上的钝化保护层，所述钝化保护层设有与第二过孔贯通的通孔；
设于所述钝化保护层上的电极层；所述电极层的一侧相对靠近所述漏极并经由所述通孔与第二过孔接触氧化物半导体层，构成源极；所述电极层的另一侧沿相对远离所述漏极的方向延伸，构成像素电极。
所述源极与所述漏极在所述栅极上方的空间内无交叠。
所述源极与所述漏极在所述栅极上方的空间内有交叠。
所述氧化物半导体层的材料为铟镓锌氧化物。
所述电极层的材料为氧化铟锡。
本发明还提供一种ESL型TFT基板结构，包括：
基板；
设于所述基板上的栅极；
设于所述栅极及基板上的栅极绝缘层；
位于所述栅极上方设于所述栅极绝缘层上的氧化物半导体层；
设于所述氧化物半导体层上的蚀刻阻挡层，所述蚀刻阻挡层对应所述氧化物半导体层的两侧分别设有第一过孔、与第二过孔；
设于所述蚀刻阻挡层上经由第一过孔接触氧化物半导体层的漏极；
设于所述漏极与蚀刻阻挡层上的钝化保护层，所述钝化保护层设有与第二过孔贯通的通孔；及
设于所述钝化保护层上的电极层；所述电极层的一侧相对靠近所述漏极并经由所述通孔与第二过孔接触氧化物半导体层，构成源极；所述电极层的另一侧沿相对远离所述漏极的方向延伸，构成像素电极；
其中，所述源极与所述漏极在所述栅极上方的空间内无交叠；
其中，所述氧化物半导体层的材料为铟镓锌氧化物；
其中，所述电极层的材料为氧化铟锡。
本发明还提供一种ESL型TFT基板的制作方法，包括以下步骤：
步骤1、提供一基板，在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，得到栅极；
步骤2、在所述栅极及基板上沉积栅极绝缘层；在所述栅极绝缘层上沉积并图案化氧化物半导体层；
步骤3、在所述氧化物半导体层上沉积蚀刻阻挡层，并采用灰阶光罩对所述蚀刻阻挡层进行图案化处理，将对应于所述氧化物半导体层一侧上方的蚀刻阻挡层完全蚀刻掉，暴露出所述氧化物半导体层的一侧区域，形成通透的第一过孔，将对应于所述氧化物半导体层另一侧上方的蚀刻阻挡层部分蚀刻掉，不暴露出所述氧化物半导体层的另一侧区域，形成盲孔形式的第二过孔；
所述第一、第二过孔之间的间隔距离定义出沟道长度；
步骤4、在所述蚀刻阻挡层上沉积第二金属层，并对所述第二金属层进行图案化处理，得到漏极；所述漏极经由所述第一过孔与所述氧化物半导体层相接触；
步骤5、在所述漏极与蚀刻阻挡层上沉积钝化保护层，并对钝化保护层进行图案化处理，形成与所述盲孔形式的第二过孔贯通的通孔，同时将所述盲孔形式的第二过孔完全挖开，形成通透的第二过孔，保持沟道长度不变；
步骤6、在所述钝化保护层上沉积并图案化电极层，所述电极层的一侧相对靠近所述漏极并经由所述通孔与第二过孔接触氧化物半导体层，构成源极；所述电极层的另一侧沿相对远离所述漏极的方向延伸，构成像素电极。
所述步骤3具体包括以下步骤：
步骤31、在所述蚀刻阻挡层上涂布光阻层，采用灰阶光罩对所述光阻层进行曝光、显影，分别得到对应位于所述氧化物半导体层一侧上方的全曝光区域，及对应位于所述氧化物半导体层另一侧上方的半曝光区域；
步骤32、以所述光阻层为遮蔽层，对所述蚀刻阻挡层进行蚀刻，将对 应位于所述全曝光区域下方的蚀刻阻挡层完全蚀刻掉，得到通透的第一过孔，将对应位于所述半曝光区域下方的蚀刻阻挡层部分蚀刻掉，形成盲孔形式的第二过孔；
步骤33、剥离所述光阻层。
所述步骤32中，所述蚀刻采用干法蚀刻工艺。
所述源极与所述漏极在所述栅极上方的空间内无交叠。
所述源极与所述漏极在所述栅极上方的空间内有交叠。
本发明的有益效果：本发明提供的一种ESL型TFT基板结构，设置同一电极层既作为源极，又作为像素电极，且漏极与源极分别位于不同层别，使得TFT的沟道长度较小，一方面能够使TFT具有良好的导电能力，一方面能够使TFT尺寸较小，从而可以提高像素开口率，降低像素设计难度。本发明提供的一种ESL型TFT基板的制作方法，先采用灰阶光罩对蚀刻阻挡层进行图案化处理，得到通透的第一过孔与盲孔形式的第二过孔，通过第一、第二过孔之间的间隔距离定义出沟道长度，再形成漏极，然后沉积并图案化钝化保护层，同时将所述盲孔形式的第二过孔完全挖开，保持沟道长度不变，最后形成同时作为源极与像素电极的电极层，能够减小沟道长度，提高TFT的导电能力，同时减小TFT尺寸，从而可以提高像素开口率，降低像素设计难度。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为现有的ESL型TFT基板的剖面结构示意图；
图2为本发明ESL型TFT基板结构的第一实施例的剖面示意图；
图3为本发明ESL型TFT基板结构的第二实施例的剖面示意图；
图4为本发明ESL型TFT基板的制作方法的流程图；
图5为本发明ESL型TFT基板的制作方法的步骤1的示意图；
图6为本发明ESL型TFT基板的制作方法的步骤2的示意图；
图7至图9为本发明ESL型TFT基板的制作方法的步骤3的示意图；
图10为本发明ESL型TFT基板的制作方法的步骤4的示意图；
图11为本发明ESL型TFT基板的制作方法的步骤5的示意图；
图12为本发明ESL型TFT基板的制作方法的步骤6的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
本发明首先提供一种ESL型TFT基板结构。图2所示为本发明ESL型TFT基板结构第一实施例的示意图，该ESL型TFT基板结构包括：
基板1；
设于所述基板1上的栅极2；
设于所述栅极2及基板1上的栅极绝缘层3；
位于所述栅极2上方设于所述栅极绝缘层2上的氧化物半导体层4；
设于所述氧化物半导体层4上的蚀刻阻挡层5，所述蚀刻阻挡层5对应所述氧化物半导体层4的两侧分别设有第一过孔51、与第二过孔52；所述第一、第二过孔51、52之间的间隔距离L4定义出了沟道长度；
设于所述蚀刻阻挡层ESL上经由第一过孔51接触氧化物半导体层4的漏极6；
设于所述漏极6与蚀刻阻挡层5上的钝化保护层7，所述钝化保护层7设有与第二过孔52贯通的通孔72；
设于所述钝化保护层7上的电极层8；所述电极层8的一侧相对靠近所述漏极6并经由所述通孔72与第二过孔52接触氧化物半导体层4，构成源极81；所述电极层8的另一侧沿相对远离所述漏极6的方向延伸，构成像素电极82。
具体地，所述氧化物半导体层4的材料为铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)。所述电极层8的材料为氧化铟锡(Indium Tin Oxide，ITO)。
值得一提的是，在图2所示的第一实施例中，所述源极81与所述漏极6在所述栅极2上方的空间内无交叠。
图3所示为本发明ESL型TFT基板结构第二实施例的示意图，该第二实施例与第一实施例的区别在于，所述源极81与所述漏极6在所述栅极2上方的空间内有交叠，相应对所述电极层8的制程精度要求相对较低一些。其余均与第一实施例相同，此处不再赘述。
本发明的ESL型TFT基板结构，设置同一电极层8既作为源极81，又作为像素电极82，且漏极6与源极81分别位于不同层别，使得TFT的沟 道长度为所述第一、第二过孔51、52之间的间隔距离L4，小于现有的ESL型TFT基板的沟道长度，一方面能够使TFT具有良好的导电能力，一方面能够使TFT尺寸较小，从而可以提高像素开口率，降低像素设计难度。
请参阅图4，本发明还提供一种ESL型TFT基板的制作方法，包括以下步骤：
步骤1、如图5所示，提供一基板1，在所述基板1上沉积第一金属层，并对所述第一金属层进行图案化处理，得到栅极2。
步骤2、如图6所示，在所述栅极2及基板1上沉积栅极绝缘层3；在所述栅极绝缘层3上沉积并图案化氧化物半导体层4。
具体地，所述氧化物半导体层4的材料为IGZO。
步骤3、如图7至9所示，在所述氧化物半导体层4上沉积蚀刻阻挡层5，并采用灰阶光罩对所述蚀刻阻挡层5进行图案化处理，将对应于所述氧化物半导体层4一侧上方的蚀刻阻挡层5完全蚀刻掉，暴露出所述氧化物半导体层4的一侧区域，形成通透的第一过孔51，将对应于所述氧化物半导体层4另一侧上方的蚀刻阻挡层5部分蚀刻掉，不暴露出所述氧化物半导体层4的另一侧区域，形成盲孔形式的第二过孔52。所述第一、第二过孔51、52之间的间隔距离L4定义出沟道长度。
具体地，该步骤3具体包括以下步骤：
步骤31、如图7所示，在所述蚀刻阻挡层5上涂布光阻层30，采用灰阶光罩对所述光阻层30进行曝光、显影，分别得到对应位于所述氧化物半导体层4一侧上方的全曝光区域301，及对应位于所述氧化物半导体层4另一侧上方的半曝光区域302。
步骤32、如图8所示，以所述光阻层30为遮蔽层，对所述蚀刻阻挡层5进行蚀刻，将对应位于所述全曝光区域301下方的蚀刻阻挡层5完全蚀刻掉，得到通透的第一过孔51，将对应位于所述半曝光区域302下方的蚀刻阻挡层5部分蚀刻掉，形成盲孔形式的第二过孔52。
步骤33、如图9所示，剥离所述光阻层30。
步骤4、如图10所示，在所述蚀刻阻挡层5上沉积第二金属层，并对所述第二金属层进行图案化处理，得到漏极6；所述漏极6经由所述第一过孔51与所述氧化物半导体层4相接触。
步骤5、如图11所示，在所述漏极6与蚀刻阻挡层5上沉积钝化保护层7，并对钝化保护层7进行图案化处理，形成与所述盲孔形式的第二过孔52贯通的通孔72，同时将所述盲孔形式的第二过孔52完全挖开，形成通透的第二过孔52，保持沟道长度不变。
步骤6、如图12所示，在所述钝化保护层7上沉积并图案化电极层8，所述电极层8的一侧相对靠近所述漏极6并经由所述通孔72与第二过孔52接触氧化物半导体层4，构成源极81；所述电极层8的另一侧沿相对远离所述漏极6的方向延伸，构成像素电极82。
具体地，所述电极层8的材料为ITO。
图12示意出了所述源极81与所述漏极6在所述栅极2上方的空间内无交叠，当然，受制程精度的限制，所述源极81与所述漏极6也可如图3所示那样在所述栅极2上方的空间内有交叠。
上述ESL型TFT基板的制作方法，先采用灰阶光罩对蚀刻阻挡层5进行图案化处理，得到通透的第一过孔51与盲孔形式的第二过孔52，通过第一、第二过孔51、52之间的间隔距离L4定义出沟道长度，再形成漏极6，然后沉积并图案化钝化保护层7，同时将所述盲孔形式的第二过孔52完全挖开，保持沟道长度不变，最后形成同时作为源极81与像素电极82的电极层，能够减小沟道长度，提高TFT的导电能力，同时减小TFT尺寸，从而可以提高像素开口率，降低像素设计难度。
综上所述，本发明的ESL型TFT基板结构，设置同一电极层既作为源极，又作为像素电极，且漏极与源极分别位于不同层别，使得TFT的沟道长度较小，一方面能够使TFT具有良好的导电能力，一方面能够使TFT尺寸较小，从而可以提高像素开口率，降低像素设计难度。本发明的ESL型TFT基板的制作方法，先采用灰阶光罩对蚀刻阻挡层进行图案化处理，得到通透的第一过孔与盲孔形式的第二过孔，通过第一、第二过孔之间的间隔距离定义出沟道长度，再形成漏极，然后沉积并图案化钝化保护层，同时将所述盲孔形式的第二过孔完全挖开，保持沟道长度不变，最后形成同时作为源极与像素电极的电极层，能够减小沟道长度，提高TFT的导电能力，同时减小TFT尺寸，从而可以提高像素开口率，降低像素设计难度。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (11)

  1. 一种ESL型TFT基板结构，包括：
    基板；
    设于所述基板上的栅极；
    设于所述栅极及基板上的栅极绝缘层；
    位于所述栅极上方设于所述栅极绝缘层上的氧化物半导体层；
    设于所述氧化物半导体层上的蚀刻阻挡层，所述蚀刻阻挡层对应所述氧化物半导体层的两侧分别设有第一过孔、与第二过孔；
    设于所述蚀刻阻挡层上经由第一过孔接触氧化物半导体层的漏极；
    设于所述漏极与蚀刻阻挡层上的钝化保护层，所述钝化保护层设有与第二过孔贯通的通孔；及
    设于所述钝化保护层上的电极层；所述电极层的一侧相对靠近所述漏极并经由所述通孔与第二过孔接触氧化物半导体层，构成源极；所述电极层的另一侧沿相对远离所述漏极的方向延伸，构成像素电极。
  2. 如权利要求1所述的ESL型TFT基板结构，其中，所述源极与所述漏极在所述栅极上方的空间内无交叠。
  3. 如权利要求1所述的ESL型TFT基板结构，其中，所述源极与所述漏极在所述栅极上方的空间内有交叠。
  4. 如权利要求1所述的ESL型TFT基板结构，其中，所述氧化物半导体层的材料为铟镓锌氧化物。
  5. 如权利要求1所述的ESL型TFT基板结构，其中，所述电极层的材料为氧化铟锡。
  6. 一种ESL型TFT基板结构，包括：
    基板；
    设于所述基板上的栅极；
    设于所述栅极及基板上的栅极绝缘层；
    位于所述栅极上方设于所述栅极绝缘层上的氧化物半导体层；
    设于所述氧化物半导体层上的蚀刻阻挡层，所述蚀刻阻挡层对应所述氧化物半导体层的两侧分别设有第一过孔、与第二过孔；
    设于所述蚀刻阻挡层上经由第一过孔接触氧化物半导体层的漏极；
    设于所述漏极与蚀刻阻挡层上的钝化保护层，所述钝化保护层设有与第二过孔贯通的通孔；及
    设于所述钝化保护层上的电极层；所述电极层的一侧相对靠近所述漏极并经由所述通孔与第二过孔接触氧化物半导体层，构成源极；所述电极层的另一侧沿相对远离所述漏极的方向延伸，构成像素电极；
    其中，所述源极与所述漏极在所述栅极上方的空间内无交叠；
    其中，所述氧化物半导体层的材料为铟镓锌氧化物；
    其中，所述电极层的材料为氧化铟锡。
  7. 一种ESL型TFT基板的制作方法，包括以下步骤：
    步骤1、提供一基板，在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，得到栅极；
    步骤2、在所述栅极及基板上沉积栅极绝缘层；在所述栅极绝缘层上沉积并图案化氧化物半导体层；
    步骤3、在所述氧化物半导体层上沉积蚀刻阻挡层，并采用灰阶光罩对所述蚀刻阻挡层进行图案化处理，将对应于所述氧化物半导体层一侧上方的蚀刻阻挡层完全蚀刻掉，暴露出所述氧化物半导体层的一侧区域，形成通透的第一过孔，将对应于所述氧化物半导体层另一侧上方的蚀刻阻挡层部分蚀刻掉，不暴露出所述氧化物半导体层的另一侧区域，形成盲孔形式的第二过孔；
    所述第一、第二过孔之间的间隔距离定义出沟道长度；
    步骤4、在所述蚀刻阻挡层上沉积第二金属层，并对所述第二金属层进行图案化处理，得到漏极；所述漏极经由所述第一过孔与所述氧化物半导体层相接触；
    步骤5、在所述漏极与蚀刻阻挡层上沉积钝化保护层，并对钝化保护层进行图案化处理，形成与所述盲孔形式的第二过孔贯通的通孔，同时将所述盲孔形式的第二过孔完全挖开，形成通透的第二过孔，保持沟道长度不变；
    步骤6、在所述钝化保护层上沉积并图案化电极层，所述电极层的一侧相对靠近所述漏极并经由所述通孔与第二过孔接触氧化物半导体层，构成源极；所述电极层的另一侧沿相对远离所述漏极的方向延伸，构成像素电极。
  8. 如权利要求7所述的ESL型TFT基板的制作方法，其中，所述步骤3具体包括以下步骤：
    步骤31、在所述蚀刻阻挡层上涂布光阻层，采用灰阶光罩对所述光阻层进行曝光、显影，分别得到对应位于所述氧化物半导体层一侧上方的全曝光区域，及对应位于所述氧化物半导体层另一侧上方的半曝光区域；
    步骤32、以所述光阻层为遮蔽层，对所述蚀刻阻挡层进行蚀刻，将对应位于所述全曝光区域下方的蚀刻阻挡层完全蚀刻掉，得到通透的第一过孔，将对应位于所述半曝光区域下方的蚀刻阻挡层部分蚀刻掉，形成盲孔形式的第二过孔；
    步骤33、剥离所述光阻层。
  9. 如权利要求8所述的ESL型TFT基板的制作方法，其中，所述步骤32中，所述蚀刻采用干法蚀刻工艺。
  10. 如权利要求7所述的ESL型TFT基板的制作方法，其中，所述源极与所述漏极在所述栅极上方的空间内无交叠。
  11. 如权利要求7所述的ESL型TFT基板的制作方法，其中，所述源极与所述漏极在所述栅极上方的空间内有交叠。
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