WO2016170724A1

WO2016170724A1 - Solid state relay

Info

Publication number: WO2016170724A1
Application number: PCT/JP2016/001439
Authority: WO
Inventors: Yu BUNGI; Yasushi KONISHI; Takuya Sunada
Original assignee: Panasonic Intellectual Property Management Co., Ltd.
Priority date: 2015-04-21
Filing date: 2016-03-14
Publication date: 2016-10-27
Also published as: JP2016208235A

Abstract

A solid state relay includes an input terminal, an input circuit for generating an output signal in response to an input signal input to the input terminal, a pair of output terminals, a semiconductor switch electrically coupled between the pair of output terminals and including a gate, and a charge-discharge circuit for charging and discharging a gate capacitance of the gate of the semiconductor switch. The semiconductor switch is configured to be turned on and off in response to the output signal, the semiconductor switch including a gate. The charge-discharge circuit includes a semiconductor element made of a depression-mode MOSFET electrically connected to the gate of the semiconductor switch and an impedance element electrically connected to the semiconductor element between a gate and a source of the semiconductor element. This solid state relay reduces a time for switching.

Description

SOLID STATE RELAY

The present invention relates to, in general, a solid state relay, and more particularly, relates to a solid state relay that electrically insulates an input from an output.

PTL 1 discloses a conventional solid state relay that electrically insulates an input from an output. This solid state relay includes an oscillator circuit that oscillates in response to an input signal, an inductor that converts the input signal into an electromagnetic signal, and a rectifier circuit that rectifies an output signal from the inductor. This solid state relay further includes a charge-discharge circuit that charges and discharges the rectifier signal, and an output Metal Oxide Semiconductor Field Effect Transistor (MOSFET) that is switched by the charge-discharge circuit. A potential difference between both ports of the charge-discharge circuit is applied to a gate and a source of the output MOSFET. The MOSFET is turned on and off in response to the potential difference between both ports of the charge-discharge circuit.

Japanese Patent Laid-Open Publication No. 2007-124518

FIG. 1 is a schematic circuit diagram of a solid state relay in accordance with Exemplary Embodiment 1. FIG. 2 illustrates an operation of the solid state relay in accordance with Embodiment 1. FIG. 3A shows an impedance element of the solid state relay in accordance with Embodiment 1. FIG. 3B shows another impedance element of the solid state relay in accordance with Embodiment 1. FIG. 3C shows still another impedance element of the solid state relay in accordance with Embodiment 1. FIG. 4 is a schematic circuit diagram of a comparative example of a solid state relay. FIG. 5 illustrates an operation of the comparative example of the solid state relay. FIG. 6 is a schematic circuit diagram of another solid state relay in accordance with Embodiment 1. FIG. 7 is a schematic circuit diagram of still another solid state relay in accordance with Embodiment 1. FIG. 8 is a schematic circuit diagram of a solid state relay in accordance with Exemplary Embodiment 2. FIG. 9 is a schematic circuit diagram of another solid state relay in accordance with Embodiment 2. FIG. 10 is a schematic circuit diagram of a solid state relay in accordance with Exemplary Embodiment 3. FIG. 11 is a schematic circuit diagram of another solid state relay in accordance with Embodiment 3.

Embodiment 1

FIG. 1 is a schematic circuit diagram of solid state relay 100 in accordance with Exemplary Embodiment 1. Solid state relay 100 includes input terminals T11 and T12, input circuit 1, a pair of output terminals T21 and T22, output circuit 4, and charge-discharge circuit 5. Input circuit 1 is electrically connected between input terminals T11 and T12, and generates an output signal in response to an input signal input to input terminals T11 and T12. Output circuit 4 includes semiconductor switches 41 and 42 that turn on and off between a pair of output terminals T21 and T22, i.e. the electrically connects and disconnects between terminals T21 and T22, in response to the output signal. Charge-discharge circuit 5 is electrically connected to output circuit 4, and charges and discharges gate capacitances of

gates

41G and 42G of semiconductor switches 41 and 42.
Charge-discharge circuit 5 includes semiconductor element 51 and impedance element 52. Semiconductor element 51 is made of a depression mode MOSFET electrically connected to

gates

41G and 42G of semiconductor switches 41 and 42. Impedance element 52 is electrically connected between gate 51G and source 51S of semiconductor element 51, and has one end 52A electrically connected to source 51S at node P21, and has another end 52B electrically connected to gate 51G of semiconductor element 51, thereby providing impedance between ends 52A and 52B.
<Structure>
Solid state relay 100 in accordance with Embodiment 1 will be detailed below. Solid state relay 100 is a contactless relay which does not include a movable contact of, e.g. a mechanical relay. Solid state relay 100 can be used in a variety of applications, such as controlling a security device, amusement device, medical device, storage battery system, heater, and DC motor.
As shown in FIG. 1, solid state relay 100 includes input circuit 1, output circuit 4, and charge-discharge circuit 5. FIG. 1 shows primary side region A1, secondary side region A2, and capacitor region A3. These regions will be detailed later.
Input circuit 1 includes oscillator circuit 2 and booster circuit 3. Input ports A11 and A12 of input circuit 1 are electrically connected to a pair of input terminals T11 and T12, respectively. Output ports A21 and A22 are electrically connected to a pair of output terminals T21 and T22, respectively.
Input terminals T11 and T12 are electrically connected to, for instance, a microprocessor which outputs an electric signal to input terminals T11 and T12 as the input signal. The pair of output terminals T21 and T22 are electrically connected to load 98 and power source 99 that supplies electric power to load 98.
Oscillator circuit 2 is implemented by, e.g. an RC oscillator, and starts oscillating upon having a voltage applied between input terminals T11 and T12. Upon starting oscillation, oscillator circuit 2 generates a pulse wave. When the voltage is not applied between input terminals T11 and T12 (i.e. no input signal), the oscillation stops, so that oscillator circuit 2 halts the generation of the pulse wave.
FIG. 2 illustrates an operation of solid state relay 100, and shows signals of the relay. Oscillator circuit 2 includes a NOT gate, and outputs oscillation signal S1 with a pulse wave obtained not through the NOT gate and oscillation signal S2 of pulse wave obtained through the NOT gate. Signals S1 and S2 have phases opposite to each other.
Booster circuit 3 includes plural (two in accordance with Embodiment 1)

capacitors

31 and 32 and plural (three in accordance with Embodiment 1)

diodes

33, 34, 35. Booster circuit 3 is so-called a charging pump circuit. Electrode 31A of capacitor 31 is electrically connected to high-voltage side output port 2A of oscillator circuit 2 while electrode 31B of capacitor 31 is electrically connected to anode 33A of diode 33. Electrode 32A of capacitor 32 is electrically connected to low-voltage side output port 2B of oscillator circuit 2. Electrode 32B of capacitor 32 is electrically connected to cathode 34B of diode 34.
Cathode 33B of diode 33 is electrically connected to high-voltage side input port 5A of charge-discharge circuit 5. Anode 34A of diode 34 is electrically connected to low-voltage side input port 5B of charge-discharge circuit 5. Diode 35 is electrically connected to between a node at which capacitor 32 is connected to diode 34 and a node at which capacitor 31 is connected to diode 33. Electrode 32B of capacitor 32 is connected to cathode 34B of diode 34 at node P11. Electrode 31B of capacitor 31 is connected to anode 33A of diode 33 at node P1. Anode 35A of diode 35 is electrically connected to node P11 of capacitor 32 and diode 34 while cathode 35B of diode 35 is electrically connected to node P1 of capacitor 31 and diode 33.
Oscillation signal S1 from oscillator circuit 2 is input to capacitor 31 while oscillation signal S2 from oscillator circuit 2 is input to capacitor 32. Booster circuit 3 boosts voltages of oscillation signals S1 and S2 (i.e. pulse waves) supplied thereto, and then outputs the boosted signals. In other words, booster circuit 3 boosts voltages of signals in response to the input signals (oscillation signals S1 and S2), and then, outputs the boosted signals as output signals.
Electrodes 31A and 32A of

capacitors

31 and 32 are electrically connected to oscillator circuit 2, namely the circuit on the input side.

Electrodes

31B and 32B of

capacitors

31 and 32 are electrically connected to output circuit 4 and charge-discharge circuit 5, respectively, namely, the circuits on the output side. This configuration allows

capacitors

31 and 32 of booster circuit 3 to isolate electrically the input from the output of solid state relay 100 in accordance with Embodiment 1.
Output circuit 4 includes two switches, namely, semiconductor switches 41 and 42 which are enhancement and n-channel type MOSFETs. The drain of semiconductor switch 41 is electrically connected to output terminal T21 while the drain of semiconductor switch 42 is electrically connected to output terminal T22. Gate 41G of semiconductor switch 41 and gate 42G of semiconductor switch 42 are electrically connected to high-voltage side output port 105A of charge-discharge circuit 5. The source of semiconductor switch 41 and the source of semiconductor switch 42 are electrically connected to low-voltage side output port 105B of charge-discharge circuit 5. In other words, semiconductor switches 41 and 42 are electrically connected in series between the pair of output terminals T21 and T22. The switches are turned on and off in response to an output signal supplied from input circuit 1.
Charge-discharge circuit 5 is electrically connected to output circuit 4, and includes semiconductor element 51 and impedance element 52. Semiconductor element 51 is a depression mode n-channel MOSFET. The drain of semiconductor element 51 is electrically connected to high-voltage side output port 103A of booster circuit 3. Gate 51G is electrically connected to low-voltage side output port 103B of booster circuit 3. Source 51S of semiconductor element 51 is electrically connected to low-voltage side output port 103A of booster circuit 3 via impedance element 52. In other words, impedance element 52 is electrically connected between gate 51G and source 51S of semiconductor element 51. Cathode 33B of diode 33 and drain 51D of semiconductor 51 are connected to gate 41G and gate 42G of semiconductor switches 41 and 42 at node P1. End 52A of impedance element 52, source 51S of semiconductor element 51, and sources of semiconductor switches 41 and 42 are connected to one another at node P21.
FIG. 3A shows impedance element 52. Impedance element 52 may be implemented by diode 521, as shown in FIG. 3A. Anode 521A of diode 521 is electrically connected to source 51S of semiconductor element 51 while cathode 521B of diode 521 is electrically connected to gate 51G of semiconductor element 51.
FIG. 3B shows another impedance element 52. Impedance element 52 may be implemented by resistor 522, as shown in FIG. 3B. In this case, one end 522A of resistor 522 is electrically connected to source 51S of semiconductor element 51 while another end 522B of resistor 522 is electrically connected to gate 51G of semiconductor element 51.
FIG. 3C shows still another impedance element 52. Impedance element 52 may be implemented by an enhancement and n-channel type MOSFET, as shown in FIG. 3C. In this case, source 523S of semiconductor element 523 is electrically connected to gate 51G of semiconductor element 51, and drain 523D of semiconductor element 523 is electrically connected to source 51S of semiconductor element 51. Gate 523G of semiconductor element 523 is electrically connected to drain 523D. Semiconductor element 523 thus functions as a resistor.
Impedance element 52 may not necessarily be implemented by either one of diode 521, resistor 522, or semiconductor 523, but may be in another structure as long as it has an impedance. Impedance element 52 may not necessarily be implemented by a single component but may be implemented by plural components. For instance, impedance element 52 may be formed by combining plural independent components, such as diode 521, or can be formed by combining plural kinds of components, such as diode 521, resistor 522, and semiconductor element 523.
<Operation>
An operation of solid state relay 100 in accordance with Embodiment 1 will be are described below. In the description below, a potential at node P11 of capacitor 32 and diode 34 is qualified as a reference potential. In the description below, oscillation signals S1 and S2 draw pulse waves that repeat alternately voltage V1 and voltage V2 lower than voltage V1, as shown in FIG. 2 (V1>V2). In solid state relay 100 in accordance with Embodiment 1, since low-voltage side input terminal T12 is electrically connected to a circuit ground, voltage V2 is 0 (zero).
Upon having the input signal input to input terminals T11 and T12, oscillator circuit 2 outputs oscillation signals S1 and S2. Upon having oscillation signals S1 and S2 input, booster circuit 3 generates a pulse wave that repeats alternately voltage (2×V1-Vf) and voltage (V1-Vf) at node P1. Voltage Vf is a forward voltage drop of each of diodes 33 to 35. A ripple voltage of about voltage (2×V1-2×Vf) is generated at node P2. In other words, booster circuit 3 boosts an amplitude of oscillation signal S1 (oscillation signal S2) by twice, and outputs the boosted output signal.
Immediately after having the input signal input to input terminals T11 and T12, semiconductor element 51 is turned on, and exhibits a low-impedance between drain 51D and source 51S, so that the electric current supplied from booster circuit 3 flows through semiconductor element 51 and impedance element 52. Then, a voltage drop occurs in impedance element 52, so that the low impedance between drain 51D and source 51S changes to a high impedance. Semiconductor element 51 is thus turned off. As a result, the electric current supplied from booster circuit 3 flows into

gates

41G and 42G of semiconductor switches 41 and 42 of output circuit 4.
In other words, the input signal input to input terminals T11 and T12 allows charge-discharge circuit 5 to charge the gate capacitances parasitic on

gates

41G and 42G of semiconductor switches 41 and 42, and then, the high impedance between the drain and the source of each of semiconductor switches 41 and 42 changes to the low impedance. This turns on semiconductor switches 41 and 42 which have been turn off, and connects electrically between the pair of output terminals T21 and T22. The gate capacitance parasitic on gate 41G of semiconductor switch 41 includes capacitor 41G1 which is called as a gate input-capacitance, and includes capacitor 41G2 which is called as a gate output-capacitance. Capacitor 41G1 is provided between the source and gate 41G of semiconductor switch 41. Capacitor 41G2 is provided between gate 41G and the drain of semiconductor switch 41. Similarly, the gate capacitance parasitic on gate 42G of semiconductor switch 42 includes capacitor 42G1 which is called as a gate input-capacitance, and includes capacitor 42G2 which is called as a gate output-capacitance. Capacitor 42G1 is provided between the source and gate 42G of semiconductor switch 42. Capacitor 42G2 is provided between gate 42G and the drain of semiconductor switch 42.
When the input signal is not input to input terminals T11 and T12, booster circuit 3 stops outputting the electric current, so that no voltage drop occurs in impedance element 52, and semiconductor element 51 is thus turned on. Then, the high impedance between drain 51D and source 51S of semiconductor element 51 change into the low impedance, so that the gate capacitances of semiconductor switches 41 and 42 are quickly discharged through semiconductor element 51. The low impedance between the drain and the source of each of semiconductor switches 41 and 42 thus change from the low impedance into the high impedance, so that semiconductor switches 41 and 42 are turned off.
In other words, while input signals are input to input terminals T11 and T12, semiconductor switches 41 and 42 are continuously turned on, so that the pair of output terminals T21 and T22 are electrically connected together, namely, solid state relay 100 in accordance with Embodiment 1 is turned on. On the other hand, when the input signals are not input to input terminals T11 and T12, semiconductor switches 41 and 42 are turned off, namely, solid state relay 100 in accordance with Embodiment 1 is turned off.
<Comparison Example>
FIG. 4 is a schematic circuit diagram of a comparative example of solid state relay 101. As shown in FIG. 4, solid state relay 101 includes resistor 102 instead of charge-discharge circuit 5. Resistor 102 has a higher resistance (e.g. from several mega ohms to several tens of mega ohms) than semiconductor element 51.
An operation of the comparative example of solid state relay 101 will be described below. FIG. 5 illustrates an operation of solid state relay 101. Upon having an input signal to input terminals T11 and T12, booster circuit 3 outputs an electric current into the gates of semiconductor switches 41 and 42 to charge the gate capacitances thereof, thereby turning on semiconductor switches 41 and 42. As a result, the pair of output terminals T21 and T22 are electrically connected to each other. When the input signal is not input to input terminals T11 and T12, the gate capacitances of semiconductor switches 41 and 42 are discharged via resistor102, thereby turning off semiconductor switches 41 and 42.
In the comparative example of solid state relay 101, the gate capacitances of semiconductor switches 41 and 42 are discharged through resistor 102 having high impedance; however, the electric charges stored in switches 41 and 42 can be hardly discharged due to a large time constant. As a result, it takes a longer time for semiconductor switches 41 and 42 to change from the low impedance (“ON” shown in FIG. 5) to the high impedance (“OFF” shown in FIG. 5). The comparative example of solid state relay 101 which have been turned on requires a longer time to be turned off, thus requiring a longer time for switching.
<Advantage>
The conventional solid state relay disclosed in PTL 1 includes a charge-discharge circuit implemented by, e.g. a resistor. In this case, since the electric charges stored between the gate and the source of an output MOSFET (semiconductor switch) are discharged via the resistor, it takes a long time for discharging. Such a solid state relay thus needs a long time for switching.
An advantage of solid state relay 100 in accordance with Embodiment 1 over the comparative example of solid state relay 101 will be described below.
Solid state relay 100 in accordance with Embodiment 1 includes charge-discharge circuit 5 as discussed above, so that the gate capacitances of semiconductor switches 41 and 42 are discharged via semiconductor element 51 having a lower impedance than resistor 102. As a result, solid state relay 100 in accordance with Embodiment 1 needs a shorter time for semiconductor switches 41 and 42 to change from the low impedance to the high impedance than solid state relay 101. In other words, solid state relay 100 in accordance with Embodiment 1 which have been turned on needs a shorter time to be turned off than solid state relay 101, namely, solid state relay 100 can reduce the time for switching.
FIG. 6 shows a partial schematic circuit diagram of another solid state relay 100A in accordance with Embodiment 1. Solid state relay 100 shown in FIG. 1 is implemented by the charging pump circuit that includes two

capacitors

31 and 32. The charging pump circuit may include more than two capacitors. Solid state relay 100A shown in FIG. 6 includes booster circuit 6 instead of booster circuit 3. FIG. 6 is a schematic circuit diagram of booster circuit 6. Input circuit 1 includes oscillator circuit 2 and booster circuit 6.
As shown in FIG. 6, booster circuit 6 includes plural (four)

capacitors

61, 62, 63, and 64, and plural (five)

diodes

65, 66, 67, 68, and 69.

Electrodes

61A and 63A of

capacitors

61 and 63 are electrically connected to high-voltage side output port 2A of oscillator circuit 2.

Electrodes

62A and 64A of capacitors 62 and 64 are electrically connected to low-voltage side output port 2B of oscillator circuit 2.
The anode of diode 65 is electrically connected to electrode 61B of capacitor 61 while the cathode thereof is electrically connected to high-voltage side input port 5A of charge-discharge circuit 5. The anode of diode 66 is electrically connected to low-voltage side input port 5B of charge-discharge circuit 5 while the cathode thereof is electrically connected to electrode 64B of capacitor 64. The anode of diode 67 is electrically connected to electrode 64B of capacitor 64 while the cathode thereof is electrically connected to electrode 63B of capacitor 63. The anode of diode 68 is electrically connected to electrode 63B of capacitor 63 while the cathode thereof is electrically connected to electrode 62B of capacitor 62. The anode of diode 69 is electrically connected to electrode 62B of capacitor 62 while the cathode thereof is electrically connected to electrode 61B of capacitor 61.
Oscillator circuit 2 supplies oscillation signal S1 to

capacitors

61 and 63, and supplies oscillation signal S2 to capacitors 62 and 64. Booster circuit 6 boosts voltages of these input signals by about four times, and outputs the boosted voltages.
The structures of output circuit 4 and charge-discharge circuit 5 are simply examples, so that the structures can be modified. FIG. 7 is a schematic diagram of still another solid state relay 100B in accordance with Embodiment 1. In FIG. 7, components identical to those of solid state relay 100 shown in FIG. 1 are denoted by the same reference numerals. Charge-discharge circuit 5 of solid state relay 100B shown in FIG. 7 includes semiconductor element 71 which is a depression mode p-channel MOSFET instead of semiconductor element 51 which is included in solid state relay 100 shown in FIG. 1 and which is formed of a depression mode n-channel MOSFET. As shown in FIG. 7, charge-discharge circuit 5 includes impedance element 52 and semiconductor element 71 of depression mode p-channel MOSFET.
Drain 71D of semiconductor element 71 is electrically connected to low-voltage side output port 103B of booster circuit 3. Gate 71G of semiconductor element 71 is electrically connected to high-voltage side output port 103A of booster circuit 3. Source 71S of semiconductor element 71 is electrically connected to high-voltage side output port 103A of booster circuit 3 via impedance element 52. In short, impedance element 52 is electrically connected between gate 71G and source 71S of semiconductor element 71. Solid state relay 100 shown in FIG. 1 and including semiconductor element 51 that is the depression-mode n-channel MOSFET is electrically connected to the low-voltage side, while solid state relay 100B including semiconductor element 71 that is the depression mode p-channel MOSFET is electrically connected to the high-voltage side.
In the above structure, upon having an input signal input to input terminals T11 and T12, semiconductor element 71 is turned off, so that the electric current supplied from booster circuit 3 flows into

gates

41G and 42G of semiconductor switches 41 and 42 of output circuit 4. In other words, upon having the input signal input to input terminals T11 and T12, charge-discharge circuit 5 charges the gate capacitances of semiconductor switches 41 and 42. When the input signal is not input to input terminals T11 and T12, semiconductor element 71 is turned on. This operation quickly charges the gate capacitances of switches 41 and 42 via semiconductor element 71. In short, this structure allows charge-discharge circuit 5 to function similar to solid state relay 100 that includes semiconductor element 51 which is the depression mode n-channel MOSFET.
The depression-mode n-channel MOSFET has a smaller size than the depression-mode p-channel MOSFET having similar performance, so that solid state relay 100 including semiconductor element 51 that is the depression-mode n-channel MOSFET can have a smaller size than solid state relay 100B including semiconductor element 71 that is the depression-mode p-channel MOSFET.
Semiconductor switches 41 and 42 of output circuit 4 may not necessarily be the enhancement MOSFETs. For instance, the structure thereof can employ Insulated Gate Bipolar Transistor (IGBT).
Solid state relay 100 in accordance with Embodiment 1 includes output circuit 4 including two semiconductor switches 41 and 42; however, output circuit 4 may have another structure, for instance, output circuit 4 may include a single semiconductor switch, or plural (three or more than three) semiconductor switches.

Embodiment 2

FIG. 8 is a schematic circuit diagram of solid state relay 200 in accordance with Exemplary Embodiment 2. In FIG. 8, components identical to those of solid state relay 100 shown in FIG. 1 in accordance with Embodiment 1 are denoted by the same reference numerals.
In solid state relay 200 in accordance with Embodiment 2, diode 34 of booster circuit 3 is used as impedance element 52 of charge-discharge circuit 5, as shown in FIG. 8. To be more specific, gate 51G of semiconductor element 51 is not connected to anode 34A of diode 34, but is connected electrically to cathode 34B of diode 34.
In other words, input circuit 1 of solid state relay 200 includes booster circuit 3 includes

plural capacitors

31 and 32 and plural diodes 33 to 35. Booster circuit 3 boosts up a signal in accordance with the input signal, and outputs the boosted signal as an output signal. In this context, “a signal in accordance with an input signal” refers to oscillation signals S1 and S2. Diode 34 out of diodes 33 to 35 functions as impedance element 52.
As discussed above, in solid state relay 200 in accordance with Embodiment 2, diode 34 out of three diodes 33 to 35 constituting booster circuit 3 also functions as impedance element 52 of charge-discharge circuit 5. As a result, solid state relay 200 has a simpler circuit structure than solid state relay 100 in accordance with Embodiment 1.
The circuit structure of charge-discharge circuit 5 is just an example, and can be modified appropriately. FIG. 9 is a schematic circuit diagram of another solid state relay 200A in accordance with Embodiment 2. In FIG. 9, components identical to those of solid state relay 100B shown in FIG. 7 in accordance with Embodiment 1 and solid state relay 200 shown in FIG. 8 are denoted by the same reference numerals. As shown in FIG. 9, semiconductor element 200A includes semiconductor element 71 that is a depression-mode p-channel MOSFET instead of semiconductor element 51 that is a depression-mode n-channel MOSFET. In solid state relay 200A, impedance element 52 is implemented by diode 33 of booster circuit 3.
As shown in FIG. 9, in solid state relay 200A, diode 33 of booster circuit 3 functions as impedance element 52 of charge-discharge circuit 5. To be more specific, gate 71G of semiconductor element 71 is not connected to cathode 33B of diode 33, but is connected electrically to anode 33A.
In solid state relay 200A, input circuit 1 includes booster circuit 3 that includes plural capacitors 31and 32 and plural diodes 33 to 35 for boosting a signal in accordance with an input signal and outputs the boosted signal as an output signal. In this context, “a signal in accordance with an input signal” refers to oscillation signals S1 and S2. Impedance element 52 is implemented by diode 33 out of diodes 33 to 35.
As discussed above, in solid state relay 200A, diode 33 out of three diodes 33 to 35 that constitute booster circuit 3 functions as impedance element 52 of charge-discharge circuit 5. As a result, solid state relay 200A allows the circuit structure of charge-discharge circuit 5 to be simpler than that of solid state relay 100B in accordance with Embodiment 1.
Solid state relay 200 (200A) in accordance with Embodiment 2 may further include another impedance element in addition to the diode functioning as impedance element 52. For instance, solid state relay 200 (200A) may further include a resistor connected in series to diode 34 (33) as the impedance element.

Embodiment 3

FIG. 10 is a schematic circuit diagram of solid state relay 300 in accordance with Exemplary Embodiment 3. In FIG. 3, components identical to those of solid state relay 100 shown in FIG. 1 in accordance with Embodiment 1 and solid state relay 200 shown in FIG. 8 in accordance with Embodiment 2 are denoted by the same reference numerals.
Solid state relay 300 in accordance with Embodiment 3 includes charge-discharge circuit 5 that further includes resistor 53 which is electrically connected between gate 51G and drain 51D of semiconductor element 51.
An operation of solid state relay 300 in accordance with Embodiment 3 will be briefly described below particularly in a difference from the operations of solid state relays 100 and 200 in accordance with

Embodiments

1 and 2. When input signals are not input to input terminals T11 and T12, semiconductor element 51 is turned on, and changes a high impedance between drain 51D and source 51S of semiconductor element 51 into a low impedance. In solid state relay 300 in accordance with Embodiment 3, since gate 51G of semiconductor element 51 is electrically connected to drain 51D via resistor 53, a rise in electric potential of a high-voltage side line raises a potential of gate 51G. That is, in solid state relay 300 in accordance with Embodiment 3, the voltage of gate 51G of semiconductor 51 tends to rise. Solid state relay 300 in accordance with Embodiment 3 thus allows the impedance between drain 51D and source 51S of semiconductor element 51 to be smaller than those of solid state relays 100 and 200 in accordance with

Embodiments

1 and 2. Solid state relay 300 thus can discharge the gate capacitances of semiconductor switches 41 and 42 more quickly than solid state relays 100 and 200 in accordance with

Embodiments

1 and 2, thereby reducing the time for switching semiconductor switches 41 and 42.
The circuit structure of charge-discharge circuit 5 discussed above is just an example and can be modified appropriately. FIG. 11 is a schematic diagram of another solid state relay 300A in accordance with Embodiment 3. In FIG. 11, components identical to those of solid state relay 300 shown in FIG. 10 and solid state relay 100B shown in FIG. 7 in accordance with Embodiment 1 are denoted by the same reference numerals. As shown in FIG. 11, solid state relay 300A includes semiconductor element 71 that is a depression-mode p-channel MOSFET instead of semiconductor element 51 that is a depression-mode n-channel MOSFET that is included in solid state relay 300 shown in FIG. 10. In solid state relay 300A, resistor 53 is electrically connected between gate 71G and drain 71D of semiconductor element 71. When semiconductor element 71 is turned on, the voltage of gate 71G tends to decrease, and the impedance between drain 71D and source 71S decreases more than solid state relays 100 and 200 in accordance with

Embodiments

1 and 2, accordingly discharging the gate capacitances of semiconductor switches 41 and 42 more quickly. As a result, solid state relay 300A needs a shorter time for switching semiconductor switches 41 and 42.
Solid state relay 300 (300A) in accordance with Embodiment 3 may allow diode 35 (33) out of plural diodes 33 to 35 of booster circuit 3 to function as impedance element 52. Solid state relay 300 (300A) may further include another impedance element in addition to the diode functioning as impedance element 52, similarly to solid state relay 200 (200A) in accordance with Embodiment 2.
Solid state relays 100, 200, and 300 (100A, 100B, 200A, and 300A) in accordance with Embodiments 1 to 3 were detailed above. The structures discussed above are just examples of the present invention, which is thus not limited to these embodiments. The structures can be modified depending on designs and so on as long as the changes follow the technical idea of the present invention.
Each of solid state relays 100, 200, and 300 (100A, 100B, 200A, and 300A) includes input circuit 1 (oscillator circuit 2 and booster circuit 3), output circuit 4, and charge-discharge circuit 5.

Circuits

1, 4, and 5 are integrated into a semiconductor chip, namely, a semiconductor integrated circuit.

Circuits

1, 4, and 5 are divided into primary side region A1, secondary side region A2, and capacitor region A3, as shown in, e.g. FIG. 1 and FIG. 6.
Primary side region A1 is located closer to input terminals T11 and T12 than capacitors 31 and 32 (or capacitors 61 to 64). Primary side region A1 refers to a region in which oscillator circuit 2 is provided. Secondary side region A2 is located closer to output terminals T21 and T22 than capacitors 31 and 32 (or capacitors 61 to 64). Secondary side region A2 refers to a region in which output circuit 4 and charge-discharge circuit 5 are provided. Output circuit 4 includes booster circuit 3 but excludes capacitors 31 and 32 (or capacitors 61 to 64). Capacitor region A3 refers to a region in which capacitors 31 and 32 (or capacitors 61 to 64) are provided.
The technique of forming primary side region A1, secondary side region A2, and capacitor region A3 in one semiconductor chip is known. For instance, this technique is publically disclosed in “10 Ω 370 V High Voltage Switches for Line Circuit Application” (IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 19, NO. 3, JUNE 1984).
This literature discloses a CMOS logic circuit (corresponding to the primary side region) and a bi-directional TRIMOS switch (corresponding to the secondary region) that are formed in one semiconductor chip having an area of 19 mm². This literature further discloses that all switches are in floating state (i.e. electrically isolated) from a control logic circuit, and that information (a signal) transmits through coupling capacitors each having one electrode made of polysilicon and another electrode made of a substrate and a metal layer, namely, the capacitors are sandwich-type capacitors. The poly-silicon of the capacitors forms an oxide film having a thickness of 500 nm, and the metal layer is electrically isolated by a silicon layer having a thickness of 1 mm from the poly-silicon.
In solid state relays 100, 200, and 300 (100A, 100B, 200A, and 300A) in accordance with Embodiments 1 to 3, primary side region A1 is electrically connected to capacitor region A3 with wirings while secondary region A2 is electrically connected to capacitor region A3 with wirings. Capacitor region A3 does not stride over any one of primary side region A1 and secondary region A2 (i.e. capacitor region A3 overlaps none of primary side region A1 and secondary side region A2 in a thickness direction of the semiconductor chip). Capacitors 31 and 32 (or capacitors 61 to 64) provided in capacitor region A3 are electrically connected to primary side region A1 and secondary side region A2 with wirings, so that these capacitors are not in floating status (i.e. they are not insulated from primary side region A1 or secondary side region A2).
In solid state relays 100, 200, and 300 (100A, 100B, 200A, and 300A) in accordance with Embodiments 1 to 3, capacitor region A3 overlaps none of primary side region A1 and secondary side region A2, so that wirings are arranged arbitrarily. In other words, these solid state relays provide engineers with a higher degree of freedom in the layout of semiconductor chips.
In the above discussion, input circuit 1, output circuit 4, and charge-discharge circuit 5 are integrated into one semiconductor chip; however, this structure is just an example, and the solid state relay may have another structure. For instance, input circuit 1 and charge-discharge circuit 5 are formed in one semiconductor chip while output circuit 4 is formed in another semiconductor chip. These two chips can be electrically connected to each other with bonding wires.

100, 100A, 100B, 200, 200A, 300, 300A solid state relay
1 input circuit
2 oscillator circuit
3,6 booster circuit
31,32 capacitor
61-64 capacitor
4 output circuit
41,42 semiconductor switch
5 charge-discharge circuit
51 semiconductor element
52 impedance element
S1 oscillation signal
S2 oscillation signal
T11,T12 input terminal
T21,T22 output terminal

Claims

A solid state relay comprising:
an input terminal;
an input circuit for generating an output signal in response to an input signal input to the input terminal;
a pair of output terminals;
a semiconductor switch electrically coupled between the pair of output terminals, the semiconductor switch being configured to be turned on and off in response to the output signal, the semiconductor switch including a gate; and
a charge-discharge circuit for charging and discharging a gate capacitance of the gate of the semiconductor switch,
wherein the charge-discharge circuit includes:
a semiconductor element made of a depression-mode MOSFET electrically connected to the gate of the semiconductor switch; and
an impedance element electrically connected to the semiconductor element between a gate and a source of the semiconductor element.
The solid state relay according to claim 1, wherein the semiconductor element is an n-channel MOSFET.
The solid state relay according to claim 1 or 2,
wherein the input circuit includes a booster circuit configured to boost a voltage of a signal in accordance with the input signal and output the boosted signal as the output signal, the booster circuit including a plurality of capacitors and a plurality of diodes, and
wherein one of the plurality of the diodes functions as the impedance element.
The solid state relay according to any one of claims 1 to 3, wherein the charge-discharge circuit further includes a resistor electrically connected between the gate and a drain of the semiconductor element.