WO2016161839A1 - 信号放大电路 - Google Patents

信号放大电路 Download PDF

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Publication number
WO2016161839A1
WO2016161839A1 PCT/CN2016/072813 CN2016072813W WO2016161839A1 WO 2016161839 A1 WO2016161839 A1 WO 2016161839A1 CN 2016072813 W CN2016072813 W CN 2016072813W WO 2016161839 A1 WO2016161839 A1 WO 2016161839A1
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WIPO (PCT)
Prior art keywords
switch
output
operational amplifier
capacitor
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2016/072813
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English (en)
French (fr)
Inventor
王雪艳
张威彦
陈强
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
Original Assignee
CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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Application filed by CSMC Technologies Fab1 Co Ltd, CSMC Technologies Fab2 Co Ltd filed Critical CSMC Technologies Fab1 Co Ltd
Priority to JP2017553082A priority Critical patent/JP6476315B2/ja
Priority to US15/565,191 priority patent/US10079577B2/en
Publication of WO2016161839A1 publication Critical patent/WO2016161839A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/38—DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers
    • H03F3/387—DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/165—A filter circuit coupled to the input of an amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45514—Indexing scheme relating to differential amplifiers the FBC comprising one or more switched capacitors, and being coupled between the LC and the IC
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45551—Indexing scheme relating to differential amplifiers the IC comprising one or more switched capacitors

Definitions

  • the present invention relates to the field of signal processing, and in particular to a signal amplifying circuit.
  • MEMS accelerometers are accelerometers fabricated using MEMS technology. They are small in size, light in weight and low in power consumption. They are widely used in vibration detection, azimuth detection, consumer applications, motion recognition and other fields.
  • Piezoresistive accelerometers are made using the piezoelectric effect of PZT (piezoelectric ceramic). When the PZT is under pressure, its resistance changes. By connecting the piezoresistive bridges, the change in resistance value is converted into a change in voltage, by detecting, amplifying and correcting, and then outputting a binary digital signal corresponding to the acceleration value.
  • the accelerometer's sensed output voltage signal is typically a few millivolts or tens of millivolts, very weak. If directly input to the analog-to-digital conversion circuit (ADC), the output dynamic range is low and the accuracy is degraded. Therefore, it must be amplified and then input to the ADC to finally obtain an accurate digital signal corresponding to the induced voltage.
  • ADC analog-to-digital conversion circuit
  • the traditional accelerometer analog front end is generally composed of an amplifying circuit and an ADC.
  • the noise that controls the harmonic frequency of the clock signal is introduced into the system, and because there are many low frequency noises (such as sound signals) in the environment, if not filtered out, Will affect the detected acceleration signal. If a filter circuit is introduced, the resistance and capacitance used by the filter capacitor cause the chip area to be too large. The sensor is always in working state during signal processing, resulting in large power consumption.
  • the front-end amplifier circuit does not remove the low-frequency 1/f noise and the input offset voltage (offset), or the snubber circuit with the large-capacitance auto-zero technology (Auto-Zero) and the related sampling technique (CDS), resulting in a large circuit area. It is not easy to integrate.
  • a signal amplifying circuit comprising:
  • a low-pass filter circuit includes a first input end, a second input end, a first switch, a second switch, a first varistor, a second varistor, a first capacitor, a second capacitor, a first output end, and a second output end, The first input end is connected to the first output end through the first switch, the first varistor, and the second input end is connected to the second output end through the second switch and the second varistor, and the first capacitor and the second capacitor are opposite in polarity Ground is respectively connected between the first output end and the second output end;
  • the buffer circuit includes a third input terminal, a fourth input terminal, a first operational amplifier, a second operational amplifier, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, and a ninth a switch, a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, a fourteenth switch, a third output end, and a fourth output end, wherein the third input end is connected to the first operation by the third switch a positive input terminal of the amplifier, the third input terminal is connected to the negative input terminal of the first operational amplifier through a fourth switch, and the positive output terminal of the first operational amplifier is connected to the third output terminal through the fifth switch, and the negative output terminal of the first operational amplifier Connecting the third output end through the sixth switch, the positive input end of the first operational amplifier is connected to the negative output end of the first operational amplifier through the seventh switch, and the negative input end of the first operational amplifier is connected to the first operational amplifier through the eighth switch a positive output terminal;
  • the switched capacitor integration circuit includes a fifth input terminal, a sixth input terminal, a third operational amplifier, a first switched capacitor module, a second switched capacitor module, a third switched capacitor module, a fourth switched capacitor module, a first capacitor module, a second capacitor module, a first chopper modulator, a second chopping modulator, a third chopping modulator, a fifth output, and a sixth output, wherein each switched capacitor module includes a capacitor and at least four switches And forming a switched capacitor structure; each capacitor module includes a tunable capacitor and at least one switch and the capacitor and the switch are connected in parallel; each chopper modulator includes at least four switches and forms a chopping modulation structure; the fifth input sequentially passes through a switching capacitor module, the first chopper modulator is connected to the positive input terminal of the third operational amplifier, and the sixth input terminal is sequentially connected to the negative input terminal of the third operational amplifier through the second switched capacitor module and the first chopper modulator; The positive input terminal of the three operational amplifiers is sequentially
  • the signal switch is configured to control the on/off of the voltage signal before the amplification, wherein the first input end and the second input end input the voltage signal before the amplification, the first output end is connected to the third input end, and the second output end is connected to the fourth output end.
  • the input end, the third output end is connected to the fifth input end, the fourth output end is connected to the sixth input end, and the fifth output end and the sixth output end output the amplified voltage signal.
  • the signal amplifying circuit can divide the working state of the circuit by controlling the opening and closing of the switch signal, the first switch and the second switch, thereby saving power consumption and achieving a low bandwidth under the same size of resistance and capacitance. Not only is the bandwidth flexible and controllable, but it also saves area and power consumption, and noise suppression is better. Selecting an adjustable resistor to increase the bandwidth adjustable range, so that the signal amplifying circuit has sufficient resolution for small signals of different ranges .
  • the first capacitor and the second capacitor are oppositely connected between the first output end and the second output end, respectively, which can effectively suppress noise introduced in the layout design.
  • FIG. 1 is a block diagram of a signal amplifying circuit of an embodiment
  • FIG. 2 is a schematic diagram showing the connection of a sensor and a low pass filter circuit according to an embodiment
  • FIG. 3 is a timing diagram of a switch control signal of a signal switch, a switch control signal of a first switch and a second switch in one cycle;
  • FIG. 4 is a schematic diagram of a buffer circuit of an embodiment
  • FIG. 5 is a timing diagram of a switch control signal and an output signal in a buffer circuit of an embodiment
  • FIG. 6 is a schematic diagram of a switched capacitor integration circuit of an embodiment
  • FIG. 7 is a timing diagram of signals in a switched capacitor integration circuit of an embodiment
  • FIG. 8 is a schematic diagram of a tunable capacitor in a first switched capacitor module or a second switched capacitor module of an embodiment
  • FIG. 9 is a schematic diagram of a tunable capacitor in a first capacitor module or a second capacitor module according to an embodiment
  • Figure 10 is a schematic illustration of a first chopper modulator of an embodiment
  • Figure 11 is a schematic diagram of a second chopper modulator or a third chopper of an embodiment.
  • all of the switches are semiconductor device switches, and are controlled by a plurality of sets of switching signals, and the switch control signals of the respective switches are respectively indicated by the symbol ⁇ .
  • 1 is a block diagram of a signal amplifying circuit of an embodiment.
  • the signal amplifying circuit includes a low pass filter circuit 100, a buffer circuit 200, a switched capacitor integrating circuit 300, a sensor 400, a signal switch S, a first connection switch S1, a second connection switch S2, and a third connection switch S3.
  • the fourth connection switch S4, FIG. 1 does not show the first connection switch S1, the second connection switch S2, the third connection switch S3, and the fourth connection switch S4.
  • FIG. 2 is a schematic diagram showing the connection of a sensor and a low pass filter circuit of an embodiment.
  • the low pass filter circuit 100 includes a first input terminal VIN1, a second input terminal VIN2, a first switch M1, a second switch M2, a first varistor RF1, a second varistor RF2, and a first capacitor C1.
  • the second capacitor C2 the first output terminal VO1 and the second output terminal VO2.
  • the first input terminal VIN1 is connected to the first output terminal VO1 through the first switch M1 and the first varistor RF1
  • the second input terminal VIN2 is connected to the second output terminal VO2 through the second switch M2 and the second varistor RF2, the first capacitor C1
  • the second capacitor C2 is opposite in polarity (the upper and lower plates are opposite) and is respectively connected between the first output terminal VO1 and the second output terminal VO2.
  • the detection and amplification signals are realized by periodic sampling of the switched capacitor.
  • the anti-aliasing filter is first used to filter the signal.
  • the detected acceleration signals will also be affected. Therefore, before detecting and amplifying the signal, the resolution of the system is improved by a low-pass filter circuit.
  • FIG. 3 is a timing diagram of a switch control signal of a signal switch, a switch control signal of a first switch and a second switch, according to an embodiment.
  • the switch control signal of the signal switch S is ⁇ m
  • the switch control signals of the first switch M1 and the second switch M2 are both ⁇ n.
  • the periodic pulse signals ⁇ m, ⁇ n respectively control the operation of the sensor 400 and the low-pass filter circuit 100, that is, the power consumption is saved, and the lower bandwidth is obtained in the case of the same size resistance and capacitance.
  • Ts is the turn-on time of the signal switch S in the period Tp, and the duty cycle (Ts/Tp) of the pulse affects the actual bandwidth. The lower the duty cycle, the smaller the resistance and capacitance values used to achieve the same bandwidth, and the smaller the area and power consumption.
  • N*Ts' Ts.
  • the rising edge of the control signal ⁇ m leads the rising edge Td of the control signal ⁇ n, and the falling edge of the control signal ⁇ m lags the falling edge Td of the control signal ⁇ n.
  • the bandwidth is determined by the ratio of the switch open time Ts to the cycle time Tp.
  • the first varistor RF1 and the second varistor RF2 use a series-parallel connection of resistors to change the resistance value and change the bandwidth of the filter.
  • the first capacitor C1 and the second capacitor C2 are two reverse-connecting capacitors of the upper and lower boards, and the capacities can be equal.
  • the output differential ends of the layout can be symmetric, which is favorable for common mode noise suppression.
  • FIG. 4 is a schematic diagram of a buffer circuit of an embodiment.
  • the buffer circuit 200 includes a third input terminal VIN3, a fourth input terminal VIN4, a first operational amplifier A1, a second operational amplifier A2, a third switch M3, a fourth switch M4, and a fifth switch M5.
  • the third input terminal VIN3 is connected to the positive input terminal of the first operational amplifier A1 through the third switch M3, and the third input terminal VIN3 is connected to the negative input terminal of the first operational amplifier A1 through the fourth switch M4.
  • the positive output of the first operational amplifier A1 The terminal is connected to the third output terminal VO3 through the fifth switch M5.
  • the negative output terminal of the first operational amplifier A1 is connected to the third output terminal VO3 through the sixth switch M6, and the positive input terminal of the first operational amplifier A1 is connected through the seventh switch M7.
  • a negative output terminal of the operational amplifier A1, the negative input terminal of the first operational amplifier A1 is connected to the positive output terminal of the first operational amplifier A1 through the eighth switch M8.
  • the fourth input terminal VIN4 is connected to the positive input terminal of the second operational amplifier A2 through the ninth switch M9, and the fourth input terminal VIN4 is connected to the negative input terminal of the second operational amplifier A2 through the tenth switch M10, and the positive output of the second operational amplifier A2
  • the terminal is connected to the fourth output terminal VO4 through the eleventh switch M11, the negative output terminal of the second operational amplifier A2 is connected to the fourth output terminal VO4 through the twelfth switch M12, and the positive input terminal of the second operational amplifier A2 passes the thirteenth switch M13 is connected to the negative output terminal of the second operational amplifier A2, and the negative input terminal of the second operational amplifier A2 is connected to the positive output terminal of the second operational amplifier A2 through the fourteenth switch M14.
  • Fig. 5 is a timing chart showing the switching control signal and the output signal in the buffer circuit of an embodiment.
  • the switch control signals of the third switch M3, the fifth switch M5, the eighth switch M8, the ninth switch M9, the eleventh switch M11, and the fourteenth switch M14 are ⁇ 1, and the fourth switch M4,
  • the switch control signals of the six switch M6, the seventh switch M7, the tenth switch M10, the twelfth switch M12 and the thirteenth switch M13 are ⁇ 2, and ⁇ 1 and ⁇ 2 are two inverted non-overlap clock signals. .
  • the two clock signals are switched between each other, and the signals are switched between the positive input terminal and the negative input terminal of the operational amplifier, which is a special case of chopping technology.
  • Vos1 and Vos2 represent the 1/f noise and offset of the low frequency of the operational amplifier.
  • the high frequency chopping clock signal modulates to the high frequency.
  • VO is the same periodic signal as the ⁇ 1 frequency.
  • the DC component of the signal is VIN, and the signal amplitude is Vos1-Vos2.
  • the post-stage amplifying circuit can remove Vos1 by integrating VOUT And Vos2 To reduce low frequency noise and improve the signal to noise ratio of the system. Since no capacitors are used, the area is greatly reduced compared to Auto-zero technology and related sampling (CDS) technology. The noise performance of the system is better because there is no noise introduced into the capacitor.
  • the amplifier itself is a low noise structure with low frequency thermal noise.
  • FIG. 6 is a schematic diagram of a switched capacitor integration circuit of an embodiment
  • FIG. 7 is a timing diagram of signals in a switched capacitor integration circuit of an embodiment.
  • the switched capacitor integration circuit 300 includes a fifth input terminal VIN5, a sixth input terminal VIN6, a third operational amplifier A3, a first switched capacitor module SC1, a second switched capacitor module SC2, and a third switch.
  • Each of the switched capacitor modules includes a capacitor and at least four control switches and forms a switched capacitor structure.
  • each of the switched capacitor modules includes a capacitor and a first control switch, a second control switch, a third control switch, and a fourth control switch, and the first plate of the capacitor is connected to the switch capacitor module through the first control switch. At the input end, the first plate of the capacitor is also grounded through the second control switch. The second plate of the capacitor is connected to the output end of the switched capacitor module through a third control switch, and the second plate of the capacitor is also grounded through the fourth control switch.
  • the capacitance capacities of the first switched capacitor module SC1 and the second switched capacitor module SC2 are both Ci, and are represented by Ci.
  • the first control switch of the first switched capacitor module SC1, the second switched capacitor module SC2, and the switch control signal of the fourth control switch are ⁇ a1, and the switch control signals of the second control switch and the third control switch are ⁇ a2.
  • ⁇ a1 and ⁇ a2 are two inverted non-overlap clock signals.
  • the capacitance capacities of the third switched capacitor module SC3 and the fourth switched capacitor module SC4 are both Cff, and are expressed by Cff.
  • the switch control signals of the first control switch and the fourth control switch of the third switched capacitor module SC3 and the fourth switched capacitor module SC4 are ⁇ b1, and the switch control signals of the second control switch and the third control switch are ⁇ b2.
  • FIG. 8 is a schematic diagram of an adjustable capacitance in a first switched capacitor module or a second switched capacitor module of an embodiment.
  • the capacitance in the first switched capacitor module SC1 and the second switched capacitor module SC2 is a tunable capacitor Ci.
  • the tunable capacitor Ci includes a plurality of capacitors (Ci0, Ci1 ... Cin) and a plurality of switches (ki0, ki1 ... kin), each capacitor (Cin) and each switch (kin) are connected in series to form a capacitive branch, all capacitors The branches are connected in parallel, and the capacitance is adjustable by introducing a capacitor through the opening and closing of the capacitor branch switch.
  • the switch of the adjustable capacitance of the first switched capacitor module SC1 (ki0, ki1 ... kin) is close to the output end of the first switched capacitor module SC1, and the switch of the adjustable capacitor of the second switched capacitor module SC2 (ki0, ki1...kin ) close to the output of the second switched capacitor module SC2.
  • the voltage across the switch affects its own resistance, so the switch must be close to the op amp input (for the first switched capacitor module SC1 is the output of the first switched capacitor module SC1, and the second switched capacitor module SC2 is The output of the second switched capacitor module SC2). Even if the input signal changes, the input of the op amp is always close to the common mode level, the voltage across the switch is not affected by the signal, and the switching characteristics are unchanged, which does not affect the amplification factor.
  • the two ends of the capacitor Ci in the first switched capacitor module SC1 are respectively connected in parallel with the capacitor CW in the third switched capacitor module SC3 through the first connection switch S1 and the second connection switch S2, and the capacitance Ci in the second switched capacitor module SC2
  • the two ends are connected in parallel with the capacitor CW in the fourth switched capacitor module SC4 through the third connection switch S3 and the fourth connection switch S4, respectively.
  • the switch control signals of the first connection switch S1, the second connection switch S2, the third connection switch S3, and the fourth connection switch S4 are ⁇ p.
  • FIG. 9 is a schematic diagram of a tunable capacitor in a first capacitor module or a second capacitor module according to an embodiment.
  • each of the capacitor modules includes a tunable capacitor Cf and a switch (represented by its control signal ⁇ r), and the tunable capacitor Cf and the switch ⁇ r are connected in parallel.
  • the tunable capacitor Cf may include a plurality of capacitors (Cf0, Cf1, ..., Cfn) and a plurality of switches (kf0, kf1, ..., kfn), each capacitor (Cfn) and each switch (kfn) being connected in series to form a capacitive branch.
  • All the capacitor branches are connected in parallel, and the capacitance is adjustable by introducing a capacitor into the opening and closing of the capacitor branch switch.
  • the switches (kf0, kf1 ... kfn) in the tunable capacitor Cf in the capacitor module are close to the input of the capacitor module (equivalent to the input of the operational amplifier).
  • Each chopper modulator (the first chopping modulator CHP1, the second chopping modulator CHP2, and the third chopping modulator CHP3) includes at least four chopping switches and forms a chopping modulation structure, in this embodiment It includes four chopping switches and forms a chopping modulation structure.
  • the chopper modulator includes a first chopping switch K1, a second chopping switch K2, a third chopping switch K3 and a fourth chopping switch K4, and the first input terminal vin1 of the chopper modulator passes through the first chopping switch K1 Connecting the first output terminal vo1 of the chopper modulator, the first input terminal vin1 of the chopper modulator is connected to the second output terminal vo2 of the chopper modulator via the second chopping switch K2, the second input terminal of the chopper modulator The vin2 is connected to the second output terminal vo2 of the chopper modulator via the third chopper switch K3, and the second input terminal vin2 of the chopper modulator is connected to the first output terminal vo1 of the chopper modulator via the fourth chopping switch K4.
  • FIG. 10 is a schematic diagram of a first chopper modulator of an embodiment
  • FIG. 11 is a schematic diagram of a second chopper modulator or a third chopper of an embodiment.
  • the switch control signals of the switches K1 and K3 of the first chopper modulator CHP1 are ⁇ ch1a
  • the switch control signals of K2 and K4 are ⁇ ch1b
  • ⁇ ch1a and ⁇ ch1b are two inverted non-overlap clock signals.
  • the switching control signals of the switches K1 and K3 of the second chopping modulator CHP2 and the third chopping modulator CHP3 are ⁇ ch2a
  • the switching control signals of K2 and K4 are ⁇ ch2b.
  • ⁇ ch2a and ⁇ ch2b are two inverted non-overlap clock signals.
  • the fifth input terminal VIN5 is sequentially connected to the positive input terminal of the third operational amplifier A3 through the first switched capacitor module SC1 and the first chopper modulator CHP1, and the sixth input terminal VIN6 sequentially passes through the second switched capacitor module SC2 and the first chopping wave.
  • the modulator CHP1 is coupled to the negative input of the third operational amplifier A3.
  • the positive input terminal of the third operational amplifier A3 is sequentially connected to the fifth output terminal VO5 through the second chopper modulator CHP2, the first capacitor module CF1, and the negative input terminal of the third operational amplifier A3 sequentially passes through the second chopper modulator CHP2.
  • the second capacitor module CF2 is connected to the sixth output terminal VO6.
  • the positive input terminal of the third operational amplifier A3 is connected to the fifth output terminal VO5 through the third switched capacitor module SC3, and the negative input terminal of the third operational amplifier A3 is connected to the sixth output terminal VO6 through the fourth switched capacitor module SC4.
  • the positive output terminal of the third operational amplifier A3 is connected to the sixth output terminal VO6 through the third chopper modulator CHP3, and the negative output terminal of the third operational amplifier A3 is connected to the fifth output terminal VO5 through the third chopper modulator CHP3.
  • Voffp and Voffn are the bias voltage at the positive input of the op amp and the bias voltage at the negative input, respectively.
  • the selection integration period should ensure that when there is no input signal, the output is zero, and the amplifier offset
  • the signal switch S is used to control the on and off of the voltage signal before amplification.
  • the first input terminal VIN1 and the second input terminal VIN2 input a voltage signal before amplification
  • the first output terminal VO1 is connected to the third input terminal VIN3
  • the second output terminal VO2 is connected to the fourth input terminal VIN4, and the third output terminal VO3 is connected to the fifth terminal.
  • the input terminal VIN5, the fourth output terminal VO4 is connected to the sixth input terminal VIN6, and the fifth output terminal VO5 and the sixth output terminal VO6 output the amplified voltage signal.
  • the sensor 400 is grounded through the signal switch S.
  • the sensor 400 is further connected to the first input terminal VIN1 and the second input terminal VIN2 of the low-pass filter circuit 100 and outputs the differential output voltage as a voltage signal before amplification by using its own resistance change.
  • the sensor 400 is an acceleration sensor composed of a Wheatstone bridge circuit using a piezoresistive element.
  • the above signal amplifying circuit can be applied to a smart digital device such as a mobile phone or a tablet computer.
  • the signal amplifying circuit can divide the working state of the circuit by controlling the opening and closing of the switch signal, the first switch and the second switch, thereby saving power consumption and achieving a low bandwidth under the same size of resistance and capacitance. Not only is the bandwidth flexible and controllable, but it also saves area and power consumption, and noise suppression is better. Selecting an adjustable resistor increases the bandwidth adjustable range, so that there is sufficient resolution for small signals of different ranges.
  • the first capacitor and the second capacitor are oppositely connected between the first output end and the second output end, respectively, which can effectively suppress noise introduced in the layout design.
  • a differential buffer circuit is formed by two operational amplifiers (a first operational amplifier and a second operational amplifier) to ensure that the post-amplification circuit samples a plurality of times without affecting the charge stored on the filter capacitor.
  • the structure of the snubber circuit can be applied to chopping, and 1/f can be removed by controlling the opening and closing of the switch in the snubber circuit. Noise and input offset voltage (offset). Moreover, the use of capacitors is avoided, the chip area is reduced, and the noise is smaller.
  • the switched capacitor integrator circuit removes the amplifier input offset voltage (offset) and reduces the 1/f noise by chopping and auto-zeroing through the closing of the switch in the control circuit.
  • the gain can be adjusted by adjusting the input-output capacitance ratio, and the noise suppression of weak signals is better.
  • the ratio of input capacitance to output capacitance increases, the amplification factor increases, is not affected by process variations, and is not affected by operating voltage and temperature. Solving different ranges requires different amplification problems and improves the resolution of weak signals.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

一种信号放大电路，包括低通滤波电路（100），该低通滤波电路（100）包括两个输入端和两个输出端，还包括两个极性相反地分别连接于两个输出端之间的电容（C1、C2）；缓冲电路（200），该缓冲电路（200）包括两个输入端、第一运算放大器（A1）、第二运算放大器（A2）、两个输出端和多个开关；开关电容积分电路（300），该开关电容积分电路（300）包括两个输入端、第三运算放大器（A3）、多个电容模块、多个斩波调制器和两个输出端；及信号开关（S），用于控制放大前的电压信号的通断。

Description

信号放大电路
【技术领域】
本发明涉及信号处理领域，特别涉及一种信号放大电路。
【背景技术】
MEMS加速度计就是使用MEMS技术制造的加速度计，具有体积小、重量轻和功耗低等优点，广泛应用于振动检测、方位检测、消费应用、动作识别等领域。
压阻式的加速度计利用PZT（压电陶瓷）的压电效应制成。当PZT受到压力时，它的电阻值发生变化。通过将压电电阻桥式连接，把电阻值的变化转化为电压的变化，通过检测、放大和修正，然后输出和加速度值对应的二进制数字信号。加速度计感应输出的电压信号一般在几个毫伏或是几十毫伏，非常微弱。如果直接输入到模数转换电路（ADC），则输出动态范围低、精度下降。因此，必须经过放大后再输入到ADC，最终得到与感应电压对应的精确的数字信号。
传统加速度计模拟前端（读出电路）一般由放大电路和ADC组成，控制时钟信号的谐波频率的噪声会引入系统，同时由于环境中存在很多低频噪声（比如声音信号），如果不滤除也会影响到检测的加速度信号。如果引入滤波电路，则滤波电容所用到的电阻和电容导致芯片面积过大。传感器在信号处理过程中，一直处于工作状态，导致功耗较大。
前端放大电路没有去除低频1/f噪声和输入偏移电压(offset)，或是采用含有大电容的自动归零技术（Auto-Zero）和相关采样技术（CDS）的缓冲电路，导致电路面积大，不容易集成。
放大电路本身的1/f 噪声和输入偏移电压（offset）同样被放大与信号相同的比例，信噪比下降，动态性能降低。放大电路固定的增益，对于传感器不同的量程，小信号分辨率不够。
【发明内容】
基于此，有必要提供一种电路面积小、功耗低、噪声抑制效果好且可变增益的信号放大电路。
一种信号放大电路，包括：
低通滤波电路，包括第一输入端、第二输入端、第一开关、第二开关、第一变阻器、第二变阻器、第一电容、第二电容，第一输出端和第二输出端，其中，第一输入端通过第一开关、第一变阻器与第一输出端连接，第二输入端通过第二开关、第二变阻器与第二输出端连接，第一电容、第二电容极性相反地分别连接于第一输出端和第二输出端之间；
缓冲电路，包括第三输入端、第四输入端、第一运算放大器、第二运算放大器、第三开关、第四开关、第五开关、第六开关、第七开关、第八开关、第九开关、第十开关、第十一开关、第十二开关、第十三开关、第十四开关、第三输出端和第四输出端，其中，第三输入端通过第三开关连接第一运算放大器的正输入端，第三输入端通过第四开关连接第一运算放大器的负输入端，第一运算放大器的正输出端通过第五开关连接第三输出端，第一运算放大器的负输出端通过第六开关连接第三输出端，第一运算放大器的正输入端通过第七开关连接第一运算放大器的负输出端，第一运算放大器的负输入端通过第八开关连接第一运算放大器的正输出端；第四输入端通过第九开关连接第二运算放大器的正输入端，第四输入端通过第十开关连接第二运算放大器的负输入端，第二运算放大器的正输出端通过第十一开关连接第四输出端，第二运算放大器的负输出端通过第十二开关连接第四输出端，第二运算放大器的正输入端通过第十三开关连接第二运算放大器的负输出端，第二运算放大器的负输入端通过第十四开关连接第二运算放大器的正输出端；
开关电容积分电路，包括第五输入端、第六输入端、第三运算放大器、第一开关电容模块、第二开关电容模块、第三开关电容模块、第四开关电容模块、第一电容模块、第二电容模块、第一斩波调制器、第二斩波调制器、第三斩波调制器、第五输出端和第六输出端，其中，每个开关电容模块包括电容和至少四个开关且形成开关电容结构；每个电容模块包括可调电容和至少一个开关且电容和开关并联连接；每个斩波调制器包括至少四个开关且形成斩波调制结构；第五输入端依次通过第一开关电容模块、第一斩波调制器连接第三运算放大器的正输入端，第六输入端依次通过第二开关电容模块、第一斩波调制器连接第三运算放大器的负输入端；第三运算放大器的正输入端依次通过第二斩波调制器、第一电容模块连接第五输出端，第三运算放大器的负输入端依次通过第二斩波调制器、第二电容模块连接第六输出端；第三运算放大器的正输入端通过第三开关电容模块连接第五输出端，第三运算放大器的负输入端通过第四开关电容模块连接第六输出端；第三运算放大器的正输出端通过第三斩波调制器连接第六输出端，第三运算放大器的负输出端通过第三斩波调制器连接第五输出端；和
信号开关，用于控制放大前的电压信号的通断，其中，第一输入端和第二输入端输入放大前的电压信号，第一输出端连接第三输入端，第二输出端连接第四输入端，第三输出端连接第五输入端，第四输出端连接第六输入端，第五输出端和第六输出端输出放大后的电压信号。
上述信号放大电路，可以通过控制开关信号、第一开关、第二开关的开闭将电路的工作状态分割，既节省了功耗又实现了在同样大小的电阻和电容情况下得到很低带宽，不仅带宽灵活可控，同时节省面积和功耗，而且噪声抑制更好。选择可调电阻加大带宽可调范围，使得信号放大电路对于不同量程的小信号也拥有足够的分辨率 。第一电容、第二电容极性相反地分别连接于第一输出端和第二输出端之间，能有效抑制版图设计中引入的噪声。
【附图说明】
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。其中：
图1是一实施例的信号放大电路的模块示意图；
图2是一实施例的传感器和低通滤波电路连接示意图；
图3是一实施例的信号开关的开关控制信号、第一开关和第二开关的开关控制信号一个周期内的时序示意图；
图4是一实施例的缓冲电路的示意图；
图5是一实施例的缓冲电路中开关控制信号和输出信号的时序示意图；
图6是一实施例的开关电容积分电路的示意图；
图7是一实施例的开关电容积分电路中各信号的时序示意图；
图8是一实施例的第一开关电容模块或第二开关电容模块中的可调电容示意图；
图9是一实施例的第一电容模块或第二电容模块中的可调电容示意图；
图10是一实施例的第一斩波调制器的示意图；
图11是一实施例的第二斩波调制器或第三斩波器的示意图；和
图12~图19为在图7中各信号控制下的开关电容积分电路的状态图。
【具体实施方式】
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的较佳实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容的理解更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在限制本发明。本文所使用的术语“和／或”包括一个或多个相关的所列项目的任意的和所有的组合。
在以下描述中，所有开关皆为半导体器件开关，并通过多组开关信号控制，用符号Φ分别表示各开关的开关控制信号。
图1是一实施例的信号放大电路的模块示意图。
如图1所示，信号放大电路包括低通滤波电路100、缓冲电路200、开关电容积分电路300、传感器400、信号开关S、第一连接开关S1、第二连接开关S2、第三连接开关S3和第四连接开关S4，图1并未示出第一连接开关S1、第二连接开关S2、第三连接开关S3和第四连接开关S4。
图2是一实施例的传感器和低通滤波电路连接示意图。
如图2所示，低通滤波电路100包括第一输入端VIN1、第二输入端VIN2、第一开关M1、第二开关M2、第一变阻器RF1、第二变阻器RF2、第一电容C1、第二电容C2、第一输出端VO1和第二输出端VO2。
第一输入端VIN1通过第一开关M1和第一变阻器RF1与第一输出端VO1连接，第二输入端VIN2通过第二开关M2和第二变阻器RF2与第二输出端VO2连接，第一电容C1、第二电容C2极性相反（上下两极板相反）地分别连接于第一输出端VO1和第二输出端VO2之间。
离散系统中，通过开关电容周期性采样实现检测和放大信号，为了避免将控制时钟信号的谐波频率的噪声引入系统，需要先使用抗混叠滤波器对信号滤波。同时由于环境中存在很多低频噪声，比如声音信号，如果不滤除也会影响到检测的加速度信号。所以检测和放大信号前，通过低通滤波电路提高系统的分辨率。
图3是一实施例的信号开关的开关控制信号、第一开关和第二开关的开关控制信号的时序示意图。
如图3所示，信号开关S的开关控制信号为Φm，第一开关M1和第二开关M2的开关控制信号均为Φn。周期脉冲信号Φm、Φn分别控制传感器400和低通滤波电路100的工作，即节省了功耗，又实现了在同样大小电阻和电容情况下得到较低带宽。Ts为信号开关S在周期Tp内的打开时间，脉冲的占空比(Ts/Tp)影响实际的带宽。占空比越低时，实现相同的带宽所用的电阻和电容值越小，面积和功耗就越小。
也可以将信号开关S的打开时间Ts分成N个小段，即N*Ts’=Ts。控制信号Φm的上升沿超前控制信号Φn上升沿Td，控制信号Φm的下降沿滞后控制信号Φn下降沿Td。带宽由开关打开时间Ts与周期时间Tp比决定。
第一变阻器RF1、第二变阻器RF2利用电阻的串并联实现电阻值变化，改变滤波器的带宽。第一电容C1、第二电容C2为两个上下级板反接电容，容量可以相等，版图中输出差分端可以对称，利于共模噪声抑制。
图4是一实施例的缓冲电路的示意图。
如图4所示，缓冲电路200包括第三输入端VIN3、第四输入端VIN4、第一运算放大器A1、第二运算放大器A2、第三开关M3、第四开关M4、第五开关M5、第六开关M6、第七开关M7、第八开关M8、第九开关M9、第十开关M10、第十一开关M11、第十二开关M12、第十三开关M13、第十四开关M14、第三输出端VO3和第四输出端VO4。
第三输入端VIN3通过第三开关M3连接第一运算放大器A1的正输入端，第三输入端VIN3通过第四开关M4连接第一运算放大器A1的负输入端，第一运算放大器A1的正输出端通过第五开关M5连接第三输出端VO3，第一运算放大器A1的负输出端通过第六开关M6连接第三输出端VO3，第一运算放大器A1的正输入端通过第七开关M7连接第一运算放大器A1的负输出端，第一运算放大器A1的负输入端通过第八开关M8连接第一运算放大器A1的正输出端。
第四输入端VIN4通过第九开关M9连接第二运算放大器A2的正输入端，第四输入端VIN4通过第十开关M10连接第二运算放大器A2的负输入端，第二运算放大器A2的正输出端通过第十一开关M11连接第四输出端VO4，第二运算放大器A2的负输出端通过第十二开关M12连接第四输出端VO4，第二运算放大器A2的正输入端通过第十三开关M13连接第二运算放大器A2的负输出端，第二运算放大器A2的负输入端通过第十四开关M14连接第二运算放大器A2的正输出端。
图5是一实施例的缓冲电路中开关控制信号和输出信号的时序示意图。
如图5所示，第三开关M3、第五开关M5、第八开关M8、第九开关M9、第十一开关M11和第十四开关M14的开关控制信号为Φ1，第四开关M4、第六开关M6、第七开关M7、第十开关M10、第十二开关M12和第十三开关M13的开关控制信号为Φ2，Φ1和Φ2为两个反相非交叠（no-overlap）时钟信号。两个时钟信号之间相互切换，信号在运算放大器的正输入端与负输入端之间相互切换，这是斩波（chopping）技术的一种特例。
Vos1和Vos2表示运算放大器低频的1/f噪声和offset，如图5被高频的chopping时钟信号调制到高频，VO为与Φ1频率相同的周期信号，信号的直流分量为VIN，信号幅度为Vos1-Vos2。后级放大电路（开关电容积分电路300）通过对VOUT积分就可以去除Vos1 和Vos2 ，实现减低低频噪声，提高系统的信噪比。由于不使用电容，与自动归零（Auto-zero）技术和相关采样（CDS）技术比较，大大节省了面积。由于没有引入电容的噪声，系统的噪声性能更好。放大器本身为低噪声结构，高频热噪声很小。
图6是一实施例的开关电容积分电路的示意图，图7是一实施例的开关电容积分电路中各信号的时序示意图。
如图6和图7所示，开关电容积分电路300包括第五输入端VIN5、第六输入端VIN6、第三运算放大器A3、第一开关电容模块SC1、第二开关电容模块SC2、第三开关电容模块SC3、第四开关电容模块SC4、第一电容模块CF1、第二电容模块CF2、第一斩波调制器CHP1、第二斩波调制器CHP2、第三斩波调制器CHP3、第五输出端VO5和第六输出端VO6。
每个开关电容模块（第一开关电容模块SC1、第二开关电容模块SC2、第三开关电容模块SC3和第四开关电容模块SC4）包括电容和至少四个控制开关且形成开关电容结构。在本实施例中，每个开关电容模块包括电容和第一控制开关、第二控制开关、第三控制开关及第四控制开关，电容的第一极板通过第一控制开关连接开关电容模块的输入端，电容的第一极板还通过第二控制开关接地。电容的第二极板通过第三控制开关连接开关电容模块的输出端，电容的第二极板还通过第四控制开关接地。
第一开关电容模块SC1、第二开关电容模块SC2的电容容量均为Ci，皆以Ci表示。第一开关电容模块SC1、第二开关电容模块SC2的第一控制开关、第四控制开关的开关控制信号为Φa1，第二控制开关、第三控制开关的开关控制信号为Φa2。Φa1和Φa2为两个反相非交叠（no-overlap）时钟信号。
第三开关电容模块SC3、第四开关电容模块SC4的电容容量均为Cff，皆以Cff表示。第三开关电容模块SC3、第四开关电容模块SC4的第一控制开关、第四控制开关的开关控制信号为Φb1，第二控制开关、第三控制开关的开关控制信号为Φb2。
图8是一实施例的第一开关电容模块或第二开关电容模块中的可调电容示意图。如图8所示，第一开关电容模块SC1和第二开关电容模块SC2中的电容为可调电容Ci。可调电容Ci包括多个电容（Ci0、Ci1……Cin）和多个开关（ki0、ki1……kin），每一电容（Cin）和每一开关（kin）串联成电容支路，所有电容支路并联连接，通过电容支路开关的开闭引入电容实现电容可调。
第一开关电容模块SC1的可调电容的开关（ki0、ki1……kin）靠近第一开关电容模块SC1的输出端，第二开关电容模块SC2的可调电容的开关（ki0、ki1……kin）靠近第二开关电容模块SC2的输出端。开关两端电压值影响其本身的阻值，所以开关必须靠近运算放大器输入端（对第一开关电容模块SC1而言为第一开关电容模块SC1的输出端，第二开关电容模块SC2而言为第二开关电容模块SC2的输出端）。即使输入信号变化，但运算放大器输入端始终接近共模电平，开关两端电压不受信号影响，开关特性不变，不影响放大倍数。
第一开关电容模块SC1中的电容Ci两端分别通过第一连接开关S1和第二连接开关S2与第三开关电容模块SC3中的电容Cff两端并联，第二开关电容模块SC2中的电容Ci两端分别通过第三连接开关S3和第四连接开关S4与第四开关电容模块SC4中的电容Cff两端并联。第一连接开关S1、第二连接开关S2、第三连接开关S3和第四连接开关S4的开关控制信号为Φp。
图9是一实施例的第一电容模块或第二电容模块中的可调电容示意图。如图9所示，每个电容模块（第一电容模块CF1和第二电容模块CF2）包括可调电容Cf和一个开关（以其控制信号Φr表示），且可调电容Cf和开关Φr并联连接。可调电容Cf可以是包括多个电容（Cf0、Cf1……Cfn）和多个开关（kf0、kf1……kfn），每一电容（Cfn）和每一开关（kfn）串联成电容支路，所有电容支路并联连接，通过电容支路开关的开闭引入电容实现电容可调。同上，电容模块中的可调电容Cf中的开关（kf0、kf1……kfn）靠近电容模块的输入端（相当于靠近运算放大器输入端）。
每个斩波调制器（第一斩波调制器CHP1、第二斩波调制器CHP2和第三斩波调制器CHP3）包括至少四个斩波开关且形成斩波调制结构，在本实施例中，包括四个斩波开关并形成斩波调制结构。斩波调制器包括第一斩波开关K1、第二斩波开关K2、第三斩波开关K3和第四斩波开关K4，斩波调制器的第一输入端vin1通过第一斩波开关K1连接斩波调制器的第一输出端vo1，斩波调制器的第一输入端vin1通过第二斩波开关K2连接斩波调制器的第二输出端vo2，斩波调制器的第二输入端vin2通过第三斩波开关K3连接斩波调制器的第二输出端vo2，斩波调制器的第二输入端vin2通过第四斩波开关K4连接斩波调制器的第一输出端vo1。
图10是一实施例的第一斩波调制器的示意图，图11是一实施例的第二斩波调制器或第三斩波器的示意图。如图10和图11所示，第一斩波调制器CHP1的开关K1、K3的开关控制信号为Φch1a，K2、K4的开关控制信号为Φch1b。Φch1a和Φch1b为两个反相非交叠（no-overlap）时钟信号。第二斩波调制器CHP2、第三斩波调制器CHP3的开关K1、K3的开关控制信号为Φch2a，K2、K4的开关控制信号为Φch2b。Φch2a和Φch2b为两个反相非交叠（no-overlap）时钟信号。
第五输入端VIN5依次通过第一开关电容模块SC1、第一斩波调制器CHP1连接第三运算放大器A3的正输入端，第六输入端VIN6依次通过第二开关电容模块SC2、第一斩波调制器CHP1连接第三运算放大器A3的负输入端。第三运算放大器A3的正输入端依次通过第二斩波调制器CHP2、第一电容模块CF1连接第五输出端VO5，第三运算放大器A3的负输入端依次通过第二斩波调制器CHP2、第二电容模块CF2连接第六输出端VO6。第三运算放大器A3的正输入端通过第三开关电容模块SC3连接第五输出端VO5，第三运算放大器A3的负输入端通过第四开关电容模块SC4连接第六输出端VO6。第三运算放大器A3的正输出端通过第三斩波调制器CHP3连接第六输出端VO6，第三运算放大器A3的负输出端通过第三斩波调制器CHP3连接第五输出端VO5。
图12~图19为在图7中各信号控制的开关电容积分电路的状态图，分别对应状态1~8。Voffp和Voffn分别为运算放大器正输入端的偏差电压和负输入端的偏差电压。状态1和状态2：VP - VN = -（ Voffp – Voffn ）；状态3：VP - VN = Voffn *( 2*Cff/Cf + 1 ) – Voffp *( 2*Cff/Cf + 1 )；状态4：VP - VN = ( 2*Cff/Cf -1 ) * ( Voffn – Voffp )，当Cff = 1/2* Cf时，输出为零；状态5：VP - VN = Ci/Cf * ( Voffp – Voffn )；状态6：VP - VN = ( Ci/Cf -2 ) * ( Voffp – Voffn )；状态7：VP - VN = 2 * ( Voffn – Voffp )；状态8：VP - VN = 0；状态8之后会继续重复状态5到状态8的过程，选择积分周期应该保证没有输入信号时，输出为零，去除放大器offset和1/f低频噪声。
信号开关S用于控制放大前的电压信号的通断。第一输入端VIN1和第二输入端VIN2输入放大前的电压信号，第一输出端VO1连接第三输入端VIN3，第二输出端VO2连接第四输入端VIN4，第三输出端VO3连接第五输入端VIN5，第四输出端VO4连接第六输入端VIN6，第五输出端VO5和第六输出端VO6输出放大后的电压信号。具体为，传感器400通过信号开关S接地，传感器400还连接低通滤波电路100的第一输入端VIN1和第二输入端VIN2并利用自身电阻变化输出差动输出电压作为放大前的电压信号。在本实施例中，传感器400是由采用压敏电阻元件的惠斯通电桥电路构成的加速度传感器。
上述信号放大电路可以应用到智能数码设备中，例如手机或平板电脑等。
上述信号放大电路，可以通过控制开关信号、第一开关、第二开关的开闭将电路的工作状态分割，既节省了功耗又实现了在同样大小的电阻和电容情况下得到很低带宽，不仅带宽灵活可控，同时节省面积和功耗，而且噪声抑制更好。选择可调电阻加大带宽可调范围，使得对于不同量程的小信号也拥有足够的分辨率。第一电容、第二电容极性相反地分别连接于第一输出端和第二输出端之间，能有效抑制版图设计中引入的噪声。
由两个运算放大器（第一运算放大器和第二运算放大器）构成差分缓冲电路，保证后级放大电路采样多次也不影响滤波电容上存储的电荷。缓冲电路的结构可以应用斩波技术（chopping），通过控制缓冲电路中开关的开闭可以去除1/f 噪声和输入偏移电压（offset）。而且避免了使用电容，减小芯片面积，噪声更小。
开关电容积分电路，通过控制电路中的开关的闭合，主要采用斩波技术（chopping）和自动归零技术（Auto-Zero）去除放大器输入偏移电压（offset）和减小1/f噪声，同时除了可以改变积分周期实现增益变化，还可以通过调节输入输出电容比实现增益可调，对微弱信号的噪声抑制更好。输入电容和输出电容比增加，放大倍数增加，不受工艺变化的影响也不受工作电压和温度的影响，解决不同量程需要不同放大倍数问题，提高微弱信号的分辨率。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种信号放大电路，包括：
    低通滤波电路，包括第一输入端、第二输入端、第一开关、第二开关、第一变阻器、第二变阻器、第一电容、第二电容，第一输出端和第二输出端，其中，所述第一输入端通过所述第一开关和所述第一变阻器与所述第一输出端连接，所述第二输入端通过所述第二开关和所述第二变阻器与所述第二输出端连接，所述第一电容和所述第二电容极性相反地分别连接于所述第一输出端和所述第二输出端之间；
    缓冲电路，包括第三输入端、第四输入端、第一运算放大器、第二运算放大器、第三开关、第四开关、第五开关、第六开关、第七开关、第八开关、第九开关、第十开关、第十一开关、第十二开关、第十三开关、第十四开关、第三输出端和第四输出端，其中，所述第三输入端通过所述第三开关连接所述第一运算放大器的正输入端，所述第三输入端通过所述第四开关连接所述第一运算放大器的负输入端，所述第一运算放大器的正输出端通过所述第五开关连接所述第三输出端，所述第一运算放大器的负输出端通过所述第六开关连接所述第三输出端，所述第一运算放大器的正输入端通过所述第七开关连接所述第一运算放大器的负输出端，所述第一运算放大器的负输入端通过所述第八开关连接所述第一运算放大器的正输出端；所述第四输入端通过所述第九开关连接所述第二运算放大器的正输入端，所述第四输入端通过所述第十开关连接所述第二运算放大器的负输入端，所述第二运算放大器的正输出端通过所述第十一开关连接所述第四输出端，所述第二运算放大器的负输出端通过所述第十二开关连接所述第四输出端，所述第二运算放大器的正输入端通过所述第十三开关连接所述第二运算放大器的负输出端，所述第二运算放大器的负输入端通过所述第十四开关连接所述第二运算放大器的正输出端；
    开关电容积分电路，包括第五输入端、第六输入端、第三运算放大器、第一开关电容模块、第二开关电容模块、第三开关电容模块、第四开关电容模块、第一电容模块、第二电容模块、第一斩波调制器、第二斩波调制器、第三斩波调制器、第五输出端和第六输出端，其中，每个所述开关电容模块包括电容和至少四个开关且形成开关电容结构；每个所述电容模块包括可调电容和至少一个开关且电容和开关并联连接；每个所述斩波调制器包括至少四个开关且形成斩波调制结构；所述第五输入端依次通过所述第一开关电容模块和所述第一斩波调制器连接所述第三运算放大器的正输入端，所述第六输入端依次通过所述第二开关电容模块和所述第一斩波调制器连接所述第三运算放大器的负输入端；所述第三运算放大器的正输入端依次通过所述第二斩波调制器和所述第一电容模块连接所述第五输出端，所述第三运算放大器的负输入端依次通过所述第二斩波调制器和所述第二电容模块连接所述第六输出端；所述第三运算放大器的正输入端通过所述第三开关电容模块连接所述第五输出端，所述第三运算放大器的负输入端通过所述第四开关电容模块连接所述第六输出端；所述第三运算放大器的正输出端通过所述第三斩波调制器连接所述第六输出端，所述第三运算放大器的负输出端通过所述第三斩波调制器连接所述第五输出端；和
    信号开关，用于控制放大前的电压信号的通断，其中，所述第一输入端和所述第二输入端输入放大前的电压信号，所述第一输出端连接所述第三输入端，所述第二输出端连接所述第四输入端，所述第三输出端连接所述第五输入端，所述第四输出端连接所述第六输入端，所述第五输出端和所述第六输出端输出放大后的电压信号。
  2. 根据权利要求1所述的信号放大电路，其特征在于，每个开关电容模块包括电容和第一控制开关、第二控制开关、第三控制开关及第四控制开关，所述电容的第一极板通过所述第一控制开关连接所述开关电容模块的输入端，所述电容的第一极板还通过所述第二控制开关接地；所述电容的第二极板通过所述第三控制开关连接所述开关电容模块的输出端，所述电容的第二极板还通过所述第四控制开关接地。
  3. 根据权利要求1所述的信号放大电路，其特征在于，所述第一开关电容模块和所述第二开关电容模块中的电容为可调电容。
  4. 根据权利要求1所述的信号放大电路，其特征在于，所述信号放大电路还包括第一连接开关、第二连接开关、第三连接开关和第四连接开关，所述第一开关电容模块中的电容两端分别通过所述第一连接开关和所述第二连接开关与所述第三开关电容模块中的电容两端并联，所述第二开关电容模块中的电容两端分别通过所述第三连接开关和所述第四连接开关与所述第四开关电容模块中的电容两端并联。
  5. 根据权利要求1所述的信号放大电路，其特征在于，所述可调电容包括多个电容和多个开关，每一电容和每一开关串联成电容支路，所有电容支路并联连接。
  6. 根据权利要求1所述的信号放大电路，其特征在于，所述电容模块中的可调电容中的开关靠近所述电容模块的输入端，所述第一开关电容模块的可调电容中的开关靠近所述第一开关电容模块的输出端，所述第二开关电容模块的可调电容中的开关靠近所述第二开关电容模块的输出端。
  7. 根据权利要求1所述的信号放大电路，其特征在于，所述斩波调制器包括第一斩波开关、第二斩波开关、第三斩波开关和第四斩波开关，所述斩波调制器的第一输入端通过所述第一斩波开关连接所述斩波调制器的第一输出端，所述斩波调制器的第一输入端通过所述第二斩波开关连接所述斩波调制器的第二输出端，所述斩波调制器的第二输入端通过所述第三斩波开关连接所述斩波调制器的第二输出端，所述斩波调制器的第二输入端通过所述第四斩波开关连接所述斩波调制器的第一输出端。
  8. 根据权利要求1所述的信号放大电路，其特征在于，还包括传感器，所述传感器通过信号开关接地，所述传感器还连接所述低通滤波电路的第一输入端和第二输入端，所述传感器利用自身电阻变化输出差动输出电压作为放大前的电压信号。
  9. 根据权利要求8所述的信号放大电路，其特征在于，所述传感器是由采用压敏电阻元件的惠斯通电桥电路构成的加速度传感器。
  10. 根据权利要求1所述的信号放大电路，其特征在于，所有所述开关皆为半导体器件开关，并通过多组开关信号控制。
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