WO2016161668A1 - 双栅极器件以及双栅极器件的制造方法 - Google Patents

双栅极器件以及双栅极器件的制造方法 Download PDF

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WO2016161668A1
WO2016161668A1 PCT/CN2015/077063 CN2015077063W WO2016161668A1 WO 2016161668 A1 WO2016161668 A1 WO 2016161668A1 CN 2015077063 W CN2015077063 W CN 2015077063W WO 2016161668 A1 WO2016161668 A1 WO 2016161668A1
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gate electrode
insulating layer
organic insulating
layer
substrate
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French (fr)
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徐洪远
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/481—Insulated gate field-effect transistors [IGFETs] characterised by the gate conductors
    • H10K10/482—Insulated gate field-effect transistors [IGFETs] characterised by the gate conductors the IGFET comprising multiple separately-addressable gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/80—Constructional details
    • H10K10/82—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
    • H10K10/471—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising only organic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/621—Providing a shape to conductive layers, e.g. patterning or selective deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to the field of electronic components, and more particularly to a dual gate device and a method of fabricating a dual gate device.
  • a TFT Thin-film transistor
  • OTFT Organic TFT
  • OFT Organic TFT
  • the new Array board technology is the most promising next-generation flexible display because of its flexibility, curlability, low process cost, and easy portability.
  • the organic layer materials of OTFT mainly include two kinds of polymers and small molecules.
  • the mobility of OTFT devices is mostly low, and it is difficult to drive OLEDs (Organic Light-Emitting Diode). , organic light-emitting diodes) required level.
  • the threshold voltage (Vth) of the organic layer material is difficult to control by the material itself or the process, which causes the power consumption of the device to be greatly increased during operation, thereby limiting the application of the OTFT in the display field.
  • the technical problem to be solved by the embodiments of the present invention is to provide a method for fabricating a dual gate device and a dual gate device.
  • the OTFT device structure adopts a double gate structure to improve device characteristics, thereby reducing threshold voltage and increasing on-state current.
  • the purpose of reducing the off-state current, and the overlap of the top gate electrode and the source-drain electrode, enables the device of the double-gate structure to reduce the device contact resistance and save power consumption.
  • a first aspect of the embodiments of the present invention discloses a method for fabricating a dual gate device, including:
  • An organic semiconductor layer, a second organic insulating layer and a third metal layer are sequentially covered on the source and drain electrodes and the first organic insulating layer;
  • the organic semiconductor layer, the second organic insulating layer, and the third metal layer are patterned by a third photomask to form a top gate electrode.
  • the first organic insulating layer covers the bottom gate electrode, the organic semiconductor layer covers the source/drain electrodes, and the top gate electrode and the source and drain electrodes overlap.
  • source and drain electrodes are located in an orthographic projection area of the bottom gate electrode.
  • the bottom gate electrode is located in a middle portion of an upper surface of the substrate.
  • the surface of the organic semiconductor coating away from the source and drain electrodes is a flat surface.
  • the top gate electrode and the source and drain electrodes overlap.
  • the manufacturing method further includes:
  • orthographic projection area of the passivation layer is the same as the orthographic projection area of the substrate.
  • the substrate is made of polyethylene naphthalate, polyethylene terephthalate or polyimide, the first metal layer, the second metal layer and the third
  • the metal layer is made of any one of gold, silver, copper, and iron.
  • Another aspect of the present invention further discloses a dual gate device comprising: a substrate, a bottom gate electrode, a first organic insulating layer, a source/drain electrode, an organic semiconductor layer, and a a second organic insulating layer and a top gate electrode, wherein:
  • the bottom gate electrode is located on an upper surface of the substrate
  • the first organic insulating layer is located on an upper surface of the substrate and covers the bottom gate electrode;
  • the source/drain electrode is located on an upper surface of the first organic insulating layer away from the substrate;
  • the organic semiconductor layer is located away from an upper surface of the first organic insulating layer of the substrate, and the organic semiconductor layer covers the source and drain electrodes;
  • the second organic insulating layer is located on an upper surface of the organic semiconductor layer away from the substrate;
  • the top gate electrode is located on an upper surface of the second organic insulating layer remote from the substrate.
  • the source/drain electrode is located in an orthographic projection area of the bottom gate electrode, and an upper surface of the organic semiconductor layer is a flat surface.
  • the front projection area of the organic semiconductor layer is the same as the front projection area of the bottom gate electrode.
  • the upper surface of the second organic insulating layer is a flat surface, and the front projection area of the second organic insulating layer is the same as the front projection area of the bottom gate electrode.
  • the upper surface of the top gate electrode is a flat surface, and the front projection area of the top gate electrode is the same as the front projection area of the bottom gate electrode.
  • the top gate electrode overlaps with the source and drain electrodes.
  • the dual gate device further comprises:
  • a passivation layer located on an upper surface of the first organic insulating layer away from the substrate, the passivation layer covering the organic semiconductor layer, the second organic insulating layer, and the Top gate electrode.
  • orthographic projection area of the passivation layer is the same as the orthographic projection area of the substrate.
  • the substrate is made of polyethylene naphthalate, polyethylene terephthalate or polyimide, the first metal layer, the second metal layer and the third
  • the metal layer is made of any one of gold, silver, copper, and iron.
  • an OTFT (Organic Thin Film Transistor) device structure adopts a double gate structure to improve device characteristics, and the embodiment of the present invention has the following beneficial effects:
  • the double gate structure can reduce the threshold voltage, increase the on-state current, and reduce the off-state current
  • the overlap of the top gate electrode and the source and drain electrodes reduces the contact resistance of the OTFT device and saves power consumption.
  • FIG. 1 is a schematic flow chart of a first embodiment of a method for fabricating a dual gate device according to an embodiment of the present invention
  • FIG. 2 is a partial schematic structural view of a dual gate device obtained according to the fabrication method shown in FIG. 1;
  • FIG. 3 is a partial structural schematic view of a dual gate device obtained according to the fabrication method shown in FIG. 1;
  • FIG. 4 is a partial structural schematic view of a dual gate device obtained according to the fabrication method shown in FIG. 1;
  • FIG. 5 is a partial structural schematic view of a dual gate device obtained according to the fabrication method shown in FIG. 1;
  • FIG. 6 is a schematic structural diagram of a first embodiment of a dual gate device according to an embodiment of the present invention.
  • FIG. 7 is a schematic flow chart of a second embodiment of a method for fabricating a dual gate device according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a second embodiment of a dual gate device according to an embodiment of the present invention.
  • connection In the description of the present invention, it should be noted that the terms “installation”, “connected”, and “connected” are to be understood broadly, and may be fixed or detachable, for example, unless otherwise explicitly defined and defined.
  • the ground connection, or the integral connection may be a mechanical connection; it may be directly connected, or may be indirectly connected through an intermediate medium, and may be internal communication between the two elements.
  • the specific meaning of the above terms in the present invention can be understood in a specific case by those skilled in the art.
  • a mask is also called a photomask.
  • part of it is a process from the layout to the wafer fabrication, that is, photomask or photomask manufacturing. This part is a key part of the process connection, the highest cost part of the process, and one of the bottlenecks that limit the minimum line width.
  • the photomask base plate is an ideal photosensitive blank for making a fine photomask pattern, and a desired photomask can be obtained by a photolithography process. Briefly, the photomask substrate becomes a photomask after being etched with the mask pattern. The carrier of the original graphics during the exposure process, through the exposure process, the information of these graphics will be transferred to the chip.
  • FIG. 1 is a schematic flow chart of a first embodiment of a method for fabricating a dual-gate device according to an embodiment of the present invention.
  • the manufacturing method includes at least the following steps.
  • Step S102 forming a first metal layer on a substrate
  • the substrate 110 may be PEN (Polyethylene naphthalene) or PET (Polyethylene terephthalate) or PI (Polyimide,
  • the first metal layer 120 is formed on the upper surface of the substrate 110 by sputtering or the like, and the material of the first metal layer 120 includes, but is not limited to, gold, silver, copper. , iron and other materials.
  • the first metal layer 120 may be made of gold.
  • Step S104 patterning the first metal layer by a first mask to form a bottom gate electrode
  • the first metal layer 120 may be patterned by a first mask using a yellow light process (such as development, wet etching, dry etching, etc.). Processing, at this time, the processed first metal layer 120 can serve as the bottom gate electrode 120.
  • the bottom gate electrode 120 may be located in the middle of the upper surface of the substrate 110.
  • the pattern of the top view of the bottom gate electrode 120 includes, but is not limited to, a straight line pattern, a curved pattern, a polygonal pattern, a circular pattern, an elliptical pattern, a star pattern, and the like. It can be understood that the specific pattern shape can be used according to actual use. It is to be determined that the embodiments of the present invention are not specifically limited herein.
  • Step S106 coating a first organic insulating layer on the bottom gate electrode and the substrate;
  • a first organic insulating layer 130 may be coated on the bottom gate electrode 120 and the substrate 110, and the first organic insulating layer 130 The bottom gate electrode 120 is covered.
  • the upper surface of the first organic insulating layer 130 away from the bottom gate electrode 120 may be a flat surface.
  • Step S108 forming a second metal layer on the first organic insulating layer
  • a second metal layer may be formed on the first organic insulating layer 130 by sputtering or the like, and the second metal layer includes, but not limited to, gold, silver, copper, iron, or the like.
  • the second metal layer may be made of gold.
  • Step S110 patterning the second metal layer by a second photomask to form a source/drain electrode
  • the second metal layer may be patterned by a yellow photomask to form a source/drain electrode 140.
  • the source/drain electrode 140 may be located at an upper surface of the first organic insulating layer 130, and may be located at a middle portion of the upper surface; the source/drain electrode 140 may be located in an orthographic projection area of the bottom gate electrode 120. That is, the source/drain electrode 140 is on the upper surface of the first organic insulating layer 130 and is located within a region surrounded by the boundary of the bottom gate electrode 120.
  • the pattern of the top view of the source/drain electrode 140 includes, but is not limited to, a straight line pattern, a curved pattern, a polygonal pattern, a circular pattern, an elliptical pattern, a star pattern, and the like. It can be understood that the specific pattern shape can be used according to actual use. It is to be determined that the embodiments of the present invention are not specifically limited herein.
  • Step S112 sequentially covering an organic half on the source/drain electrode and the first organic insulating layer a conductor layer, a second organic insulating layer and a third metal layer;
  • an organic semiconductor layer 150, a second organic insulating layer 160, and a third metal layer 170 may be sequentially covered on the source and drain electrodes 140 and the first organic insulating layer 130.
  • the third metal layer 170 may be made of a material including, but not limited to, gold, silver, copper, iron, etc., preferably, the third metal layer 170 may be made of gold.
  • Step S114 patterning the organic semiconductor layer, the second organic insulating layer and the third metal layer by a third mask to form a top gate electrode;
  • the organic semiconductor layer 150, the second layer may be passed through the third mask by a yellow light process (such as development, wet etching, dry etching, etc.).
  • the organic insulating layer 160 and the third metal layer 170 are patterned, and at this time, the processed third metal layer 170 serves as the top gate electrode 170.
  • the pattern of the top view of the top gate electrode 170 includes, but is not limited to, a straight line pattern, a curved pattern, a polygonal pattern, a circular pattern, an elliptical pattern, a star pattern, and the like. It can be understood that the specific pattern shape can be used according to actual use. It is to be determined that the embodiments of the present invention are not specifically limited herein.
  • a schematic flowchart of a second embodiment of a method for fabricating a dual-gate device according to an embodiment of the present invention includes:
  • Step S202 forming a first metal layer on a substrate
  • Step S204 patterning the first metal layer by a first mask to form a bottom gate electrode
  • Step S208 sputtering a second metal layer on the first organic insulating layer
  • Step S210 patterning the second metal layer by a second photomask to form a source/drain electrode
  • Step S212 sequentially covering an organic semiconductor layer, a second organic insulating layer and a third metal layer on the source/drain electrode and the first organic insulating layer;
  • steps S102 to S214 may refer to steps S102 to S114 in the foregoing embodiment of FIG. 1, and details are not described herein again.
  • Step S216 coating a passivation layer on the first organic insulating layer, the organic semiconductor layer, the second organic insulating layer and the top gate electrode, the passivation layer being coated away from the An upper surface of the first organic insulating layer of the substrate, the passivation layer covering the first organic insulating layer, the organic semiconductor layer, the second organic insulating layer, and the top gate electrode;
  • a passivation may be applied on the first organic insulating layer 130, the organic semiconductor layer 150, the second organic insulating layer 160, and the top gate electrode 170.
  • Layer 180 in an embodiment of the invention, the passivation layer 180 can be an organic glass layer.
  • the passivation layer 180 is located on an upper surface of the first organic insulating layer 130, and the passivation layer 180 covers the organic semiconductor layer 150, the second organic insulating layer 160, and the top gate electrode 170.
  • the orthographic projection area of the passivation layer 180 is the same as the orthographic projection area of the substrate 110.
  • the substrate 110 may be PEN or PET or PI, and a first metal layer may be formed on the upper surface of the substrate 110 by sputtering or the like.
  • the material of the first metal layer includes, but is not limited to, gold, silver, copper. , iron and other materials.
  • the material of the first metal layer may be gold.
  • the first metal layer may be patterned by a first mask by a yellow light process (such as development, wet etching, dry etching, etc.). At this time, the processed first metal layer may serve as the bottom gate electrode 120. .
  • the bottom gate electrode 120 may be located at a middle portion of an upper surface of the substrate 110.
  • the pattern of the top view of the bottom gate electrode 120 includes, but is not limited to, a straight line pattern, a curved pattern, a polygonal pattern, a circular pattern, an elliptical pattern, a star pattern, and the like. It can be understood that the specific pattern shape can be used according to actual use. It is to be determined that the embodiments of the present invention are not specifically limited herein.
  • the source/drain electrode 140 may be located at an upper surface of the first organic insulating layer 130 away from the substrate 110, and may be located at a middle portion of the upper surface; the source/drain electrode 140 may be located at the bottom gate electrode 120. In the orthographic projection area, that is, the source/drain electrode 140 is located at the boundary of the bottom gate electrode 120 Within the scope of the enclosed area.
  • the pattern of the top view of the source/drain electrode 140 includes, but is not limited to, a straight line pattern, a curved pattern, a polygonal pattern, a circular pattern, an elliptical pattern, a star pattern, and the like. It can be understood that the specific pattern shape can be used according to actual use. It is to be determined that the embodiments of the present invention are not specifically limited herein.
  • the organic semiconductor layer 150 is located away from the upper surface of the first organic insulating layer 130 of the substrate 110, the organic semiconductor layer 150 covers the source and drain electrodes 140; the organic semiconductor layer 150 is away from the
  • the upper surface of the source-drain electrode 140 may be a flat surface, and the orthographic projection area of the organic semiconductor layer 150 may be the same as the orthographic projection area of the bottom gate electrode 120.
  • the second organic insulating layer 160 is located away from the upper surface of the organic semiconductor layer 150 of the substrate 110; the upper surface of the second organic insulating layer 160 away from the source and drain electrodes 140 may be a flat surface.
  • the orthographic projection area of the second organic insulating layer 160 may be the same as the orthographic projection area of the bottom gate electrode 120.
  • the top gate electrode 170 is located away from the upper surface of the second organic insulating layer 160 of the substrate 110; the upper surface of the top gate electrode 170 away from the source and drain electrode 140 may be a flat surface,
  • the orthographic projection area of the top gate electrode 170 may be the same as the orthographic projection area of the bottom gate electrode 120.
  • the pattern of the top view of the top gate electrode 170 includes, but is not limited to, a straight line pattern, a curved pattern, a polygonal pattern, a circular pattern, an elliptical pattern, a star pattern, and the like. It can be understood that the specific pattern shape can be used according to actual use. It is to be determined that the embodiments of the present invention are not specifically limited herein.
  • the material of the top gate electrode 170 includes, but is not limited to, gold, silver, copper, iron, and the like. Preferably, the material of the top gate electrode 170 may be gold.
  • the passivation layer 180 is located away from an upper surface of the first organic insulating layer 130 of the substrate 110, and the passivation layer 180 is coated on the organic semiconductor layer 150, the second organic insulating layer 160, and Above the top gate electrode 170.
  • the passivation layer 180 can be a layer of organic glass.
  • the orthographic projection area of the passivation layer 180 is the same as the orthographic projection area of the substrate 110.
  • the dual gate device shown in FIG. 8 can be manufactured according to the manufacturing method of the dual gate device shown in FIG. 1 or FIG. 7 , and details are not described herein again.
  • the double gate structure can reduce the threshold voltage, increase the on-state current, and reduce the off-state current
  • the overlap of the top gate electrode and the source and drain electrodes reduces the contact resistance of the OTFT device and saves power consumption.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

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Abstract

双栅极器件的制作方法，包括：在一基板（110）形成一第一金属层（120）；对第一金属层（120）进行图案化处理以形成底栅电极（120）；在底栅电极和基板上涂覆一第一有机绝缘层（130）；在第一有机绝缘层上溅镀形成第二金属层；对第二金属层进行图案化处理以形成源漏电极（140）；在源漏电极和第一有机绝缘层上依次覆盖一有机半导体层（150）、一第二有机绝缘层（160）和一第三金属层（170）；通过第三光罩对有机半导体层、第二有机绝缘层和第三金属层进行图案化处理以形成顶栅电极（170）。顶栅电极与源漏电极的交叠，使得双栅极结构的器件能减小器件接触电阻，节约功耗。

Description

双栅极器件以及双栅极器件的制造方法
本发明要求2015年04月08日递交的发明名称为“双栅极器件以及双栅极器件的制造方法”的申请号为201510163163.6的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及电子元器件领域，尤其涉及一种双栅极器件以及一种双栅极器件的制造方法。
背景技术
TFT(Thin-film transistor，薄膜晶体管)是一种主要用于平板显示器件中像素单元的开关元件。OTFT(Organic TFT，有机薄膜晶体管)是一种使用有机物作为半导体材料的薄膜晶体管，因其具有柔韧性好、可卷曲、制程成本低、携带方便等特点，成为当前最具潜力的下一代柔性显示器的新型Array板技术。
OTFT的有机层材料主要有聚合物(polymer)和小分子(small molecule)两种，但由于材料自身特性的限制，目前OTFT器件的迁移率大多较低，难以达到驱动OLED(Organic Light-Emitting Diode，有机发光二极管)所需的水平。此外，有机层材料的阈值电压(Vth)很难通过材料自身或制程去调控，如此会导致器件在操作时的功耗大大增加，进而限制了OTFT在显示器领域的应用。
发明内容
本发明实施例所要解决的技术问题在于，提供一种双栅极器件的制作方法及双栅极器件，OTFT器件结构采用双栅极结构改善器件特性，达到减小阈值电压，增大开态电流，减小关态电流的目的，且顶栅电极与源漏电极的交叠，使得双栅极结构的器件能减小器件接触电阻，节约功耗。
为了解决上述技术问题，本发明实施例第一方面公开了一种双栅极器件的制作方法，包括：
在一基板形成一第一金属层；
通过第一光罩对所述第一金属层进行图案化处理以形成底栅电极；
在所述底栅电极和所述基板上涂覆一第一有机绝缘层；
在所述第一有机绝缘层上溅镀形成第二金属层；
通过第二光罩对所述第二金属层进行图案化处理以形成源漏电极；
在所述源漏电极和所述第一有机绝缘层上依次覆盖一有机半导体层、一第二有机绝缘层和一第三金属层；
通过第三光罩对所述有机半导体层、所述第二有机绝缘层和所述第三金属层进行图案化处理以形成顶栅电极。
其中，所述第一有机绝缘层包覆所述底栅电极，所述有机半导体层包覆所述源漏电极，所述顶栅电极与所述源漏电极之间交叠。
其中，所述源漏电极位于所述底栅电极的正投影区域内。
其中，所述底栅电极位于所述基板上表面的中部。
其中，所述有机半导体涂层远离所述源漏电极的表面为一平整面。
其中，所述顶栅电极与所述源漏电极之间相交叠。
其中，所述制作方法还包括：
在所述第一有机绝缘层、所述有机半导体层、所述第二有机绝缘层和所述顶栅电极之上涂覆一钝化层，所述钝化层涂覆于远离所述基板的所述第一有机绝缘层的上表面，所述钝化层包覆所述有机半导体层、所述第二有机绝缘层和所述顶栅电极。
其中，所述钝化层的正投影区域与所述基板的正投影区域相同。
其中，所述基板由聚萘二甲酸乙二醇酯、聚对苯二甲酸乙二醇酯或聚酰亚胺制成，所述第一金属层、所述第二金属层及所述第三金属层由金、银、铜、铁中的任意一种材料制成。
本发明实施例另一方面还公开了一种双栅极器件，该双栅极器件包括：一基板、一底栅电极、一第一有机绝缘层、一源漏电极、一有机半导体层、一第二有机绝缘层和一顶栅电极，其中：
所述底栅电极位于所述基板的上表面；
所述第一有机绝缘层位于所述基板的上表面，且包覆所述底栅电极；
所述源漏电极位于远离所述基板的所述第一有机绝缘层的上表面；
所述有机半导体层位于远离所述基板的所述第一有机绝缘层的上表面，且所述有机半导体层包覆所述源漏电极；
所述第二有机绝缘层位于远离所述基板的所述有机半导体层的上表面；
所述顶栅电极位于远离所述基板的所述第二有机绝缘层的上表面。
其中，所述源漏电极位于所述底栅电极的正投影区域内，所述有机半导体层的上表面为一平整面。
其中，所述有机半导体层的正投影区域与所述底栅电极的正投影区域相同。
其中，所述第二有机绝缘层的上表面为一平整面，所述第二有机绝缘层的正投影区域与所述底栅电极的正投影区域相同。
其中，所述顶栅电极的上表面为一平整面，所述顶栅电极的正投影区域与所述底栅电极的正投影区域相同。
其中，所述顶栅电极与所述源漏电极之间交叠。
其中，所述双栅极器件还包括：
一钝化层，所述钝化层位于远离所述基板的所述第一有机绝缘层的上表面，所述钝化层包覆所述有机半导体层、所述第二有机绝缘层和所述顶栅电极。
其中，所述钝化层的正投影区域与所述基板的正投影区域相同。
其中，所述基板由聚萘二甲酸乙二醇酯、聚对苯二甲酸乙二醇酯或聚酰亚胺制成，所述第一金属层、所述第二金属层及所述第三金属层由金、银、铜、铁中的任意一种材料制成。
实施本发明实施例，OTFT(Organic Thin Film Transistor，有机薄膜晶体管)器件结构采用双栅极结构改善器件特性，本发明实施例具有如下有益效果：
1、双栅极结构能够减小阈值电压，增大开态电流，减小关态电流；
2、顶栅电极与源漏电极的交叠，使得OTFT器件的接触电阻减小，节约功耗。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施 例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的双栅极器件的制作方法的第一实施例的流程示意图；
图2是根据图1所示的制作方法得到的双栅极器件的部分结构示意图；
图3是根据图1所示的制作方法得到的双栅极器件的部分结构示意图；
图4是根据图1所示的制作方法得到的双栅极器件的部分结构示意图；
图5是根据图1所示的制作方法得到的双栅极器件的部分结构示意图；
图6是本发明实施例提供的双栅极器件的第一实施例的结构示意图；
图7是本发明实施例提供的双栅极器件的制作方法的第二实施例的流程示意图；及
图8是本发明实施例提供的双栅极器件的第二实施例的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
需要说明的是，在本发明实施例中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本发明。在本发明实施例和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。此外，以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明中所提到的方向用语，例如，“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”、“侧面”等，仅是参考附加图式的方向，因此，使用的方向用语是为了更好、更清楚地说明及理解本发明，而不是指示或暗指所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸地连接，或者一体地连接；可以是机械连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
此外，在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。本说明书中“工序”的用语不仅是指独立的工序，在与其它工序无法明确区别时，只要能实现该工序所预期的作用则也包括在本用语中。另外，本说明书中用“～”表示的数值范围是指将“～”前后记载的数值分别作为最小值及最大值包括在内的范围。在附图中，结构相似或相同的单元用相同的标号表示。
黄光制程为通过对涂覆在玻璃表面的光敏性物质(又称为光刻胶或光阻)，经曝光、显影后留下的部分对底层起保护作用，然后进行蚀刻脱膜并最终获得永久性图形的过程。
光罩(mask)又称光掩膜板，在半导体制造的整个流程中，其中一部分就是从版图到wafer(晶圆)制造中间的一个过程，即光掩膜或称光罩制造。这一部分是流程衔接的关键部分，是流程中造价最高的一部分，也是限制最小线宽的瓶颈之一。光掩膜基版是制作微细光掩膜图形的理想感光性空白板，通过光刻制版工艺可以获得所需光掩膜版。简单地说，光掩膜基版在被刻蚀上掩膜图形之后就成为光掩膜版。曝光过程中的原始图形的载体，通过曝光过程，这些图形的信息将被传递到芯片上。
参见图1，本发明实施例提供的双栅极器件的制作方法的第一实施例的流程示意图，该制作方法至少可包括以下步骤。
步骤S102：在一基板形成一第一金属层；
具体地，如图2所示，所述基板110可以是PEN(Polyethylene naphthalene，聚萘二甲酸乙二醇酯)或PET(Polyethylene terephthalate，聚对苯二甲酸乙二醇酯)或PI(Polyimide，聚酰亚胺)制成的，并可通过溅镀等方式在该基板110的上表面形成所述第一金属层120，所述第一金属层120的材料包含但不限于金、银、铜、铁等材料。较佳地，所述第一金属层120可以由是金制成。
步骤S104：通过第一光罩对所述第一金属层进行图案化处理以形成底栅 电极；
具体地，如图2所示，在本发明的一实施例中，可以采用黄光制程(如显影、湿刻、干刻等)通过第一光罩对所述第一金属层120进行图形化处理，此时，处理后的第一金属层120可以作为底栅电极120。该底栅电极120可以位于所述基板110的上表面的中部。所述底栅电极120的俯视图的图案包括但不限于：直线图案、曲线图案、多边形图案、圆形图案、椭圆形图案、星形图案等图案，可以理解，具体的图案形状可根据实际使用来确定，本发明的实施方案在此不作具体限定。
步骤S106：在所述底栅电极和所述基板上涂覆一第一有机绝缘层；
具体地，如图3所示，在本发明的一实施例中，可以在所述底栅电极120和所述基板110上涂覆第一有机绝缘层130，所述第一有机绝缘层130包覆所述底栅电极120。所述第一有机绝缘层130远离所述底栅电极120的上表面可为一平整面。
步骤S108：在所述第一有机绝缘层上形成一第二金属层；
具体地，可以通过溅镀等方式在所述第一有机绝缘层130上形成一层第二金属层，所述第二金属层包含但不限于：金、银、铜、铁等材料。较佳地，所述第二金属层可以由金制成。
步骤S110：通过第二光罩对所述第二金属层进行图案化处理以形成源漏电极；
具体地，如图4所示，在本发明的一实施例中，可以采用黄光制程通过第二光罩对所述第二金属层进行图形化处理，形成源漏电极140。所述源漏电极140可以位于所述第一有机绝缘层130的上表面，具体可位于该上表面的中部位置；所述源漏电极140可以位于所述底栅电极120的正投影区域内，即该源漏电极140在该第一有机绝缘层130上表面，并位于该底栅电极120的边界所围成的区域范围之内。所述源漏电极140的俯视图的图案包括但不限于：直线图案、曲线图案、多边形图案、圆形图案、椭圆形图案、星形图案等图案，可以理解，具体的图案形状可根据实际使用来确定，本发明的实施方案在此不作具体限定。
步骤S112：在所述源漏电极和所述第一有机绝缘层上依次覆盖一有机半 导体层、一第二有机绝缘层和一第三金属层；
具体地，如图5所示，可以在所述源漏电极140和所述第一有机绝缘层130上依次覆盖一有机半导体层150、一第二有机绝缘层160和一第三金属层170。所述第三金属层170可由包含但不限于金、银、铜、铁等材料制成，较佳地，所述第三金属层170可以由金制成。
步骤S114：通过第三光罩对所述有机半导体层、所述第二有机绝缘层和所述第三金属层进行图案化处理以形成顶栅电极；
具体地，如图6所示，在本发明的实施例中，可以采用黄光制程(如显影、湿刻、干刻等)通过第三光罩对所述有机半导体层150、所述第二有机绝缘层160和所述第三金属层170进行图形化处理，此时，处理后的第三金属层170作为顶栅电极170。所述顶栅电极170的俯视图的图案包括但不限于：直线图案、曲线图案、多边形图案、圆形图案、椭圆形图案、星形图案等图案，可以理解，具体的图案形状可根据实际使用来确定，本发明的实施方案在此不作具体限定。
参见图7，本发明实施例提供的双栅极器件的制作方法的第二实施例的流程示意图，该方法包括：
步骤S202：在一基板形成一第一金属层；
步骤S204：通过第一光罩对所述第一金属层进行图案化处理以形成底栅电极；
步骤S206：在所述底栅电极和所述基板上涂覆一第一有机绝缘层；
步骤S208：在所述第一有机绝缘层上溅镀形成第二金属层；
步骤S210：通过第二光罩对所述第二金属层进行图案化处理以形成源漏电极；
步骤S212：在所述源漏电极和所述第一有机绝缘层上依次覆盖一有机半导体层、一第二有机绝缘层和一第三金属层；
步骤S214：通过第三光罩对所述有机半导体层、所述第二有机绝缘层和所述第三金属层进行图案化处理以形成顶栅电极；
具体地，步骤S202至S214可以参考上述图1实施例中步骤S102至S114，这里不再赘述。
步骤S216：在所述第一有机绝缘层、所述有机半导体层、所述第二有机绝缘层和所述顶栅电极之上涂覆一钝化层，所述钝化层涂覆于远离所述基板的所述第一有机绝缘层的上表面，所述钝化层包覆所述第一有机绝缘层、所述有机半导体层、所述第二有机绝缘层和所述顶栅电极；
具体地，如图8所示，可以在所述第一有机绝缘层130、所述有机半导体层150、所述第二有机绝缘层160和所述顶栅电极170之上涂覆一层钝化层180，在本发明的实施例中，该钝化层180可为一有机玻璃层。所述钝化层180位于所述第一有机绝缘层130的上表面，所述钝化层180包覆所述有机半导体层150、所述第二有机绝缘层160和所述顶栅电极170。其中，所述钝化层180的正投影区域与所述基板110的正投影区域相同。
参见图8，图8是本发明实施例提供的双栅极器件的第二实施例的结构示意图。在本发明的实施例中，双栅极器件100包括：基板110、底栅电极120、第一有机绝缘层130、源漏电极140、有机半导体层150、第二有机绝缘层160和顶栅电极170和钝化层180。
所述基板110可以是PEN或PET或PI，并可通过溅镀等方式在该基板110的上表面形成一第一金属层，所述第一金属层的材料包含但不限于金、银、铜、铁等材料。较佳地，所述第一金属层的材料可以是金。可以采用黄光制程(如显影、湿刻、干刻等工艺)通过第一光罩对所述第一金属层进行图形化处理，此时，处理后的第一金属层可以作为底栅电极120。
所述底栅电极120可以位于所述基板110的上表面的中部。所述底栅电极120的俯视图的图案包括但不限于：直线图案、曲线图案、多边形图案、圆形图案、椭圆形图案、星形图案等图案，可以理解，具体的图案形状可根据实际使用来确定，本发明的实施方案在此不作具体限定。
所述第一有机绝缘层130位于所述底栅电极120和所述基板110之上，所述第一有机绝缘层130可以包覆所述底栅电极120；所述第一有机绝缘层130的远离所述底栅电极120的上表面可以为一平整面。
所述源漏电极140可以位于远离所述基板110的所述第一有机绝缘层130的上表面，具体可位于该上表面的中部；所述源漏电极140可以位于所述底栅电极120的正投影区域内，即所述源漏电极140位于所述底栅电极120的边界 所围成的区域范围之内。所述源漏电极140的俯视图的图案包括但不限于：直线图案、曲线图案、多边形图案、圆形图案、椭圆形图案、星形图案等图案，可以理解，具体的图案形状可根据实际使用来确定，本发明的实施方案在此不作具体限定。
所述有机半导体层150位于远离所述基板110的所述第一有机绝缘层130的上表面，所述有机半导体层150包覆所述源漏电极140；所述有机半导体层150的远离所述源漏电极140的上表面可以为一平整面，所述有机半导体层150的正投影区域可以与所述底栅电极120的正投影区域相同。
所述第二有机绝缘层160位于远离所述基板110的所述有机半导体层150的上表面；所述第二有机绝缘层160的远离所述源漏电极140的上表面可以为一平整面，所述第二有机绝缘层160的正投影区域可以与所述底栅电极120的正投影区域相同。
所述顶栅电极170位于远离所述基板110的所述第二有机绝缘层160的上表面；所述顶栅电极170的远离所述源漏电极140的上表面可以为一平整面，所述顶栅电极170的正投影区域可以与所述底栅电极120的正投影区域相同。所述顶栅电极170的俯视图的图案包括但不限于：直线图案、曲线图案、多边形图案、圆形图案、椭圆形图案、星形图案等图案，可以理解，具体的图案形状可根据实际使用来确定，本发明的实施方案在此不作具体限定。所述顶栅电极170的材料包含但不限于金、银、铜、铁等材料。较佳地，所述顶栅电极170的材料可以是金。
所述钝化层180位于远离所述基板110的所述第一有机绝缘层130的上表面，所述钝化层180包覆在所述有机半导体层150、所述第二有机绝缘层160和所述顶栅电极170之上。在本发明的实施例中，该钝化层180可为一有机玻璃层。其中，所述钝化层180的正投影区域与所述基板110的正投影区域相同。
可以理解的是，图8所示的双栅极器件可以根据图1或图7所示的双栅极器件的制作方法而制造而成的，此处不再赘述。
综上所述，通过实施本发明实施例，提供一种双栅极器件的制作方法及双栅极器件，OTFT(Organic Thin Film Transistor，有机薄膜晶体管)器件结构采用双栅极结构改善器件特性，本发明实施例具有如下有益效果：
1、双栅极结构能够减小阈值电压，增大开态电流，减小关态电流；
2、顶栅电极与源漏电极的交叠，使得OTFT器件的接触电阻减小，节约功耗。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)或随机存储记忆体(Random Access Memory，RAM)等。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。而且，描述的具体特征、结构、材料或特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (18)

  1. 一种双栅极器件的制作方法，其中，包括：
    在一基板形成一第一金属层；
    通过第一光罩对所述第一金属层进行图案化处理以形成底栅电极；
    在所述底栅电极和所述基板上涂覆一第一有机绝缘层；
    在所述第一有机绝缘层上溅镀形成第二金属层；
    通过第二光罩对所述第二金属层进行图案化处理以形成源漏电极；
    在所述源漏电极和所述第一有机绝缘层上依次覆盖一有机半导体层、一第二有机绝缘层和一第三金属层；
    通过第三光罩对所述有机半导体层、所述第二有机绝缘层和所述第三金属层进行图案化处理以形成顶栅电极。
  2. 如权利要求1所述的制作方法，其中，所述第一有机绝缘层包覆所述底栅电极，所述有机半导体层包覆所述源漏电极，所述顶栅电极与所述源漏电极之间交叠。
  3. 如权利要求1所述的制作方法，其中，所述源漏电极位于所述底栅电极的正投影区域内。
  4. 如权利要求1所述的制作方法，其中，所述底栅电极位于所述基板上表面的中部。
  5. 如权利要求1所述的制作方法，其中，所述有机半导体涂层远离所述源漏电极的表面为一平整面。
  6. 如权利要求1所述的制作方法，其中，所述顶栅电极与所述源漏电极之间相交叠。
  7. 如权利要求1所述的制作方法，其中，所述制作方法还包括：
    在所述第一有机绝缘层、所述有机半导体层、所述第二有机绝缘层和所述顶栅电极之上涂覆一钝化层，所述钝化层涂覆于远离所述基板的所述第一有机绝缘层的上表面，所述钝化层包覆所述有机半导体层、所述第二有机绝缘层和所述顶栅电极。
  8. 如权利要求7所述的方法，其中，所述钝化层的正投影区域与所述基板的正投影区域相同。
  9. 如权利要求1所述的方法，其中，所述基板由聚萘二甲酸乙二醇酯、聚对苯二甲酸乙二醇酯或聚酰亚胺制成，所述第一金属层、所述第二金属层及所述第三金属层由金、银、铜、铁中的任意一种材料制成。
  10. 一种双栅极器件，其中，包括：一基板、一底栅电极、一第一有机绝缘层、一源漏电极、一有机半导体层、一第二有机绝缘层和一顶栅电极，其中：
    所述底栅电极位于所述基板的上表面；
    所述第一有机绝缘层位于所述基板的上表面，且包覆所述底栅电极；
    所述源漏电极位于远离所述基板的所述第一有机绝缘层的上表面；
    所述有机半导体层位于远离所述基板的所述第一有机绝缘层的上表面，且所述有机半导体层包覆所述源漏电极；
    所述第二有机绝缘层位于远离所述基板的所述有机半导体层的上表面；
    所述顶栅电极位于远离所述基板的所述第二有机绝缘层的上表面。
  11. 如权利要求10所述的双栅极器件，其中，所述源漏电极位于所述底栅电极的正投影区域内，所述有机半导体层的上表面为一平整面。
  12. 如权利要求11所述的双栅极器件，其中，所述有机半导体层的正投影区域与所述底栅电极的正投影区域相同。
  13. 如权利要求11所述的双栅极器件，其中，所述第二有机绝缘层的上表面为一平整面，所述第二有机绝缘层的正投影区域与所述底栅电极的正投影区域相同。
  14. 如权利要求13所述的双栅极器件，其中，所述顶栅电极的上表面为一平整面，所述顶栅电极的正投影区域与所述底栅电极的正投影区域相同。
  15. 如权利要求10所述的双栅极器件，其中，所述顶栅电极与所述源漏电极之间交叠。
  16. 如权利要求10所述的双栅极器件，其中，所述双栅极器件还包括：
    一钝化层，所述钝化层位于远离所述基板的所述第一有机绝缘层的上表面，所述钝化层包覆所述有机半导体层、所述第二有机绝缘层和所述顶栅电极。
  17. 如权利要求16所述的双栅极器件，其中，所述钝化层的正投影区域与所述基板的正投影区域相同。
  18. 如权利要求10所述的双栅极器件，其中，所述基板由聚萘二甲酸乙二醇酯、聚对苯二甲酸乙二醇酯或聚酰亚胺制成，所述第一金属层、所述第二金属层及所述第三金属层由金、银、铜、铁中的任意一种材料制成。
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