WO2016161643A1 - Appareil et procédé d'égalisation de rétroaction de décision et système de transmission optique - Google Patents

Appareil et procédé d'égalisation de rétroaction de décision et système de transmission optique Download PDF

Info

Publication number
WO2016161643A1
WO2016161643A1 PCT/CN2015/076346 CN2015076346W WO2016161643A1 WO 2016161643 A1 WO2016161643 A1 WO 2016161643A1 CN 2015076346 W CN2015076346 W CN 2015076346W WO 2016161643 A1 WO2016161643 A1 WO 2016161643A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
equalizer
tap coefficient
coefficient
adder
Prior art date
Application number
PCT/CN2015/076346
Other languages
English (en)
Chinese (zh)
Inventor
马雅男
吴波
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2015/076346 priority Critical patent/WO2016161643A1/fr
Priority to CN201580078482.5A priority patent/CN107534629B/zh
Publication of WO2016161643A1 publication Critical patent/WO2016161643A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/01—Equalisers

Definitions

  • the present invention relates to the field of optical communication technologies, and in particular, to a decision feedback equalization apparatus, method, and optical transmission system.
  • the 10G rate optical transmission system has a dispersion tolerance of about 1000 ps/nm, and a 40G rate optical transmission system.
  • the dispersion tolerance is less than 65ps/nm, and the dispersion tolerance of the 100G optical transmission system is less than 10ps/nm, that is, the dispersion tolerance of the 100G system is only 1/100 of the 10G system, which causes errors in the transmission of optical signals.
  • the code rate is extremely high, which in turn causes the receiver to not receive the optical signal correctly.
  • the embodiment of the invention provides a decision feedback equalization device, a method and an optical transmission system, which further improve the equalization performance of the decision feedback equalization device, effectively reduce inter-symbol interference, and ensure that the receiving receiver can correctly receive the optical signal.
  • a decision feedback equalization apparatus including:
  • a first equalizer a first adder, a first decision unit, a second equalizer, a third equalizer, a second adder, and a second decision unit;
  • the first equalizer is configured to receive a signal and perform equalization processing on the received signal
  • the first adder is configured to add an output signal of the first equalizer and an output signal of the second equalizer
  • the first determining unit is configured to determine an output signal of the first adder
  • the second equalizer is configured to perform equalization processing on an output signal of the first determining unit
  • the third equalizer is configured to perform equalization processing on an output signal of the first adder
  • the second adder is configured to add an output signal of the third equalizer and an output signal of the second equalizer
  • the second determining unit is configured to determine an output signal of the second adder, and output the determined signal.
  • the decision feedback equalization apparatus further includes:
  • a fourth adder a first coefficient update module, a second coefficient update module, a fifth adder, and a third coefficient update module
  • the fourth adder is configured to add an output signal of the first determining unit and the first equalizer output signal to obtain a first error signal
  • the first coefficient update module is configured to update a first tap coefficient of the first equalizer according to the first error signal, and output the first tap coefficient to the first equalizer;
  • the second coefficient update module is configured to update a second tap coefficient of the second equalizer according to the first error signal, and output the second tap coefficient to the second equalizer;
  • the fifth adder is configured to add an output signal of the second determining unit and the third equalizer output signal to obtain a second error signal;
  • the third coefficient update module is configured to update a third tap coefficient of the third equalizer according to the second error signal, and output the third tap coefficient to the third equalizer.
  • the first coefficient update module, the second coefficient update module, and the third coefficient update module both update the tap coefficients by using a least mean square algorithm.
  • the first coefficient update module does not update the step size of the first tap coefficient of the first equalizer Equal to the second coefficient update module updating the step size of the second tap coefficient of the second equalizer.
  • the first possible implementation of the first aspect, the second possible implementation of the first aspect, or the third possible implementation of the first aspect, the fourth possibility in the first aspect are all horizontal digital filters.
  • a receiver including the decision feedback equalization apparatus described above.
  • an optical transmission system comprising a transmitter for transmitting an optical signal and the receiver described above.
  • a signal processing method including the steps of:
  • the method further includes the following steps:
  • the first tap coefficient, the second tap coefficient, and the third tap coefficient are all updated using a least mean square algorithm.
  • Updating the step size of the first tap coefficient is not equal to updating the step size of the second tap coefficient.
  • a data communication apparatus including a processor, a memory, and a bus system, the processor and the memory being connected by the bus system, the memory is configured to store an instruction, and the processor is configured to execute the instruction stored by the memory,
  • the processor is configured to receive the first signal, perform equalization processing on the received first signal, to obtain a second signal, add the second signal and the third signal to obtain a fourth signal, and obtain the fourth signal. Performing a decision to obtain a fifth signal; performing equalization processing on the fifth signal to integrate the equalization As a new third signal; performing equalization processing on the fourth signal to obtain a sixth signal; adding the sixth signal and the new third signal to obtain a seventh signal; The signal is judged and the eighth signal after the decision is output.
  • the processor is further configured to:
  • the first tap coefficient, the second tap coefficient, and Third tap coefficient are provided in a second possible implementation manner of the fifth aspect.
  • the step of updating the first tap coefficient is not equal to updating the second tap coefficient Step size.
  • the received signal is equalized by receiving the signal by the first equalizer; the first adder adds the output signal of the first equalizer and the output signal of the second equalizer;
  • the determining unit determines the output signal of the first adder; the second equalizer performs equalization processing on the output signal of the first determining unit; and the third equalizer equalizes the output signal of the first adder Processing; the second adder adds the output signal of the third equalizer and the output signal of the second equalizer; and the second determining unit is configured to determine, output the output signal of the second adder Signal after the judgment.
  • the equalization performance of the decision feedback equalization device is effectively improved by the multiplexing cascade mode, and the problem that the receiver cannot receive the correct signal due to the dispersion is solved, the bit error rate is further reduced, and the stability of the system is improved.
  • FIG. 1 is a schematic block diagram of an application scenario according to an embodiment of the present disclosure
  • FIG. 2 is a structural diagram of a decision feedback equalization apparatus according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of an internal principle of a first equalizer according to an embodiment of the present disclosure
  • FIG. 5 is a flowchart of a signal processing method according to an embodiment of the present invention.
  • FIG. 6 is a flowchart of another signal processing method according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a data communication apparatus according to an embodiment of the present invention.
  • FIG. 1 shows a schematic block diagram of an application scenario according to an embodiment of the present invention.
  • the short-distance optical interconnection system includes a transmitter 100, a multi-mode fiber (MMF), and a receiver 200.
  • the transmitter 100 includes an electric modulator, a driver, and a transmitting laser, and is electrically modulated.
  • the device loads the data information onto the electrical signal, and the driver adjusts the modulated electrical signal to a voltage range required by the transmitting laser, and the transmitting laser converts the electrical signal into an optical signal for transmission.
  • the emitted light is sent to the receiver 200 through the fiber link.
  • the receiver 200 includes a photoelectric converter, an amplifier and a decision feedback equalization device. After the photoelectric converter converts the optical signal into an electrical signal, the amplifier amplifies the electrical signal and then performs an equalization decision. Process the output for further processing.
  • the improvement of the present invention lies in the decision feedback equalization device of the receiver 200.
  • FIG. 2 is a structural diagram of a decision feedback equalization apparatus according to an embodiment of the present invention.
  • the decision feedback equalization apparatus 200 includes a first equalizer 201, a first adder 202, a first decision unit 203, a second equalizer 204, a third equalizer 205, a second adder 206, and a second decision unit 207.
  • the first equalizer 210 is configured to receive a signal and perform equalization processing on the received signal.
  • the first adder 220 is configured to add the output signal of the first equalizer 210 and the output signal of the second equalizer 204.
  • the first decision unit 230 is configured to determine the output signal of the first adder 220.
  • the second equalizer 204 is configured to perform equalization processing on the output signal of the first decision unit 230.
  • Third equilibrium The unit 205 is configured to perform equalization processing on the output signal of the first adder 206.
  • the second adder 206 is for adding the output signal of the third equalizer 205 and the output signal of the second equalizer 204.
  • the second decision unit 207 is configured to determine the output signal of the second adder 206 and output the determined signal.
  • the first equalizer is configured to perform equalization processing on the to-be-processed symbol at the current sampling time to obtain a first estimated value of the to-be-processed symbol, where the first estimated value of the to-be-processed symbol is located in the current sampling moment.
  • the first adder superimposes the first estimated value output by the first equalizer and the second estimated value output by the second equalizer to obtain a third estimated value.
  • the first determining unit determines the third estimated value to obtain a decision value of the third estimated value.
  • the second equalizer receives the decision value of the third estimated value, and performs equalization processing on the decision value of the third estimated value to be processed at the current sampling time to obtain the second estimated value, and the second estimated value is used as a new third. estimated value.
  • the second estimated value is equal to a sum of products of all decision values located in the second equalizer and their corresponding tap coefficients at the current sampling instant.
  • the third equalizer receives the third estimated value, and performs equalization processing on the third estimated value to be processed at the current sampling time to obtain a fourth estimated value, where the fourth estimated value is equal to the current sampling time is located in the third equalizer. The sum of the products of all third estimates and their corresponding tap coefficients.
  • a second adder configured to superimpose the fourth estimated value and the second estimated value output by the second equalizer at the current sampling time to obtain a fifth estimated value.
  • a second determining unit configured to determine the fifth estimated value to obtain a decision value of the fifth estimated value.
  • the first equalizer 201, the second equalizer 204, and the third equalizer 205 are all horizontal digital filters.
  • the specific principle of the horizontal digital filter is described in detail below.
  • the first equalizer 201 is a transversal filter having 2N+1 taps, and the transversal filter is composed of 2N horizontally arranged delay units T b and 2N+1 taps, and the tap coefficient sequence is expressed as ⁇ c - N , ... c 0 , ... c N ⁇ , as shown in Fig. 3. Assuming the kth sampling instant, the output signal is equal to:
  • x kn is the symbol located in the first equalizer 201 at the kth sampling time
  • c n is the tap coefficient of the first equalizer 2N+1 taps. It can be seen that the first estimate output by the first equalizer at the kth sampling instant will be determined by the sum of 2N+1 c i and x ki products.
  • the first equalizer 201 is a transversal filter having three taps.
  • the fourth adder 208 is configured to add the output signal of the first decision unit and the first equalizer output signal to obtain a first error signal.
  • the first coefficient update module 209 is configured to update the second tap coefficient of the second equalizer according to the first error signal, and output the second tap coefficient to the second equalizer.
  • the second coefficient updating module 210 is configured to update the second tap coefficient of the second equalizer according to the first error signal, and output the second tap coefficient to the second equalizer.
  • the fifth adder 211 is configured to add the output signal of the second determining unit and the third equalizer output signal to obtain a second error signal.
  • the third coefficient updating module 212 is configured to update the third tap coefficient of the third equalizer according to the second error signal, and output the third tap coefficient to the third equalizer.
  • the first coefficient update module 209, the second coefficient update module 210, and the third coefficient update module 212 may adopt, for example, a Least Mean Square (LMS) coefficient update algorithm.
  • LMS Least Mean Square
  • w(n+1) is the updated tap coefficient
  • w(n) is the tap coefficient before the update
  • ⁇ is the step size of the tap coefficient update
  • the error decision error e(n) is equal to d(n)-y(n)
  • d(n) is the decision value
  • y(n) is the output value of the equalizer
  • x(n) is the input value of the equalizer
  • y(n) w T (n)x(n)
  • w T ( n) is the transposed matrix of the equalizer tap coefficient matrix.
  • the steps of the first equalizer 201, the second equalizer 204, and the third equalizer 205 can be arbitrarily set.
  • the step of updating the first tap coefficient of the first equalizer by the first coefficient update module is not equal to the step size of updating the second tap coefficient of the second equalizer by the second coefficient update module.
  • the first equalizer 201 and the third equalizer 205 multiplex the second equalizer 204. It has become a two-stage DFE equalization system, which effectively improves the equalization performance compared with the traditional FFE equalizer. Moreover, even if the first-level equalization error occurs, the current correct data stored in the second-level equalizer can be used to timely correct the first-order balanced output to prevent the occurrence of the error, so that the receiver can normally receive the correct signal.
  • FIG. 4 is a diagram of a balanced effect of a decision feedback equalization apparatus according to an embodiment of the present invention.
  • Fig. 3(a) is an eye diagram before equalization
  • Fig. 3(b) is an eye diagram after equalization.
  • the decision feedback equalization device disclosed in the embodiment of the invention is applied to a short-distance optical interconnection system, and the inter-code crosstalk between systems is eliminated by equalization to ensure that the receiver can correctly receive data.
  • the present invention is not limited thereto, and any system that uses the decision feedback equalization apparatus disclosed in the embodiments of the present invention is included in the scope of the present invention.
  • an embodiment of the present invention provides a signal processing method. As shown in FIG. 4, the process includes the following steps:
  • the following signal processing flow can be performed by the decision feedback equalization apparatus shown in FIG. 2 above.
  • the flow of each unit or module in the specific equalization apparatus is as follows:
  • Step 501 The first equalizer 201 receives the first signal, and performs equalization processing on the received first signal to obtain a second signal.
  • Step 502 the first adder 202 adds the second signal and the third signal to obtain a fourth signal.
  • Step 503 the first determining unit 203 determines the fourth signal to obtain a fifth signal.
  • Step 504 The second equalizer 204 performs equalization processing on the fifth signal, and uses the equalization result as a new third signal.
  • Step 505 The third equalizer 205 performs equalization processing on the fourth signal to obtain a sixth signal.
  • Step 506 the second adder 206 adds the sixth signal and the new third signal to obtain a seventh signal.
  • Step S507 the second determining unit 207 determines the seventh signal, and outputs the eighth signal after the decision.
  • step 503 further includes the following steps:
  • Step S508 the fourth adder 208 adds the fifth signal and the second signal to obtain a first error signal.
  • Step S509 the first coefficient updating module 209 updates the first tap coefficient according to the first error signal, and outputs the first tap coefficient to the first equalizer 201.
  • Step S510 the second coefficient updating module 210 updates the second tap coefficient according to the first error signal, and outputs the second tap coefficient to the second equalizer 204.
  • the step S507 further includes the following steps:
  • step S511 the fifth adder 211 adds the eighth signal and the sixth signal to obtain a second error signal.
  • Step S512 the third coefficient updating module 212 updates the third tap coefficient according to the second error signal, and outputs the third tap coefficient to the third equalizer 205.
  • the above-mentioned signal processing flow can be performed by the decision feedback equalization apparatus shown in FIG. 2 above.
  • the specific implementation process refer to the specific description of the embodiment of FIG. 2, and details are not described herein again.
  • the first equalizer 201 and the third equalizer 205 multiplex the second equalizer 204 to form a two-stage DFE equalization system, which effectively improves the equalization performance compared with the conventional FFE equalizer. Moreover, even if the first-level equalization error occurs, the current correct data stored in the second-level equalizer can be used to timely correct the first-order balanced output to prevent the occurrence of the error, so that the receiver can normally receive the correct signal.
  • an embodiment of the present invention further provides a data communication apparatus 700.
  • the apparatus 700 includes a processor 710, a memory 720, and a bus system 730.
  • the processor 710 and the memory 720 are connected by the bus system 730.
  • the memory 720 is configured to store instructions, and the processor 710 is configured to execute the instructions stored in the memory 720, wherein the processor 710 is configured to receive the first signal, perform equalization processing on the received first signal, to obtain a second signal; Adding the second signal and the third signal to obtain a fourth signal; determining the fourth signal to obtain a fifth signal; performing equalization processing on the fifth signal, and using the equalization result as a new third a signal; performing equalization processing on the fourth signal to obtain a sixth signal; adding the sixth signal and the new third signal to obtain a seventh signal; performing a decision on the seventh signal, and outputting a decision After the eighth signal.
  • the processor 710 is further configured to add the fifth signal and the second signal to obtain a first error signal; update the first tap coefficient according to the first error signal, and output the first a tap coefficient; updating a second tap coefficient according to the first error signal, and outputting the second tap coefficient; adding the eighth signal and the sixth signal to obtain a second error signal; The second error signal updates the third tap coefficient and outputs the third tap coefficient.
  • the first tap coefficient, the second tap coefficient and the third tap coefficient are updated by a least mean square algorithm.
  • updating the step size of the first tap coefficient is not equal to updating the step size of the second tap coefficient.
  • the equalization performance of the decision feedback equalization device is effectively improved by the multiplexing cascade mode, and the problem that the receiver cannot receive the correct signal due to the dispersion is solved, the bit error rate is further reduced, and the stability of the system is improved.
  • the processor 710 may be a central processing unit (“CPU"), and the processor 710 may also be other general-purpose processors, digital signal processors (DSPs).
  • DSPs digital signal processors
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the memory 720 can include read only memory and random access memory and provides instructions and data to the processor 710. A portion of the memory 720 can also include a non-volatile random access memory. For example, the memory 720 can also store information of the device type.
  • the bus system 730 may include a power bus, a control bus, a status signal bus, and the like in addition to the data bus. However, for clarity of description, various buses are labeled as bus system 730 in the figure.
  • the disclosed systems, devices, and The method can be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, or an electrical, mechanical or other form of connection.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present invention.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • the technical solution of the present invention contributes in essence or to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium.
  • a number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

La présente invention concerne un appareil et un procédé d'égalisation de rétroaction de décision et un système de transmission optique. L'appareil d'égalisation de rétroaction de décision consiste en un premier égaliseur, un premier additionneur, une première unité de décision, un deuxième égaliseur, un troisième additionneur, un deuxième égaliseur et une deuxième unité de décision. Selon les modes de réalisation de la présente invention, au moyen d'un multiplexage et d'une cascade, la performance d'égalisation d'un appareil d'égalisation de rétroaction de décision est effectivement améliorée, le problème selon lequel un récepteur ne peut pas recevoir le correct signal en raison de la dispersion chromatique est résolu, le taux d'erreur binaire est en outre réduit, la stabilité du système est améliorée et les exigences d'un système de 40G à 100G peut être satisfaite.
PCT/CN2015/076346 2015-04-10 2015-04-10 Appareil et procédé d'égalisation de rétroaction de décision et système de transmission optique WO2016161643A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2015/076346 WO2016161643A1 (fr) 2015-04-10 2015-04-10 Appareil et procédé d'égalisation de rétroaction de décision et système de transmission optique
CN201580078482.5A CN107534629B (zh) 2015-04-10 2015-04-10 判决反馈均衡装置、方法及光传输系统

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2015/076346 WO2016161643A1 (fr) 2015-04-10 2015-04-10 Appareil et procédé d'égalisation de rétroaction de décision et système de transmission optique

Publications (1)

Publication Number Publication Date
WO2016161643A1 true WO2016161643A1 (fr) 2016-10-13

Family

ID=57071713

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/076346 WO2016161643A1 (fr) 2015-04-10 2015-04-10 Appareil et procédé d'égalisation de rétroaction de décision et système de transmission optique

Country Status (2)

Country Link
CN (1) CN107534629B (fr)
WO (1) WO2016161643A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109981500A (zh) * 2017-12-28 2019-07-05 海思光电子有限公司 一种信号处理的方法及信号处理装置

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113595949B (zh) 2021-09-30 2021-12-21 苏州浪潮智能科技有限公司 自适应pam4判决反馈均衡电路
CN115314347A (zh) * 2022-07-28 2022-11-08 苏州大学 基于高斯混合模型的光信号判决反馈均衡器

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101635576A (zh) * 2008-07-25 2010-01-27 台湾积体电路制造股份有限公司 用于判决反馈均衡器的加法器的输入控制电路
CN101807940A (zh) * 2010-01-22 2010-08-18 北京航空航天大学 一种gnss接收系统的抗多径干扰装置及其方法
CN102164106A (zh) * 2011-04-15 2011-08-24 南京信息工程大学 分数间隔判决反馈瑞利Renyi熵小波盲均衡方法
CN102647376A (zh) * 2012-03-14 2012-08-22 华为技术有限公司 信号处理方法和装置、及终端
CN103229473A (zh) * 2012-12-28 2013-07-31 华为技术有限公司 判决反馈均衡器和接收机

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3499768B2 (ja) * 1999-04-05 2004-02-23 松下電器産業株式会社 波形等化器及びこれを用いた移動無線装置、基地局無線装置並びに移動通信システム
CN100562076C (zh) * 2006-06-29 2009-11-18 上海高清数字科技产业有限公司 时域自适应均衡器及其包含的判决反馈滤波器
JP4648363B2 (ja) * 2007-06-13 2011-03-09 株式会社日立製作所 光伝送装置および光伝送装置制御方法
CN103401821B (zh) * 2013-07-22 2017-02-22 苏州英菲泰尔电子科技有限公司 蓝牙4.0低功耗接收机自适应均衡器及其实现方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101635576A (zh) * 2008-07-25 2010-01-27 台湾积体电路制造股份有限公司 用于判决反馈均衡器的加法器的输入控制电路
CN101807940A (zh) * 2010-01-22 2010-08-18 北京航空航天大学 一种gnss接收系统的抗多径干扰装置及其方法
CN102164106A (zh) * 2011-04-15 2011-08-24 南京信息工程大学 分数间隔判决反馈瑞利Renyi熵小波盲均衡方法
CN102647376A (zh) * 2012-03-14 2012-08-22 华为技术有限公司 信号处理方法和装置、及终端
CN103229473A (zh) * 2012-12-28 2013-07-31 华为技术有限公司 判决反馈均衡器和接收机

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109981500A (zh) * 2017-12-28 2019-07-05 海思光电子有限公司 一种信号处理的方法及信号处理装置
CN109981500B (zh) * 2017-12-28 2023-04-28 海思光电子有限公司 一种信号处理的方法及信号处理装置

Also Published As

Publication number Publication date
CN107534629B (zh) 2020-02-14
CN107534629A (zh) 2018-01-02

Similar Documents

Publication Publication Date Title
US8260156B2 (en) Adaptive crossing frequency domain equalization (FDE) in digital PolMux coherent systems
US8442406B2 (en) Filter, coherent receiver device and coherent receiving method
JP5353878B2 (ja) 波形等化回路および波形等化方法
WO2004004192A2 (fr) Procede et appareil pour l'egalisation de canaux
JP6485670B2 (ja) 光信号を復号する方法、並びに光信号を受信及び復号する受信機
US10009195B2 (en) Nonlinear equalizer
US9935682B1 (en) System and method for PAM-4 transmitter bit equalization for improved channel performance
WO2016161643A1 (fr) Appareil et procédé d'égalisation de rétroaction de décision et système de transmission optique
WO2021121056A1 (fr) Procédé d'égalisation de domaine fréquentiel, égaliseur, récepteur optique et système
CN104410593B (zh) 基于判决反馈模型的数字符号非线性误差修正均衡方法
US20020191257A1 (en) Compensation of polarization mode dispersion in single mode fiber for maximum-likelihood sequence estimation
JP4386196B2 (ja) パーシャル・レスポンス伝送システムおよびそのイコライズ回路
WO2018120615A1 (fr) Dispositif et procédé destinés à une égalisation de rétroaction de décision adaptative, et support d'informations
JP2018518077A (ja) マルチチャネル受信機におけるクロックリカバリおよび等化器推定
EP2487848B1 (fr) Égaliseur de phase temporelle continue analogique pour la transmission de données
Shah et al. Low-complexity design of noninteger fractionally spaced adaptive equalizers for coherent optical receivers
WO2018006800A1 (fr) Procédé, appareil, et système d'équilibrage d'horloge pour système qpsk
JP2008219078A (ja) 等化回路および歪軽減方法
JP4515418B2 (ja) 等化回路
CN107078978B (zh) 一种信号补偿方法和设备
Glentis et al. Cost-effective adaptive optical network technologies for Metropolitan Area Networks
KR102656362B1 (ko) 비선형 왜곡을 완화하기 위한 프리코딩 방법 및 이를 수행하는 프리코더
US20230308318A1 (en) Method of equalization for high-speed processing and equalizer thereof
WO2023152947A1 (fr) Système de communication, récepteur, circuit de traitement de signal d'égalisation, procédé et support lisible par ordinateur
Aziz et al. A class of downsampled floating tap DFE architectures with application to serial links

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15888199

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15888199

Country of ref document: EP

Kind code of ref document: A1