WO2016161643A1

WO2016161643A1 - Decision feedback equalization apparatus and method, and optical transmission system

Info

Publication number: WO2016161643A1
Application number: PCT/CN2015/076346
Authority: WO
Inventors: 马雅男; 吴波
Original assignee: 华为技术有限公司
Priority date: 2015-04-10
Filing date: 2015-04-10
Publication date: 2016-10-13
Also published as: CN107534629B; CN107534629A

Abstract

Disclosed are a decision feedback equalization apparatus and method, and an optical transmission system. The decision feedback equalization apparatus comprises a first equalizer, a first adder, a first decision unit, a second equalizer, a third equalizer, a second adder and a second decision unit. In the embodiments of the present invention, by means of multiplexing and cascading, the equalization performance of a decision feedback equalization apparatus is effectively improved, the problem that a receiver cannot receive the correct signal due to chromatic dispersion is solved, the bit error rate is further reduced, system stability is improved, and the requirements of a 40G to 100G system can be satisfied.

Description

Decision feedback equalization device, method and optical transmission system

Technical field

The present invention relates to the field of optical communication technologies, and in particular, to a decision feedback equalization apparatus, method, and optical transmission system.

Background technique

As optical transmission systems continue to develop in the direction of ultra-high speed (Ultra-high speed, Ultra-long haul, Ultra-large capacity, 3U), the chromatic dispersion of optical fibers (CD, Chromatic Dispersion) Factors such as Polarization Mode Dispersion (PMD) and Optical Signal Noise Ratio (OSNR) have an increasing impact on the performance of transmission systems. The Inter Symbol Interference (ISI) caused by dispersion causes a high bit error rate (BER), which prevents the receiver from receiving the correct signal. The receiver needs to use an equalizer for equalization. In terms of dispersion tolerance, as the link rate continues to increase, its tolerance is drastically reduced. For example, in the same modulation format, the 10G rate optical transmission system has a dispersion tolerance of about 1000 ps/nm, and a 40G rate optical transmission system. The dispersion tolerance is less than 65ps/nm, and the dispersion tolerance of the 100G optical transmission system is less than 10ps/nm, that is, the dispersion tolerance of the 100G system is only 1/100 of the 10G system, which causes errors in the transmission of optical signals. The code rate is extremely high, which in turn causes the receiver to not receive the optical signal correctly.

Summary of the invention

The embodiment of the invention provides a decision feedback equalization device, a method and an optical transmission system, which further improve the equalization performance of the decision feedback equalization device, effectively reduce inter-symbol interference, and ensure that the receiving receiver can correctly receive the optical signal.

In a first aspect, a decision feedback equalization apparatus is provided, including:

a first equalizer, a first adder, a first decision unit, a second equalizer, a third equalizer, a second adder, and a second decision unit;

The first equalizer is configured to receive a signal and perform equalization processing on the received signal;

The first adder is configured to add an output signal of the first equalizer and an output signal of the second equalizer;

The first determining unit is configured to determine an output signal of the first adder;

The second equalizer is configured to perform equalization processing on an output signal of the first determining unit;

The third equalizer is configured to perform equalization processing on an output signal of the first adder;

The second adder is configured to add an output signal of the third equalizer and an output signal of the second equalizer;

The second determining unit is configured to determine an output signal of the second adder, and output the determined signal.

In conjunction with the first aspect, in a first possible implementation of the first aspect, the decision feedback equalization apparatus further includes:

a fourth adder, a first coefficient update module, a second coefficient update module, a fifth adder, and a third coefficient update module;

The fourth adder is configured to add an output signal of the first determining unit and the first equalizer output signal to obtain a first error signal;

The first coefficient update module is configured to update a first tap coefficient of the first equalizer according to the first error signal, and output the first tap coefficient to the first equalizer;

The second coefficient update module is configured to update a second tap coefficient of the second equalizer according to the first error signal, and output the second tap coefficient to the second equalizer;

The fifth adder is configured to add an output signal of the second determining unit and the third equalizer output signal to obtain a second error signal;

The third coefficient update module is configured to update a third tap coefficient of the third equalizer according to the second error signal, and output the third tap coefficient to the third equalizer.

In conjunction with the first aspect, in a second possible implementation manner of the first aspect, the first coefficient update module, the second coefficient update module, and the third coefficient update module both update the tap coefficients by using a least mean square algorithm.

In conjunction with the second possible implementation of the first aspect, in a third possible implementation manner of the first aspect, the first coefficient update module does not update the step size of the first tap coefficient of the first equalizer Equal to the second coefficient update module updating the step size of the second tap coefficient of the second equalizer.

In conjunction with the first aspect, the first possible implementation of the first aspect, the second possible implementation of the first aspect, or the third possible implementation of the first aspect, the fourth possibility in the first aspect In the implementation manner, the first equalizer, the second equalizer, and the third equalizer are all horizontal digital filters.

In a second aspect, a receiver is provided, including the decision feedback equalization apparatus described above.

In a third aspect, an optical transmission system is provided, comprising a transmitter for transmitting an optical signal and the receiver described above.

In a fourth aspect, a signal processing method is provided, including the steps of:

Receiving a first signal, performing equalization processing on the received first signal to obtain a second signal;

Adding the second signal and the third signal to obtain a fourth signal;

Determining the fourth signal to obtain a fifth signal;

Performing equalization processing on the fifth signal, and using the equalization result as a new third signal;

Performing equalization processing on the fourth signal to obtain a sixth signal;

Adding the sixth signal and the new third signal to obtain a seventh signal;

Determining the seventh signal, and outputting the eighth signal after the decision.

In combination with the fourth aspect, in a first possible implementation manner, the method further includes the following steps:

Adding the fifth signal and the second signal to obtain a first error signal;

Updating a first tap coefficient according to the first error signal, and outputting the first tap coefficient;

Updating a second tap coefficient according to the first error signal, and outputting the second tap coefficient;

Adding the eighth signal and the sixth signal to obtain a second error signal;

Updating the third tap coefficient according to the second error signal, and outputting the third tap coefficient.

With reference to the fourth aspect or the first possible implementation manner of the fourth aspect, in a second possible implementation manner of the fourth aspect,

The first tap coefficient, the second tap coefficient, and the third tap coefficient are all updated using a least mean square algorithm.

With reference to the fourth aspect or the second possible implementation manner of the fourth aspect, in a third possible implementation manner of the fourth aspect,

Updating the step size of the first tap coefficient is not equal to updating the step size of the second tap coefficient.

In a fifth aspect, a data communication apparatus is provided, including a processor, a memory, and a bus system, the processor and the memory being connected by the bus system, the memory is configured to store an instruction, and the processor is configured to execute the instruction stored by the memory,

The processor is configured to receive the first signal, perform equalization processing on the received first signal, to obtain a second signal, add the second signal and the third signal to obtain a fourth signal, and obtain the fourth signal. Performing a decision to obtain a fifth signal; performing equalization processing on the fifth signal to integrate the equalization As a new third signal; performing equalization processing on the fourth signal to obtain a sixth signal; adding the sixth signal and the new third signal to obtain a seventh signal; The signal is judged and the eighth signal after the decision is output.

In conjunction with the fifth aspect, in a first possible implementation manner of the fifth aspect, the processor is further configured to:

Adding the fifth signal and the second signal to obtain a first error signal;

Adding the eighth signal and the sixth signal to obtain a second error signal;

With reference to the fifth aspect or the first possible implementation manner of the fifth aspect, in a second possible implementation manner of the fifth aspect, the first tap coefficient, the second tap coefficient, and Third tap coefficient.

With reference to the fifth aspect or the second possible implementation manner of the fifth aspect, in a third possible implementation manner of the fifth aspect, the step of updating the first tap coefficient is not equal to updating the second tap coefficient Step size.

According to the above technical solution, the received signal is equalized by receiving the signal by the first equalizer; the first adder adds the output signal of the first equalizer and the output signal of the second equalizer; The determining unit determines the output signal of the first adder; the second equalizer performs equalization processing on the output signal of the first determining unit; and the third equalizer equalizes the output signal of the first adder Processing; the second adder adds the output signal of the third equalizer and the output signal of the second equalizer; and the second determining unit is configured to determine, output the output signal of the second adder Signal after the judgment. In the embodiment of the invention, the equalization performance of the decision feedback equalization device is effectively improved by the multiplexing cascade mode, and the problem that the receiver cannot receive the correct signal due to the dispersion is solved, the bit error rate is further reduced, and the stability of the system is improved.

DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings to be used in the embodiments of the present invention will be briefly described below. It is obvious that the drawings described below are only some embodiments of the present invention, One of ordinary skill in the art, without creative labor Further drawings can also be obtained from these drawings.

FIG. 1 is a schematic block diagram of an application scenario according to an embodiment of the present disclosure;

2 is a structural diagram of a decision feedback equalization apparatus according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an internal principle of a first equalizer according to an embodiment of the present disclosure;

4 is a balanced effect diagram of an equalization apparatus according to an embodiment of the present invention;

FIG. 5 is a flowchart of a signal processing method according to an embodiment of the present invention; FIG.

FIG. 6 is a flowchart of another signal processing method according to an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a data communication apparatus according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of the present invention.

FIG. 1 shows a schematic block diagram of an application scenario according to an embodiment of the present invention. As shown in FIG. 1, the short-distance optical interconnection system includes a transmitter 100, a multi-mode fiber (MMF), and a receiver 200. The transmitter 100 includes an electric modulator, a driver, and a transmitting laser, and is electrically modulated. The device loads the data information onto the electrical signal, and the driver adjusts the modulated electrical signal to a voltage range required by the transmitting laser, and the transmitting laser converts the electrical signal into an optical signal for transmission. The emitted light is sent to the receiver 200 through the fiber link. The receiver 200 includes a photoelectric converter, an amplifier and a decision feedback equalization device. After the photoelectric converter converts the optical signal into an electrical signal, the amplifier amplifies the electrical signal and then performs an equalization decision. Process the output for further processing. The improvement of the present invention lies in the decision feedback equalization device of the receiver 200.

As shown in FIG. 2, FIG. 2 is a structural diagram of a decision feedback equalization apparatus according to an embodiment of the present invention. The decision feedback equalization apparatus 200 includes a first equalizer 201, a first adder 202, a first decision unit 203, a second equalizer 204, a third equalizer 205, a second adder 206, and a second decision unit 207.

The first equalizer 210 is configured to receive a signal and perform equalization processing on the received signal. The first adder 220 is configured to add the output signal of the first equalizer 210 and the output signal of the second equalizer 204. The first decision unit 230 is configured to determine the output signal of the first adder 220. The second equalizer 204 is configured to perform equalization processing on the output signal of the first decision unit 230. Third equilibrium The unit 205 is configured to perform equalization processing on the output signal of the first adder 206. The second adder 206 is for adding the output signal of the third equalizer 205 and the output signal of the second equalizer 204. The second decision unit 207 is configured to determine the output signal of the second adder 206 and output the determined signal.

Specifically, the first equalizer is configured to perform equalization processing on the to-be-processed symbol at the current sampling time to obtain a first estimated value of the to-be-processed symbol, where the first estimated value of the to-be-processed symbol is located in the current sampling moment. The sum of the values of all symbols in the first equalizer and their corresponding tap coefficients. The first adder superimposes the first estimated value output by the first equalizer and the second estimated value output by the second equalizer to obtain a third estimated value. The first determining unit determines the third estimated value to obtain a decision value of the third estimated value. The second equalizer receives the decision value of the third estimated value, and performs equalization processing on the decision value of the third estimated value to be processed at the current sampling time to obtain the second estimated value, and the second estimated value is used as a new third. estimated value. The second estimated value is equal to a sum of products of all decision values located in the second equalizer and their corresponding tap coefficients at the current sampling instant. The third equalizer receives the third estimated value, and performs equalization processing on the third estimated value to be processed at the current sampling time to obtain a fourth estimated value, where the fourth estimated value is equal to the current sampling time is located in the third equalizer. The sum of the products of all third estimates and their corresponding tap coefficients. And a second adder, configured to superimpose the fourth estimated value and the second estimated value output by the second equalizer at the current sampling time to obtain a fifth estimated value. And a second determining unit, configured to determine the fifth estimated value to obtain a decision value of the fifth estimated value.

In this embodiment, the first equalizer 201, the second equalizer 204, and the third equalizer 205 are all horizontal digital filters. The specific principle of the horizontal digital filter is described in detail below.

For example, the first equalizer 201 is a transversal filter having 2N+1 taps, and the transversal filter is composed of 2N horizontally arranged delay units T _b and 2N+1 taps, and the tap coefficient sequence is expressed as { c _{- N} , ... c ₀ , ... c _N }, as shown in Fig. 3. Assuming the kth sampling instant, the output signal is equal to:

Where x _kn is the symbol located in the first equalizer 201 at the kth sampling time, and c _n is the tap coefficient of the first equalizer 2N+1 taps. It can be seen that the first estimate output by the first equalizer at the kth sampling instant will be determined _{by the} sum of 2N+1 c _i and x _ki products.

When N=1, the first equalizer 201 is a transversal filter having three taps.

When k=1,

When k=2,

.

When k=n,

It can be seen from the above that all the symbols located in the first equalizer 201 at the nth (n is a natural number) are x _n+1 , x _n , x _n-1 , including the current sampling time to be processed symbol x _n .

The decision feedback equalization apparatus in the embodiment of the present invention further includes:

The fourth adder 208 is configured to add the output signal of the first decision unit and the first equalizer output signal to obtain a first error signal.

The first coefficient update module 209 is configured to update the second tap coefficient of the second equalizer according to the first error signal, and output the second tap coefficient to the second equalizer.

The second coefficient updating module 210 is configured to update the second tap coefficient of the second equalizer according to the first error signal, and output the second tap coefficient to the second equalizer.

The fifth adder 211 is configured to add the output signal of the second determining unit and the third equalizer output signal to obtain a second error signal.

The third coefficient updating module 212 is configured to update the third tap coefficient of the third equalizer according to the second error signal, and output the third tap coefficient to the third equalizer.

The first coefficient update module 209, the second coefficient update module 210, and the third coefficient update module 212 may adopt, for example, a Least Mean Square (LMS) coefficient update algorithm. The adjustment formula is:

w(n+1)=w(n)+μe(n)x(n),

Where w(n+1) is the updated tap coefficient, w(n) is the tap coefficient before the update, μ is the step size of the tap coefficient update, and the error decision error e(n) is equal to d(n)-y(n) ), d(n) is the decision value, y(n) is the output value of the equalizer, x(n) is the input value of the equalizer, y(n)=w ^T (n)x(n), w ^T ( n) is the transposed matrix of the equalizer tap coefficient matrix.

The steps of the first equalizer 201, the second equalizer 204, and the third equalizer 205 can be arbitrarily set. Preferably, the step of updating the first tap coefficient of the first equalizer by the first coefficient update module is not equal to the step size of updating the second tap coefficient of the second equalizer by the second coefficient update module.

In this embodiment, the first equalizer 201 and the third equalizer 205 multiplex the second equalizer 204. It has become a two-stage DFE equalization system, which effectively improves the equalization performance compared with the traditional FFE equalizer. Moreover, even if the first-level equalization error occurs, the current correct data stored in the second-level equalizer can be used to timely correct the first-order balanced output to prevent the occurrence of the error, so that the receiver can normally receive the correct signal.

As shown in FIG. 4, FIG. 4 is a diagram of a balanced effect of a decision feedback equalization apparatus according to an embodiment of the present invention. Fig. 3(a) is an eye diagram before equalization, and Fig. 3(b) is an eye diagram after equalization. By comparison, it is found that the decision feedback equalization apparatus of the embodiment of the present invention can significantly reduce the bit error rate, and can realize error-free transmission, which further proves the effectiveness of the decision feedback equalization apparatus of the embodiment of the present invention.

The decision feedback equalization device disclosed in the embodiment of the invention is applied to a short-distance optical interconnection system, and the inter-code crosstalk between systems is eliminated by equalization to ensure that the receiver can correctly receive data. Of course, the present invention is not limited thereto, and any system that uses the decision feedback equalization apparatus disclosed in the embodiments of the present invention is included in the scope of the present invention.

Based on the above embodiment, an embodiment of the present invention provides a signal processing method. As shown in FIG. 4, the process includes the following steps:

The following signal processing flow can be performed by the decision feedback equalization apparatus shown in FIG. 2 above. The flow of each unit or module in the specific equalization apparatus is as follows:

Step 501: The first equalizer 201 receives the first signal, and performs equalization processing on the received first signal to obtain a second signal.

Step 502, the first adder 202 adds the second signal and the third signal to obtain a fourth signal.

Step 503, the first determining unit 203 determines the fourth signal to obtain a fifth signal.

Step 504: The second equalizer 204 performs equalization processing on the fifth signal, and uses the equalization result as a new third signal.

Step 505: The third equalizer 205 performs equalization processing on the fourth signal to obtain a sixth signal.

Step 506, the second adder 206 adds the sixth signal and the new third signal to obtain a seventh signal.

Step S507, the second determining unit 207 determines the seventh signal, and outputs the eighth signal after the decision.

For the equalizer whose tap coefficient is dynamically adjustable, as shown in FIG. 6, the above step 503 further includes the following steps:

Step S508, the fourth adder 208 adds the fifth signal and the second signal to obtain a first error signal.

Step S509, the first coefficient updating module 209 updates the first tap coefficient according to the first error signal, and outputs the first tap coefficient to the first equalizer 201.

Step S510, the second coefficient updating module 210 updates the second tap coefficient according to the first error signal, and outputs the second tap coefficient to the second equalizer 204.

The step S507 further includes the following steps:

In step S511, the fifth adder 211 adds the eighth signal and the sixth signal to obtain a second error signal.

Step S512, the third coefficient updating module 212 updates the third tap coefficient according to the second error signal, and outputs the third tap coefficient to the third equalizer 205.

The above-mentioned signal processing flow can be performed by the decision feedback equalization apparatus shown in FIG. 2 above. For the specific implementation process, refer to the specific description of the embodiment of FIG. 2, and details are not described herein again.

In this embodiment, the first equalizer 201 and the third equalizer 205 multiplex the second equalizer 204 to form a two-stage DFE equalization system, which effectively improves the equalization performance compared with the conventional FFE equalizer. Moreover, even if the first-level equalization error occurs, the current correct data stored in the second-level equalizer can be used to timely correct the first-order balanced output to prevent the occurrence of the error, so that the receiver can normally receive the correct signal.

As shown in FIG. 6, an embodiment of the present invention further provides a data communication apparatus 700. The apparatus 700 includes a processor 710, a memory 720, and a bus system 730. The processor 710 and the memory 720 are connected by the bus system 730. The memory 720 is configured to store instructions, and the processor 710 is configured to execute the instructions stored in the memory 720, wherein the processor 710 is configured to receive the first signal, perform equalization processing on the received first signal, to obtain a second signal; Adding the second signal and the third signal to obtain a fourth signal; determining the fourth signal to obtain a fifth signal; performing equalization processing on the fifth signal, and using the equalization result as a new third a signal; performing equalization processing on the fourth signal to obtain a sixth signal; adding the sixth signal and the new third signal to obtain a seventh signal; performing a decision on the seventh signal, and outputting a decision After the eighth signal.

Further, the processor 710 is further configured to add the fifth signal and the second signal to obtain a first error signal; update the first tap coefficient according to the first error signal, and output the first a tap coefficient; updating a second tap coefficient according to the first error signal, and outputting the second tap coefficient; adding the eighth signal and the sixth signal to obtain a second error signal; The second error signal updates the third tap coefficient and outputs the third tap coefficient.

Wherein, the first tap coefficient, the second tap coefficient and the third tap coefficient are updated by a least mean square algorithm. Preferably, updating the step size of the first tap coefficient is not equal to updating the step size of the second tap coefficient.

In the embodiment of the invention, the equalization performance of the decision feedback equalization device is effectively improved by the multiplexing cascade mode, and the problem that the receiver cannot receive the correct signal due to the dispersion is solved, the bit error rate is further reduced, and the stability of the system is improved.

For a specific execution process of the specific processor 710, refer to the corresponding description of the flowchart shown in FIG. 5, and details are not described herein again.

It should be understood that, in the embodiment of the present invention, the processor 710 may be a central processing unit ("CPU"), and the processor 710 may also be other general-purpose processors, digital signal processors (DSPs). An application specific integrated circuit (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, and the like. The general purpose processor may be a microprocessor or the processor or any conventional processor or the like.

The memory 720 can include read only memory and random access memory and provides instructions and data to the processor 710. A portion of the memory 720 can also include a non-volatile random access memory. For example, the memory 720 can also store information of the device type.

The bus system 730 may include a power bus, a control bus, a status signal bus, and the like in addition to the data bus. However, for clarity of description, various buses are labeled as bus system 730 in the figure.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both, for clarity of hardware and software. Interchangeability, the composition and steps of the various examples have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods for implementing the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present invention.

A person skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working process of the system, the device and the unit described above can refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.

In the several embodiments provided herein, it should be understood that the disclosed systems, devices, and The method can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, or an electrical, mechanical or other form of connection.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present invention.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention contributes in essence or to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium. A number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

The above is only the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any equivalent person can be easily conceived within the technical scope of the present invention by any person skilled in the art. Modifications or substitutions are intended to be included within the scope of the invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

A decision feedback equalization device, comprising:

a first equalizer, a first adder, a first decision unit, a second equalizer, a third equalizer, a second adder, and a second decision unit;

The first equalizer is configured to receive a signal and perform equalization processing on the received signal;

The first adder is configured to add an output signal of the first equalizer and an output signal of the second equalizer;

The first determining unit is configured to determine an output signal of the first adder;

The second equalizer is configured to perform equalization processing on an output signal of the first determining unit;

The third equalizer is configured to perform equalization processing on an output signal of the first adder;

The second adder is configured to add an output signal of the third equalizer and an output signal of the second equalizer;

The second determining unit is configured to determine an output signal of the second adder, and output the determined signal.
The decision feedback equalization apparatus according to claim 1, further comprising:

a fourth adder, a first coefficient update module, a second coefficient update module, a fifth adder, and a third coefficient update module;

The fourth adder is configured to add an output signal of the first determining unit and the first equalizer output signal to obtain a first error signal;

The first coefficient update module is configured to update a first tap coefficient of the first equalizer according to the first error signal, and output the first tap coefficient to the first equalizer;

The second coefficient update module is configured to update a second tap coefficient of the second equalizer according to the first error signal, and output the second tap coefficient to the second equalizer;

The fifth adder is configured to add an output signal of the second determining unit and the third equalizer output signal to obtain a second error signal;

The third coefficient update module is configured to update a third tap coefficient of the third equalizer according to the second error signal, and output the third tap coefficient to the third equalizer.
The decision feedback equalization apparatus according to claim 1, wherein the first coefficient update module, the second coefficient update module, and the third coefficient update module both update the tap coefficients by using a least mean square algorithm.
The decision feedback equalization apparatus according to claim 3, wherein the step of updating the first tap coefficient of the first equalizer by the first coefficient update module is not equal to the update by the second coefficient update module The step size of the second tap coefficient of the second equalizer.
The decision feedback equalization apparatus according to any one of claims 1 to 4, wherein the first equalizer, the second equalizer, and the third equalizer are horizontal digital filters.
A receiver comprising the decision feedback equalization apparatus of any of claims 1-5.
An optical transmission system comprising a transmitter for transmitting an optical signal and the receiver of claim 6.
A signal processing method, comprising the steps of:

Receiving a first signal, performing equalization processing on the received first signal to obtain a second signal;

Adding the second signal and the third signal to obtain a fourth signal;

Determining the fourth signal to obtain a fifth signal;

Performing equalization processing on the fifth signal, and using the equalization result as a new third signal;

Performing equalization processing on the fourth signal to obtain a sixth signal;

Adding the sixth signal and the new third signal to obtain a seventh signal;

Determining the seventh signal, and outputting the eighth signal after the decision.
The signal processing method according to claim 8, further comprising:

Adding the fifth signal and the second signal to obtain a first error signal;

Updating a first tap coefficient according to the first error signal, and outputting the first tap coefficient;

Updating a second tap coefficient according to the first error signal, and outputting the second tap coefficient;

Adding the eighth signal and the sixth signal to obtain a second error signal;

Updating the third tap coefficient according to the second error signal, and outputting the third tap coefficient.
The signal processing method according to claim 9, wherein the first tap coefficient, the second tap coefficient, and the third tap coefficient are both updated using a least mean square algorithm.
The signal processing method according to claim 10, wherein the step of updating the first tap coefficient is not equal to the step of updating the second tap coefficient.
A data communication apparatus, comprising: a processor, a memory, and a bus system, wherein the processor and the memory are connected by the bus system, the memory is for storing instructions, and the processor is configured to execute the memory Stored instructions,

The processor is configured to: receive a first signal, perform equalization processing on the received first signal, to obtain a second signal; add the second signal and the third signal to obtain a fourth signal; Determining the fourth signal to obtain a fifth signal; performing equalization processing on the fifth signal, using the equalization result as a new third signal; performing equalization processing on the fourth signal to obtain a sixth signal; And summing the signal and the new third signal to obtain a seventh signal; determining the seventh signal, and outputting the eighth signal after the decision.
The data communication device according to claim 12, wherein the processor is further configured to:

Adding the fifth signal and the second signal to obtain a first error signal;

Updating a first tap coefficient according to the first error signal, and outputting the first tap coefficient;

Updating a second tap coefficient according to the first error signal, and outputting the second tap coefficient;

Adding the eighth signal and the sixth signal to obtain a second error signal;

Updating the third tap coefficient according to the second error signal, and outputting the third tap coefficient.
The data communication apparatus according to claim 13, wherein the first tap coefficient, the second tap coefficient, and the third tap coefficient are both updated using a least mean square algorithm.
The data communication apparatus according to claim 14, wherein the step of updating said first tap coefficient is not equal to a step of updating said second tap coefficient.