CN100562076C - Time-domain adaptive equalizer and the decision feedback filter device that comprises thereof - Google Patents
Time-domain adaptive equalizer and the decision feedback filter device that comprises thereof Download PDFInfo
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Abstract
The present invention relates to a kind of time-domain adaptive equalizer, wherein input signal flows into forward-direction filter, the output of forward-direction filter flows into an input of adder, adder in addition two be input as the output of first feedback filter and the output of second feedback filter.Adder is to the input signal addition, and its output is connected to the input of decision device.The error maker is according to the input and output generated error signal of decision device.The tap coefficient renovator generates tap coefficient according to error signal, upgrades the tap coefficient of described forward-direction filter and described decision feedback filter device.First feedback filter uses transpose configuration, and second feedback filter uses non-transpose configuration and its input of importing with respect to first feedback filter that certain time-delay is arranged.The progression of transpose configuration and non-transpose configuration is to determine according to the required the longest back length directly that tackles.
Description
Technical field
The present invention relates to a kind of time-domain adaptive equalizer, relate in particular to a kind of time-domain adaptive equalizer based on the time-delay coupling.
Background technology
In the practical application of many different digital informations such as sound, data and video communication etc., equalizer is a kind of very important element.Equalizer is used as the Echo Canceller (compensator), Digital Television of speakerphone in the full-duplex communication or video anti-ghost device, radio modem and the wireless telephonic signal conditioner etc. in the digital cable transmission.In signals transmission, because the existence of multipath signal can bring intersymbol interference (ISI) in the channel, and intersymbol interference is a major reason that produces error, in most of single carrier digital application, generally all use time-domain adaptive equalizer to revise the ISI mistake.
Fig. 1 is the modular structure block diagram sketch of traditional time-domain adaptive equalizer 100.Usually in digital receiver, time-domain adaptive equalizer 100 comprises 20, one error makers 50 of 40, one feedback filters of 10, one decision devices of 60, one forward-direction filters of a tap coefficient renovator and an adder 30.Forward-direction filter 10 can be realized with finite impulse response (FIR) (FIR) filter.Forward-direction filter 10 is used for receiving inputted signal, eliminates the forward direction multipath, the multipath signal that promptly main relatively transmission signals arrives in advance.The output sum1 of forward-direction filter 10 is connected to an adder 30.Another input of adder 30 receives the output sum2 from feedback filter 20.Adder 30 is with input signal sum1 and sum2 one of adduction output and signal sum_EQ mutually, as the output signal of whole time-domain adaptive equalizer 100.Simultaneously, equalizer output signal sum_EQ flows into decision device 40 again, and decision device 40 is made judgement according to its input information sum_EQ and the relation of constellation point, and the output valve of decision device is from the immediate constellation point numerical value of sum_EQ.Simultaneously, if the output of decision device 40 directly as an input of feedback filter 20, so such feedback filter 20 just belongs to the decision feedback filter device.The output of feedback filter 20 adds and is worth the output signal sum_EQ that sum2 will revise equalizer, to eliminate the back to multipath, promptly is later than the multipath signal that main transmission signals arrives, and can eliminate the residual signal that forward-direction filter 10 produces.Error signal is generated according to the output of decision device 40 and the difference of input signal by error maker 50.Tap coefficient renovator 60 is used for receiving error signal, and generates the filter coefficient of forward-direction filter 10 and feedback filter 20.There are a lot of feasible methods to be applicable to the generation filter coefficient, comprise lowest mean square (LMS) and recursive least square (RLS) algorithm.The form of filter also has multiple, can be real filter, that is, the number average of tap coefficient and register is a real number, and the multiplying of filter also is real arithmetic; Also can be complex filter, that is, the number average of tap coefficient and register be a plural number, and the multiplying of filter is a complex operation; Can also be accurate complex filter, that is, though counting of tap coefficient and register is plural number, the multiplying of filter be real arithmetic.
Fig. 2 shows and is traditional concrete block diagram of time-domain adaptive equalizer modular structure.Compared to Figure 1, Fig. 2 provides the concrete structure of forward-direction filter 10 and feedback filter 20.Specifically, forward-direction filter 10 and feedback filter 20 all adopt the non-transpose configuration shown in Fig. 3 a to realize.Referring to Fig. 2 and Fig. 3 a, be example with the non-transpose configuration of feedback filter 20, wherein comprise the M level delayer of cascade, (the output of decision device of the input signal of feedback filter
) through 1 grade, 2 grades ... M level delayer is delayed time respectively, obtain a corresponding M delayer output, be respectively the output of the 1st grade of delayer, the output of the 2nd grade of delayer ..., M level delayer output, the corresponding multiplier of M is exported M delayer respectively and corresponding filter coefficient d
1, d
K, d
MMultiplying each other obtains a corresponding M multiplier output, and M multiplier output obtains the output of feedback filter 20 at last by an adder addition.Forward-direction filter 10 also has similar non-transpose configuration.
In theory, need only the progression long enough of feedback filter in the equalizer, just can tackle the multipath channel of endless.But actually, the realization of equalizer is subjected to the restriction of 2 factors: hardware resource expense and sequential relationship.For the former, because the development of FPGA technology and asic technology, and consider that the length of multipath signal is always limited, the hardware resource expense no longer has been the bottleneck problem of restriction equalizer realization; For the latter, the sequential anxiety mainly is subject to the arithmetic speed of feedback filter.This is because forward-direction filter (FIR) always can solve with streamline (Pipeline) technology group delay and insensitive.And feedback filter need be finished in a symbol period usually and allly in the filter takes advantage of, adds computing.Especially, when adopting Blind Equalization Technique, the data that enter feedback filter no longer are to declare data firmly, but equalizer adds and soft value, feedback filter will become infinite impulse response (IIR) filter this moment, multiplier in the feedback filter can't replace with XOR gate, and sequential relationship will be nervous more.For this reason, the feedback filter that proposes in the time-domain adaptive equalizer of someone adopts transpose configuration to realize.
Fig. 3 b illustrates the exemplary plot of transpose configuration.Transpose configuration shown in Fig. 3 b comprises M multiplier, a M-1 delayer and M-1 adder, and input signal is earlier without time-delay, but via M multiplier respectively with a corresponding M tap coefficient d
M, d
M-1..., d
1Multiply each other, obtain M output product value.Input signal and coefficient d
MMultiply each other first product value input first order delayer of gained, resulting time-delay output and input signal and coefficient d
M-1The multiply each other second product value addition of gained, it adds and is worth and imports second level delayer, resulting time-delay output and input signal and coefficient d
M-2Multiply each other the 3rd product value addition of gained, the rest may be inferred, the delayer output of M-1 level and input signal and coefficient d
1The multiply each other M product value addition of gained finally obtains the output of the filter of transpose configuration.The input of the time-delay earlier data of transpose configuration and traditional non-transpose configuration all are consistent with multiply each other the respectively mode output signal of addition then of N level coefficient with filter effect again.Yet the basic structure of add tree is M=2
nIndividual input is carried out obtaining M/2 result behind the first order addition, and partial input is M/2 output of the first order, obtains M/4 output valve after the second level adds, and each grade addition needs the time-delay of a symbol period, and is general, if 2
n＜M＜=2
N+1Be exactly the progression n+1 level that needs so altogether is always if n+1 the symbol period of delaying time is special M=2
n, the progression that needs so altogether is exactly log
2The M level, log always delays time
2M symbol period, traditional non-transpose configuration will be through log between from the input signal to the output signal
2So the add tree of M level is must be through the log of add tree
2The time-delay of M symbol period just can have output; The shortest between the input and output signal of transpose configuration have only an adder, so time-delay has only the time-delay of one-level addition, just a symbol period.Therefore, because traditional non-transpose configuration generally can use add tree that M product value summed up, can introduce log like this
2The addition time-delay of M symbol period, and the benefit of transpose configuration is reduced to this time-delay 1 symbol period exactly, and do not have any influence for the pipeline processes of handling.If the time-delay of feedback filter is greater than 1 symbol period, be assumed to be d greater than 1, back in the individual symbol period in main back (d-1), footpath not can do with to this feedback filter of multipath so, if traditional non-transpose configuration feedback filter wants can do with all back footpaths, must be all M product value addition output in a symbol period, this just brings corresponding sequence problem, and transpose configuration then can be avoided this sequence problem.But the drawback that realizes with transpose configuration is: because the fixed point above the hardware is handled, whenever do a sub-addition, in order to guarantee not overflow, the bit bit wide of output is imported data relatively will increase by one, along with add and carrying out, the bit accuracy that needs will be more and more higher.The bit bit wide of exporting transpose configuration such as the addition of N level will increase the N-1 position, and traditional non-transpose configuration only can increase log
2N bit bit wide.Than non-transpose configuration, the consumption of the hardware resource of transpose configuration will increase like this.If the progression of feedback filter is a lot, in order to save hardware resource, need the number of bits of restriction input signal, so not only limited the realization of blind equalization, also be a big obstacle for the modulation system that realizes many constellation point.
In sum, the hardware resource expense of non-transpose configuration is few, based on the development of FPGA technology and asic technology, no longer is problem, but the sequential relationship anxiety.And the output result of transpose configuration and non-transpose configuration is identical, alleviated sequential relationship, but the hardware resource expense is very big.
Therefore traditional time-domain adaptive equalizer can't resist the long multipath in the Channel Transmission, and especially long and strong is back to multipath.
Summary of the invention
The present invention is directed to digital terrestrial television transmission system the deficiencies in the prior art and defective, the structure of conventional equalizer is improved, proposed a kind of time-domain adaptive equalizer based on the time-delay coupling.By the delay line of design of feedback filter meticulously, make the feedback filter of longer progression also can realize with traditional transverse filter structure, so not only saved hardware resource, can also effectively improve the precision of equalizer, effectively offset long multipath, and make blind equalization become possibility.
In one embodiment of the invention, provide a kind of decision feedback filter device, having comprised: first feedback filter, it has transpose configuration; Second feedback filter, its input signal has the first predetermined time-delay and has non-transpose configuration with respect to the input signal of first feedback filter.
In another embodiment of the present invention, the decision feedback filter device also comprises a plurality of delayers, described a plurality of delayer is cascade, the previous stage delayer is output as the input of next stage delayer, the input of first delayer is the input signal of described first feedback filter in wherein a plurality of delayers, and the delayer output that the input signal of relative first feedback filter has the described first predetermined time-delay is the input of described second feedback filter.
In another embodiment of the present invention, a kind of time-domain adaptive equalizer is provided, comprising: forward-direction filter, its receiving inputted signal is used to eliminate the forward direction multipath; The decision feedback filter device is used for eliminating the back to multipath; Adder, it receives output from forward-direction filter and decision feedback filter device as input, carries out sum operation and exports an equalizer output; Decision device receives described equalizer output as input signal, and output is offered described decision-feedback wave filter; The error signal maker generates error signal according to the input signal of described decision device and the output of described decision device; The tap coefficient renovator generates tap coefficient to upgrade the tap coefficient of forward-direction filter and decision feedback filter device according to described error signal, and described decision feedback filter device comprises: first feedback filter, and it has transpose configuration; Second feedback filter, its input signal has the first predetermined time-delay and has non-transpose configuration with respect to the input signal of first feedback filter.
In yet another embodiment of the present invention, time-domain adaptive equalizer also comprises a plurality of delayers, described a plurality of delayer is cascade, the previous stage delayer is output as the input of next stage delayer, the input of first delayer is the input signal of described first feedback filter in wherein a plurality of delayers, and the delayer output that the input signal of relative first feedback filter has the described first predetermined time-delay is the input of described second feedback filter.
Description of drawings
Fig. 1 is traditional time-domain adaptive equalizer modular structure block diagram sketch.
Fig. 2 is traditional concrete block diagram of time-domain adaptive equalizer modular structure.
Fig. 3 a is the exemplary plot of non-transpose configuration.
Fig. 3 b is the exemplary plot of transpose configuration.
Fig. 4 is the time-domain adaptive equalizer structured flowchart sketch based on the time-delay coupling.
Fig. 5 is the concrete block diagram of time-domain adaptive equalizer structure based on the time-delay coupling.
Embodiment
Provide following examples in conjunction with content of the present invention, be applied in the digital tv ground broadcasting.
Fig. 4 is the structured flowchart sketch based on the time-domain adaptive equalizer 200 of time-delay coupling.In one embodiment of the invention, the time-domain adaptive equalizer 200 based on the time-delay coupling comprises: forward-direction filter 10, first feedback filter 21, second feedback filter 22, decision device 40, error maker 50, tap coefficient renovator 60 and adder 30.Interconnected relationship between its each parts is: input signal at first enters forward-direction filter 10, and the output sum1 of forward-direction filter 10 is connected to an adder 30.The output that in addition two input sum2 of adder 30 and sum3 are respectively first feedback filter 21 and second feedback filter 22.Adder 30 is with input signal sum1, sum2 and sum3 addition, and output sum_EQ signal, as the output signal of whole time-domain adaptive equalizer 200.Equalizer output sum_EQ flows into decision device 40 again, and decision device 40 is made judgement according to its input information sum_EQ and the relation of constellation point, and the output valve of decision device is from the immediate constellation point numerical value of sum_EQ.Simultaneously, if the output of decision device 40 is directly as an input of first feedback filter 21, the output that the output of first feedback filter 21 adds and be worth the sum2 and second feedback filter 22 adds and is worth the output signal sum_EQ that sum3 will revise equalizer, to eliminate the back to multipath, promptly be later than the multipath signal that main transmission signals arrives, and can eliminate the residual signal that forward-direction filter 10 produces.Error signal is generated according to the output of decision device 40 and the difference of input signal by error maker 50.Tap coefficient renovator 60 is used for receiving error signal, and generates the filter coefficient of forward-direction filter 10, first feedback filter 21 and first feedback filter 22.Wherein, first feedback filter 21 is the B level altogether, second feedback filter 22 is the M level altogether, M=2^ (B-A) wherein, A is a delayer progression, the input of representing second feedback filter 22 is with respect to the input of first feedback filter 21 time-delay through A level delayer, A be more than or equal to zero, smaller or equal to the integer of B.
Referring to Fig. 5, Fig. 5 is the concrete block diagram of structure based on the time-domain adaptive equalizer 100 of time-delay coupling.Wherein, first feedback filter 21 is to be realized by transpose configuration shown in Figure 3, and second feedback filter 22 is to be realized by non-transpose configuration shown in Figure 3.The output SUM_EQ of equalizer can obtain decision value through a decision device 40
As the input of first feedback filter 21, and the output of the A level delayer in a plurality of delayers in first feedback filter 21
As the input of second feedback filter 22, SUM_EQ and
Difference by error maker 50 generated error signals, error signal input tap coefficient renovator 60 is to upgrade the tap of forward-direction filter 10
The tap of first feedback filter 21
And the tap of second feedback filter
The generation of tap coefficient and update mode all are known in those skilled in the art.
Below a plurality of delayers in first feedback filter 21 are illustrated.Described a plurality of delayer is cascade, the previous stage delayer is output as the input of next stage delayer, the input of first delayer is the input signal of described first feedback filter in wherein a plurality of delayers, the output of A level delayer then is the input of described second feedback filter, and the input that it makes second feedback filter has certain time-delay with respect to the input of first feedback filter.
In the above description, the amount of delay of each grade all equates with unit amount of delay in forward-direction filter, transpose configuration and the non-transpose configuration.
Wherein, forward-direction filter 10 is that a length is 400 grades, the complex filter of mark space; First feedback filter 21 is the complex filters that length is 32 grades mark space, the employing transpose configuration is realized, like this can one finish in the symbol beat and add and export, and because progression is shorter, it is too big that the bit width that adds and export is unlikely to, the output that is input as decision device 40 of first feedback filter 21; Second feedback filter 22, totally 2
(32-23)=512 grades.The progression of second feedback filter is index not necessarily, in principle as long as can realize by hardware less than this exponential quantity, but needs only the hardware resource permission, then can select usually to represent near this maximum.Because progression is a lot, adopt transpose configuration to realize relatively difficulty, be difficult to control the bit bit wide of output, be unfavorable for the control hardware resource, so adopt the mode of the time-delay coupling of traditional non-transpose configuration to realize, the tap output of the 23rd grade of delayer that is input as first feedback filter 21 of second feedback filter 22, wherein, the amount of delay of each grade delayer equates.So just allow the structure realization that is used for streamline with the time-delay that (32-23)=9 clock cycle can be arranged that adds of second feedback filter 22, the feedback filter that such structure can satisfy all progression in a symbol beat, finish add and the sequential requirement, again can better controlled the bit bit wide of output, it is 32+2 that whole structure is equivalent to a total progression
(32-23)The decision feedback filter device, can guarantee in a symbol period, to finish and add and export, and final equalizer output bit bit wide can be remained in the zone of reasonableness.
This feedback filter arrangement based on the time-delay coupling can be supported the input signal of the output of any one position the position of B+1 altogether after the afterbody time-delay before the first order time-delay of first feedback filter 21 as second feedback filter 22.
For example, in another embodiment of the present invention, first feedback filter 21 still is the complex filter of 32 grades mark space for length, the employing transpose configuration is realized, and the just output before its 1st grade of delayer of first feedback filter 21, the input signal that is equivalent to first feedback filter 21 and second feedback filter 22 is identical, corresponding to the A=0 here, because B still equals 32, the progression of second feedback filter just is 2 so
(32-0)So just allow the structure realization that is used for streamline with the time-delay that (32-0)=32 clock cycle can be arranged that adds of second feedback filter 22, the feedback filter that such structure can satisfy all progression in a symbol beat, finish add and the sequential requirement, again can better controlled the bit bit wide of output, it is 32+2 that whole structure is equivalent to a total progression
(32-0)DFF 200, also can guarantee in a symbol period, to finish and add and export, and the output bit bit wide of final equalizer 200 can be remained in the zone of reasonableness.
Again for example, in another embodiment of the present invention, first feedback filter 21 still is the complex filter of 32 grades mark space for length, the employing transpose configuration is realized, if and first feedback filter 21 is in its afterbody time-delay back output, so just corresponding to A=B here, owing to B still gets 32, A=32 then, this moment, the progression of second feedback filter 22 just was 2
(32-32)=1, whole feedback filter just is equivalent to progression 32+2
(32-32)=33 feedback filter.
Value about B also can change, and still generally speaking the selection of B and A is to determine according to the required the longest back length directly that tackles.By above description as can be known, second feedback filter in the time-domain adaptive equalizer of the present invention is 2
B-ALevel, A is the integer more than or equal to 0, that is, second feedback filter can be at most 2
BLevel (when getting A=0).That is to say that it is B+2 that feedback filter of the present invention can be equivalent to progression at most
BFeedback filter.The longest multipath that tackles if desired needs the feedback filter of X level time-delay, as long as can satisfy X＜B+2 so
B, just can do with the longest multipath.For example, when the longest multipath that tackles when needs needs 512 grades feedback filter, consider and to satisfy 512＜B+2
B, B is again an integer, so the value of B is B 〉=9.Therefore, B gets the longest multipath that any value more than or equal to 9 all can do with needs 512 grades of feedback filters, for example in the present invention, and B=32.After the B value has been determined, again according to the satisfied condition X＜B+2 of need
B-ADetermine the A value.In this example, because X=512, therefore B=32 draws A more than or equal to 0 and smaller or equal to 23 integer.
The progression one of delayer regularly in first feedback filter 21, the input of using first feedback filter 21 is through the delayer of different progression and the output that obtains is that those of ordinary skill in the art can contemplate easily as the operation of the input of second feedback filter 22, the present invention is not limited to the embodiment of the output at the the 0th, the 23rd, the 32nd grade of delayer place of above-mentioned usefulness as 22 inputs of second feedback filter, and the position of other delayer outputs also is feasible.
In that a further aspect of the present invention, feedback filter also is not limited to the first and second above-mentioned feedback filters, but can comprise three or more feedback filters.For example, if at original B=32, on the basis of A=23, the input of using first feedback filter 21 obtains the input of the 3rd feedback filter through the output of C level delayer, carry out filter operations similarly then, wherein A＜C＜B.The output of the 3rd feedback filter is input summer 30 also.Decision feedback filter device of Xing Chenging and the adaptive equalizer that comprises described decision feedback filter device also can solve technical problem of the present invention like this.
More than disclosed according to the time-domain adaptive equalizer based on the time-delay coupling of the present invention.
Those skilled in the art will appreciate that information and signal can represent with in multiple different technologies and the technology any.For example, data, instruction, order, information, signal, bit, code element and the chip that may relate in the above-mentioned explanation can be represented with voltage, electric current, electromagnetic wave, magnetic field or its particle, light field or its particle or their combination in any.
Those skilled in the art can further understand, and can be used as electronic hardware, computer software or both combinations in conjunction with the described various illustrative logical blocks of embodiment disclosed herein, module and algorithm steps and realizes.In order to clearly demonstrate the interchangeability between hardware and software, as various illustrative assemblies, block diagram, module, circuit and the step 1 according to its functional elaboration.These are functional realizes specific application program and the design of depending on that whole system adopts as hardware or software actually.The technical staff can recognize the interactivity of hardware and software in these cases, and the described function that how to realize each application-specific best.The technical staff may be realizing described function for the different mode of each application-specific, but this realization decision should not be interpreted as causing and deviates from scope of the present invention.
The realization of various illustrative logical block, module and the algorithm steps of describing in conjunction with embodiment as described herein or carry out and to use: general processor, digital signal processor (DSP), application-specific integrated circuit (ASIC) (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components or for carrying out the combination in any that function described here designs.General processor may be a microprocessor, yet or, processor can be processor, controller, microcontroller or the state machine of any routine.Processor also may realize with the combination of computing equipment, as, the combination of DSP and microprocessor, a plurality of microprocessor, in conjunction with one or more microprocessors of DSP kernel or other this configuration arbitrarily.
In the software module that the method for describing in conjunction with disclosed embodiment here or the step of algorithm may directly be included in the hardware, carried out by processor or in the middle of both.Software module may reside in the storage medium of RAM memory, flash memory, ROM memory, eprom memory, eeprom memory, register, hard disk, removable dish, CD-ROM or any other form as known in the art.The coupling of exemplary storage medium and processor makes that processor can be from read information, or information is write storage medium.Perhaps, storage medium can be integrated with processor.Processor and storage medium may reside among the ASIC.ASIC may reside in the user terminal.Perhaps, processor and storage medium may reside in the user terminal as discrete component.
The description of above preferred embodiment makes those skilled in the art can make or use the present invention.The various modifications of these embodiment are conspicuous for a person skilled in the art, and Ding Yi General Principle can be applied among other embodiment and not deviate from the spirit or scope of the present invention here.Therefore, the embodiment that the present invention is not limited to illustrate here, and will meet and the principle and the novel feature the most wide in range consistent scope that disclose here.
Claims (16)
1. decision feedback filter device is characterized in that comprising:
First feedback filter, it has transpose configuration;
Second feedback filter, its input signal has the first predetermined time-delay and has non-transpose configuration with respect to the input signal of first feedback filter.
2. decision feedback filter device as claimed in claim 1 is characterized in that,
Described transpose configuration comprises:
A plurality of multipliers, an input of each multiplier in described a plurality of multipliers receives the first feedback filter input signal, and another input receives corresponding filter factor, and they be multiply by mutually obtains corresponding multiplier output;
A plurality of delayers, first delayer in described a plurality of delayer receives the output of first multiplier in described a plurality of multiplier, it is delayed time to obtain first multiplier output through time-delay to output to first adder, and the output of all the other delayers reception previous stage adders in described a plurality of delayers except that first delayer is as input; And
A plurality of adders, an input of each adder in described a plurality of adder receives the output through the current level multiplier of time-delay, another input receives a next stage multiplier output, and they are carried out addition, the output of all adders in described a plurality of adder except that last adder is the input of next stage delayer, last adder is output as the output of transpose configuration in described a plurality of adder
Described non-transpose configuration comprises:
A plurality of delayers, first delayer in described a plurality of delayers receives the input signal of second feedback filter, the cascade successively of described a plurality of delayers;
A plurality of multipliers, input of each multiplier in described a plurality of multipliers receives the input signal through the time-delay of corresponding delay device, and another input receives corresponding filter factor, and they be multiply by mutually obtains a plurality of corresponding multipliers outputs; And
An adder, described adder is carried out addition to described a plurality of multiplier outputs, is output as the output of non-transpose configuration.
3. decision feedback filter device as claimed in claim 1 or 2, it is characterized in that also comprising a plurality of delayers, described a plurality of delayer is cascade, the previous stage delayer is output as the input of next stage delayer, the input of first delayer is the input signal of described first feedback filter in wherein a plurality of delayers, and the delayer output that the input signal of relative first feedback filter has the described first predetermined time-delay is the input of described second feedback filter.
4. decision feedback filter device as claimed in claim 3 is characterized in that, described transpose configuration is the B level, and described non-transpose configuration is the M level, M=2
B-A, wherein A is the progression of the delayer of the realization described first predetermined time-delay, the value of B and M is to determine according to the required the longest back length directly that tackles.
5. as claim 3 or 4 described decision feedback filter devices, it is characterized in that the output sum of described first feedback filter and second feedback filter is the output of described decision feedback filter device.
6. decision feedback filter device as claimed in claim 1, it is characterized in that also comprising the 3rd feedback filter, its input signal has the second predetermined time-delay with respect to the input signal of first feedback filter, the described second predetermined time-delay is greater than the described first predetermined time-delay, and described the 3rd feedback filter is non-transpose configuration.
7. as the described DFF of claim 5 or 6, it is characterized in that any in described first feedback filter, second feedback filter, the 3rd feedback filter is one of them of real filter, complex filter and accurate complex filter.
8. decision feedback filter device as claimed in claim 4 is characterized in that, A is the integer more than or equal to 0.
9. time-domain adaptive equalizer comprises:
Forward-direction filter, its receiving inputted signal is used to eliminate the forward direction multipath;
The decision feedback filter device is used for eliminating the back to multipath;
Adder, it receives output from forward-direction filter and decision feedback filter device as input, carries out sum operation and exports an equalizer output;
Decision device receives described equalizer output as input signal, and output is offered described decision-feedback wave filter;
The error signal maker generates error signal according to the input signal of described decision device and the output of described decision device;
The tap coefficient renovator generates the tap coefficient of tap coefficient with renewal forward-direction filter and decision feedback filter device according to described error signal,
It is characterized in that described decision feedback filter device comprises:
First feedback filter, it has transpose configuration;
Second feedback filter, its input signal has the first predetermined time-delay and has non-transpose configuration with respect to the input signal of first feedback filter.
10. time-domain adaptive equalizer as claimed in claim 9 is characterized in that,
Described transpose configuration comprises:
A plurality of multipliers, an input of each multiplier in described a plurality of multipliers receives the first feedback filter input signal, and another input receives corresponding filter factor, and they be multiply by mutually obtains corresponding multiplier output;
A plurality of delayers, first delayer in described a plurality of delayer receives the output of first multiplier in described a plurality of multiplier, it is delayed time to obtain first multiplier output through time-delay to output to first adder, and the output of all the other delayers reception previous stage adders in described a plurality of delayers except that first delayer is as input; And
A plurality of adders, an input of each adder in described a plurality of adder receives the output through the current level multiplier of time-delay, another input receives a next stage multiplier output, and they are carried out addition, the output of all adders in described a plurality of adder except that last adder is the input of next stage delayer, last adder is output as the output of transpose configuration in described a plurality of adder
Described non-transpose configuration comprises:
A plurality of delayers, first delayer in described a plurality of delayers receives the input signal of second feedback filter, the cascade successively of described a plurality of delayers;
A plurality of multipliers, input of each multiplier in described a plurality of multipliers receives the input signal through the time-delay of corresponding delay device, and another input receives corresponding filter factor, and they be multiply by mutually obtains a plurality of corresponding multipliers outputs; And
An adder, described adder is carried out addition to described a plurality of multiplier outputs, is output as the output of non-transpose configuration.
11. as claim 9 or 10 described time-domain adaptive equalizers, it is characterized in that also comprising a plurality of delayers, described a plurality of delayer is cascade, the previous stage delayer is output as the input of next stage delayer, the input of first delayer is the input signal of described first feedback filter in wherein a plurality of delayers, and the delayer output that the input signal of relative first feedback filter has the described first predetermined time-delay is the input of described second feedback filter.
12. time-domain adaptive equalizer as claimed in claim 11 is characterized in that, described transpose configuration is the B level, and described non-transpose configuration is the M level, M=2
B-A, wherein A is the progression of the delayer of the realization described first predetermined time-delay, the value of B and M is to determine according to the required the longest back length directly that tackles.
13., it is characterized in that the output sum of described first feedback filter and second feedback filter is the output of described decision feedback filter device as claim 11 or 12 described time-domain adaptive equalizers.
14. time-domain adaptive equalizer as claimed in claim 9, it is characterized in that also comprising the 3rd feedback filter, its input signal has the second predetermined time-delay with respect to the input signal of first feedback filter, the described second predetermined time-delay is greater than the described first predetermined time-delay, and described the 3rd feedback filter is non-transpose configuration.
15. as claim 13 or 14 described time-domain adaptive equalizers, it is characterized in that any in described first feedback filter, second feedback filter, the 3rd feedback filter is one of them of real filter, complex filter and accurate complex filter.
16. time-domain adaptive equalizer as claimed in claim 12 is characterized in that, A is the integer more than or equal to 0.
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| CNB2006100283491A CN100562076C (en) | 2006-06-29 | 2006-06-29 | Time-domain adaptive equalizer and the decision feedback filter device that comprises thereof |
| HK08107321.7A HK1116970A1 (en) | 2006-06-29 | 2008-07-02 | Time-domain adaptive equalizer and judging feedback filter included in which |
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| CN101527697B (en) * | 2009-03-16 | 2012-08-29 | 上海高清数字科技产业有限公司 | Time-domain automatic-adaptive equalizer and equalizing method thereof |
| CN102223328B (en) * | 2010-04-14 | 2014-04-16 | 华为技术有限公司 | Signal decision method and device |
| CN102437978B (en) * | 2010-09-29 | 2015-03-25 | 中兴通讯股份有限公司 | Method and device for balancing digital microwaves |
| CN103179060B (en) * | 2011-12-26 | 2016-04-27 | 富士通株式会社 | The coefficient updating device of equalizer and method |
| CN102714639B (en) * | 2012-01-21 | 2014-03-26 | 华为技术有限公司 | Adaptive equalization method and adaptive equalizer |
| CN103067320B (en) * | 2012-12-28 | 2015-09-16 | 成都泰格微波技术股份有限公司 | Mesh MANET channel adaptive equalization device |
| CN103516648B (en) * | 2013-10-18 | 2016-09-28 | 南京信息工程大学 | A kind of mould judgement multi-mode blind equalization method of correction |
| CN104682919B (en) * | 2013-11-29 | 2018-02-27 | 无锡华润矽科微电子有限公司 | A kind of method that the frequency of occurrences is drifted about after solution balanced device fixed point |
| CN107005307B (en) * | 2014-12-09 | 2019-06-28 | 华为技术有限公司 | A kind of method and balancer that balancer is set |
| WO2016161643A1 (en) * | 2015-04-10 | 2016-10-13 | 华为技术有限公司 | Decision feedback equalization apparatus and method, and optical transmission system |
| CN105827557A (en) * | 2016-05-24 | 2016-08-03 | 桂林市思奇通信设备有限公司 | Time-domain equalizer based on MIMO (Multiple-Input Multiple-Output) |
| CN108616265B (en) * | 2018-05-04 | 2022-07-01 | 重庆邮电大学 | Circuit structure of RNS DWT filter bank based on five-modulus residue number basis |
| CN110224955B (en) * | 2019-06-19 | 2020-07-03 | 北京邮电大学 | Digital equalizer structure and implementation method |
| CN110957995B (en) * | 2019-10-25 | 2023-06-30 | 四川汇源光通信有限公司 | IIR filtering system of distributed fault monitoring device and design method thereof |
| CN113595949B (en) * | 2021-09-30 | 2021-12-21 | 苏州浪潮智能科技有限公司 | Self-adaptive PAM4 decision feedback equalization circuit |
| CN113992485B (en) * | 2021-10-27 | 2023-05-30 | 西安微电子技术研究所 | Decision feedback equalization circuit and high-speed signal channel transmission system |
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