CN100547988C

CN100547988C - Adaptive Equalization Circuit in Cable Digital TV

Info

Publication number: CN100547988C
Application number: CNB2006100407719A
Authority: CN
Inventors: 吴建辉; 黄伟; 李红; 张萌; 时龙兴
Original assignee: Southeast University
Current assignee: Southeast University
Priority date: 2006-06-01
Filing date: 2006-06-01
Publication date: 2009-10-07
Anticipated expiration: 2026-06-01
Also published as: CN1889552A

Abstract

The invention discloses an adaptive equalization circuit in a cable digital television conforming to the DVB-C standard. The circuit comprises a feedforward tap block operation circuit (1), an equalized Q-way output adder (2), and an equalized I-way output adder. device (3), decision circuit (4), error calculation circuit (5), quantization circuit (6), shift control amount addition circuit (7) and feed back tap block operation circuit (8); through quantization circuit (6) and the shift control value addition circuit (7) to complete the coefficient update, and adopt the block processing mode of the feed-forward tap block operation circuit (1) and the feed-back tap block operation circuit (8), the above design techniques can effectively reduce the required The number of multipliers reduces the cost of chip design. The invention can effectively reduce the complexity of realization under the condition of ensuring the performance, and at the same time verify the performance of the circuit through the constellation diagram, and the result shows that it can effectively eliminate the intersymbol interference, and has practical application value.

Description

Adaptive Equalization Circuit in Cable Digital TV

技术领域 technical field

本发明涉及数字通信领域的接收技术，具体涉及一种符合DVB-C标准的有线数字电视中的自适应均衡电路。The invention relates to a receiving technology in the field of digital communication, in particular to an adaptive equalization circuit in a cable digital television conforming to the DVB-C standard.

背景技术 Background technique

QAM(正交幅度调制)由于其高效的频谱利用率，被应用于DVB-C标准中。但是在带限信道上传输高速的数字信号时，由于存在信道的衰落和多径干扰，且在安装有线网络设备的时候，接插件安装的问题将会导致信号传输中产生大回波，除此之外传输过程中的放大器、滤波器等都可能产生回波，这将会导致很高的误码率。QAM (Quadrature Amplitude Modulation) is applied in the DVB-C standard because of its efficient spectrum utilization. However, when transmitting high-speed digital signals on band-limited channels, due to channel fading and multipath interference, and when installing wired network equipment, the problem of connector installation will cause large echoes in signal transmission. In addition, amplifiers, filters, etc. in the transmission process may generate echoes, which will lead to a high bit error rate.

自适应均衡电路就是为了对抗码间干扰和大的回波干扰，首先利用常模方法(Constant Modulus Algorithm，简称CMA)方法提供均衡器均衡值的初始收敛，以迫使“眼图”张开，当在一定时间内的误差小于一定数值后均衡方法转为最小均方误差(LMS)方法以提供更快的收敛速度和收敛后更小的误差。所设计的均衡电路采用的是判决反馈均衡器，判决反馈均衡器(DFE)有两个横向滤波器即前置均衡器和反馈均衡器组成，前馈滤波器器用来抵消前向干扰，反馈滤波器来消除后续干扰。The adaptive equalization circuit is to combat inter-symbol interference and large echo interference. First, the Constant Modulus Algorithm (CMA) method is used to provide the initial convergence of the equalizer equalization value to force the "eye diagram" to open. After the error within a certain period of time is less than a certain value, the equalization method is changed to the least mean square error (LMS) method to provide faster convergence speed and smaller error after convergence. The designed equalization circuit adopts a decision feedback equalizer. The decision feedback equalizer (DFE) consists of two transversal filters, namely a pre-equalizer and a feedback equalizer. The feed-forward filter is used to offset the forward interference, and the feedback filter device to eliminate subsequent interference.

假设X_k ^T是t＝kT时刻均衡器前馈和反馈滤波器中的信号值，C_k是第k个符号间隔中的均衡器系数向量，则Assuming that X _k ^T is the signal value in the feedforward and feedback filters of the equalizer at time t=kT, and C _k is the equalizer coefficient vector in the kth symbol interval, then

X_k＝{x_k+K1，x_k+K1-1，...x_k，d_k-1，d_k-2，...d_k-K2}^T X _k ＝{x _k+K1 ，x _k+K1-1 ，...x _k ，d _k-1 ，d _k-2 ，...d _k-K2 } ^T

C_k＝{C_k，-K1，C_k，-K1+1...C_k，0，C_k，1，C_k，2...C_k，K2}^T C _k = {C _{k, -K1} , C _{k, -K1+1} ... C _{k, 0} , C _{k, 1} , C _{k, 2} ... C _{k, K2} } ^T

其中K1、K2分别是前馈滤波器和判决反馈滤波器的抽头数，均衡器的输出y_k的表达式为：Among them, K1 and K2 are the tap numbers of the feedforward filter and the decision feedback filter respectively, and the expression of the output y _k of the equalizer is:

${y the y}_{k k} = = {X x}_{k k}^{T T} {C C}_{k k} = = {C C}_{k k}^{T T} {X x}_{k k} = = {Σ Σ}_{j j = = - - K K 11}^{K K 22} {x x}_{k k - - j j} \times \times {C C}_{k k,, j j}$

1最小均方误差(LMS)方法1 Least mean square error (LMS) method

LMS方法是一种面向判决的，目前获得最广泛应用的均衡方法。考虑输入为复数时，其误差信号e_n的表达式为：The LMS method is a decision-oriented equalization method that is currently the most widely used. Considering that the input is a complex number, the expression of its error signal e _n is:

误差信号为：e(k)＝e_I(k)+je_Q(k)＝(d_I，k-y_I，k)+j(d_Q，k-y_Q，k) (1)The error signal is: e(k)=e _I (k)+je _Q (k)=(d _{I, k} -y _{I, k} )+j(d _{Q, k} -y _{Q, k} ) (1)

其中，d_I，k和d_Q，k分别为t＝k时刻均衡输出的判决信号。Wherein, d _{I, k} and d _{Q, k} are the decision signals output by equalization at time t=k respectively.

抽头系数更新为：The tap coefficients are updated as:

C_I(k+1)＝C_I(k)+μ_LMS[e_I(k)X_I(k)+e_Q(k)X_Q(k)]C _I (k+1)＝C _I (k)+μ _LMS [e _I (k)X _I (k)+e _Q (k)X _Q (k)]

(2) (2)

C_Q(k+1)＝C_Q(k)+μ_LMS[e_Q(k)X_I(k)-e_I(k)X_Q(k)]C _Q (k+1)＝C _Q (k)+μ _LMS [e _Q (k)X _I (k)-e _I (k)X _Q (k)]

均衡器输出公式为：The equalizer output formula is:

$y the y ((k k)) = = {y the y}_{I I} ((k k)) + + {jy jy}_{Q Q} ((k k)) - - - - - - ((33))$

$= = {C C}_{I I}^{T T} ((k k)) {X x}_{I I} ((k k)) - - {C C}_{Q Q}^{T T} ((k k)) {X x}_{Q Q} ((k k)) + + j j [[{C C}_{I I}^{T T} ((k k)) {X x}_{Q Q} ((k k)) + + {C C}_{Q Q}^{T T} ((k k)) {X x}_{I I} ((k k))]]$

式中，X_I(k)和X_Q(k)是k时刻输入至均衡器的I和Q路信号，μ_LMS是均衡器处于LMS方法时刻的步长。e_I和e_Q分别是k时刻LMS方法的误差。In the formula, X _I (k) and X _Q (k) are the I and Q signals input to the equalizer at time k, and μ _LMS is the step size when the equalizer is in the LMS method. e _I and e _Q are the errors of the LMS method at time k, respectively.

2常模方法(CMA)2 Normative Method (CMA)

其误差信号为：Its error signal is:

e(k)＝e_I(k)+je_Q(k)＝y_I，k*(R₂-|y_k|²)+jy_Q，k*(R₂-|y_k|²) (4)e(k)＝e _I (k)+je _Q (k)＝y _I，k *(R ₂ -|y _k | ² )+jy _Q，k *(R ₂ -|y _k | ² ) (4 )

抽头系数更新为：The tap coefficients are updated as:

C_I(k+1)＝C_I(k)+μ_CMA[e_I(k)X_I(k)+e_Q(k)X_Q(k)]C _I (k+1)＝C _I (k)+μ _CMA [e _I (k)X _I (k)+e _Q (k)X _Q (k)]

(5)

C_Q(k+1)＝C_Q(k)+μ_CMA[e_Q(k)X_I(k)-e_I(k)X_Q(k)]C _Q (k+1)＝C _Q (k)+μ _CMA [e _Q (k)X _I (k)-e _I (k)X _Q (k)]

常模方法的输出为The output of the normative method is

$y the y ((k k)) = = {y the y}_{I I} ((k k)) + + {jy jy}_{Q Q} ((k k)) - - - - - - ((66))$

其中，e_I和e_Q分别是k时刻CMA方法的误差，μ_CMA是当均衡器处于CMAAmong them, e _I and e _Q are the errors of the CMA method at time k, respectively, μ _CMA is when the equalizer is in CMA

方法时刻的步长method time step

实现上述系数操作和计算均衡输出会消耗大量的硬件结构。以前馈和后馈的抽头数分别为6和15为例，整个均衡电路需要84个乘法器来完成系数更新和均衡输出的运算，这样将消耗大量的硬件规模和占用大量的芯片面积，因此，采用优化高效的设计技术对于减少芯片面积和减少芯片的成本具有非常重要的意义。Implementing the above-mentioned coefficient operations and computing the equalized output consumes a large amount of hardware structure. For example, the number of taps of feedforward and feedback is 6 and 15 respectively, and the whole equalization circuit needs 84 multipliers to complete the calculation of coefficient update and equalization output, which will consume a large amount of hardware scale and occupy a large amount of chip area. Therefore, Adopting optimized and efficient design technology is of great significance to reduce chip area and chip cost.

发明内容 Contents of the invention

本发明的目的在于解决上述硬件消耗庞大的问题，提供一种有线数字电视中的自适应均衡电路，在保证性能的前提下能减少约四分之三的硬件规模。The purpose of the present invention is to solve the above-mentioned problem of huge hardware consumption, and provide an adaptive equalization circuit in cable digital TV, which can reduce the hardware scale by about three quarters under the premise of ensuring performance.

本发明采用如下技术方案来解决上述技术问题：The present invention adopts following technical scheme to solve the above technical problems:

一种有线数字电视中的自适应均衡电路，包含前馈抽头块运算电路1，均衡Q路输出加法器2，均衡I路输出加法器3，判决电路4，误差计算电路5，量化电路6，移位控制量加法电路7和后馈抽头块运算电路8，带有码间干扰的第k+k1时刻I路抽头输入数据x_I，k+k1和第k+k1时刻Q路抽头输入数据x_Q，k+k1接第一个前馈抽头块运算电路1，第一个前馈抽头块运算电路1的I路块输出y_I，1接均衡I路输出加法器3，Q路块输出y_Q，1接均衡Q路输出加法器2，第一个前馈抽头块运算电路1输出的第k+k1-2时刻I路数据x_I，k+k1-2和第k+k1-2时刻Q路数据x_Q，k+k1-2顺次地接第二个前馈抽头块运算电路，依此类推直到I路x_I，k+1和Q路x_Q，k+1接最后一个前馈抽头块运算电路，上述所有的前馈抽头块运算电路的I路输出都接均衡I路输出加法器3，Q路输出都接均衡Q路输出加法器2，此时均衡Q路输出加法器2的输出为第k时刻的均衡Q路输出值y_Q，k，均衡I路输出加法器3的输出为第k时刻的均衡I路输出值y_I，k，上述均衡Q路输出值y_Q，k和均衡I路输出值y_I，k分别输出至判决电路4和误差计算电路5，判决电路4输出的第k时刻I路判决输出d_I，k和Q路判决输出d_Q，k，分别输入至误差计算电路5和后馈抽头块运算电路8，误差计算电路5的输出为第k时刻的I路误差信号e_I和Q路误差信号e_Q，其分别输入至量化电路6，量化电路6的输出为I路量化误差信号Qe_I和Q路量化误差信号Qe_Q，其分别输入至移位控制量加法电路7，移位控制量加法电路7的另外两个输入为步长μ_LMS和μ_CMA，移位控制量加法电路7的输出为I路移位控制量S_I和Q路移位控制量S_Q，其分别输入至各个前馈抽头块运算电路1和各个后馈抽头块运算电路8中，第一个后馈抽头块运算电路8的I路块输出Z_I，1接均衡I路输出加法器3，Q路的块输出Z_Q，1接均衡Q路输出加法器2，第一个后馈抽头块运算电路8输出的第k-2时刻I路数据d_I，k-2和第k-2时刻Q路数据d_Q，k-2顺次地接第二个后馈抽头块运算电路，依此类推直到I路第k-k2+1时刻数据d_I，k-k2+1和Q路第k-k2+1时刻数据d_Q，k-k2+1接最后一个后馈抽头块运算电路，上述所有的后馈抽头块运算电路的I路输出都接均衡I路输出加法器3，Q路输出也都接均衡Q路输出加法器2。An adaptive equalization circuit in a cable digital television, comprising a feedforward tap block operation circuit 1, an equalized Q-way output adder 2, an equalized I-way output adder 3, a decision circuit 4, an error calculation circuit 5, and a quantization circuit 6, The shift control amount addition circuit 7 and the feed-back tap block operation circuit 8, the I-way tap input data x _{I at the k+k1 moment with intersymbol interference, and the Q-way tap input data x at the k+k1} and k+k1 moments _{Q, k+k1} is connected to the first feedforward tap block operation circuit 1, the I block output y I of the first feedforward tap block operation circuit 1 _{, 1} is connected to the equalized I block output adder 3, and the Q block output y _{Q, 1} is connected to the equalized Q road output adder 2, the k+k1-2 moment I road data x _{I, k+k1-2} and the k+k1-2 moment of the first feedforward tap block operation circuit 1 output Q-way data x _{Q, k+k1-2} are sequentially connected to the second feed-forward tap block operation circuit, and so on until I-way x _{I, k+1} and Q-way x _{Q, k+1} are connected to the last front Feed the tap block operation circuit, the I road output of all above-mentioned feedforward tap block operation circuits is all connected to the balanced I road output adder 3, and the Q road output is all connected to the balanced Q road output adder 2, and now the balanced Q road output adder The output of 2 is the balanced Q-way output value y _{Q at the kth moment, k} , the output of the balanced I-way output adder 3 is the balanced I-way output value y _{I, k} at the k-th moment, and the above-mentioned balanced Q-way output value _{yQ , k} and the balanced I-way output value y _{I, k} are output to the decision circuit 4 and the error calculation circuit 5 respectively, the k-th moment I-way decision output d _{I of the decision circuit 4 output, k} and the Q-way decision output _{dQ, k} , Input to the error calculation circuit 5 and the feed-back tap block operation circuit 8 respectively, the output of the error calculation circuit 5 is the I-way error signal e _I and the Q-way error signal e _Q at the k moment, which are respectively input to the quantization circuit 6, quantized The output of the circuit 6 is the quantization error signal Qe _I of the I channel and the quantization error signal Qe _Q of the Q channel, which are respectively input to the shift control amount addition circuit 7, and the other two inputs of the shift control amount addition circuit 7 are the step size μ _LMS and μ _CMA , the output of the shift control amount addition circuit 7 is the I-way shift control amount S _I and the Q-way shift control amount S _Q , which are respectively input to each feedforward tap block operation circuit 1 and each feedback tap block In the operation circuit 8, the I road block output Z _{I of the first feed-back tap block operation circuit 8, 1} is connected to the balanced I road output adder 3, the block output of the Q road is Z _{Q, and 1} is connected to the balanced Q road output adder 2 , the k-2th moment I road data d _I,k-2 and the k-2th moment Q road data d _{Q,k-2 of} the k-2th moment output of the first feed-back tap block operation circuit 8 are sequentially connected to the second rear Feed the tap block operation circuit, and so on until the I road k-k2+1 time data d _{I, k-k2+1} and the Q road k-k2+1 time data d _{Q, k-k2+1} connect to the last Back-feeding tap block operation circuit, the I road output of all above-mentioned back-feeding tap block operation circuits are all connected to the balanced I road output adder 3, Q road The outputs are also connected to the equalized Q-way output adder 2 .

本发明的工作原理如下：由于有线信道非理想性，均衡电路在需要以盲均衡方法来提供初始的收敛，然后转到面向判决的方法，所带来的影响是在这两种不同的方法下，其误差函数的计算式(1)(4)是不同的，在系数更新式(2)(5)中，可以看到误差是需要参与和数据的乘法运算的，由于均衡电路的抽头比较多，一般在20以上。因此每次抽头的更新都需要复数的乘法器，硬件消耗很大，本专利采用将误差首先量化到2的幂指数的方式，从而将乘法实现转换为移位实现，另外，由于每个抽头都需要经过计算均衡输出和系数更新的过程，在一个符号周期内可以通过块处理的方式，串行的计算出相邻两个抽头的系数和输出值，从而就可以进一步减少硬件代价。The working principle of the present invention is as follows: due to the non-ideality of the wired channel, the equalization circuit needs to provide initial convergence with a blind equalization method, and then turns to a decision-oriented method. The impact brought is that under these two different methods , the calculation formula (1) (4) of the error function is different. In the coefficient update formula (2) (5), it can be seen that the error needs to participate in the multiplication operation of the data, because the taps of the equalization circuit are more , generally above 20. Therefore, complex multipliers are required for each tap update, which consumes a lot of hardware. This patent adopts the method of firstly quantizing the error to a power of 2, thereby converting the multiplication implementation into a shift implementation. In addition, because each tap is It is necessary to go through the process of calculating the equalization output and updating the coefficients. In one symbol period, the coefficients and output values of two adjacent taps can be calculated serially through block processing, so that the hardware cost can be further reduced.

将误差量化到2的幂次方是按照如下的方程更新系数：Quantizing the error to a power of 2 is to update the coefficients according to the following equation:

C(k+1)＝C(k)+μ*Q(e)*X(k)^* (7)C(k+1)＝C(k)+μ*Q(e)*X(k) ^* (7)

Q(.)表示量化函数，量化后的数值表示为2^b，因为实践中通常将μ设为2^a，那么μ*Q(e)可以表示为2^a+b，因此步长和误差的乘积可以用电路上的对输入数据的移位加以实现，其中误差是由算法所处的时刻决定的，见式(1)和(4)。Q(.) represents the quantization function, and the quantized value is expressed as 2 ^b , because in practice, μ is usually set to 2 ^a , then μ*Q(e) can be expressed as 2 ^a+b , so the product of the step size and the error It can be implemented by shifting the input data on the circuit, where the error is determined by the moment of the algorithm, see formulas (1) and (4).

采用抽头块处理的方式可以有效的减少计算均衡输出和系数更新模块的数目，其原理是将抽头并行的运算转换到局部的处理，具体而言，就是采用将相邻两个抽头的系数更新和乘法运算模块复用，从而可以减少一半数目的乘法器。The method of tap block processing can effectively reduce the number of calculation equalization output and coefficient update modules. The principle is to convert the parallel operation of taps to local processing. Specifically, the coefficient update and Multiplication operation modules are multiplexed, thereby reducing the number of multipliers by half.

与现有技术相比，本发明具有如下优点：传统的均衡器在系数更新的计算上采用误差和数据的相乘，然后根据步长大小对数据移位来完成系数更新。本发明首先将误差量化到2的幂指数，因此系数的更新只需要通过对数据的移位来完成，相当于减少了一个乘法器。而在计算均衡输出时，并没有采用并行计算方法，而是将2路抽头结合起来使用一个系数更新和计算抽头的乘法器模块。以2路抽头I和Q路的计算量而言：并行的实现需要8个乘法和4个移位电路，而采用本专利设计技术后，硬件规模为2个乘法器，1个移位电路和1个量化器(量化器在整个均衡电路中只需要一个)，硬件减少到四分之一。本发明所设计的均衡器结构简单，易于VLSI实现，能够有效的消除码间干扰，对基于DVB-C的接收芯片具有非常实际的参考意义。Compared with the prior art, the present invention has the following advantages: traditional equalizers use the multiplication of error and data in the calculation of coefficient update, and then complete the coefficient update by shifting the data according to the step size. The present invention firstly quantizes the error to a power of 2, so the update of the coefficient only needs to be completed by shifting the data, which is equivalent to reducing a multiplier. When calculating the equalized output, the parallel calculation method is not adopted, but the 2-way taps are combined to use a multiplier module for updating coefficients and calculating the taps. In terms of the calculation amount of 2-way tap I and Q-way: parallel implementation requires 8 multiplication and 4 shift circuits, and after adopting this patented design technology, the hardware scale is 2 multipliers, 1 shift circuit and 1 quantizer (only one quantizer is needed in the whole equalization circuit), the hardware is reduced to a quarter. The equalizer designed by the invention has a simple structure, is easy to implement in VLSI, can effectively eliminate intersymbol interference, and has very practical reference significance for receiving chips based on DVB-C.

附图说明 Description of drawings

图1是本发明提出的用于实施正交调幅信号解调的均衡电路的原理框图。FIG. 1 is a functional block diagram of an equalization circuit for demodulating quadrature amplitude modulation signals proposed by the present invention.

图2是用于实施正交调幅信号解调的均衡电路前馈抽头块运算电路框图。Fig. 2 is a block diagram of an equalization circuit feed-forward tap block operation circuit for demodulating quadrature amplitude modulation signals.

图3是用于实施正交调幅信号解调的均衡电路后馈抽头块运算电路框图。Fig. 3 is a block diagram of an equalizing circuit for implementing quadrature amplitude modulation signal demodulation and feeding back a tap block operation circuit.

图4是本发明用于计算实施抽头块运算电路的I路块输出电路的电路图。Fig. 4 is a circuit diagram of an I-way block output circuit used to calculate and implement a tap block operation circuit in the present invention.

图5是本发明用于计算实施抽头块运算电路的Q路块输出电路的电路图。Fig. 5 is a circuit diagram of the Q block output circuit used to calculate and implement the tap block operation circuit in the present invention.

图6是本发明用于实施正交调幅信号解调的均衡电路的取补电路的电路图。Fig. 6 is a circuit diagram of the complement circuit of the equalization circuit for demodulating the quadrature amplitude modulation signal according to the present invention.

图7是本发明用于实施正交调幅信号解调的均衡电路的误差计算的电路图。Fig. 7 is a circuit diagram of the error calculation of the equalization circuit for demodulating the quadrature amplitude modulation signal according to the present invention.

图8是本发明用于误差计算电路中的有限状态机的电路图。Fig. 8 is a circuit diagram of the finite state machine used in the error calculation circuit of the present invention.

图9是本发明提出的量化器的电路图。Fig. 9 is a circuit diagram of a quantizer proposed by the present invention.

图10是本发明用于实施正交调幅信号解调的均衡电路的移位更新模块的电路图。FIG. 10 is a circuit diagram of a shift updating module of an equalization circuit for demodulating a quadrature amplitude modulation signal according to the present invention.

图11是以往技术中实施正交调幅信号解调的I路均衡电路的电路图。FIG. 11 is a circuit diagram of an I-way equalization circuit implementing quadrature amplitude modulation signal demodulation in the prior art.

图12是本发明提出的用于实施正交调幅信号解调的均衡电路的锁存器的电路图。FIG. 12 is a circuit diagram of a latch of an equalization circuit for implementing demodulation of a quadrature amplitude modulation signal proposed by the present invention.

图13是本发明所使用的判决电路。Fig. 13 is a decision circuit used in the present invention.

图14是未受干扰的接收信号星座图Figure 14 is the undisturbed received signal constellation diagram

图15是经过噪声和码间干扰后的星座图。Fig. 15 is a constellation diagram after noise and intersymbol interference.

图16是经过均衡器恢复后的星座图。Fig. 16 is a constellation diagram after restoration by an equalizer.

图17是经过均衡器工作过程中的均方误差。Figure 17 shows the mean square error during the equalizer working process.

具体实施方式 Detailed ways

如图1所示，一种有线数字电视中的自适应均衡电路，包含前馈抽头块运算电路1，均衡Q路输出加法器2，均衡I路输出加法器3，判决电路4，误差计算电路5，量化电路6，移位控制量加法电路7和后馈抽头块运算电路8，带有码间干扰的第k+k1时刻I路抽头输入数据x_I，k+k1和第k+k1时刻Q路抽头输入数据x_Q，k+k1接第一个前馈抽头块运算电路1，第一个前馈抽头块运算电路1的I路块输出y_I，1接均衡I路输出加法器3，Q路块输出y_Q，1接均衡Q路输出加法器2，第一个前馈抽头块运算电路1输出的第k+k1-2时刻I路数据x_I，k+k1-2和第k+k1-2时刻Q路数据x_Q，k+k1-2顺次地接第二个前馈抽头块运算电路，依此类推直到I路x_I，k+1和Q路x_Q，k+1接最后一个前馈抽头块运算电路，上述所有的前馈抽头块运算电路的I路输出都接均衡I路输出加法器3，Q路输出都接均衡Q路输出加法器2，此时均衡Q路输出加法器2的输出为第k时刻的均衡Q路输出值y_Q，k，均衡I路输出加法器3的输出为第k时刻的均衡I路输出值y_I，k，上述均衡Q路输出值y_Q，k和均衡I路输出值y_I，k分别输出至判决电路4和误差计算电路5，判决电路4输出的第k时刻I路判决输出d_I，k和Q路判决输出d_Q，k，分别输入至误差计算电路5和后馈抽头块运算电路8，误差计算电路5的输出为第k时刻的I路误差信号e_I和Q路误差信号e_Q，其分别输入至量化电路6，量化电路6的输出为I路量化误差信号Qe_I和Q路量化误差信号Qe_Q，其分别输入至移位控制量加法电路7，移位控制量加法电路7的另外两个输入为步长μ_LMS和μ_CMA，移位控制量加法电路7的输出为I路移位控制量S_I和Q路移位控制量S_Q，其分别输入至各个前馈抽头块运算电路1和各个后馈抽头块运算电路8中，第一个后馈抽头块运算电路8的I路块输出Z_I，1接均衡I路输出加法器3，Q路的块输出Z_Q，1接均衡Q路输出加法器2，第一个后馈抽头块运算电路8输出的第k-2时刻I路数据d_I，k-2和第k-2时刻Q路数据d_Q，k-2顺次地接第二个后馈抽头块运算电路，依此类推直到I路第k-k2+1时刻数据d_I，k-k2+1和Q路第k-k2+1时刻数据d_Q，k-k2+1接最后一个后馈抽头块运算电路，上述所有的后馈抽头块运算电路的I路输出都接均衡I路输出加法器3，Q路输出也都接均衡Q路输出加法器2。As shown in Figure 1, an adaptive equalization circuit in a cable digital television includes a feedforward tap block operation circuit 1, an equalized Q-way output adder 2, an equalized I-way output adder 3, a decision circuit 4, and an error calculation circuit 5. Quantization circuit 6, shift control amount addition circuit 7 and feed-back tap block operation circuit 8, with intersymbol interference at k+k1 moment I tap input data x _{I, k+k1} and k+k1 moment Q-way tap input data x _{Q, k+k1} is connected to the first feed-forward tap block operation circuit 1, and the I-way block output y _{I of the first feed-forward tap block operation circuit 1} is connected to the equalized I-way output adder 3 , the Q road block output y _{Q, 1} is connected to the balanced Q road output adder 2, the first feedforward tap block operation circuit 1 outputs the I road data x _{I at the k+k1-2 moment, k+k1-2} and the first At k+k1-2, the Q-way data x _{Q, k+k1-2} are sequentially connected to the second feed-forward tap block operation circuit, and so on until I-way x _{I, k+1} and Q-way x _{Q, k +1} is connected to the last feed-forward tap block operation circuit, the I road output of all the above-mentioned feed-forward tap block operation circuits is connected to the balanced I road output adder 3, and the Q road output is connected to the balanced Q road output adder 2, at this time The output of the balanced Q road output adder 2 is the balanced Q road output value y _{Q at the k moment, k} , and the output of the balanced I road output adder 3 is the balanced I road output value y _{I at the k time, k} . Q road output value y _{Q, k} and balanced I road output value y _{I, k} are output to decision circuit 4 and error calculation circuit 5 respectively, and the kth moment I road judgment output d _{I of judgment circuit 4 output, k} and Q road judgment The output d _{Q, k} are respectively input to the error calculation circuit 5 and the feed-back tap block operation circuit 8, the output of the error calculation circuit 5 is the I-way error signal e _I and the Q-way error signal e _Q at the kth moment, which are respectively input To the quantization circuit 6, the output of the quantization circuit 6 is the quantization error signal Qe _I of the I road and the quantization error signal Qe _Q of the Q road, which are respectively input to the shift control amount addition circuit 7, and the other two of the shift control amount addition circuit 7 The input is the step size μ _LMS and μ _CMA , and the output of the shift control amount addition circuit 7 is the I-way shift control amount S _I and the Q-way shift control amount S _Q , which are respectively input to each feedforward tap block operation circuit 1 And in each back-feeding tap block computing circuit 8, the I road block output Z _{I of the first back-feeding tap block computing circuit 8, 1} is connected to the balanced I road output adder 3, and the block output Z _{Q of the Q road, 1} is connected to the balanced Q road output adder 2, the k-2 moment I road data d _{I of the first feed-back tap block operation circuit 8 output, k-2} and the k-2 time Q road data d _{Q, k-2} sequentially The ground is connected to the second feed-back tap block operation circuit, and so on until the I road k-k2+1 time data d _{I, k-k2+1} and the Q road k-k2+1 time data d _{Q, k- k2+1} is connected to the last feed-back tap block operation circuit, and the I-way output of all the above-mentioned back-feed tap block operation circuits is connected to the balanced I-way output plus The legal device 3 and the output of the Q path are also connected to the output adder 2 of the balanced Q path.

如图2所示，上述前馈抽头块运算电路1，其I路数据的连接方式和Q路数据的连接方式完全相同，第k+k1时刻I路抽关输入数据x_I，k+k1接锁存器11的输入端，同时接数据选择器12的B输入端，锁存器11的输出第k+k1-1时刻I路数据x_I，k+k1-1接锁存器17的输入，锁存器17的输出第k+k1-2时刻I路数据x_I，k+k1-2接上述第二个前馈抽头块运算电路，同时上述第k+k1-1时刻I路数据x_I，k+k1-1接数据选择器12的A输入端，数据选择器的C控制端由内部时序控制，在一个符号周期的前半时刻选择第k+k1时刻I路输入数据x_I，k+k1，后半时刻选择第k+k1-1时刻I路输入x_I，k+k1-1输出，数据选择器12的输出分别接I路块输出电路13、Q路块输出电路14和系数更新模块16，同理Q路第k+k1时刻抽头输入数据x_Q，k+k1接锁存器18和数据选择器20的A输入端，锁存器18的输出第k+k1-1时刻Q路数据x_Q，k+k1-1接数据选择器20的B输入端和锁存器19，锁存器19的输出第k+k1-2时刻Q路数据x_Q，k+k1-2接上述第二个前馈抽头块运算电路，数据选择器20的输出也分别接I路块输出电路13、Q路块输出电路14和系数更新模块16，上述I路移位控制量S_I和Q路移位控制量S_Q接系数更新模块16，系数更新模块16的输出接串并转换电路21和锁存器15，锁存器15的输出接系数更新模块16，串并转换电路21的第一输出I路前馈系数C_I，1和第二输出Q路前馈系数C_Q，1同时分别接I路块输出电路13和Q路块输出电路14，I路块输出电路13的输出为y_I，1，Q路块输出电路14的输出为y_Q，1。As shown in Fig. 2, above-mentioned feed-forward tap block operation circuit 1, the connection mode of its I road data and the connection mode of Q road data are exactly the same, the k+k1 moment I road tap input data x _{1, k+k1} connects The input terminal of latch 11 is connected to the B input terminal of data selector 12 simultaneously, and the output k+k1-1 moment I road data x _{1 of latch 11, k+k1-1} connects the input of latch 17 , the output of the latch 17 at the k+k1-2 moment I road data x1 _{, k+k1-2} is connected to the above-mentioned second feed-forward tap block operation circuit, while the above-mentioned k+k1-1 moment I road data x _{I, k+k1-1} is connected to the A input terminal of the data selector 12, and the C control terminal of the data selector is controlled by the internal sequence, and selects the k+k1 moment I road input data x _{I at the first half of a symbol period, k +k1} , the second half of the time selects the k+k1-1 moment I road input x _{I, k+k1-1} output, the output of the data selector 12 is respectively connected to the I road block output circuit 13, the Q road block output circuit 14 and the coefficient Updating module 16, similarly, Q road taps input data x _{Q at the k+k1th moment, k+k1} is connected to the A input end of the latch 18 and the data selector 20, and the output of the latch 18 is at the k+k1-1th moment Q-way data x _{Q, k+k1-1} is connected to the B input terminal of the data selector 20 and the latch 19, and the output of the latch 19 is the Q-way data x _{Q, k+k1-2} at the k+k1-2 moment Connect the above-mentioned second feed-forward tap block arithmetic circuit, the output of data selector 20 also connects respectively I road block output circuit 13, Q road block output circuit 14 and coefficient update module 16, above-mentioned I road shift control amount S ₁ and The Q-way shift control amount S _Q is connected to the coefficient updating module 16, and the output of the coefficient updating module 16 is connected to the serial-parallel conversion circuit 21 and the latch 15, and the output of the latch 15 is connected to the coefficient updating module 16, and the output of the serial-parallel conversion circuit 21 The first output I road feed-forward coefficient C _{I, 1} and the second output Q road feed-forward coefficient C _{Q, 1} are respectively connected to the I road block output circuit 13 and the Q road block output circuit 14, the output of the I road block output circuit 13 is y _I,1 , and the output of the Q block output circuit 14 is y _Q,1 .

如图3所示，上述后馈抽头块运算电路8，其电路结构和前馈抽头块运算电路1完全相同，判决后第k时刻I路数据d_I，k接锁存器11的输入端，同时接数据选择器12的B输入端，锁存器11的输出第k-1时刻I路数据d_I，k-1接锁存器17的输入，锁存器17输出的第k-2时刻I路数据d_I，k-2接上述第二个后馈抽头块运算电路，同时上述第k-1时刻I路数据d_I，k-1接数据选择器12的A输入端，数据选择器的C控制端由内部时序控制，在一个符号周期的前半时刻选择第k时刻I路数据d_I，k，后半时刻选择第k-1时刻I路数据d_I，k-1输出，数据选择器12的输出分别接I路块输出电路13、Q路块输出电路14和系数更新模块16，同理判决后第k时刻Q路数据d_Q，k接锁存器18和数据选择器20的A输入端，锁存器18的输出第k-1时刻Q路数据d_Q，k-1接数据选择器20的B输入端和锁存器19，锁存器19输出的第k-2时刻Q路数据d_Q，k-2接上述第二个后馈抽头块运算电路，数据选择器20的输出也分别接I路块输出电路13、Q路块输出电路14和系数更新模块16，上述I路移位控制量S_I和Q路移位控制量S_Q接系数更新模块16，系数更新模块16的输出接串并转换电路21和锁存器15，锁存器15的输出接系数更新模块16。串并转换电路21的第一输出后馈I路系数C_I，1 ^B和第二输出后馈Q路系数C_Q，1 ^B同时分别接I路块输出电路13和Q路块输出电路14，I路块输出电路13的输出为Z_I，1，Q路块输出电路14的输出为Z_Q，1。As shown in Figure 3, the above-mentioned feed-back tap block operation circuit 8 has the same circuit structure as the feed-forward tap block operation circuit 1, and the I-way data d1 at the kth moment after the judgment _{, k} is connected to the input end of the latch 11, Connect the B input end of data selector 12 simultaneously, the output k-1 moment I road data d 1 of latch 11 _{, k-1} connects the input of latch 17, the k-2 moment that latch 17 outputs Road I data d _{I, k-2} is connected to the above-mentioned second feed-back tap block operation circuit, while the above-mentioned k-1th moment I road data d _{I, k-1} is connected to the A input end of the data selector 12, and the data selector The C control terminal of C is controlled by the internal timing. In the first half of a symbol period, the I-channel data d _I,k at the k-th time is selected, and the I-channel data d _I,k-1 at the k-1th time is selected at the second half of the time. Output, data selection The output of the device 12 is respectively connected to the block output circuit 13 of the I road, the block output circuit 14 of the Q road and the coefficient update module 16, and the data d _{Q of the Q road at the k time after the similar decision, k} is connected to the latch 18 and the data selector 20 A input end, the output of the latch 18 at the k-1th moment Q road data d _{Q, k-1} is connected to the B input end of the data selector 20 and the latch 19, the k-2th moment at which the latch 19 outputs Q road data d _{Q, k-2} connects above-mentioned second feed-back tap block computing circuit, the output of data selector 20 also connects I road block output circuit 13, Q road block output circuit 14 and coefficient updating module 16 respectively, above-mentioned The I-way shift control amount S _I and the Q-way shift control amount S _Q are connected to the coefficient update module 16, and the output of the coefficient update module 16 is connected to the serial-to-parallel conversion circuit 21 and the latch 15, and the output of the latch 15 is connected to the coefficient update Module 16. After the first output of the serial-to-parallel conversion circuit 21, feed back the I-way coefficient C _{I, 1} ^B and the second output and feed the Q-way coefficient C _{Q, 1} ^B to connect the I-way block output circuit 13 and the Q-way block output circuit 14 respectively simultaneously, The output of the I block output circuit 13 is Z _I,1 , and the output of the Q block output circuit 14 is Z _Q,1 .

如图9所示，上述量化电路6包含比较器601，比较器602和与门603，对I路和Q路作并行处理，且处理方式完全相同，上述误差计算电路(5)输出的第k时刻的I路误差信号e_I和Q路误差信号e_Q分别输入到比较器601和比较器602的一个输入端，比较器601的另一个输入端为固定阈值α2，比较器602的另一个输入端为固定阈值α1，上述两个比较器的输出分别接与门603的第一输入端和第二输入端，量化值接与门603的第三输入端，与门603的输出为I路量化误差信号Qe_I和Q路量化误差信号Qe_Q。As shown in Figure 9, above-mentioned quantization circuit 6 comprises comparator 601, comparator 602 and AND gate 603, and I road and Q road are processed in parallel, and processing mode is exactly the same, the kth output of above-mentioned error calculation circuit (5) The I-way error signal e _I and the Q-way error signal _eQ at the moment are respectively input to one input end of the comparator 601 and the comparator 602, the other input end of the comparator 601 is a fixed threshold α2, and the other input end of the comparator 602 End is fixed threshold α1, the output of above-mentioned two comparators connects the first input end and the second input end of AND gate 603 respectively, and the quantization value connects the 3rd input end of AND gate 603, and the output of AND gate 603 is I road quantization Error signal Qe _I and Q channel quantization error signal Qe _Q .

在图2中，系数更新模块16按下式进行系数更新：In Fig. 2, coefficient update module 16 carries out coefficient update as follows:

${C C}_{I I} ((k k + + 11)) = = {C C}_{I I} ((k k)) + + {X x}_{I I} 22^{- - {S S}_{I I}} + + {X x}_{Q Q} 22^{- - {S S}_{Q Q}}$

${C C}_{Q Q} ((k k + + 11)) = = {C C}_{Q Q} ((k k)) + + {X x}_{I I} 22^{- - {S S}_{Q Q}} - - {X x}_{Q Q} 22^{- - {S S}_{I I}} - - - - - - ((88))$

其中S_I和S_Q为移位控制加法电路的输出，系数更新模块16在前半符号周期完成x_I，k+k1和x_Q，k+k1的系数更新，在后半符号周期完成x_I，k+k1-1和x_Q，k+k-1的系数更新。I路块输出13完成I路系数和数据的相乘，其工作过程为在前半符号周期完成I路第k+k1抽头与系数的乘减运算，在符号周期的后半部分完成第I路第k+k1-1抽头与系数的乘减运算，并将两次抽头运算的结果相加得到y_I，1。Q路块输出14完成Q路系数和数据的相乘，其工作过程为在前半符号周期完成Q路第k+k1抽头与系数的乘减，在符号周期的后半部分完成Q路第k+k1-1抽头与系数的乘减运算，并将并将两次抽头运算的结果相加得到y_Q，1。Wherein S _I and S _Q are the outputs of the shift control addition circuit, and the coefficient update module 16 completes x _{I, k+k1} and x _{Q, the coefficient update of k+k1} in the first half symbol period, completes x _{I in the second half symbol period,} The coefficients of _k+k1-1 and x _Q,k+k-1 are updated. The I road block output 13 completes the multiplication of the I road coefficient and the data, and its working process is to complete the multiplication and subtraction of the I road k+k1 tap and the coefficient in the first half of the symbol period, and complete the I road and the first tap in the second half of the symbol period. The multiplication and subtraction operation of k+k1-1 taps and coefficients, and adding the results of the two tap operations to obtain y _I,1 . The Q-way block output 14 completes the multiplication of Q-way coefficients and data. Its working process is to complete the multiplication and subtraction of Q-way k+k1 taps and coefficients in the first half of the symbol period, and complete the Q-way k+th tap in the second half of the symbol period. The multiplication and subtraction operation between the k1-1 tap and the coefficient, and adding the results of the two tap operations to obtain y _Q,1 .

在图3中，后馈抽头块运算单元8的结构，其连接关系和工作过程与前馈块运算单元的结构完全相同，区别在于后馈抽头块运算单元的输入为判决后第k时刻的数据d_I，k和d_Q，k，输出为至下一后馈抽头块运算单元的数据为第k-2时刻的d_I，k-2和d_Q，k-2，输出至均衡Q路输出加法器2的后馈Q路输出Z_Q，1，输出至均衡I路输出加法器3的后馈I路输出Z_I，1。In Fig. 3, the structure of the feed-back tap block operation unit 8, its connection relationship and working process are exactly the same as the structure of the feed-forward block operation unit, the difference is that the input of the feed-back tap block operation unit is the data at the kth moment after the decision d _{I, k} and d _{Q, k} , output to the next feed-back tap block operation unit is d _{I, k-2} and d _{Q, k-2} at the k-2th moment, output to the balanced Q output The feed-back Q output Z _Q,1 of the adder 2 is output to the feed-back I output Z _I,1 of the balance I output adder 3 .

如图4所示，用于前馈抽头块运算电路1的I路输出13包括乘法器131，求补电路132(如图6)，加法器133，与门134和触发器135。输入至13的为数据x_I和x_Q，系数C_I和C_Q，其工作过程为在一个符号周期的上半时间内，与门的控制端输入为0，此时计算前馈抽头块运算电路1中第k+k1时刻I和Q路数据x_I，k+k1和x_Q，k+k1和系数的乘减运算，见公式(3)(6)，在符号周期的的后半时间内，与门的控制端输入为1，上述第k+k1时刻I和Q路数据x_I，k+k1和x_Q，k+k1和系数的乘减结果通过触发器135反馈至加法器133，并进行前馈抽头块运算电路1中第k+k1-1时刻I和Q路数据x_I，k+k1-1和x_Q，k+k1-1和系数的乘减运算，加法器133完成相邻两抽头输出的相加，加法器133的输出即为前馈I路输出y_I，1。As shown in FIG. 4 , the I output 13 for the feedforward tap block operation circuit 1 includes a multiplier 131 , a complement circuit 132 (as in FIG. 6 ), an adder 133 , an AND gate 134 and a flip-flop 135 . The input to 13 is the data x _I and x _Q , the coefficients C _I and C _Q , and its working process is that in the first half of a symbol period, the input of the control terminal of the AND gate is 0, and the feedforward tap block operation is calculated at this time In circuit 1, the multiplication and subtraction of I and Q channel data x _{I, k+k1} and x _{Q, k+k1} and coefficients at the k+k1th moment in circuit 1, see formula (3)(6), in the second half of the symbol period Inside, the control terminal input of the AND gate is 1, and the above k+k1th moment I and Q channel data x _{I, k+k1} and x _{Q, the multiplication and subtraction results of k+k1} and the coefficient are fed back to the adder 133 through the flip-flop 135 , and carry out the k+k1-1 moment I and Q road data x _{I in feed-forward tap block operation circuit 1, k+k1-1} and x _{Q, the multiplication and subtraction operation of k+k1-1} and coefficient, adder 133 The addition of the outputs of two adjacent taps is completed, and the output of the adder 133 is the output of the feedforward I channel y _I,1 .

如图5所示，用于前馈抽头块运算电路1的Q路块输出电路14包括乘法器141，加法器142，与门143和触发器144。输入至14的为数据x_I和x_Q，系数C_I和C_Q，其工作过程为在一个符号周期的上半时间内，与门的控制端输入为0，此时计算前馈抽头块运算电路1中第k+k1时刻I和Q路数据x_I，k+k1和x_Q，k+k1和系数的乘加运算，见公式(3)(6)，在符号周期的的后半时间内，与门的控制端输入为1，上述第k+k1时刻的I和Q路数据x_I，k+k1和x_Q，k+k1和系数的乘加结果通过触发器144反馈至加法器142，并进行前馈抽头块运算电路1中第k+k1-1时刻I和Q路数据数据x_I，k+k1-1和x_Q，k+k1-1和系数的乘加运算，加法器142完成相邻两抽头输出的相加，加法器142的输出即为前馈的Q路输出y_Q，1。As shown in FIG. 5 , the Q-block output circuit 14 used in the feedforward tap block operation circuit 1 includes a multiplier 141 , an adder 142 , an AND gate 143 and a flip-flop 144 . The input to 14 is the data x _I and x _Q , the coefficients C _I and C _Q , and its working process is that in the first half of a symbol period, the input of the control terminal of the AND gate is 0, and the feedforward tap block operation is calculated at this time The multiplication and addition operation of I and Q channel data x _{I, k+k1} and x _{Q, k+k1} and coefficients at the k+k1th moment in circuit 1, see formula (3)(6), in the second half of the symbol period Inside, the input of the control terminal of the AND gate is 1, and the above-mentioned I and Q channel data x _{I, k+k1} and x _{Q at the k+k1 moment, and the multiplication and addition results of k+k1} and the coefficient are fed back to the adder through the flip-flop 144 142, and carry out the k+k1-1 moment I and Q road data data x _{I in the feed-forward tap block operation circuit 1, k+k1-1} and x _{Q, k+k1-1} and the multiplication and addition operation of coefficient, addition The adder 142 completes the addition of the outputs of two adjacent taps, and the output of the adder 142 is the feedforward Q output y _Q,1 .

如图7所示，上述误差计算电路5输入为均衡Q路输出加法器2输出y_Q，k，均衡I路输出加法器3输出y_I，k，判决电路4的输出d_I，k和d_Q，k，输出为误差信号e_I，k和e_Q，k，其工作原理是分别计算出LMS方法和CMA方法情况下的误差，根据式(1)(4)，所计算出的误差e_lms和e_cma可以分为I和Q路，并分别接至数据选择器的A和B端，数据选择器的选择端C由有限状态机501的输出控制，因此误差计算电路的输出即为k时刻的误差信号。As shown in Figure 7, the above-mentioned error calculation circuit 5 input is the output y _{Q of the balanced Q-way output adder 2, k} , the output y I _{, k of the balanced I-way output adder 3, and} the output d _{I, k} and d of the decision circuit 4 _{Q, k} , the output is the error signal e _{I, k} and e _{Q, k} , its working principle is to calculate the error of the LMS method and the CMA method respectively, according to the formula (1) (4), the calculated error e _lms and e _cma can be divided into I and Q circuits, and are respectively connected to terminals A and B of the data selector. The selection terminal C of the data selector is controlled by the output of the finite state machine 501, so the output of the error calculation circuit is k time error signal.

如图8所示，上述有限状态机501的输入为误差计算电路中的e_lms，有限状态机501的工作原理是累加出一定时间内误差e_lms的绝对值，并将该累加值与固定的数值α(由寄存器给出)比较来作为算法切换的依据。有限状态机501中计数器起定时作用，计数器输出在每隔固定时间后输出为低，其他时间为高。当计数器输出为高时，e_lms的的误差绝对值不停的累计，当到一定时间后，输出为低，上述累加的误差值输出至比较器，当该误差累加值小于给定数值α时，CONT输出为0，反之CONT输出为1。As shown in Figure 8, the input of the above-mentioned finite state machine 501 is e _lms in the error calculation circuit, the working principle of the finite state machine 501 is to accumulate the absolute value of the error e _lms within a certain period of time, and compare the accumulated value with a fixed The value α (given by the register) is compared as the basis for algorithm switching. The counter in the finite state machine 501 plays a timing role, and the output of the counter is low after every fixed time, and high at other times. When the counter output is high, the absolute value of the error of e _lms is continuously accumulated. After a certain period of time, the output is low, and the above-mentioned accumulated error value is output to the comparator. When the accumulated error value is less than the given value α , CONT output is 0, otherwise CONT output is 1.

如图9所示，描述的是将I路误差信号e_I，k量化至I路输出量化值Qe_I的过程，Q路误差信号的处理过程完全和I路相同，即I和Q路的处理为并行的结构。上述量化电路6的电路输入为上述误差计算电路5的输出I和Q路的误差信号e_I，k和e_Q，k，输出为I和Q路的量化误差输出值Qe_I和Qe_Q，量化电路6的工作原理为将输入的I和Q路误差e_I，k和e_Q，k根据大小量化到2^b，b为3bit。根据上述工作原理可以看到，量化电路6可以由比较器所构成，图9描述了当输入的误差e_I，k和e_Q，k取值范围在[α1，α2]时的量化电路，此时，两个比较器的输出都为1，因此与门的输出由预先设定的量化值决定。同理，对于不同的输入e_I，k和e_Q，k，预先设定不同的输入取值范围情况下的量化值即可得到不同的I和Q量化误差输出值Qe_I和Qe_Q。经过以上的处理，就得出了第k时刻I和Q路误差量化值Qe_I和Qe_Q，该第k时刻I和Q路误差量化值Qe_I和Qe_Q进入移位控制量加法电路7，移位控制量加法电路7根据均衡电路在k时刻的工作状态(CMA或者LMS，由有限状态机501确定)将第k时刻I和Q路量化误差值Qe_I和Qe_Q与步长μ_LMS或者μ_CMA相加，步长的切换由有限状态机501确定，CONT输出为1时选择μ_LMS，反之选择μ_CMA，其大小由寄存器写入。移位控制量加法电路7的输出为第k时刻I和Q路移位量S_I，k和S_Q，k，第k时刻I和Q移位量S_I，k和S_Q，k用来计算下一时刻(k+1)的系数，见公式8。As shown in Figure 9, it describes the process of quantizing the I-way error signal e _{I, k} to the I-way output quantization value Qe _I , and the processing process of the Q-way error signal is completely the same as that of the I-way, that is, the processing of the I-way and the Q-way as a parallel structure. The circuit input of above-mentioned quantization circuit 6 is the output I of above-mentioned error calculation circuit 5 and the error signal e I of Q road _{, k} and e _{Q, k} , output is the quantization error output value Qe _I and Qe _Q of I and Q road, quantization The working principle of the circuit 6 is to quantize the input I and Q channel errors e _{I, k} and e _{Q, k} to 2 ^b according to the size, and b is 3 bits. According to the above working principle, it can be seen that the quantization circuit 6 can be composed of a comparator. Figure 9 describes the quantization circuit when the input errors e _{I, k} and e _{Q, k} range in [α1, α2]. When , the output of the two comparators is 1, so the output of the AND gate is determined by the preset quantization value. Similarly, for different inputs e _{I, k} and e _{Q, k} , by presetting the quantization values under different input value ranges, different I and Q quantization error output values Qe _I and Qe _Q can be obtained. Through the above processing, the I and Q path error quantization values Qe _I and Qe _Q are obtained at the kth moment, and the I and Q path error quantization values Qe _I and Qe _Q enter the shift control amount addition circuit 7 at the k moment, The shift control quantity addition circuit 7 is according to the operating state (CMA or LMS, determined by the finite state machine 501) of the equalization circuit at the k moment with the quantization error values Qe _I and Qe _Q of the kth moment I and Q paths and the step size μ _LMS or μ _CMA is added, and the switching of the step size is determined by the finite state machine 501. When the CONT output is 1, μ _LMS is selected, otherwise μ _CMA is selected, and its size is written by the register. The output of the shift control amount addition circuit 7 is the kth moment I and the Q channel shift amount S _{I, k} and S _{Q, k} , and the kth moment I and the Q shift amount S _{I, k} and S _{Q, k} are used for Calculate the coefficient for the next moment (k+1), see formula 8.

如图10所示，上述前馈抽头块运算电路1中系数更新模块16的具体电路实现中，输入为上述的移位控制量加法电路7的输出为第k时刻I和Q移位量S_I，k和S_Q，k，前一时刻的抽头系数值C_n，前一时刻的抽头系数值C_n是由系数更新模块16的输出C_n+1经过锁存器15延迟得到的，系数更新模块16的输入还包括数据选择器12和20的输出.内部控制逻辑在一个符号周期内按0101变化。在第k时刻系数更新模块16的作用是在一个符号周期内算出第k1个抽头和第k1-1抽头在下一时刻的抽头系数C_n+1(I和Q路串行输出)并输出至串转并电路21。从而在k+1时刻完成一次新的计算均衡输出。图10中初始输入为第k+k1时刻的I和Q路数据x_I，k+k1和x_Q，k+k1，在前半符号周期内，内部控制逻辑为0，此时完成的是Q路系数更新，得到第k+k1+1时刻的C_Q，k+1+k1，当内部控制逻辑为1，此时完成的是I路系数更新，得到第k+k1+1时刻的C_I，k+1+k1。后半符号周期内完成的是第k+k1-1个抽头的系数更新，处理过程与上述第k抽头的处理相同。经过以上的处理就得到了第k+1时刻的相邻两抽头的系数值，因此经过I路块输出13，Q路块输出14计算得到第k+1时刻的y_I，1和y_Q，1，第k+1时刻的y_I，1和y_Q，1输出至均衡I路输出加法器3，均衡Q路输出加法器2，就可以得到y_I，k+1和y_Q，k+1，从而完成了一次完整的系数更新。As shown in Figure 10, in the specific circuit implementation of the coefficient updating module 16 in the above-mentioned feedforward tap block operation circuit 1, the input is the above-mentioned shift control amount addition circuit 7, and the output is the kth moment I and Q shift amount S _{1 , k} and S _{Q, k} , the tap coefficient value C _n at the previous moment, the tap coefficient value C _n at the previous moment is obtained by delaying the output C _n+1 of the coefficient update module 16 through the latch 15, and the coefficient update The inputs to module 16 also include the outputs of data selectors 12 and 20. The internal control logic changes by 0101 during one symbol period. The function of the coefficient update module 16 at the kth moment is to calculate the tap coefficient C _n+1 of the k1th tap and the k1-1th tap at the next moment in one symbol period (serial output of I and Q roads) and output to the serial Turn to parallel circuit 21. Thus, a new calculation and equalization output is completed at time k+1. In Figure 10, the initial input is the I and Q channel data x _{I, k+k1} and x _{Q, k+k1} at the k+k1th moment. In the first half symbol period, the internal control logic is 0, and the Q channel is completed at this time. The coefficient is updated to obtain the C _{Q at the k+k1+1 time, k+1+k1} . When the internal control logic is 1, the coefficient update of the I channel is completed at this time, and the C _{I at the k+k1+1 time is obtained. k+1+k1} . What is completed in the second half of the symbol period is the coefficient update of the k+k1-1th tap, and the processing process is the same as that of the kth tap above. Through the above processing, the coefficient values of the adjacent two taps at the k+1th moment are obtained, so through the I road block output 13, the Q road block output 14 is calculated to obtain y _{I, 1} and y _{Q at the k+1th moment, 1} , y _{I, 1} and y _{Q at the k+1th moment, 1} are output to the equalized I-way output adder 3, and the balanced Q-way output adder 2 can obtain y _{I, k+1} and y _{Q, k+ 1} , thus completing a complete coefficient update.

图11为以往技术中并行实现的均衡电路的I路结构，其需要消耗大量的硬件代价，每个系数更新和计算均衡输出都需要一个乘法器，Q路结构也是如此。因此整个均衡电路需要消耗大量的芯片面积，同本专利的发明方法相比，本专利的发明方法可以减少近四分之三的规模。Figure 11 shows the I-way structure of the equalization circuit implemented in parallel in the prior art, which consumes a lot of hardware costs. Each coefficient update and calculation of the equalized output requires a multiplier, and the Q-way structure is the same. Therefore, the entire equalization circuit needs to consume a large amount of chip area. Compared with the inventive method of this patent, the inventive method of this patent can reduce the scale by nearly three-quarters.

图12是本发明中的锁存器的结构。Fig. 12 is the structure of the latch in the present invention.

如图13所示，描述的是将上述I路输出信号y_I，k叛决为I路判决值d_I，k的过程，Q路输出信号的处理过程完全和I路相同，即I和Q路的处理为并行的结构。判决电路的功能是将星座点周围一定区域内的输出值都输出为该星座点。由于矩形的QAM星座图相当于在两个正交载波上施加两个PAM信号产生，其判决原则可以参考普罗斯基编著的《数字通信》电子工业出版社2004年2月第3版P192～194。当第k时刻的均衡输出值在数值固定阈值1和固定阈值2时，比较器输出为1，从而选通与门打开，则判决电路的输出d_I，k为该区域内的星座点值。As shown in Figure 13, it describes the process of resolving the above-mentioned I-way output signal y _{I, k} into the I-way decision value d _{I, k} , and the processing process of the Q-way output signal is completely the same as that of the I-way, that is, I and Q Ways are processed in a parallel structure. The function of the judgment circuit is to output all the output values in a certain area around the constellation point as the constellation point. Since the rectangular QAM constellation diagram is equivalent to applying two PAM signals on two orthogonal carriers, its judgment principle can refer to "Digital Communication" edited by Prosky, Electronic Industry Press, February 2004, third edition, P192-194 . When the balanced output value at the kth moment is between the fixed threshold value 1 and the fixed threshold value 2, the output of the comparator is 1, so that the strobe AND gate is opened, and the output d _{I, k} of the decision circuit is the constellation point value in this area.

另外，本发明涉及的数据选择器、数据比较器、D触发器，串转并电路结构均采用公知的结构，例如可以采用黄正瑾编著《计算机结构与逻辑设计》高等教育出版社2001年6月第1版P71～P73、P166～P168，P106～P108，P127～P129中公知的结构，本发明涉及的数据选择器、数据比较器、D触发器的工作原理均与此相同。本发明D触发器中没有标注的CP端都接时钟CLK。该发明中的移位控制量加法电路的结构即为普通的加法电路。In addition, the data selector, data comparator, D flip-flop involved in the present invention, and the serial-to-parallel circuit structure all adopt known structures, for example, "Computer Structure and Logic Design" edited by Huang Zhengjin, June 2001, No. The known structures in P71～P73, P166～P168, P106～P108, P127～P129 of the 1st version, and the working principles of the data selector, data comparator and D flip-flop involved in the present invention are all the same. The CP terminals not marked in the D flip-flop of the present invention are all connected to the clock CLK. The structure of the shift control amount addition circuit in this invention is a common addition circuit.

实际的均衡效果图可以通过图14～17体现：图14是描述的是未受干扰的理想接收星座图，传输模式采用的是64QAM。图15描述的是经过码间干扰后的接收星座图(未经均衡)，星座点相当混乱，误码率很高。图16描述的是经过本发明后的均衡电路后的输出星座图，星座点相当的清晰，图17描述了在整个均衡处理过程中的误码率，可以看到7500个符号后误码率非常的小，也就是说均衡能够很有效的消除码间干扰。The actual equalization effect diagrams can be shown in Figures 14 to 17: Figure 14 describes the ideal receiving constellation diagram without interference, and the transmission mode adopts 64QAM. Figure 15 depicts the receiving constellation diagram after intersymbol interference (without equalization), the constellation points are quite chaotic, and the bit error rate is high. What Fig. 16 describes is the output constellation diagram after the equalization circuit of the present invention, and the constellation point is quite clear, and Fig. 17 has described the bit error rate in the whole equalization processing process, and it can be seen that the bit error rate is very high after 7500 symbols. is small, that is to say, equalization can effectively eliminate intersymbol interference.

Claims

1. An adaptive equalization circuit in a cable digital television, comprising a feed-forward tap block operation circuit (1), an equalized Q-way output adder (2), an equalized I-way output adder (3), and a decision circuit (4) , an error calculation circuit (5), a quantization circuit (6), a shift control amount addition circuit (7) and a feed-back tap block operation circuit (8), with the k+k1 moment I road tap input data of intersymbol interference x _{I, k+k1} and k+k1 moment Q road tap input data x _{Q, k+k1} connects the first feed-forward tap block operation circuit (1), the first feed-forward tap block operation circuit (1) I road block output y _{I, 1} is connected to balanced I road output adder (3), Q road block output y _{Q, 1} is connected to balanced Q road output adder (2), the first feedforward tap block operation circuit (1) The outputted k+k1-2 moment I channel data x _{I, k+k1-2} and k+k1-2 moment Q channel data x _{Q, k+k1-2} are sequentially connected to the second feedforward tap block Operation circuit, and so on until I road x _{I, k+1} and Q road x _{Q, k+1} is connected to the last feed-forward tap block operation circuit, and the I road outputs of all the above-mentioned feed-forward tap block operation circuits are connected to equalization I road output adder (3), Q road output all connects balanced Q road output adder (2), and now the output of balanced Q road output adder (2) is the balanced Q road output value y _{Q of the k moment, k} , the output of the balanced I-way output adder (3) is the balanced I-way output value y _{I at the k moment, k} , and the above-mentioned balanced Q-way output value y _{Q, k} and the balanced I-way output value y _{I, k} are output respectively To the judgment circuit (4) and the error calculation circuit (5), the kth moment I road judgment output d _{I of the judgment circuit (4) output, k} and the Q road judgment output _{dQ, k} are input to the error calculation circuit (5) respectively ) and the feed-back tap block operation circuit (8), the output of the error calculation circuit (5) is the I-way error signal e _I and the Q-way error signal e _Q of the k moment, which are respectively input to the quantization circuit (6), quantized The output of the circuit (6) is the quantization error signal Qe _I of the I road and the quantization error signal Qe _Q of the Q road, which are respectively input to the shift control amount addition circuit (7), and the other two of the shift control amount addition circuit (7) The input is the step size μ _LMS and μ _CMA , and the output of the shift control amount addition circuit (7) is the I-way shift control amount S _I and the Q-way shift control amount S _Q , which are respectively input to each feedforward tap block operation In circuit (1) and each back-feeding tap block operation circuit (8), the I road block output Z _{I of the first back-feeding tap block operation circuit (8), 1} connects equalization I road output adder (3), Q The block output Z _{Q of road, 1} is connected with balanced Q road output adder (2), the k-2th moment I road data d _{I of the k-2 moment output of the first feed-back tap block operation circuit (8), k-2} and the kth -2 moment Q road data d _{Q, k-2} is sequentially connected to the second feed-back tap block operation circuit, and so on until the I road k-k2+1 time data d _{I, k-k2+1} and Q road The k-k2+1 moment data d _{Q, k-k2+1} is connected to the last feed-back tap block operation circuit, and the I-way output of all the above-mentioned back-feed tap block operation circuits is connected to the balanced I-way output adder (3) , the output of the Q road is also connected to the equalized Q road output adder (2).

2. The adaptive equalization circuit in the cable digital television according to claim 1, above-mentioned feed-forward tap block operation circuit (1), the connection mode of its I road data and the connection mode of Q road data are exactly the same, the k+th K1 moment I road tap input data x _{1, k+k1} connects the input end of latch (11), connects the B input end of data selector (12) simultaneously, the output k+k1-th of latch (11) 1 moment I road data x _{1, k+k1-1} connects the input of latch (17), the output k+k1-2 moment I road data x _{1 of latch (17), k+k1-2} connects Above-mentioned second feed-forward tap block operation circuit, simultaneously above-mentioned k+k1-1 moment I road data x1 _{, k+k1-1} connects the A input terminal of data selector (12), the C control terminal of data selector Controlled by the internal timing, in the first half of a symbol period, the input data x _{I, k+k1} of the I channel is selected at the k+k1th moment, and the input data of the I channel x _{I, k+k1- 1} output, the output of the data selector (12) is respectively connected to the I road block output circuit (13), the Q road block output circuit (14) and the coefficient update module (16), and the tap input data at the k+k1 moment of the Q road in the same way x _{Q, k+k1} connects the A input end of latch (18) and data selector (20), the output k+k1-1 moment Q road data x _{Q of latch (18), k+k1- 1} connects the B input terminal of data selector (20) and latch (19), the output k+k1-2 moment Q road data x _{Q of the output of latch (19), k+k1-2} connects above-mentioned second A feed-forward tap block operation circuit, the output of the data selector (20) is also respectively connected to the I road block output circuit (13), the Q road block output circuit (14) and the coefficient update module (16), and the above-mentioned I road shift control Quantity S _I and Q road shift control quantity S _Q connect coefficient update module (16), the output of coefficient update module (16) connects series-to-parallel conversion circuit (21) and latch (15), latch (15) The output of the connection coefficient update module (16), the first output I road feed-forward coefficient C _{I of the serial-to-parallel conversion circuit (21), 1} and the second output Q road feed-forward coefficient C _{Q, 1} are respectively connected to the I road block output simultaneously Circuit (13) and Q road block output circuit (14), the output of I road block output circuit (13) is y _I,1 , the output of Q road block output circuit (14) is y _Q,1 .

3. The adaptive equalization circuit in the cable digital television according to claim 1, the above-mentioned feed-back tap block operation circuit (8), its circuit structure is exactly the same as the feed-forward tap block operation circuit (1), and the k-th Time I road data d _{I, k} connects the input end of latch (11), connects the B input end of data selector (12) simultaneously, the k-1th moment I road data d _I of latch (11) output _{, k-1} connects the input of latch (17), the k-2 moment I road data d _{1 of latch (17) output, k-2} connects above-mentioned second feed-back tap block operation circuit, above-mentioned simultaneously The k-1 moment I road data d _{I, k-1} connects the A input end of data selector (12), and the C control end of data selector is controlled by internal timing, selects the kth moment I in the first half moment of a symbol period Road data d _{I, k} , the second half moment selects k-1 moment I road data d _{I, k-1} output, the output of data selector (12) connects I road block output circuit (13), Q road block output respectively Circuit (14) and coefficient updating module (16), the Q road data d _{Q of the kth moment after the similar decision, k} connects the A input end of latch (18) and data selector (20), latch (18 ) output k-1 moment Q road data d _{Q, k-1} connects the B input terminal of data selector (20) and latch (19), the output k-2 moment Q of latch (19) Road data d _{Q, k-2} connect above-mentioned second feed back tap block computing circuit, the output of data selector (20) also connect respectively I road block output circuit (13), Q road block output circuit (14) and coefficient Update module (16), above-mentioned I road shift control amount S _I and Q road shift control amount S _Q connect coefficient update module (16), the output of coefficient update module (16) connects series-to-parallel conversion circuit (21) and lock register (15), and the output of the latch (15) is connected to the coefficient updating module (16). After the first output of the serial-to-parallel conversion circuit (21), feed back the I-way coefficient C _{I, 1} ^B and the second output and feed the Q-way coefficient C _{Q, and 1} ^B connect the I-way block output circuit (13) and the Q-way block respectively simultaneously In the output circuit (14), the output of the I block output circuit (13) is Z _I,1 , and the output of the Q block output circuit (14) is Z _Q,1 .

4. The adaptive equalization circuit in the cable digital television according to claim 1, above-mentioned quantization circuit (6) comprises the first comparator (601), the second comparator (602) and AND gate (603), to I The road and the Q road are processed in parallel, and the processing method is exactly the same, and the I road error signal e _I and the Q road error signal e _Q of the k moment of the above-mentioned error calculation circuit (5) output are respectively input to the first comparator (601) and one input terminal of the second comparator (602), the other input terminal of the first comparator (601) is a fixed threshold value α2, and the other input terminal of the first comparator (601) is a fixed threshold value α1, the above-mentioned first , the output of the second comparator is connected to the first input terminal and the second input terminal of the AND gate (603) respectively, and the quantized value preset according to the input error range is connected to the third input terminal of the AND gate (603), The output of the AND gate (603) is the I-channel quantization error signal Qe _I and the Q-channel quantization error signal Qe _Q .