CN100547988C - Adpative equalizing circuit in the cable digital TV - Google Patents

Abstract

The invention discloses the Adpative equalizing circuit in a kind of cable digital TV of the DVB-C of meeting standard, this circuit comprises forward taps piece computing circuit (1), balanced Q road output adder (2), balanced I road output adder (3), decision circuit (4), error calculation circuit (5), sample circuit (6), displacement controlled quentity controlled variable add circuit (7) and rear feed tap piece computing circuit (8); Finish coefficient update by sample circuit (6) and displacement controlled quentity controlled variable add circuit (7), and the piece processing mode of employing forward taps piece computing circuit (1) and rear feed tap piece computing circuit (8), above designing technique can effectively reduce the quantity of required multiplier, lowers the cost of chip design.The present invention can effectively reduce the complexity of realization under the situation of guaranteed performance, verified the performance of circuit simultaneously by planisphere, and the result shows and can effectively eliminate intersymbol interference to have actual using value.

Description

Adpative equalizing circuit in the cable digital TV

Technical field

The present invention relates to the reception technique of digital communicating field, be specifically related to the Adpative equalizing circuit in a kind of cable digital TV of the DVB-C of meeting standard.

Background technology

QAM (quadrature amplitude modulation) since its availability of frequency spectrum efficiently be applied in the DVB-C standard.But on bandwidth efficient channel during the digital signal of transmitting high speed, owing to exist the decline of channel and multipath to disturb, and when spider lines equipment is installed, the problem that connector is installed will cause producing big echo in the signal transmission, in addition the amplifier in the transmission course, filter etc. all may produce echo, and this will cause the very high error rate.

Adpative equalizing circuit is exactly in order to resist intersymbol interference and big echo interference, at first utilize norm method (Constant Modulus Algorithm, abbreviation CMA) method provides the initial convergence of equalizer equalizes value, forcing " eye pattern " to open, when within a certain period of time error transfers least mean-square error (LMS) method to littler error after convergence rate and convergence are provided faster less than certain numerical value post-equalization method.What designed equalizing circuit adopted is DFF, and DFF (DFE) is that pre-equalizer and feedback equalizer are formed by two transversal filters, and the feedforward filter device is used for offsetting forward direction and disturbs, and feedback filter is eliminated subsequent interference.

Suppose X _k ^TBe the signal value in t=kT equalizer feedforward constantly and the feedback filter, C _kBe k the equalizer coefficient vector in the mark space, then

X _k＝{x _k+K1，x _k+K1-1，...x _k，d _k-1，d _k-2，...d _k-K2} ^T

C _k＝{C _k，-K1，C _k，-K1+1...C _k，0，C _k，1，C _k，2...C _k，K2} ^T

Wherein K1, K2 are respectively the tap number of feedforward filter and decision feedback filter device, the output y of equalizer _kExpression formula be:

$y_k=X_k^T{C}_k=C_k^T{X}_k=\underset{j=-K1}{\overset{K2}{\mathrm{\Σ}}}{x}_{k-j}\×C_{k,j}$

1 least mean-square error (LMS) method

The LMS method is a kind of towards judgement, obtains the equalization methods of extensive use at present.When considering to be input as plural number, its error signal e _nExpression formula be:

Error signal is: e (k)=e _I(k)+je _Q(k)=(d _{I, k}-y _{I, k})+j (d _{Q, k}-y _{Q, k}) (1)

Wherein, d _{I, k}And d _{Q, k}Be respectively the t=k decision signal of balanced output constantly.

Tap coefficient is updated to:

C _I(k+1)＝C _I(k)+μ _LMS[e _I(k)X _I(k)+e _Q(k)X _Q(k)]

(2)

C _Q(k+1)＝C _Q(k)+μ _LMS[e _Q(k)X _I(k)-e _I(k)X _Q(k)]

Equalizer output formula is:

$y\left(k\right)=y_I\left(k\right)+{\mathrm{jy}}_Q\left(k\right)---\left(3\right)$

$=C_I^T\left(k\right)X_I\left(k\right)-C_Q^T\left(k\right)X_Q\left(k\right)+j[C_I^T\left(k\right)X_Q\left(k\right)+C_Q^T\left(k\right)X_I\left(k\right)]$

In the formula, X _I(k) and X _Q(k) be I and the Q road signal that k inputs to equalizer constantly, μ _LMSBe that equalizer is in LMS method step-length constantly.e _IAnd e _QIt is respectively the k error of LMS method constantly.

2 norm methods (CMA)

Its error signal is:

e(k)＝e _I(k)+je _Q(k)＝y _I，k*(R ₂-|y _k| ²)+jy _Q，k*(R ₂-|y _k| ²) (4)

Tap coefficient is updated to:

C _I(k+1)＝C _I(k)+μ _CMA[e _I(k)X _I(k)+e _Q(k)X _Q(k)]

(5)

C _Q(k+1)＝C _Q(k)+μ _CMA[e _Q(k)X _I(k)-e _I(k)X _Q(k)]

The norm method is output as

$y\left(k\right)=y_I\left(k\right)+{\mathrm{jy}}_Q\left(k\right)---\left(6\right)$

$=C_I^T\left(k\right)X_I\left(k\right)-C_Q^T\left(k\right)X_Q\left(k\right)+j[C_I^T\left(k\right)X_Q\left(k\right)+C_Q^T\left(k\right)X_I\left(k\right)]$

Wherein, e _IAnd e _QBe respectively the k error of CMA method constantly, μ _CMABe to be in CMA when equalizer

Method step-length constantly

Realize above-mentioned coefficient operation and calculate balanced output consuming a large amount of hardware configurations.Being respectively 6 and 15 with the feedforward and the tap number of rear feed is example, whole equalizing circuit needs 84 multipliers to finish the computing of coefficient update and balanced output, to consume a large amount of hardware sizes like this and take a large amount of chip areas, therefore, adopt and to optimize designing technique efficiently and have very important significance for the cost that reduces chip area and reduce chip.

Summary of the invention

The objective of the invention is to solve the huge problem of above-mentioned hardware consumption, the Adpative equalizing circuit in a kind of cable digital TV is provided, under the prerequisite of guaranteed performance, can reduce by about 3/4ths hardware size.

The present invention adopts following technical scheme to solve above-mentioned technical problem:

Adpative equalizing circuit in a kind of cable digital TV, comprise forward taps piece computing circuit 1, balanced Q road output adder 2, balanced I road output adder 3, decision circuit 4, error calculation circuit 5, sample circuit 6, displacement controlled quentity controlled variable add circuit 7 and rear feed tap piece computing circuit 8, data x is imported in the k+k1 I road tap constantly that has intersymbol interference _{I, k+k1}With k+k1 Q road tap constantly input data x _{Q, k+k1}Connect first forward taps piece computing circuit 1, the I road piece output y of first forward taps piece computing circuit 1 _{I, 1}Connect balanced I road output adder 3, Q road piece output y _{Q, 1}Connect balanced Q road output adder 2, the k+k1-2 of first forward taps piece computing circuit 1 output is I circuit-switched data x constantly _{I, k+k1-2}With k+k1-2 moment Q circuit-switched data x _{Q, k+k1-2}Connect second forward taps piece computing circuit in turn, the rest may be inferred up to I road x _{I, k+1}With Q road x _{Q, k+1}Connect last forward taps piece computing circuit, the I road output of above-mentioned all forward taps piece computing circuit all connects balanced I road output adder 3, the output of Q road all connects balanced Q road output adder 2, and balanced Q road output adder 2 is output as k balanced Q road output valve y constantly at this moment _{Q, k}, balanced I road output adder 3 is output as k balanced I road output valve y constantly _{I, k}, above-mentioned balanced Q road output valve y _{Q, k}With balanced I road output valve y _{I, k}Export decision circuit 4 and error calculation circuit 5 respectively to, the k of decision circuit 4 outputs I road judgement constantly output d _{I, k}With Q road judgement output d _{Q, k}, inputing to error calculation circuit 5 and rear feed tap piece computing circuit 8 respectively, error calculation circuit 5 is output as k I road error signal e constantly _IWith Q road error signal e _Q, it inputs to sample circuit 6 respectively, and sample circuit 6 is output as I road quantization error signal Qe _IWith Q road quantization error signal Qe _Q, it inputs to displacement controlled quentity controlled variable add circuit 7 respectively, and two other of displacement controlled quentity controlled variable add circuit 7 is input as step size mu _LMSAnd μ _CMA, displacement controlled quentity controlled variable add circuit 7 is output as I road displacement controlled quentity controlled variable S _IWith Q road displacement controlled quentity controlled variable S _Q, it inputs to respectively in each forward taps piece computing circuit 1 and each rear feed tap piece computing circuit 8, the I road piece output Z of first rear feed tap piece computing circuit 8 _{I, 1}Connect balanced I road output adder 3, the piece output Z on Q road _{Q, 1}Connect balanced Q road output adder 2, the k-2 of first rear feed tap piece computing circuit 8 outputs is I circuit-switched data d constantly _{I, k-2}With k-2 moment Q circuit-switched data d _{Q, k-2}Connect second rear feed tap piece computing circuit in turn, the rest may be inferred up to I road k-k2+1 moment data d _{I, k-k2+1}With Q road k-k2+1 moment data d _{Q, k-k2+1}Connect last rear feed tap piece computing circuit, the I road output of above-mentioned all rear feed tap piece computing circuit all connects balanced I road output adder 3, and the output of Q road also all connects balanced Q road output adder 2.

Operation principle of the present invention is as follows: because the wire message way imperfection, equalizing circuit need provide initial convergence with blind balance method, forward to then towards the method for judgement, the influence that is brought is under these two kinds of diverse ways, the calculating formula of its error function (1) (4) is different, in coefficient update formula (2) (5), can see that error is need to participate in and the multiplying of data, because the tapping ratio of equalizing circuit is more, generally more than 20.More new capital of therefore each tap needs the multiplier of plural number, hardware consumption is very big, this patent adopts the mode of error at first being quantized to 2 power exponent, thereby multiplication is realized being converted to displacement to be realized, in addition, owing to each tap all needs through calculating the process of balanced output and coefficient update, can be in a symbol period by the mode of piece processing, the coefficient that calculates adjacent two taps and the output valve of serial, thus just can further reduce hardware costs.

With the power power of error quantization to 2 is according to following equation update coefficients:

C(k+1)＝C(k)+μ*Q(e)*X(k) ^* (7)

Q (.) represents quantization function, and the numeric representation after the quantification is 2 ^b, because usually μ is made as 2 in the practice ^a, μ * Q (e) can be expressed as 2 so ^A+b, so the product of step-length and error can be realized that wherein error is seen formula (1) and (4) by the residing moment decision of algorithm with the displacement to the input data on the circuit.

The mode that adopts the tap piece to handle can effectively reduce the number that calculates balanced output and coefficient updating module, its principle is that the computing that tap is parallel is transformed into local processing, particularly, be exactly coefficient update and the multiplying module reuse that adopts adjacent two taps, thereby can reduce the multiplier of half number.

Compared with prior art, the present invention has following advantage: traditional equalizer adopts multiplying each other of sum of errors data in the calculating of coefficient update, according to step sizes data is shifted then and finishes coefficient update.The present invention is at first with the power exponent of error quantization to 2, so the renewal of coefficient only need finish by the displacement to data, is equivalent to reduce a multiplier.And when calculating balanced output, do not adopt parallel calculating method, but 2 tunnel taps are combined the multiplication module of using a coefficient update and calculating tap.Amount of calculation with 2 tunnel tap I and Q road: parallel realization needs 8 multiplication and 4 shift circuits, and after adopting this patent designing technique, hardware size is 2 multipliers, 1 shift circuit and 1 quantizer (quantizer only needs in whole equalizing circuit), hardware reduces to 1/4th.The designed equaliser structure of the present invention is simple, is easy to VLSI and realizes, can effectively eliminate intersymbol interference, and the receiving chip based on DVB-C is had very actual reference significance.

Description of drawings

Fig. 1 is the theory diagram that the present invention implements being used to of proposing the equalizing circuit of quadrature amplitude modulation signal demodulation.

Fig. 2 is the equalizing circuit forward taps piece computing circuit block diagram that is used to implement quadrature amplitude modulation signal demodulation.

Fig. 3 is the equalizing circuit rear feed tap piece computing circuit block diagram that is used to implement quadrature amplitude modulation signal demodulation.

Fig. 4 is the circuit diagram that the present invention is used to calculate the I road piece output circuit of implementing tap piece computing circuit.

Fig. 5 is the circuit diagram that the present invention is used to calculate the Q road piece output circuit of implementing tap piece computing circuit.

Fig. 6 is the circuit diagram of mending circuit of getting of the present invention's equalizing circuit of being used to implement quadrature amplitude modulation signal demodulation.

Fig. 7 is the circuit diagram of the Error Calculation of the present invention's equalizing circuit of being used to implement quadrature amplitude modulation signal demodulation.

Fig. 8 is the circuit diagram that the present invention is used for the finite state machine of error calculation circuit.

Fig. 9 is the circuit diagram of the quantizer that proposes of the present invention.

Figure 10 is the circuit diagram of the displacement update module of the present invention's equalizing circuit of being used to implement quadrature amplitude modulation signal demodulation.

Figure 11 is a circuit diagram of implementing the I road equalizing circuit of quadrature amplitude modulation signal demodulation in the conventional art.

Figure 12 is the circuit diagram of the latch of the present invention's equalizing circuit of implementing being used to of proposing quadrature amplitude modulation signal demodulation.

Figure 13 is a decision circuit used in the present invention.

Figure 14 is undisturbed received signal planisphere

Figure 15 is through the planisphere after noise and the intersymbol interference.

Figure 16 is the planisphere after recovering through equalizer.

Figure 17 is through the mean square error in the equalizer course of work.

Embodiment

As shown in Figure 1, Adpative equalizing circuit in a kind of cable digital TV, comprise forward taps piece computing circuit 1, balanced Q road output adder 2, balanced I road output adder 3, decision circuit 4, error calculation circuit 5, sample circuit 6, displacement controlled quentity controlled variable add circuit 7 and rear feed tap piece computing circuit 8, data x is imported in the k+k1 I road tap constantly that has intersymbol interference _{I, k+k1}With k+k1 Q road tap constantly input data x _{Q, k+k1}Connect first forward taps piece computing circuit 1, the I road piece output y of first forward taps piece computing circuit 1 _{I, 1}Connect balanced I road output adder 3, Q road piece output y _{Q, 1}Connect balanced Q road output adder 2, the k+k1-2 of first forward taps piece computing circuit 1 output is I circuit-switched data x constantly _{I, k+k1-2}With k+k1-2 moment Q circuit-switched data x _{Q, k+k1-2}Connect second forward taps piece computing circuit in turn, the rest may be inferred up to I road x _{I, k+1}With Q road x _{Q, k+1}Connect last forward taps piece computing circuit, the I road output of above-mentioned all forward taps piece computing circuit all connects balanced I road output adder 3, the output of Q road all connects balanced Q road output adder 2, and balanced Q road output adder 2 is output as k balanced Q road output valve y constantly at this moment _{Q, k}, balanced I road output adder 3 is output as k balanced I road output valve y constantly _{I, k}, above-mentioned balanced Q road output valve y _{Q, k}With balanced I road output valve y _{I, k}Export decision circuit 4 and error calculation circuit 5 respectively to, the k of decision circuit 4 outputs I road judgement constantly output d _{I, k}With Q road judgement output d _{Q, k}, inputing to error calculation circuit 5 and rear feed tap piece computing circuit 8 respectively, error calculation circuit 5 is output as k I road error signal e constantly _IWith Q road error signal e _Q, it inputs to sample circuit 6 respectively, and sample circuit 6 is output as I road quantization error signal Qe _IWith Q road quantization error signal Qe _Q, it inputs to displacement controlled quentity controlled variable add circuit 7 respectively, and two other of displacement controlled quentity controlled variable add circuit 7 is input as step size mu _LMSAnd μ _CMA, displacement controlled quentity controlled variable add circuit 7 is output as I road displacement controlled quentity controlled variable S _IWith Q road displacement controlled quentity controlled variable S _Q, it inputs to respectively in each forward taps piece computing circuit 1 and each rear feed tap piece computing circuit 8, the I road piece output Z of first rear feed tap piece computing circuit 8 _{I, 1}Connect balanced I road output adder 3, the piece output Z on Q road _{Q, 1}Connect balanced Q road output adder 2, the k-2 of first rear feed tap piece computing circuit 8 outputs is I circuit-switched data d constantly _{I, k-2}With k-2 moment Q circuit-switched data d _{Q, k-2}Connect second rear feed tap piece computing circuit in turn, the rest may be inferred up to I road k-k2+1 moment data d _{I, k-k2+1}With Q road k-k2+1 moment data d _{Q, k-k2+1}Connect last rear feed tap piece computing circuit, the I road output of above-mentioned all rear feed tap piece computing circuit all connects balanced I road output adder 3, and the output of Q road also all connects balanced Q road output adder 2.

As shown in Figure 2, above-mentioned forward taps piece computing circuit 1, the connected mode of the connected mode of its I circuit-switched data and Q circuit-switched data is identical, and k+k1 I constantly takes out on the road pass input data x _{I, k+k1}Connect the input of latch 11, connect the B input of data selector 12 simultaneously, the output k+k1-1 of latch 11 is I circuit-switched data x constantly _{I, k+k1-1}Connect the input of latch 17, the output k+k1-2 of latch 17 is I circuit-switched data x constantly _{I, k+k1-2}Connect above-mentioned second forward taps piece computing circuit, simultaneously above-mentioned k+k1-1 is I circuit-switched data x constantly _{I, k+k1-1}Connect the A input of data selector 12, the C control end of data selector is carved selection k+k1 I road input constantly data x by inner sequencing control at the preceding half of a symbol period _{I, k+k1}, the later half moment is selected k+k1-1 I road input constantly x _{I, k+k1-1}Output, the output of data selector 12 connects I road piece output circuit 13, Q road piece output circuit 14 and coefficient updating module 16 respectively, the input of Q road k+k1 tap constantly in like manner data x _{Q, k+k1}Connect the A input of latch 18 and data selector 20, the output k+k1-1 of latch 18 is Q circuit-switched data x constantly _{Q, k+k1-1}Connect the B input and the latch 19 of data selector 20, the output k+k1-2 of latch 19 is Q circuit-switched data x constantly _{Q, k+k1-2}Connect above-mentioned second forward taps piece computing circuit, the output of data selector 20 also connects I road piece output circuit 13, Q road piece output circuit 14 and coefficient updating module 16 respectively, above-mentioned I road displacement controlled quentity controlled variable S _IWith Q road displacement controlled quentity controlled variable S _QConnect coefficient updating module 16, the output of coefficient updating module 16 connects serial-parallel conversion circuit 21 and latch 15, and the output of latch 15 connects coefficient updating module 16, the first output I road feed-forward coefficients C of serial-parallel conversion circuit 21 _{I, 1}With the second output Q road feed-forward coefficients C _{Q, 1}Connect I road piece output circuit 13 and Q road piece output circuit 14 simultaneously respectively, I road piece output circuit 13 is output as y _{I, 1}, Q road piece output circuit 14 is output as y _{Q, 1}

As shown in Figure 3, above-mentioned rear feed tap piece computing circuit 8, its circuit structure and forward taps piece computing circuit 1 are identical, and judgement back k is I circuit-switched data d constantly _{I, k}Connect the input of latch 11, connect the B input of data selector 12 simultaneously, the output k-1 of latch 11 is I circuit-switched data d constantly _{I, k-1}Connect the input of latch 17, the k-2 of latch 17 outputs is I circuit-switched data d constantly _{I, k-2}Connect above-mentioned second rear feed tap piece computing circuit, simultaneously above-mentioned k-1 is I circuit-switched data d constantly _{I, k-1}Connect the A input of data selector 12, the C control end of data selector is carved selection k I circuit-switched data d constantly by inner sequencing control at the preceding half of a symbol period _{I, k}, the later half moment is selected k-1 I circuit-switched data d constantly _{I, k-1}Output, the output of data selector 12 connects I road piece output circuit 13, Q road piece output circuit 14 and coefficient updating module 16 respectively, in like manner judgement back k moment Q circuit-switched data d _{Q, k}Connect the A input of latch 18 and data selector 20, the output k-1 of latch 18 is Q circuit-switched data d constantly _{Q, k-1}Connect the B input and the latch 19 of data selector 20, the k-2 of latch 19 outputs is Q circuit-switched data d constantly _{Q, k-2}Connect above-mentioned second rear feed tap piece computing circuit, the output of data selector 20 also connects I road piece output circuit 13, Q road piece output circuit 14 and coefficient updating module 16 respectively, above-mentioned I road displacement controlled quentity controlled variable S _IWith Q road displacement controlled quentity controlled variable S _QConnect coefficient updating module 16, the output of coefficient updating module 16 connects serial-parallel conversion circuit 21 and latch 15, and the output of latch 15 connects coefficient updating module 16.The first output rear feed I road coefficient C of serial-parallel conversion circuit 21 _{I, 1} ^BWith the second output rear feed Q road coefficient C _{Q, 1} ^BConnect I road piece output circuit 13 and Q road piece output circuit 14 simultaneously respectively, I road piece output circuit 13 is output as Z _{I, 1}, Q road piece output circuit 14 is output as Z _{Q, 1}

As shown in Figure 9, above-mentioned sample circuit 6 comprises comparator 601, comparator 602 and with door 603, parallel processing is done on I road and Q road, and processing mode is identical, the k of above-mentioned error calculation circuit (5) output I road error signal e constantly _IWith Q road error signal e _QBe input to an input of comparator 601 and comparator 602 respectively, another input of comparator 601 is fixed threshold α 2, another input of comparator 602 is fixed threshold α 1, the output of above-mentioned two comparators connects the first input end and second input with door 603 respectively, quantized value connects the 3rd input with door 603, is output as I road quantization error signal Qe with door 603 _IWith Q road quantization error signal Qe _Q

In Fig. 2, coefficient updating module 16 is carried out coefficient update by following formula:

$C_I(k+1)=C_I\left(k\right)+X_I{2}^{-S_I}+X_Q{2}^{-S_Q}$

$C_Q(k+1)=C_Q\left(k\right)+X_I{2}^{-S_Q}-X_Q{2}^{-S_I}---\left(8\right)$

S wherein _IAnd S _QBe the output of displacement control add circuit, coefficient updating module 16 is finished x at preceding half symbol period _{I, k+k1}And x _{Q, k+k1}Coefficient update, finish x at later half symbol period _{I, k+k1-1}And x _{Q, k+k-1}Coefficient update.Multiplying each other of I road coefficient and data finished in I road piece output 13, its course of work subtracts computing for finishing taking advantage of of k+k1 tap of I road and coefficient at preceding half symbol period, finish taking advantage of of k+k1-1 tap of I road and coefficient at the latter half of symbol period and subtract computing, and the results added of twice tap computing is obtained y _{I, 1}Multiplying each other of Q road coefficient and data finished in Q road piece output 14, its course of work is for finishing the k+k1 tap of Q road and taking advantage of of coefficient subtracts at preceding half symbol period, finish taking advantage of of k+k1-1 tap of Q road and coefficient at the latter half of symbol period and subtract computing, and will and the results added of twice tap computing be obtained y _{Q, 1}

In Fig. 3, the structure of rear feed tap piece arithmetic element 8, the structure of its annexation and the course of work and feed-forward block arithmetic element is identical, and what difference was rear feed tap piece arithmetic element is input as judgement back k data d constantly _{I, k}And d _{Q, k}, be output as to the data of next rear feed tap piece arithmetic element be k-2 d constantly _{I, k-2}And d _{Q, k-2}, Z is exported on the rear feed Q road that exports balanced Q road output adder 2 to _{Q, 1}, Z is exported on the rear feed I road that exports balanced I road output adder 3 to _{I, 1}

As shown in Figure 4, the I road output 13 that is used for forward taps piece computing circuit 1 comprises multiplier 131, complementing circuit 132 (as Fig. 6), and adder 133 is with door 134 and trigger 135.Input to 13 for data x _IAnd x _Q, coefficient C _IAnd C _Q, its course of work be between the first half of a symbol period in, be input as 0 with the control end of door, calculate in the forward taps piece computing circuit 1 k+k1 I and Q circuit-switched data x constantly this moment _{I, k+k1}And x _{Q, k+k1}Subtract computing with taking advantage of of coefficient, see formula (3) (6), symbol period the later half time in, be input as 1 with the control end of door, above-mentioned k+k1 is I and Q circuit-switched data x constantly _{I, k+k1}And x _{Q, k+k1}Subtract the result with taking advantage of of coefficient and feed back to adder 133, and carry out k+k1-1 moment I and Q circuit-switched data x in the forward taps piece computing circuit 1 by trigger 135 _{I, k+k1-1}And x _{Q, k+k1-1}Subtract computing with taking advantage of of coefficient, adder 133 is finished the addition of adjacent two taps output, and the output of adder 133 is feedforward I road output y _{I, 1}

As shown in Figure 5, the Q road piece output circuit 14 that is used for forward taps piece computing circuit 1 comprises multiplier 141, and adder 142 is with door 143 and trigger 144.Input to 14 for data x _IAnd x _Q, coefficient C _IAnd C _Q, its course of work be between the first half of a symbol period in, be input as 0 with the control end of door, calculate in the forward taps piece computing circuit 1 k+k1 I and Q circuit-switched data x constantly this moment _{I, k+k1}And x _{Q, k+k1}With the multiply-add operation of coefficient, see formula (3) (6), symbol period the later half time in, be input as 1 with the control end of door, above-mentioned k+k1 I and Q circuit-switched data x constantly _{I, k+k1}And x _{Q, k+k1}Add the result with taking advantage of of coefficient and feed back to adder 142, and carry out k+k1-1 moment I and Q circuit-switched data data x in the forward taps piece computing circuit 1 by trigger 144 _{I, k+k1-1}And x _{Q, k+k1-1}With the multiply-add operation of coefficient, adder 142 is finished the addition of adjacent two taps output, and the output of adder 142 is the Q road output y of feedforward _{Q, 1}

As shown in Figure 7, above-mentioned error calculation circuit 5 is input as balanced Q road output adder 2 output y _{Q, k}, balanced I road output adder 3 output y _{I, k}, the output d of decision circuit 4 _{I, k}And d _{Q, k}, be output as error signal e _{I, k}And e _{Q, k}, its operation principle is the error that calculates respectively under LMS method and the CMA method situation, according to formula (1) (4), the error e that is calculated _LmsAnd e _CmaCan be divided into I and Q road, and be connected to the A and the B end of data selector respectively, Choice of data selectors end C is by the output control of finite state machine 501, so the output of error calculation circuit is k error signal constantly.

As shown in Figure 8, above-mentioned finite state machine 501 is input as e in the error calculation circuit _Lms, the operation principle of finite state machine 501 is the interior error e of certain hour that add up out _LmsAbsolute value, and this accumulated value and fixed numeric values α (being provided by register) relatively be used as the foundation that algorithm switches.Counter plays time action in the finite state machine 501, and counter output is being output as lowly after the set time, and other times be height.When counter is output as when high e _LmsThe Error Absolute Value accumulative total of not stopping, when behind certain hour, be output as lowly, the above-mentioned error amount that adds up exports comparator to, when this error accumulation value during less than given numerical value α, CONT is output as 0, on the contrary CONT is output as 1.

As shown in Figure 9, description is with I road error signal e _{I, k}Be quantized to I road output quantized value Qe _IProcess, the processing procedure of Q road error signal is fully identical with the I road, promptly I and Q road is treated to parallel structure.The circuit of above-mentioned sample circuit 6 is input as the output I of above-mentioned error calculation circuit 5 and the error signal e on Q road _{I, k}And e _{Q, k}, be output as the quantization error output valve Qe on I and Q road _IAnd Qe _Q, the operation principle of sample circuit 6 is I and the Q road error e with input _{I, k}And e _{Q, k}Quantize to 2 according to size ^b, b is 3bit.Can see that according to above-mentioned operation principle sample circuit 6 can be made of comparator, Fig. 9 has described the error e when input _{I, k}And e _{Q, k}The sample circuit of span when [α 1, and α 2], at this moment, the output of two comparators all is 1, therefore the output with door is determined by predefined quantized value.In like manner, for different input e _{I, k}And e _{Q, k}, the quantized value that preestablishes under the different input span situations can obtain different I and Q quantization error output valve Qe _IAnd Qe _QThrough above processing, k I and Q road error quantization value Qe have constantly just been drawn _IAnd Qe _Q, this k is I and Q road error quantization value Qe constantly _IAnd Qe _QEnter displacement controlled quentity controlled variable add circuit 7, displacement controlled quentity controlled variable add circuit 7 according to equalizing circuit in k operating state (CMA or LMS are determined by finite state machine 501) constantly with k I and Q road quantization error value Qe constantly _IAnd Qe _QWith step size mu _LMSPerhaps μ _CMAAddition, the switching of step-length are determined that by finite state machine 501 CONT is output as at 1 o'clock and selects μ _LMSOtherwise, select μ _CMA, its size is write by register.Displacement controlled quentity controlled variable add circuit 7 is output as k I and Q road shift amount S constantly _{I, k}And S _{Q, k}, k is I and Q shift amount S constantly _{I, k}And S _{Q, k}Be used for calculating next coefficient of (k+1) constantly, see formula 8.

As shown in figure 10, during the physical circuit of coefficient updating module 16 is realized in the above-mentioned forward taps piece computing circuit 1, be input as above-mentioned displacement controlled quentity controlled variable add circuit 7 and be output as k I and Q shift amount S constantly _{I, k}And S _{Q, k}, the tap coefficients value C of previous moment _n, the tap coefficients value C of previous moment _nBe output C by coefficient updating module 16 _N+115 delays obtain through latch, and the input of coefficient updating module 16 also comprises the output of data selector 12 and 20. and inner control logic changes by 0101 in a symbol period.In the k effect of coefficient updating module 16 constantly is to calculate k1 tap and the k1-1 tap tap coefficient C in next moment in a symbol period _N+1(I and Q road serial output) also exports string commentaries on classics and circuit 21 to.Thereby finish once the balanced output of new calculating constantly at k+1.Initial input is k+k1 I and Q circuit-switched data x constantly among Figure 10 _{I, k+k1}And x _{Q, k+k1}, in preceding half symbol period, inner control logic is 0, what finished this moment is Q road coefficient update, obtains k+k1+1 C constantly _{Q, k+1+k1}, when inner control logic is 1, what finished this moment is I road coefficient update, obtains k+k1+1 C constantly _{I, k+1+k1}What finish in the later half symbol period is the coefficient update of k+k1-1 tap, and processing procedure is identical with the processing of above-mentioned k tap.The above processing of process has just obtained the coefficient value of k+1 adjacent two taps constantly, and therefore through I road piece output 13, Q road piece is exported 14 and calculated k+1 y constantly _{I, 1}And y _{Q, 1}, k+1 y constantly _{I, 1}And y _{Q, 1}Export balanced I road output adder 3 to, balanced Q road output adder 2 just can obtain y _{I, k+1}And y _{Q, k+1}Thereby, finished once complete coefficient update.

Figure 11 is the I line structure of the equalizing circuit of Parallel Implementation in the conventional art, and it need consume a large amount of hardware costs, and the balanced output of each coefficient update and calculating all needs a multiplier, and the Q line structure also is like this.Therefore whole equalizing circuit need consume a large amount of chip areas, compares with the inventive method of this patent, and the inventive method of this patent can reduce by nearly 3/4ths scale.

Figure 12 is the structure of the latch among the present invention.

As shown in figure 13, description is with above-mentioned I road output signal y _{I, k}Betraing determines is I road decision value d _{I, k}Process, the processing procedure of Q road output signal is fully identical with the I road, promptly I and Q road is treated to parallel structure.The function of decision circuit is that the output valve in certain zone around the constellation point all is output as this constellation point., the qam constellation figure of rectangle produces the 3rd edition P192～194 in " digital communication " Electronic Industry Press February in 2004 that its judgement principle can be write with reference to the Prose base because being equivalent to apply two PAM signals on two quadrature carriers.When k balanced output valve constantly during at numerical value fixed threshold 1 and fixed threshold 2, comparator is output as 1, thereby gating is opened the output d of decision circuit then with door _{I, k}Be the constellation point value in this zone.

In addition, the data selector that the present invention relates to, data comparator, d type flip flop, string changes and circuit structure all adopts known structure, for example can adopt Huang Zhengjin to write " Computer Structure and Logic Design " Higher Education Publishing House June calendar year 2001 the 1st edition P71～P73, P166～P168, P106～P108, known structure among P127～P129, the operation principle of the data selector that the present invention relates to, data comparator, d type flip flop are all identical therewith.There is not the CP end of mark all to meet clock CLK in the d type flip flop of the present invention.The structure of the displacement controlled quentity controlled variable add circuit in this invention is common add circuit.

Actual portfolio effect figure can embody by Figure 14～17: Figure 14 are that what to describe is the undisturbed desirable planisphere that receives, the transmission mode employing be 64QAM.What Figure 15 described is through the reception planisphere (not equalized) after the intersymbol interference, and constellation point is quite chaotic, and the error rate is very high.What Figure 16 described is through the output planisphere behind the equalizing circuit behind the present invention, suitable clear of constellation point, Figure 17 has described the error rate in whole equalization process, can see very little of the error rate behind 7500 symbols, that is to say that equilibrium can effectively elimination intersymbol interference.

Claims (4)

1, the Adpative equalizing circuit in a kind of cable digital TV, comprise forward taps piece computing circuit (1), balanced Q road output adder (2), balanced I road output adder (3), decision circuit (4), error calculation circuit (5), sample circuit (6), displacement controlled quentity controlled variable add circuit (7) and rear feed tap piece computing circuit (8), data x is imported in the k+k1 I road tap constantly that has intersymbol interference _{I, k+k1}With k+k1 Q road tap constantly input data x _{Q, k+k1}Connect first forward taps piece computing circuit (1), the I road piece output y of first forward taps piece computing circuit (1) _{I, 1}Connect balanced I road output adder (3), Q road piece output y _{Q, 1}Connect balanced Q road output adder (2), the k+k1-2 of first forward taps piece computing circuit (1) output is I circuit-switched data x constantly _{I, k+k1-2}With k+k1-2 moment Q circuit-switched data x _{Q, k+k1-2}Connect second forward taps piece computing circuit in turn, the rest may be inferred up to I road x _{I, k+1}With Q road x _{Q, k+1}Connect last forward taps piece computing circuit, the I road output of above-mentioned all forward taps piece computing circuit all connects balanced I road output adder (3), the output of Q road all connects balanced Q road output adder (2), and balanced Q road output adder this moment (2) is output as k balanced Q road output valve y constantly _{Q, k}, balanced I road output adder (3) is output as k balanced I road output valve y constantly _{I, k}, above-mentioned balanced Q road output valve y _{Q, k}With balanced I road output valve y _{I, k}Export decision circuit (4) and error calculation circuit (5) respectively to, the k of decision circuit (4) output I road judgement constantly output d _{I, k}With Q road judgement output d _{Q, k}, inputing to error calculation circuit (5) and rear feed tap piece computing circuit (8) respectively, error calculation circuit (5) is output as k I road error signal e constantly _IWith Q road error signal e _Q, it inputs to sample circuit (6) respectively, and sample circuit (6) is output as I road quantization error signal Qe _IWith Q road quantization error signal Qe _Q, it inputs to displacement controlled quentity controlled variable add circuit (7) respectively, and two other of displacement controlled quentity controlled variable add circuit (7) is input as step size mu _LMSAnd μ _CMA, displacement controlled quentity controlled variable add circuit (7) is output as I road displacement controlled quentity controlled variable S _IWith Q road displacement controlled quentity controlled variable S _Q, it inputs to respectively in each forward taps piece computing circuit (1) and each rear feed tap piece computing circuit (8), the I road piece output Z of first rear feed tap piece computing circuit (8) _{I, 1}Connect balanced I road output adder (3), the piece output Z on Q road _{Q, 1}Connect balanced Q road output adder (2), the k-2 of first rear feed tap piece computing circuit (8) output is I circuit-switched data d constantly _{I, k-2}With k-2 moment Q circuit-switched data d _{Q, k-2}Connect second rear feed tap piece computing circuit in turn, the rest may be inferred up to I road k-k2+1 moment data d _{I, k-k2+1}With Q road k-k2+1 moment data d _{Q, k-k2+1}Connect last rear feed tap piece computing circuit, the I road output of above-mentioned all rear feed tap piece computing circuit all connects balanced I road output adder (3), and the output of Q road also all connects balanced Q road output adder (2).

2, the Adpative equalizing circuit in the cable digital TV according to claim 1, above-mentioned forward taps piece computing circuit (1), the connected mode of the connected mode of its I circuit-switched data and Q circuit-switched data is identical, k+k1 I road tap constantly input data x _{I, k+k1}Connect the input of latch (11), connect the B input of data selector (12) simultaneously, the output k+k1-1 of latch (11) is I circuit-switched data x constantly _{I, k+k1-1}Connect the input of latch (17), the output k+k1-2 of latch (17) is I circuit-switched data x constantly _{I, k+k1-2}Connect above-mentioned second forward taps piece computing circuit, simultaneously above-mentioned k+k1-1 is I circuit-switched data x constantly _{I, k+k1-1}Connect the A input of data selector (12), the C control end of data selector is carved selection k+k1 I road input constantly data x by inner sequencing control at the preceding half of a symbol period _{I, k+k1}, the later half moment is selected k+k1-1 I road input constantly x _{I, k+k1-1}Output, the output of data selector (12) connects I road piece output circuit (13), Q road piece output circuit (14) and coefficient updating module (16) respectively, the input of Q road k+k1 tap constantly in like manner data x _{Q, k+k1}Connect the A input of latch (18) and data selector (20), the output k+k1-1 of latch (18) is Q circuit-switched data x constantly _{Q, k+k1-1}Connect the B input and the latch (19) of data selector (20), the output k+k1-2 of latch (19) is Q circuit-switched data x constantly _{Q, k+k1-2}Connect above-mentioned second forward taps piece computing circuit, the output of data selector (20) also connects I road piece output circuit (13), Q road piece output circuit (14) and coefficient updating module (16) respectively, above-mentioned I road displacement controlled quentity controlled variable S _IWith Q road displacement controlled quentity controlled variable S _QConnect coefficient updating module (16), the output of coefficient updating module (16) connects serial-parallel conversion circuit (21) and latch (15), and the output of latch (15) connects coefficient updating module (16), the first output I road feed-forward coefficients C of serial-parallel conversion circuit (21) _{I, 1}With the second output Q road feed-forward coefficients C _{Q, 1}Connect I road piece output circuit (13) and Q road piece output circuit (14) simultaneously respectively, I road piece output circuit (13) is output as y _{I, 1}, Q road piece output circuit (14) is output as y _{Q, 1}

3, the Adpative equalizing circuit in the cable digital TV according to claim 1, above-mentioned rear feed tap piece computing circuit (8), its circuit structure and forward taps piece computing circuit (1) are identical, and judgement back k is I circuit-switched data d constantly _{I, k}Connect the input of latch (11), connect the B input of data selector (12) simultaneously, the k-1 of latch (11) output is I circuit-switched data d constantly _{I, k-1}Connect the input of latch (17), the k-2 of latch (17) output is I circuit-switched data d constantly _{I, k-2}Connect above-mentioned second rear feed tap piece computing circuit, simultaneously above-mentioned k-1 is I circuit-switched data d constantly _{I, k-1}Connect the A input of data selector (12), the C control end of data selector is carved selection k I circuit-switched data d constantly by inner sequencing control at the preceding half of a symbol period _{I, k}, the later half moment is selected k-1 I circuit-switched data d constantly _{I, k-1}Output, the output of data selector (12) connects I road piece output circuit (13), Q road piece output circuit (14) and coefficient updating module (16) respectively, in like manner judgement back k moment Q circuit-switched data d _{Q, k}Connect the A input of latch (18) and data selector (20), the output k-1 of latch (18) is Q circuit-switched data d constantly _{Q, k-1}Connect the B input and the latch (19) of data selector (20), the output k-2 of latch (19) is Q circuit-switched data d constantly _{Q, k-2}Connect above-mentioned second rear feed tap piece computing circuit, the output of data selector (20) also connects I road piece output circuit (13), Q road piece output circuit (14) and coefficient updating module (16) respectively, above-mentioned I road displacement controlled quentity controlled variable S _IWith Q road displacement controlled quentity controlled variable S _QConnect coefficient updating module (16), the output of coefficient updating module (16) connects serial-parallel conversion circuit (21) and latch (15), and the output of latch (15) connects coefficient updating module (16).The first output rear feed I road coefficient C of serial-parallel conversion circuit (21) _{I, 1} ^BWith the second output rear feed Q road coefficient C _{Q, 1} ^BConnect I road piece output circuit (13) and Q road piece output circuit (14) simultaneously respectively, I road piece output circuit (13) is output as Z _{I, 1}, Q road piece output circuit (14) is output as Z _{Q, 1}

4, the Adpative equalizing circuit in the cable digital TV according to claim 1, above-mentioned sample circuit (6) comprises first comparator (601), second comparator (602) and with door (603), parallel processing is done on I road and Q road, and processing mode is identical, the k I road error signal e constantly of above-mentioned error calculation circuit (5) output _IWith Q road error signal e _QBe input to an input of first comparator (601) and second comparator (602) respectively, another input of first comparator (601) is fixed threshold α 2, another input of first comparator (601) is fixed threshold α 1, the output of above-mentioned first, second comparator connects the first input end and second input with door (603) respectively, according to the error originated from input span and predefined quantized value connect with the door (603) the 3rd input, be output as I road quantization error signal Qe with door (603) _IWith Q road quantization error signal Qe _Q

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