CN107534629A - Decision feedback equalization device, method and optical transmission system - Google Patents
Decision feedback equalization device, method and optical transmission system Download PDFInfo
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Abstract
The invention discloses a kind of decision feedback equalization device, method and optical transmission system, the decision feedback equalization device includes the first balanced device, first adder, the first decision unit, the second balanced device, the 3rd balanced device, second adder and the second decision unit, the embodiment of the present invention effectively increases the equalization performance of decision feedback equalization device by being multiplexed cascade system, solve because dispersion causes receiver can not receive correct signal problem, it reduce further the bit error rate, the stability of system is improved, can meet the needs of 40G or even 100G systems.
Description
The present invention relates to the field of optical communication technologies, and in particular, to a decision feedback equalization apparatus and method, and an optical transmission system.
As the Optical transmission system is continuously developed towards Ultra high speed, Ultra long distance, and Ultra large capacity (3U), the performance of the transmission system is more and more affected by the Chromatic Dispersion (CD), Polarization Mode Dispersion (PMD), and Optical Signal to Noise Ratio (OSNR) of the link. Inter Symbol Interference (ISI) caused by chromatic dispersion results in a high Bit Error Rate (BER), which makes a receiver unable to receive correct signals, and an equalizer is required at the receiver for equalization. In the aspect of dispersion tolerance, as the link rate is continuously increased, the tolerance thereof is sharply reduced, for example, under the same modulation format, the dispersion tolerance of an optical transmission system with a 10G rate is about 1000ps/nm, the dispersion tolerance of an optical transmission system with a 40G rate is less than 65ps/nm, and the dispersion tolerance of an optical transmission system with a 100G rate is less than 10ps/nm, that is, the dispersion tolerance of a 100G system is only 1/100 of a 10G system, so that the error rate in the optical signal transmission process is extremely high, and the optical signal cannot be correctly received by a receiver.
Disclosure of Invention
The embodiment of the invention provides a decision feedback equalization device, a decision feedback equalization method and an optical transmission system, which further improve the equalization performance of the decision feedback equalization device, effectively reduce intersymbol interference and ensure that a receiving receiver can correctly receive optical signals.
In a first aspect, a decision feedback equalization apparatus is provided, including:
the first equalizer, the first adder, the first decision unit, the second equalizer, the third equalizer, the second adder and the second decision unit;
the first equalizer is used for receiving signals and equalizing the received signals;
the first adder is configured to add an output signal of the first equalizer and an output signal of the second equalizer;
the first decision unit is configured to decide an output signal of the first adder;
the second equalizer is used for equalizing the output signal of the first decision unit;
the third equalizer is used for performing equalization processing on the output signal of the first adder;
the second adder is configured to add an output signal of the third equalizer and an output signal of the second equalizer;
and the second decision unit is configured to decide an output signal of the second adder and output the decided signal.
With reference to the first aspect, in a first possible implementation manner of the first aspect, the decision feedback equalization apparatus further includes:
the fourth adder, the first coefficient updating module, the second coefficient updating module, the fifth adder and the third coefficient updating module;
the fourth adder is configured to add the output signal of the first decision unit and the output signal of the first equalizer to obtain a first error signal;
the first coefficient updating module is configured to update a first tap coefficient of the first equalizer according to the first error signal, and output the first tap coefficient to the first equalizer;
the second coefficient updating module is configured to update a second tap coefficient of the second equalizer according to the first error signal, and output the second tap coefficient to the second equalizer;
the fifth equalizer is configured to generate a second equalizer output signal according to the second error signal;
the third coefficient updating module is configured to update a third tap coefficient of the third equalizer according to the second error signal, and output the third tap coefficient to the third equalizer.
With reference to the first aspect, in a second possible implementation manner of the first aspect, the first coefficient updating module, the second coefficient updating module, and the third coefficient updating module all update the tap coefficient by using a least mean square algorithm.
With reference to the second possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect, a step size of the first coefficient updating module updating the first tap coefficient of the first equalizer is not equal to a step size of the second coefficient updating module updating the second tap coefficient of the second equalizer.
With reference to the first aspect, the first possible implementation manner of the first aspect, the second possible implementation manner of the first aspect, or the third possible implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, the first equalizer, the second equalizer, and the third equalizer are all transversal digital filters.
In a second aspect, a receiver is provided, which includes the above decision feedback equalization apparatus.
In a third aspect, an optical transmission system is provided, comprising a transmitter for transmitting an optical signal and the above receiver.
In a fourth aspect, there is provided a signal processing method comprising the steps of:
receiving a first signal, and carrying out equalization processing on the received first signal to obtain a second signal;
adding the second signal and the third signal to obtain a fourth signal;
judging the fourth signal to obtain a fifth signal;
carrying out equalization processing on the fifth signal, and taking an equalization result as a new third signal;
performing equalization processing on the fourth signal to obtain a sixth signal;
adding the sixth signal and the new third signal to obtain a seventh signal;
and judging the seventh signal and outputting an eighth judged signal.
With reference to the fourth aspect, in a first possible implementation manner, the method further includes:
adding the fifth signal and the second signal to obtain a first error signal;
updating a first tap coefficient according to the first error signal, and outputting the first tap coefficient;
updating a second tap coefficient according to the first error signal, and outputting the second tap coefficient;
adding the eighth signal and the sixth signal to obtain a second error signal;
and updating the third tap coefficient according to the second error signal, and outputting the third tap coefficient.
With reference to the fourth aspect or the first possible implementation manner of the fourth aspect, in a second possible implementation manner of the fourth aspect,
the first tap coefficient, the second tap coefficient and the third tap coefficient are all updated by a least mean square algorithm.
With reference to the fourth aspect or the second possible implementation manner of the fourth aspect, in a third possible implementation manner of the fourth aspect,
the step size for updating the first tap coefficient is not equal to the step size for updating the second tap coefficient.
In a fifth aspect, there is provided a data communication device comprising a processor, a memory and a bus system, the processor and the memory being connected via the bus system, the memory being adapted to store instructions, the processor being adapted to execute the instructions stored by the memory,
the processor is used for receiving a first signal and carrying out equalization processing on the received first signal to obtain a second signal; adding the second signal and the third signal to obtain a fourth signal; judging the fourth signal to obtain a fifth signal; carrying out equalization processing on the fifth signal, and taking an equalization result as a new third signal; performing equalization processing on the fourth signal to obtain a sixth signal; adding the sixth signal and the new third signal to obtain a seventh signal; and judging the seventh signal and outputting an eighth judged signal.
With reference to the fifth aspect, in a first possible implementation manner of the fifth aspect, the processor is further configured to:
adding the fifth signal and the second signal to obtain a first error signal;
updating a first tap coefficient according to the first error signal, and outputting the first tap coefficient;
updating a second tap coefficient according to the first error signal, and outputting the second tap coefficient;
adding the eighth signal and the sixth signal to obtain a second error signal;
and updating the third tap coefficient according to the second error signal, and outputting the third tap coefficient.
With reference to the fifth aspect or the first possible implementation manner of the fifth aspect, in a second possible implementation manner of the fifth aspect, the first tap coefficient, the second tap coefficient, and the third tap coefficient are updated by a least mean square algorithm.
With reference to the fifth aspect or the second possible implementation manner of the fifth aspect, in a third possible implementation manner of the fifth aspect, a step size for updating the first tap coefficient is not equal to a step size for updating the second tap coefficient.
Based on the technical scheme, the signal is received through the first equalizer, and the received signal is equalized; a first adder adding an output signal of the first equalizer and an output signal of the second equalizer; a first decision unit decides an output signal of the first adder; the second equalizer is used for equalizing the output signal of the first decision unit; the third equalizer performs equalization processing on the output signal of the first adder; a second adder adding an output signal of the third equalizer and an output signal of the second equalizer; and the second decision unit is used for deciding the output signal of the second adder and outputting the decided signal. The embodiment of the invention effectively improves the balance performance of the decision feedback balance device in a multiplexing cascade mode, solves the problem that a receiver cannot receive correct signals due to chromatic dispersion, further reduces the error rate and improves the stability of a system.
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic block diagram of an application scenario provided in an embodiment of the present invention;
fig. 2 is a structural diagram of a decision feedback equalization apparatus according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating an internal principle of a first equalizer according to an embodiment of the present invention;
fig. 4 is a diagram illustrating an equalizing effect of the equalizing device according to the embodiment of the present invention;
fig. 5 is a flowchart of a signal processing method according to an embodiment of the present invention;
FIG. 6 is a flow chart of another signal processing method provided in accordance with an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a data communication device according to an embodiment of the present invention.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, shall fall within the scope of protection of the present invention.
Fig. 1 shows a schematic block diagram of an application scenario according to an embodiment of the present invention. As shown in fig. 1, the short-distance optical interconnection system includes a transmitter 100, a Multi-Mode Fiber (MMF), and a receiver 200, where the transmitter 100 includes an electrical modulator, a driver, and a transmitting laser, the electrical modulator loads data information onto an electrical signal, the driver adjusts the modulated electrical signal to a voltage range required by the transmitting laser, and the transmitting laser converts the electrical signal into an optical signal to be transmitted. The emitted light is sent to the receiver 200 through an optical fiber link, the receiver 200 includes a photoelectric converter, an amplifier and a decision feedback equalization device, the photoelectric converter converts the optical signal into an electrical signal, and the amplifier amplifies the electrical signal and then performs an equalization decision process to output for further processing. The improvement of the present invention resides in the decision feedback equalization means of the receiver 200.
As shown in fig. 2, fig. 2 is a structural diagram of a decision feedback equalization apparatus according to an embodiment of the present invention. The decision feedback equalization apparatus 200 includes: a first equalizer 201, a first adder 202, a first decision unit 203, a second equalizer 204, a third equalizer 205, a second adder 206 and a second decision unit 207.
The first equalizer 210 is configured to receive a signal and perform equalization processing on the received signal. The first adder 220 is used for adding the output signal of the first equalizer 210 and the output signal of the second equalizer 204. The first decision unit 230 is used for deciding the output signal of the first adder 220. The second equalizer 204 is used for equalizing the output signal of the first decision unit 230. And a third equalizer 205 for equalizing the output signal of the first adder 206. The second adder 206 is used to add the output signal of the third equalizer 205 and the output signal of the second equalizer 204. The second decision unit 207 is configured to decide an output signal of the second adder 206 and output the decided signal.
Specifically, the first equalizer is configured to perform equalization processing on a symbol to be processed at a current sampling time to obtain a first estimated value of the symbol to be processed, where the first estimated value of the symbol to be processed is a sum of products of values of all symbols located in the first equalizer at the current sampling time and tap coefficients corresponding to the values. And the first adder superposes the first estimation value output by the first equalizer and the second estimation value output by the second equalizer to obtain a third estimation value. And the first judging unit judges the third estimation value to obtain a judgment value of the third estimation value. And the second equalizer receives the decision value of the third estimation value, performs equalization processing on the decision value of the third estimation value to be processed at the current sampling moment to obtain the second estimation value, and the second estimation value is used as a new third estimation value. The second estimate is equal to the sum of the products of all decision values located within the second equalizer at the current sampling instant and their corresponding tap coefficients. And the third equalizer receives the third estimated value, and performs equalization processing on the third estimated value to be processed at the current sampling time to obtain a fourth estimated value, wherein the fourth estimated value is equal to the sum of products of all third estimated values and corresponding tap coefficients, and the third estimated values are positioned in the third equalizer at the current sampling time. And the second adder is used for superposing the fourth estimated value and a second estimated value output by the second equalizer at the current sampling moment to obtain a fifth estimated value. And the second judging unit is used for judging the fifth estimation value to obtain a judgment value of the fifth estimation value.
In this embodiment, the first equalizer 201, the second equalizer 204, and the third equalizer 205 are all transversal digital filters. The specific principles of the transversal digital filter will be described in detail below.
For example, the first equalizer 201 is a transversal filter having 2N +1 taps, and the transversal filter is composed of 2N delay units T arranged in the transversal directionbAnd 2N +1 taps, the tap coefficient sequence being denoted c-N、…c0、…cNAs shown in fig. 3. Assuming the kth sampling instant, the output signal is equal to:
wherein x isk-nSymbols located in the first equalizer 201 for the k-th sampling instant, cnTap coefficients for 2N +1 taps for the first equalizer. It can be seen that the first estimate output by the first equalizer at the k-th sampling instant will consist of 2N +1 ciAnd xk-iThe sum of the products.
When N is 1 i.e. the first equalizer 201 is a transversal filter with three taps,
when k is equal to 1, the first step is carried out,
when k is equal to 2, the number of the bits is increased,
.
.
.
when k is equal to n, the number of n,
as can be seen from the above, all symbols located in the first equalizer 201 at the nth (n is a natural number) time are xn+1、xn、xn-1Including the symbol x to be processed at the current sampling momentn。
The decision feedback equalization device in the embodiment of the invention further comprises:
a fourth adder 208, configured to add the output signal of the first decision unit and the output signal of the first equalizer to obtain a first error signal.
A first coefficient updating module 209 for updating a second tap coefficient of the second equalizer according to the first error signal and outputting the second tap coefficient to the second equalizer.
A second coefficient updating module 210 for updating a second tap coefficient of the second equalizer according to the first error signal and outputting the second tap coefficient to the second equalizer.
A fifth adder 211, configured to add the output signal of the second decision unit and the output signal of the third equalizer to obtain a second error signal.
A third coefficient updating module 212, configured to update a third tap coefficient of the third equalizer according to the second error signal, and output the third tap coefficient to the third equalizer.
The first coefficient updating module 209, the second coefficient updating module 210, and the third coefficient updating module 212 may adopt, for example, a Least Mean Square (LMS) coefficient updating algorithm. The adjustment formula is as follows:
w(n+1)＝w(n)+μe(n)x(n)，
where w (n +1) is the updated tap coefficient, w (n) is the tap coefficient before updating, μ is the step size of the tap coefficient update, error decision error e (n) is equal to d (n) -y (n), d (n) is the decision value, y (n) is the equalizer output value, x (n) is the equalizer input value, y (n) is wT(n)x(n)，wT(n) is the transpose of the equalizer tap coefficient matrix.
The step sizes of the first equalizer 201, the second equalizer 204, and the third equalizer 205 may be arbitrarily set. Preferably, the step size of the first coefficient updating module updating the first tap coefficient of the first equalizer is not equal to the step size of the second coefficient updating module updating the second tap coefficient of the second equalizer.
In this embodiment, the first equalizer 201 and the third equalizer 205 multiplex the second equalizer 204 to form a two-stage DFE equalization system, which effectively improves the equalization performance compared with the conventional FFE equalizer. Even if the first-stage equalization is in error, the current correct data stored in the second-stage equalizer can be used for correcting the first-stage equalization output in time, so that the error code is prevented, and the receiver can normally receive correct signals.
As shown in fig. 4, fig. 4 is a diagram illustrating an equalizing effect of the decision feedback equalizing apparatus according to the embodiment of the present invention. Fig. 3(a) is an eye diagram before equalization, and fig. 3(b) is an eye diagram after equalization. Through comparison, the decision feedback equalization device provided by the embodiment of the invention can obviously reduce the error rate, can realize error-free transmission, and further proves the effectiveness of the decision feedback equalization device provided by the embodiment of the invention.
The decision feedback equalization device disclosed by the embodiment of the invention is applied to a short-distance optical interconnection system, eliminates intersystem crosstalk between systems through equalization, and ensures that a receiver can correctly receive data. Of course, the present invention is not limited thereto, and any system using the decision feedback equalization apparatus disclosed in the embodiments of the present invention is included in the scope of the present invention.
Based on the above embodiments, an embodiment of the present invention provides a signal processing method, as shown in fig. 4, the process includes the steps of:
the following signal processing flow can be executed by the decision feedback equalization apparatus shown in fig. 2, and the flow of each unit or module in the decision equalization apparatus is as follows:
in step 501, the first equalizer 201 receives a first signal, and performs equalization processing on the received first signal to obtain a second signal.
Step 502, the first adder 202 adds the second signal and the third signal to obtain a fourth signal.
In step 503, the first decision unit 203 decides the fourth signal to obtain a fifth signal.
In step 504, the second equalizer 204 performs an equalization process on the fifth signal, and uses the equalization result as a new third signal.
In step 505, the third equalizer 205 performs an equalization process on the fourth signal to obtain a sixth signal.
In step 506, the second adder 206 adds the sixth signal and the new third signal to obtain a seventh signal.
In step S507, the second decision unit 207 decides the seventh signal and outputs an eighth decided signal.
For the equalizer with dynamically adjustable tap coefficients, as shown in fig. 6, the step 503 further includes the following steps:
in step S508, the fourth adder 208 adds the fifth signal and the second signal to obtain a first error signal.
In step S509, the first coefficient updating module 209 updates the first tap coefficient according to the first error signal and outputs the first tap coefficient to the first equalizer 201.
In step S510, the second coefficient updating module 210 updates the second tap coefficient according to the first error signal and outputs the second tap coefficient to the second equalizer 204.
The step S507 further includes the following steps:
in step S511, the fifth adder 211 adds the eighth signal and the sixth signal to obtain a second error signal.
In step S512, the third coefficient updating module 212 updates the third tap coefficient according to the second error signal and outputs the third tap coefficient to the third equalizer 205.
The signal processing flow may be executed by the decision feedback equalization apparatus shown in fig. 2, and for a specific execution process, reference is made to the detailed description of the embodiment of fig. 2, which is not repeated here.
In this embodiment, the first equalizer 201 and the third equalizer 205 multiplex the second equalizer 204 to form a two-stage DFE equalization system, which effectively improves the equalization performance compared with the conventional FFE equalizer. Even if the first-stage equalization is in error, the current correct data stored in the second-stage equalizer can be used for correcting the first-stage equalization output in time, so that the error code is prevented, and the receiver can normally receive correct signals.
As shown in fig. 6, an embodiment of the present invention further provides a data communication apparatus 700, where the apparatus 700 includes a processor 710, a memory 720, and a bus system 730, where the processor 710 and the memory 720 are connected through the bus system 730, the memory 720 is configured to store instructions, and the processor 710 is configured to execute the instructions stored in the memory 720, where the processor 710 is configured to receive a first signal, perform an equalization process on the received first signal, and obtain a second signal; adding the second signal and the third signal to obtain a fourth signal; judging the fourth signal to obtain a fifth signal; carrying out equalization processing on the fifth signal, and taking an equalization result as a new third signal; performing equalization processing on the fourth signal to obtain a sixth signal; adding the sixth signal and the new third signal to obtain a seventh signal; and judging the seventh signal and outputting an eighth judged signal.
Further, the processor 710 may be further configured to add the fifth signal and the second signal to obtain a first error signal; updating a first tap coefficient according to the first error signal, and outputting the first tap coefficient; updating a second tap coefficient according to the first error signal, and outputting the second tap coefficient; adding the eighth signal and the sixth signal to obtain a second error signal; and updating the third tap coefficient according to the second error signal, and outputting the third tap coefficient.
And updating the first tap coefficient, the second tap coefficient and the third tap coefficient by adopting a least mean square algorithm. Preferably, the step size for updating the first tap coefficient is not equal to the step size for updating the second tap coefficient.
The embodiment of the invention effectively improves the balance performance of the decision feedback balance device in a multiplexing cascade mode, solves the problem that a receiver cannot receive correct signals due to chromatic dispersion, further reduces the error rate and improves the stability of a system.
The specific execution flow of the specific processor 710 may refer to the description corresponding to the flowchart shown in fig. 5, and is not described herein again.
It should be understood that, in the embodiment of the present invention, the processor 710 may be a Central Processing Unit (CPU), and the processor 710 may also be other general processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 720 may include both read-only memory and random-access memory, and provides instructions and data to the processor 710. A portion of memory 720 may also include non-volatile random access memory. For example, memory 720 may also store device type information.
The bus system 730 may include a power bus, a control bus, a status signal bus, and the like, in addition to a data bus. For clarity of illustration, however, the various buses are designated in the figure as the bus system 730.
Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may also be an electric, mechanical or other form of connection.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present invention.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (15)
- A decision feedback equalization apparatus, comprising:the first equalizer, the first adder, the first decision unit, the second equalizer, the third equalizer, the second adder and the second decision unit;the first equalizer is used for receiving signals and equalizing the received signals;the first adder is configured to add an output signal of the first equalizer and an output signal of the second equalizer;the first decision unit is configured to decide an output signal of the first adder;the second equalizer is used for equalizing the output signal of the first decision unit;the third equalizer is used for performing equalization processing on the output signal of the first adder;the second adder is configured to add an output signal of the third equalizer and an output signal of the second equalizer;and the second decision unit is configured to decide an output signal of the second adder and output the decided signal.
- The decision feedback equalization apparatus of claim 1, further comprising:the fourth adder, the first coefficient updating module, the second coefficient updating module, the fifth adder and the third coefficient updating module;the fourth adder is configured to add the output signal of the first decision unit and the output signal of the first equalizer to obtain a first error signal;the first coefficient updating module is configured to update a first tap coefficient of the first equalizer according to the first error signal, and output the first tap coefficient to the first equalizer;the second coefficient updating module is configured to update a second tap coefficient of the second equalizer according to the first error signal, and output the second tap coefficient to the second equalizer;the fifth equalizer is configured to generate a second equalizer output signal according to the second error signal;the third coefficient updating module is configured to update a third tap coefficient of the third equalizer according to the second error signal, and output the third tap coefficient to the third equalizer.
- The apparatus according to claim 1, wherein the first coefficient updating module, the second coefficient updating module and the third coefficient updating module all update tap coefficients by a least mean square algorithm.
- The apparatus according to claim 3, wherein the step size of the first coefficient update module updating the first tap coefficients of the first equalizer is not equal to the step size of the second coefficient update module updating the second tap coefficients of the second equalizer.
- The decision feedback equalization apparatus of any of claims 1-4 wherein the first equalizer, the second equalizer, and the third equalizer are all transversal digital filters.
- A receiver comprising a decision feedback equalization apparatus as claimed in any one of claims 1 to 5.
- An optical transmission system comprising a transmitter for transmitting an optical signal and the receiver of claim 6.
- A signal processing method, comprising the steps of:receiving a first signal, and carrying out equalization processing on the received first signal to obtain a second signal;adding the second signal and the third signal to obtain a fourth signal;judging the fourth signal to obtain a fifth signal;carrying out equalization processing on the fifth signal, and taking an equalization result as a new third signal;performing equalization processing on the fourth signal to obtain a sixth signal;adding the sixth signal and the new third signal to obtain a seventh signal;and judging the seventh signal and outputting an eighth judged signal.
- The signal processing method of claim 8, further comprising:adding the fifth signal and the second signal to obtain a first error signal;updating a first tap coefficient according to the first error signal, and outputting the first tap coefficient;updating a second tap coefficient according to the first error signal, and outputting the second tap coefficient;adding the eighth signal and the sixth signal to obtain a second error signal;and updating the third tap coefficient according to the second error signal, and outputting the third tap coefficient.
- The signal processing method of claim 9, wherein the first tap coefficient, the second tap coefficient and the third tap coefficient are all updated using a least mean square algorithm.
- The signal processing method of claim 10, wherein the step size for updating the first tap coefficient is not equal to the step size for updating the second tap coefficient.
- A data communication device comprising a processor, a memory and a bus system via which the processor and the memory are connected, the memory being adapted to store instructions and the processor being adapted to execute instructions stored by the memory,wherein the processor is configured to: receiving a first signal, and carrying out equalization processing on the received first signal to obtain a second signal; adding the second signal and the third signal to obtain a fourth signal; judging the fourth signal to obtain a fifth signal; carrying out equalization processing on the fifth signal, and taking an equalization result as a new third signal; performing equalization processing on the fourth signal to obtain a sixth signal; adding the sixth signal and the new third signal to obtain a seventh signal; and judging the seventh signal and outputting an eighth judged signal.
- The data communication apparatus of claim 12, wherein the processor is further configured to:adding the fifth signal and the second signal to obtain a first error signal;updating a first tap coefficient according to the first error signal, and outputting the first tap coefficient;updating a second tap coefficient according to the first error signal, and outputting the second tap coefficient;adding the eighth signal and the sixth signal to obtain a second error signal;and updating the third tap coefficient according to the second error signal, and outputting the third tap coefficient.
- The data communication apparatus according to claim 13, wherein the first tap coefficient, the second tap coefficient and the third tap coefficient are each updated using a least mean square algorithm.
- The data communication apparatus according to claim 14, wherein a step size for updating the first tap coefficient is not equal to a step size for updating the second tap coefficient.
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| PCT/CN2015/076346 WO2016161643A1 (en) | 2015-04-10 | 2015-04-10 | Decision feedback equalization apparatus and method, and optical transmission system |
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