JP4953856B2 - Equalization circuit - Google Patents

Description

  The present invention relates to an equalizing circuit for correcting distortion of a waveform of a received data signal used for a digital transmission system for transmitting a digital data signal before identification reproduction.

  With the recent increase in the speed of digital transmission systems, signal quality degradation in the transmission line cannot be ignored. In the transmission line system, not only the loss of the transmission line, but also wavelength degradation (GVD) and polarization mode dispersion (PMD), and in the system using the multimode fiber, the waveform deterioration due to the mode dispersion is a big problem.

  Conventionally, an adaptive waveform equalization technique using an electric circuit has been applied as one of small and low-cost solutions. As typical equalization circuits, a transversal type equalization circuit (also called a finite impulse response filter) and a recursive type equalization circuit (also called an infinite impulse response filter) are widely used as communication systems. (See, for example, Non-Patent Document 1).

  A conventional equalization circuit will be described with reference to FIG. FIG. 9 is a diagram for explaining the operation of a conventional equalization circuit. As shown in FIG. 9, the conventional equalization circuit shapes the waveform by shifting the deteriorated waveform on the time axis, performing weighting, and performing addition / subtraction. As shown in FIG. 10, the distribution circuit 1 generates a plurality of replica signals of the received signal, the delay circuits 42 to 4n-n give different delays to the replica signals, and each replica signal has a multiplier circuit 51 to The signal strength is weighted by 5n and then added by the adder circuit 16.

  By changing the number of distributions (also called the number of stages and the number of taps) and the weighting setting of each replica signal, the transfer function of the equalization circuit can be changed, and various waveform deteriorations can be realized. As shown in FIG. 11, the configuration includes n distribution circuits 61 to 6n, n delay circuits 71 to 7n, (n + 1) multiplication circuits 81 to 8 (n + 1), and one addition circuit 32. As a result, the total delay time amount of the delay circuits 71 to 7n is reduced, and the circuit can be reduced in size. Since the state change of the deterioration factor is not known in advance, it is adaptive equalization to perform self-learning so that the weighting setting of each replica signal becomes an optimum condition (for example, see Non-Patent Document 2).

M.M. Nakamura, H .; Nosaka, M .; Ida, K .; Kurishima, and M.K. Tokumitsu, paperTuG4, OFC2004, “Electrical PMD equalizer ICs for a40-Gbit / s transmission” Translation of Yoshikazu Sabatani “Digital Communication”, Science and Technology Publishing, Sections 10-1-2 and 10-2

  In order to correct precisely, it is preferable to replicate the time difference between each replica signal finely. On the other hand, in order to correct large waveform deterioration, it is necessary to make the delay time difference between the first replica signal and the last replica signal large enough to include the deteriorated waveform. Many replica signals are required, which complicates the circuit.

  That is, the analysis and design of the transversal equalization circuit has conventionally been analyzed and designed on the assumption that the delay time difference between the replica signals is equal. This is because a mathematical model of the waveform deterioration factor is discretized at equal intervals, and therefore it is natural to analyze at equal intervals in response to distortion modeling for the compensation (for example, Non-patent document 2).

  For this reason, if the delay time difference between the first replica signal and the last replica signal is large enough to include a deteriorated waveform, it is indispensable to increase the number of replica signals to be replicated, and the circuit becomes complicated.

  The present invention has been made under such a background, and an object thereof is to provide an equalization circuit and a distortion reduction method capable of improving the correction capability with a small number of replica signals.

  The equalization circuit of the present invention is characterized in that the correction capability of the equalization circuit is improved with a small number of replica signals by making the delay time difference between the replica signals unequal.

  That is, the present invention provides an equalization circuit that duplicates a plurality of replica signals from a received signal, delays each replica signal, adds and subtracts each replica signal by weighting, and reduces distortion of the received signal. is there.

  Here, a feature of the present invention resides in that there is provided means for giving a delay amount so that at least one of the delay times between the replica signals is different from other delay times.

  For example, when the number of replica signal replicas is an odd number, the delay time of the central replica signal is used as a reference delay time. When the number of replica signal replicas is an even number, the average of the delay times of two central replica signals is used as a reference. It is desirable that the delay time is such that the maximum difference between the reference delay time and the delay time of each replica signal is greater than 0.75 times the reciprocal time of the symbol rate and not more than 1.2 times.

  For example, when there are four replica signals and the replica signals are arranged in ascending order of the delay time, the delay time difference between the second and third replica signals becomes the delay time difference between the other replica signals. Shorter than that. However, the delay time difference between the second and third replica signals may be equal to the delay time difference between some other replica signals.

  In this case, the delay time difference between the second and third replica signals is not more than 0.5 times the reciprocal time of the symbol rate, and the first one measured from the average delay time between the two replicas. It is desirable that at least one of the delay time differences of the replica signal or the fourth replica signal is greater than 0.75 times the reciprocal of the symbol rate and not more than 1.2 times.

  The present invention can also be viewed from the viewpoint of a distortion reducing method. That is, the present invention provides an equalization circuit that duplicates a plurality of replica signals from a received signal, delays each replica signal, adds and subtracts each replica signal by weighting, and reduces distortion of the received signal. This is a distortion reduction method to be performed.

  Here, the feature of the present invention is that the delay amount is given so that at least one of the delay times between the replica signals is different from the other delay times.

  According to the present invention, the correction characteristic of the equalization circuit can be improved even with a simple circuit configuration in which the number of replica signals is about four.

(First Example)
An equalizing circuit according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows an example in the case of 4 taps as a configuration example of the equalization circuit of this embodiment. The received signal distorted by transmission is duplicated and distributed by the distribution circuit 1 into a plurality of replica signals # 1 to # 4.

  The replica signals # 1 to # 4 pass through the delay circuits 2 to 7, respectively, are weighted by the multiplication circuits 12 to 15, and then synthesized by the adder circuit 16. In the figure, fine delay circuits 8 to 11 are circuits that give a smaller delay time than delay circuits 2 to 7. All the delay circuits 2 to 7 have the same delay time, and all the fine delay circuits 8 to 11 have the same delay time.

Thereby, the delay time difference between the replica signals # 1 and # 2 is
One delay circuit plus one fine delay circuit. Also, the delay time difference between replica signals # 2 and # 3 is
This is equivalent to one delay circuit. Also, the delay time difference between replica signals # 3 and # 4 is
One delay circuit plus one fine delay circuit.

  Therefore, the delay time difference between replica signals # 2 and # 3 is shorter than the delay time difference between replica signals # 1 and # 2 and the delay time difference between replica signals # 3 and # 4.

  Further, as shown in FIG. 2, the distribution circuits 20 to 22 are connected in multiple stages as two distributions, and delay circuits 23 to 25 and fine delay circuits 26 and 27 are arranged between the distribution circuits 20 to 22, thereby sequentially giving delays. May be. Replica signals # 1 to # 4 distributed by distribution circuits 20 to 22 are weighted by multiplication circuits 28 to 31, respectively, and then synthesized by addition circuit 32.

  FIG. 3 shows the effect of the present invention by numerical analysis. This is an example in which the improvement effect of waveform degradation due to polarization dispersion is calculated by an equalization circuit having 4 replicas, and the 44 Gbps DQPSK signal has a small distortion (DGD = 25 ps) as the polarization dispersion magnitude. In the case of medium (DGD = 30 ps) and large (DGD = 35 ps), the effect of correcting the distorted waveform by transmitting through each transmission line, the delay time of the fine delay circuit on the horizontal axis, The vertical axis represents the improvement in signal quality (Quality: Q value). The delay time of the delay circuit was 0.5 times the inverse of the baud rate. The unit of time is drawn as the reciprocal of the baud rate.

  The horizontal axis at the top of the graph shows the difference between the reference delay time and the delay time of the replica signal # 1 or # 4 when the average delay time of the replica signals # 2 and # 3 is used as the reference delay time. The larger value was entered.

  By introducing a fine delay circuit and making the delay time unequal intervals, the correction capability is improved particularly when the distortion is large. The correction capability is most improved when the average delay time of the replica signals # 2 and # 3 is set as the reference delay time, and the difference between the reference delay time and the delay time of the replica signal # 1 or # 4. If the larger value is around 1 times the reciprocal of the baud rate and is greater than 0.75 times (equal intervals) and less than 1.2 times, the correction capability can be improved.

(Second embodiment)
An equalizing circuit according to a second embodiment of the present invention will be described with reference to FIGS. In this embodiment, as shown in FIGS. 4 and 5, only the delay time difference between the replica signals # 1 and # 2 is increased. In this case, the fine delay circuit 11 of FIG. 1 and the fine delay circuit 27 of FIG. 2 do not exist in the configurations of FIG. 4 and FIG.

Thereby, the delay time difference between the replica signals # 1 and # 2 is
One delay circuit plus one fine delay circuit. Also, the delay time difference between replica signals # 2 and # 3 is
This is equivalent to one delay circuit. Also, the delay time difference between replica signals # 3 and # 4 is
This is equivalent to one delay circuit.

  Therefore, the delay time difference between replica signals # 2 and # 3 is equal to the delay time difference between replica signals # 3 and # 4, but more than the delay time difference between replica signals # 1 and # 2. Shorter.

  Alternatively, as shown in FIGS. 6 and 7, only the delay time between replica signals # 3 and # 4 may be increased. In this case, compared with the configuration of FIGS. 1 and 2, the fine delay circuits 8, 9, 11 of FIG. 1 and the fine delay circuit 26 of FIG. 2 are not present in the configurations of FIGS.

Thereby, the delay time difference between the replica signals # 1 and # 2 is
This is equivalent to one delay circuit. Also, the delay time difference between replica signals # 2 and # 3 is
This is equivalent to one delay circuit. Also, the delay time difference between replica signals # 3 and # 4 is
One delay circuit plus one fine delay circuit.

  Therefore, the delay time difference between replica signals # 2 and # 3 is equal to the delay time difference between replica signals # 1 and # 2, but more than the delay time difference between replica signals # 3 and # 4. Shorter.

  FIG. 8 shows the effect of the configuration examples of FIGS. 6 and 7 by numerical analysis. In the configuration example of FIGS. 6 and 7, the delay time difference between replica signals # 1 and # 2 and between replica signals # 2 and # 3 are equal, and each is 0.5 times the reciprocal of the baud rate. is there. The conditions are the same as in FIG. 3, and the results are shown only when the distortion is large (DGD = 35 ps).

  By introducing a fine delay circuit and making the delay times unequal, the correction capability when the distortion is large is improved. The correction capability is most improved when the average delay time of the replica signals # 2 and # 3 is set as the reference delay time, and the difference between the reference delay time and the delay time of the replica signal # 1 or # 4 is large. If one of the values is near 1 times the reciprocal of the baud rate and is greater than 0.75 times (equal intervals) and less than 1.2 times, the correction capability can be improved. Similar effects can be obtained with the configurations of FIGS.

(Supplementary example)
By changing the delay times of the fine delay circuits 8 to 11, 26 and 27 in the equalization circuit of the first embodiment shown in FIGS. 1 and 2, a delay time equivalent to that of the equalization circuit shown in FIGS. An equalization circuit having

  Further, in this embodiment, for the sake of easy understanding, the configuration in which the fine delay circuits 8 to 11, 26 and 27 are added to the delay circuits 2 to 7, 23 to 25 is illustrated. A delay circuit having a delay time equivalent to that obtained by adding fine delay circuits 8 to 11, 26, and 27 to 23 to 25 may be provided.

  According to the present invention, the correction characteristic of the equalization circuit can be improved even with a simple circuit configuration having about four replica signals. Therefore, the present invention is effectively used to improve the correction characteristic while avoiding the complexity of the equalization circuit. it can. In particular, it can be effectively used to improve the distortion correction capability of the equalization circuit when the distortion is large.

The block diagram of the equalization circuit of a 1st Example (1 stage of distribution circuits). The block diagram of the equalization circuit of a 1st Example (distribution circuit multistage). The figure which shows the effect of this invention by numerical analysis (1st Example). The block diagram of the equalization circuit of a 2nd Example (one stage of distribution circuits, a front fine delay). The block diagram of the equalization circuit of a 2nd Example (a distribution circuit is multistage, and a front fine delay). The block diagram of the equalization circuit of a 2nd Example (a distribution circuit is 1 step | paragraph, and a back fine delay). The block diagram of the equalization circuit of a 2nd Example (a distribution circuit is multistage, and a back fine delay). The figure which shows the effect of this invention by a numerical analysis (2nd Example). The figure for demonstrating operation | movement of the conventional equalization circuit. The block diagram of the conventional equalization circuit (1 stage of distribution circuits). The block diagram of the conventional equalization circuit (distribution circuit multistage).

Explanation of symbols

1, 20 to 22, 61 to 6n Distribution circuits 2 to 7, 23 to 25, 42, 43-1, 43-2, 4n-1 to 4n-n, 71 to 7n Delay circuits 8 to 11, 26, 27 Delay circuits 12-15, 28-31, 51-5n, 81-8 (n + 1) Multiplier circuits 16, 32 Adder circuits # 1- # 4 Replica signal

Claims (2)

In an equalization circuit that replicates four replica signals from a received signal, delays each replica signal, adds and subtracts each replica signal by weighting, and reduces distortion of the received signal.
Receives 44 Gbit / s DQPSK signal,
The differential group delay difference (DGD) received by the received signal is 30 ps or 35 ps,
The delay time for one delay circuit is 0.5 times the reciprocal time of the symbol rate,
The delay time for one fine delay circuit is smaller than the delay time for one delay circuit,
The four paths for giving a delay to the replica signal are a first path without a delay time, a second path for giving a delay time consisting of one delay circuit and one fine delay circuit, and a delay circuit 2. A third path that gives a delay time consisting of one delay circuit and one fine delay circuit, and a fourth path that gives a delay time consisting of three delay circuits and two fine delay circuits ,
The average delay time of the second path and the third path, that is, the delay time consisting of 1.5 delay circuits and 1 fine delay circuit is set as a reference delay time ,
The difference between the reference delay time and the delay times of the first path and the fourth path, that is, the delay time consisting of 1.5 delay circuits and one fine delay circuit is a time that is the reciprocal of the symbol rate. An equalization circuit that is greater than 0.75 times and 1.2 times or less.
In an equalization circuit that replicates four replica signals from a received signal, delays each replica signal, adds and subtracts each replica signal by weighting, and reduces distortion of the received signal.
Receives 44 Gbit / s DQPSK signal,
The differential group delay difference (DGD) received by the received signal is 35 ps,
The delay time for one delay circuit is 0.5 times the reciprocal time of the symbol rate,
The delay time for one fine delay circuit is smaller than the delay time for one delay circuit,
The four paths that give a delay to the replica signal are a first path without a delay time, a second path that gives a delay time consisting of one delay circuit, and a third path that gives a delay time consisting of two delay circuits. A path and a fourth path giving a delay time consisting of three delay circuits and one fine delay circuit,
The average delay time of the second path and the third path, that is, the delay time consisting of 1.5 delay circuits is set as the reference delay time,
The difference between the reference delay time and the delay time of the fourth path, that is, the delay time consisting of 1.5 delay circuits and one fine delay circuit is 0.75 times the reciprocal of the symbol rate. Larger than 1.2 times
An equalization circuit characterized by that .

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