WO2016155609A1 - 一种发光二极管芯片及其制备方法 - Google Patents

一种发光二极管芯片及其制备方法 Download PDF

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WO2016155609A1
WO2016155609A1 PCT/CN2016/077758 CN2016077758W WO2016155609A1 WO 2016155609 A1 WO2016155609 A1 WO 2016155609A1 CN 2016077758 W CN2016077758 W CN 2016077758W WO 2016155609 A1 WO2016155609 A1 WO 2016155609A1
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layer
electrode
metal catalyst
catalyst layer
emitting diode
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PCT/CN2016/077758
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French (fr)
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谢鹏
尹灵峰
韩涛
王江波
李鹏
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华灿光电股份有限公司
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Publication of WO2016155609A1 publication Critical patent/WO2016155609A1/zh
Priority to US15/719,603 priority Critical patent/US10553762B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0025—Processes relating to coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/005—Processes relating to semiconductor body packages relating to encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0075—Processes relating to semiconductor body packages relating to heat extraction or cooling elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/56—Materials, e.g. epoxy or silicone resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/641—Heat extraction or cooling elements characterized by the materials

Definitions

  • the present invention relates to the field of light emitting diodes, and in particular to an LED chip and a method of fabricating the same.
  • Light-emitting diode is a kind of green illumination source. It has the characteristics of energy saving, high reliability, long life, fast response, vibration resistance and easy maintenance. It has been widely used in flat panel display, traffic signal, lighting and lamp. Light-emitting diodes are a new generation of illumination sources that can replace incandescent and fluorescent lamps.
  • the most widely used light emitting diode chip includes a substrate layer, an N-type semiconductor layer sequentially laminated on the substrate, an active layer, and a P-type semiconductor layer.
  • a step is etched on the sequentially stacked N-type semiconductor layer, the active layer and the P-type semiconductor layer, and a transparent conductive layer and a P electrode are disposed on the upper horizontal end surface of the step, and an N electrode is disposed on the lower horizontal end surface of the step.
  • the step is covered with a protective layer.
  • the existing protective layer is mainly composed of silicon dioxide, which causes the waterproof and heat dissipation performance of the protective layer to be unsatisfactory.
  • the embodiment of the invention provides an LED chip and a preparation method thereof.
  • the technical solution is as follows:
  • an embodiment of the present invention provides a method for fabricating an LED chip, and the method for fabricating the LED chip includes:
  • Step surface Forming a step on the N-type semiconductor layer, the active layer, and the P-type semiconductor layer, the step including an upper horizontal end surface, a lower horizontal end surface, and a stage connecting the upper horizontal end surface and the lower horizontal end surface Step surface
  • a protective layer of fluorographene is formed on the metal catalyst layer.
  • the forming a metal catalyst layer on the LED chip formed with the N electrode and the P electrode comprises:
  • the central region of the top surface of the N electrode and the P electrode and the metal on the step surface are removed by a negative stripping method, and the photoresist is removed to form the metal catalyst layer.
  • the metal catalyst layer is composed of Ni, In, Ti, Rh, or Zn; or the metal catalyst layer is composed of at least Ni, In, Ti, Rh, and Zn.
  • the alloy composition is composed of two kinds of alloys; or the metal catalyst layer is composed of a Mo source containing Ni, In, Ti, Rh or Zn.
  • the metal catalyst layer has a thickness of 1-15 nm.
  • the forming a fluorographene protective layer on the metal catalyst layer comprises:
  • the fluorographene protective layer is formed on the surface of the chip.
  • the protective layer of the fluorographene has a thickness of 1-10 layers of monoatomic fluorographene.
  • an embodiment of the present invention further provides an LED chip, the LED chip comprising: a substrate, an N-type semiconductor layer sequentially stacked on the substrate, an active layer, and a P-type semiconductor layer,
  • the N-type semiconductor layer, the active layer, and the P-type semiconductor layer sequentially stacked are sequentially etched with a step, and the step includes an upper horizontal end surface, a lower horizontal end surface, and the upper horizontal end surface and the lower surface a step surface of the horizontal end surface, the lower horizontal end surface is provided with an N electrode, the upper horizontal end surface is covered with a transparent conductive layer, the transparent conductive layer is provided with an etched hole in the middle, and the P hole is disposed in the etched hole
  • the light emitting diode chip further includes a metal catalyst layer and a protective layer of fluorographene, the metal catalyst layer covering a central region of a surface of the light emitting diode chip except the top surface of the N electrode and the P electrode, and In a region other than the step surface, the fluorographene protective layer covers the metal catalyst layer.
  • the metal catalyst layer is composed of Ni, In, Ti, Rh, or Zn; or the metal catalyst layer is composed of at least two of Ni, In, Ti, Rh, and Zn.
  • An alloy composition of the composition; or the metal catalyst layer is composed of a Mo source containing Ni, In, Ti, Rh or Zn.
  • the metal catalyst layer has a thickness of 1-15 nm.
  • the protective layer of the fluorographene has a thickness of 1-10 layers of monoatomic fluorographene.
  • the metal catalyst layer and the fluorographene protective layer constitute a protective layer of the entire chip in the present invention by growing a metal catalyst layer and a fluorographene protective layer on the light emitting diode chip formed with the N electrode and the P electrode.
  • the protective layer in the present invention covers the surface of the light emitting diode chip The central region of the top surface of the N electrode and the P electrode and the region outside the step surface, that is, only the central region and the stepped surface of the top surface of the N electrode and the P electrode are exposed, so that the protective layer has a large protective area for the entire chip;
  • Graphene is impervious to water, so the protective layer has good waterproof effect; metal and fluorographene have high thermal conductivity and good thermal conductivity, which can help the chip to dissipate heat during operation. Therefore, the chip using the metal catalyst layer and the fluorographene protective layer as the protective layer has good waterproof and heat dissipation properties.
  • FIG. 1 is a flow chart of a method for fabricating an LED chip according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of an LED chip according to an embodiment of the present invention.
  • FIG. 3 is a top plan view of an LED chip according to an embodiment of the invention.
  • FIG. 1 is a flow chart of a method for fabricating an LED chip. Referring to FIG. 1, the LED chip manufacturing method includes:
  • Step 101 Providing a substrate.
  • the substrate includes, but is not limited to, a sapphire substrate or a silicon substrate.
  • Step 102 sequentially growing an N-type semiconductor layer, an active layer, and a P-type semiconductor layer on the substrate.
  • an N-type semiconductor layer, an active layer, and a P-type semiconductor layer may be sequentially grown on a substrate by a MOCVD (Metal-Organic Chemical Vapor Deposition) method.
  • MOCVD Metal-Organic Chemical Vapor Deposition
  • At least one buffer layer may be grown on the substrate. To better grow the follow-up structure.
  • Step 103 forming a step on the N-type semiconductor layer, the active layer, and the P-type semiconductor layer, the step including an upper horizontal end surface, a lower horizontal end surface, and a step surface connecting the upper horizontal end surface and the lower horizontal end surface.
  • a step may be formed on the N-type semiconductor layer, the active layer, and the P-type semiconductor layer by an ICP (Inductively Coupled Plasma) etching process.
  • ICP Inductively Coupled Plasma
  • a part of the N-type semiconductor layer, the active layer, and the P-type semiconductor layer are removed by ICP etching to form a step.
  • the height of the step is greater than the sum of the thicknesses of both the P-type semiconductor layer and the active layer, and is smaller than the sum of the thicknesses of the N-type semiconductor layer, the active layer, and the P-type semiconductor layer. That is to say, when etching the step, the P-type semiconductor layer is completely etched, the active layer is completely etched, and a part of the N-type semiconductor layer is finally etched.
  • the upper horizontal end surface is the surface of the unetched P-type semiconductor layer
  • the lower horizontal end surface is the surface of the etched N-type semiconductor layer
  • the step surface is sequentially passed through the N-type semiconductor layer and the active layer. And a section of the P-type semiconductor.
  • Step 104 growing a transparent conductive layer on the upper horizontal end surface and forming an etched hole in the middle of the transparent conductive layer.
  • the transparent conductive layer may be an ITO (Indium Tin Oxide) film.
  • the transparent conductive layer can be prepared by electron beam evaporation or magnetron sputtering. For example, a transparent conductive layer is evaporated by electron beam evaporation on the upper horizontal end surface of the step.
  • Step 105 An N electrode is disposed on the lower horizontal end surface, and a P electrode is disposed in the etching hole.
  • the N electrode and the P electrode can be prepared by a thermal evaporation method.
  • the P electrode is disposed on the P-type semiconductor layer.
  • Step 106 growing a metal catalyst layer on the light-emitting diode chip formed with the N electrode and the P electrode, the metal catalyst layer covering the surface of the light-emitting diode chip except the central region and the step surface of the top surface of the N electrode and the P electrode Area.
  • step 106 can be implemented in the following manner:
  • N electrode Forming an N electrode by magnetron sputtering, thermal evaporation, solution or electron beam evaporation Depositing a layer of metal on the surface of the LED chip of the P electrode;
  • the central region of the metal on the top surface of the N electrode and the P electrode and the metal on the step surface are removed by a negative stripping method, and the photoresist is removed to form a metal catalyst layer.
  • the metal on the photoresist in the central region of the top surface of the N electrode and the P electrode may be stripped by a blue film.
  • the method of applying the photoresist may be spin coating, and the photoresist may be applied evenly by applying the photoresist by spin coating, and the thickness of the photoresist may be relatively easily controlled by controlling the speed of the spin coating.
  • the embodiments of the present invention do not limit this.
  • the metal catalyst layer is composed of Ni, In, Ti, Rh or Zn; or the metal catalyst layer is composed of an alloy composed of at least two of Ni, In, Ti, Rh and Zn; or, metal
  • the catalyst layer is composed of a Mo source containing Ni, In, Ti, Rh or Zn such as trimethylindium.
  • the material of the metal catalyst layer is only exemplified, and the metal material in the embodiment of the present invention may also be composed of other metal materials, which is not limited in the present invention.
  • the metal catalyst layer may have a thickness of from 1 to 15 nm.
  • the thickness of the metal catalyst layer should not be too thick or too thin. If the metal catalyst layer is too thick, the ability to absorb light is strong; if the metal catalyst layer is too thin, the catalytic effect is not satisfactory, and the normal growth of the subsequent protective layer of the fluorographene cannot be ensured. Therefore, the metal catalyst layer having the above thickness is selected so that the metal catalyst has a small thickness and good light transmittance, and the fluorinated graphene has an extremely high transmittance in the visible light band, thereby making the overall light transmittance of the chip good; The use of the metal catalyst layer of the above thickness can ensure the catalytic effect of the metal catalyst layer.
  • Step 107 Forming a protective layer of fluorographene on the surface of the metal catalyst layer.
  • step 107 can be implemented in the following manner:
  • the light-emitting diode chip formed with the metal catalyst layer is placed in the surface wave plasma chemical vapor deposition cavity; the pressure in the cavity is controlled below 1000 Pa, the temperature is controlled at 500-750 ° C, and H 2 , CH 4 and F are introduced. 2 and open the microwave source for 5-20min to produce a protective layer of fluorographene on the surface of the chip.
  • the pressure in the cavity is preferably 300-600 Pa.
  • H 2 , CH 4 and F 2 are introduced at 2:4:1, and the above gas ratio is only a preferred value, and the embodiment of the invention is not limited.
  • the role of the metal catalyst layer is to grow fluorographene at a low temperature, the above growth occurs.
  • the protective layer of fluorographene is only grown on the surface of the metal catalyst layer.
  • the thickness of the fluorographene protective layer may be 1-10 layers of monoatomic fluorographene.
  • the thickness of the protective layer of fluorographene should not be too thick or too thin.
  • the protective layer of fluorographene is too thick, and the light transmittance is poor, which affects the normal light output of the chip; if the protective layer of the fluorographene is too thin, the waterproof performance is not good. Therefore, the use of the above-mentioned thickness of the fluorographene protective layer can not only affect the normal light output of the chip, but also ensure the good waterproof performance of the fluorographene protective layer.
  • the thickness of the protective layer of fluorographene is the thickness of 5 layers of monoatomic fluorographene.
  • a metal catalyst layer and a fluorographene protective layer are grown on the light emitting diode chip formed with the N electrode and the P electrode, and in the present invention, the metal catalyst layer and the fluorographene protective layer constitute the entire a protective layer of the chip;
  • the protective layer of the present invention covers a surface of the surface of the light-emitting diode chip except the central region of the top surface of the N electrode and the P electrode and the step surface, that is, the center of only the top surface of the N electrode and the P electrode is exposed The area and the step surface make the protective layer have a large protective area for the whole chip;
  • the fluorinated graphene is impervious to water, so the waterproof effect of the protective layer is good;
  • the metal and fluorographene have high thermal conductivity and good thermal conductivity, which can be very A good help chip dissipates heat while working. Therefore, the chip using the metal catalyst layer and the fluorographene protective layer as the protective layer has good waterproof and heat dissipation
  • FIG. 2 is a schematic structural diagram of an LED chip, which can be fabricated by using the LED chip manufacturing method provided in FIG. 1.
  • the LED chip includes: a substrate 201, and N stacked on the substrate 201 in sequence.
  • the semiconductor layer 202, the active layer 203 and the P-type semiconductor layer 204, the N-type semiconductor layer 202, the active layer 203, and the P-type semiconductor layer 204 which are sequentially stacked are sequentially etched with a step 200, and the step 200 includes an upper horizontal end surface and a lower surface.
  • the horizontal end surface and the step surface connecting the upper horizontal end surface and the lower horizontal end surface, the lower horizontal end surface of the step 200 is provided with an N electrode 206, and the upper horizontal end surface of the step 200 is covered with a transparent conductive layer 205, and the transparent conductive layer 205 is provided in the middle portion thereof.
  • the P hole 207 is provided in the etched hole of the transparent conductive layer 205.
  • the light emitting diode chip further includes a metal catalyst layer 208 and a fluorographene protective layer 209 covering the surface of the light emitting diode chip except the central region and the step surface of the top surface of the N electrode 206 and the P electrode 207. In the region, the central region of the top surface of the N electrode 206 and the P electrode 207 is exposed, and the fluorographene protective layer 209 is overlaid on the metal catalyst layer 208.
  • FIG. 3 provides a top view of a light emitting diode chip in which a fluorographene protective layer 209 covers the surface of the entire chip except for the central regions of the N electrode 206 and the P electrode 207.
  • the metal catalyst layer is composed of Ni, In, Ti, Rh or Zn; or the metal catalyst layer is composed of an alloy composed of at least two of Ni, In, Ti, Rh and Zn; or, metal
  • the catalyst layer is composed of a Mo source containing Ni, In, Ti, Rh or Zn such as trimethylindium.
  • the material of the metal catalyst layer is only exemplified, and the metal material in the embodiment of the present invention may also be composed of other metal materials, which is not limited in the present invention.
  • the metal catalyst layer has a thickness of from 1 to 15 nm.
  • the thickness of the metal catalyst layer should not be too thick or too thin. If the metal catalyst layer is too thick, the ability to absorb light is strong; if the metal catalyst layer is too thin, the catalytic effect is not satisfactory, and the normal growth of the subsequent protective layer of the fluorographene cannot be ensured. Therefore, the metal catalyst layer having the above thickness is selected so that the metal catalyst has a small thickness and good light transmittance, and the fluorinated graphene has an extremely high transmittance in the visible light band, thereby making the overall light transmittance of the chip good; The use of the metal catalyst layer of the above thickness can ensure the catalytic effect of the metal catalyst layer.
  • the thickness of the fluorographene protective layer may be 1-10 layers of monoatomic fluorographene.
  • the thickness of the protective layer of fluorographene should not be too thick or too thin.
  • the protective layer of fluorographene is too thick, and the light transmittance is poor, which affects the normal light output of the chip; if the protective layer of the fluorographene is too thin, the waterproof performance is not good. Therefore, the use of the above-mentioned thickness of the fluorographene protective layer can not only affect the normal light output of the chip, but also ensure the good waterproof performance of the fluorographene protective layer.
  • the thickness of the protective layer of fluorographene is the thickness of 5 layers of monoatomic fluorographene.
  • the substrate 201 includes, but is not limited to, a sapphire substrate or a silicon substrate.
  • FIG. 2 is a schematic structural diagram of an LED chip, which is only an example of an LED chip in the embodiment of the present invention.
  • the order of the layers in the LED chip can be varied, and the LED chip can also include more or less films.
  • the layer (such as a buffer layer between the substrate and the N-type semiconductor layer), as long as the necessary elements of the LED chip are fabricated, it is ensured that the LED chip can work normally.
  • a metal catalyst layer and a fluorographene protective layer are grown on the light emitting diode chip formed with the N electrode and the P electrode, and the metal catalyst layer and the fluorine in the present invention
  • the graphene protective layer constitutes a protective layer of the entire chip;
  • the protective layer of the present invention covers the surface of the light emitting diode chip except the central region of the top surface of the N electrode and the P electrode and the stepped surface, that is, only the N electrode is exposed and
  • the central region and the stepped surface of the top surface of the P electrode make the protective layer have a large protective area for the entire chip;
  • the fluorographene is impervious to water, so the waterproof effect of the protective layer is good; the thermal conductivity of the metal and the fluorographene is high.
  • the thermal conductivity is good, which can help the chip to dissipate heat during operation. Therefore, the chip using the above metal catalyst layer and the fluorographene protective layer as a protective layer has good waterproof and heat dissi

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Abstract

一种发光二极管芯片及其制备方法，属于发光二极管领域。该方法包括：提供一衬底（201）；在衬底（201）上依次生长N型半导体层（202）、有源层（203）和P型半导体层（204）；在N型半导体层（202）、有源层（203）和P型半导体层（204）上形成台阶（200），台阶（200）包括上水平端面、下水平端面及连接上水平端面和下水平端面的台阶面；在上水平端面上生长透明导电层（205），并在透明导电层（205）中部形成蚀孔；在下水平端面上设置N电极（206），在蚀孔内设置P电极（207）；在形成有N电极（206）和P电极（207）的发光二极管芯片上生长一层金属催化剂层（208），金属催化剂层（208）覆盖在发光二极管芯片的表面除N电极（206）和P电极（207）的顶面的中心区域及台阶面之外的区域；在金属催化剂层（208）上形成氟代石墨烯保护层（209）。

Description

一种发光二极管芯片及其制备方法 技术领域
本发明涉及发光二极管领域，特别涉及一种发光二极管芯片及其制备方法。
背景技术
发光二极管是一种绿色照明光源，具有节能环保、可靠性高、寿命长、响应速度快、耐振动、易维护等特点，已广泛用于平板显示、交通信号灯、照明及车灯等领域。发光二极管是可取代白炽灯、荧光灯的新一代照明光源。
现有技术中，应用最广泛的发光二极管芯片包括：衬底层、依次层叠在衬底上的N型半导体层、有源层和P型半导体层。在依次层叠的N型半导体层、有源层和P型半导体层上刻蚀有一个台阶，台阶的上水平端面上设有透明导电层和P电极，台阶的下水平端面上设有N电极，在台阶上覆盖有保护层。
在实现本发明的过程中，发明人发现现有技术至少存在以下问题：
现有保护层主要由二氧化硅构成，造成保护层的防水和散热性能不理想。
发明内容
为了解决现有技术中保护层的防水和散热性能不理想的问题，本发明实施例提供了一种发光二极管芯片及其制备方法。所述技术方案如下：
第一方面，本发明实施例提供了一种发光二极管芯片制备方法，所述发光二极管芯片制备方法包括：
提供一衬底；
在所述衬底上依次生长N型半导体层、有源层和P型半导体层；
在所述N型半导体层、有源层和P型半导体层上形成台阶，所述台阶包括上水平端面、下水平端面及连接所述上水平端面和所述下水平端面的台 阶面；
在所述上水平端面上生长透明导电层，并在所述透明导电层中部形成蚀孔；
在所述下水平端面上设置N电极，在所述蚀孔内设置P电极；
在形成有所述N电极和所述P电极的所述发光二极管芯片上生长一层金属催化剂层，所述金属催化剂层覆盖在所述发光二极管芯片的表面除所述N电极和所述P电极的顶面的中心区域及所述台阶面之外的区域；
在所述金属催化剂层上形成氟代石墨烯保护层。
在本发明实施例的一种实现方式中，所述在形成有所述N电极和所述P电极的所述发光二极管芯片上生长一层金属催化剂层，包括：
在所述N电极和所述P电极的顶面的中心区域及所述台阶面上涂一层光刻胶；
采用磁控溅射法、热蒸发法、溶液法或电子束蒸发法在形成有所述N电极和所述P电极的所述发光二极管芯片的表面沉积一层金属；
利用负胶剥离法除去所述N电极和所述P电极的顶面的中心区域及所述台阶面上的金属，并除去光刻胶，形成所述金属催化剂层。
在本发明实施例的另一种实现方式中，所述金属催化剂层由Ni、In、Ti、Rh或Zn构成；或者，所述金属催化剂层由Ni、In、Ti、Rh和Zn中的至少两种构成的合金构成；或者，所述金属催化剂层由Mo源构成，所述Mo源含Ni、In、Ti、Rh或Zn。
在本发明实施例的另一种实现方式中，所述金属催化剂层的厚度为1-15nm。
在本发明实施例的另一种实现方式中，所述在所述金属催化剂层上形成氟代石墨烯保护层包括：
将形成有所述金属催化剂层的所述发光二极管芯片放置于表面波等离子体化学气相沉积腔体中；
将所述表面波等离子体化学气相沉积腔体内的压强控制在1000Pa以下，温度控制在500-750℃，通入H2、CH4和F2并开启微波源5-20min，在 所述发光二极管芯片表面生成所述氟代石墨烯保护层。
在本发明实施例的另一种实现方式中，所述氟代石墨烯保护层的厚度为1-10层单原子氟代石墨烯的厚度。
第二方面，本发明实施例还提供了一种发光二极管芯片，所述发光二极管芯片包括：衬底、依次层叠在所述衬底上的N型半导体层、有源层和P型半导体层，依次层叠的所述N型半导体层、所述有源层、所述P型半导体层共同刻蚀有一台阶，所述台阶包括上水平端面、下水平端面及连接所述上水平端面和所述下水平端面的台阶面，所述下水平端面设有N电极，所述上水平端面上覆盖有一层透明导电层，所述透明导电层中部设有蚀孔，所述蚀孔内设有P电极，
所述该发光二极管芯片还包括金属催化剂层和氟代石墨烯保护层，所述金属催化剂层覆盖在所述发光二极管芯片的表面除所述N电极和所述P电极的顶面的中心区域及所述台阶面之外的区域，所述氟代石墨烯保护层覆盖在所述金属催化剂层上。
在本发明实施例的一种实现方式中，所述金属催化剂层由Ni、In、Ti、Rh或Zn构成；或者，所述金属催化剂层由Ni、In、Ti、Rh和Zn中的至少两种构成的合金构成；或者，所述金属催化剂层由Mo源构成，所述Mo源含Ni、In、Ti、Rh或Zn。
在本发明实施例的另一种实现方式中，所述金属催化剂层的厚度为1-15nm。
在本发明实施例的另一种实现方式中，所述氟代石墨烯保护层的厚度为1-10层单原子氟代石墨烯的厚度。
本发明实施例提供的技术方案带来的有益效果是：
通过在形成有N电极和P电极的发光二极管芯片上生长一层金属催化剂层和一层氟代石墨烯保护层，在本发明中金属催化剂层和氟代石墨烯保护层构成整个芯片的保护层；本发明中的保护层覆盖发光二极管芯片的表面除 N电极和P电极的顶面的中心区域及台阶面之外的区域，即仅露出N电极和P电极的顶面的中心区域和台阶面，使得保护层对整个芯片进行保护面积足够大；氟代石墨烯不透水，因此该保护层的防水效果好；金属和氟代石墨烯的导热系数高，导热性能好，可以很好的帮助芯片在工作时进行散热。故上述采用金属催化剂层和氟代石墨烯保护层作为保护层的芯片具有良好的防水和散热性能。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种发光二极管芯片制备方法流程图；
图2是本发明实施例提供的一种发光二极管芯片的结构示意图；
图3是本发明实施例提供的一种发光二极管芯片的俯视图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
图1提供了一种发光二极管芯片制备方法流程图，参见图1，该发光二极管芯片制备方法包括：
步骤101：提供一衬底。
在本实施例中，该衬底包括但不限于蓝宝石衬底或者硅衬底。
步骤102：在衬底上依次生长N型半导体层、有源层和P型半导体层。
在本实施例中，可以采用MOCVD(Metal-organic Chemical Vapor Deposition，金属有机化合物化学气相沉淀)法在衬底上依次生长N型半导体层、有源层和P型半导体层。
进一步地，在步骤102之前，还可以现在衬底上生长至少一层缓冲层， 以更好的生长后续结构。
步骤103：在N型半导体层、有源层和P型半导体层上形成台阶，台阶包括上水平端面、下水平端面及连接上水平端面和下水平端面的台阶面。
在本实施例中，可以采用ICP(Inductively Coupled Plasma，感应耦合等离子体)刻蚀工艺在N型半导体层、有源层和P型半导体层上形成台阶。具体地，在依次层叠的N型半导体层、有源层和P型半导体层上，用ICP刻蚀法去掉部分的N型半导体层、有源层和P型半导体层，形成台阶。该台阶的高度大于P型半导体层和有源层两者的厚度之和，且小于N型半导体层、有源层和P型半导体层三者的厚度之和。也就是说，刻蚀台阶时，先将P型半导体层刻蚀完全，再将有源层刻蚀完全，最后刻蚀部分的N型半导体层。
其中，上水平端面即为未被刻蚀的P型半导体层的表面，下水平端面即为刻蚀形成的N型半导体层的表面，而台阶面则是依次经过N型半导体层、有源层和P型半导体的一个断面。
步骤104：在上水平端面上生长透明导电层，并在透明导电层中部形成蚀孔。
在本实施例中，透明导电层可以为ITO(Indium Tin Oxide，氧化铟锡)薄膜。该透明导电层可以通过电子束蒸发法或者磁控溅射法制备。例如，在台阶的上水平端面上利用电子束蒸发法蒸镀一层透明导电层。
步骤105：在下水平端面上设置N电极，在蚀孔内设置P电极。
在本实施例中，N电极和P电极可以采用热蒸发法制备。
其中，P电极设置在P型半导体层上。
步骤106：在形成有N电极和P电极的发光二极管芯片上生长一层金属催化剂层，金属催化剂层覆盖在发光二极管芯片的表面除N电极和P电极的顶面的中心区域及台阶面之外的区域。
具体地，步骤106可以采用下述方式实现：
在N电极和P电极的顶面的中心区域及台阶面上涂一层光刻胶；
采用磁控溅射法、热蒸发法、溶液法或电子束蒸发法在形成有N电极 和P电极的发光二极管芯片的表面沉积一层金属；
利用负胶剥离法除去N电极和P电极的顶面的金属的中心区域及台阶面上的金属，并除去光刻胶，形成金属催化剂层。具体地，可以采用蓝膜剥离N电极和P电极顶面的中心区域的光刻胶上的金属。
其中，涂抹光刻胶的方式可以是旋涂，通过旋涂涂抹光刻胶可以使得光刻胶涂抹比较均匀，通过控制旋涂转速的快慢还能够比较容易的控制光刻胶的厚度。当然本发明实施例并不对此进行限制。
在本发明实施例中，金属催化剂层由Ni、In、Ti、Rh或Zn构成；或者，金属催化剂层由Ni、In、Ti、Rh和Zn中的至少两种构成的合金构成；或者，金属催化剂层由Mo源构成，Mo源含Ni、In、Ti、Rh或Zn，如三甲基铟。上述金属催化剂层的材料仅为举例，本发明实施例中的金属材料还可以由其他金属材料构成，本发明对此不做限制。
优选地，金属催化剂层的厚度可以为1-15nm。金属催化剂层的厚度不能太厚，也不能太薄。金属催化剂层太厚则会吸收光的能力强；金属催化剂层太薄则会使得催化效果不理想，无法保证后续氟代石墨烯保护层的正常生长。因此，选用上述厚度的金属催化剂层，使得金属催化剂厚度小，透光性好，而氟代石墨烯在可见光波段具有极高的透过率，因此使得芯片整体的的透光性好；另外，选用上述厚度的金属催化剂层，又可以保证金属催化剂层的催化效果。
步骤107：在金属催化剂层表面形成氟代石墨烯保护层。
具体地，步骤107可以采用下述方式实现：
将形成有金属催化剂层的发光二极管芯片放置于表面波等离子体化学气相沉积腔体中；将腔体内的压强控制在1000Pa以下，温度控制在500-750℃，通入H2、CH4和F2并开启微波源5-20min，使芯片表面产生氟代石墨烯保护层。其中，腔体内的压强优选为300-600Pa。其中，H2、CH4和F2按2：4：1通入，上述气体比例只是作为优选值，而并不能对本发明实施例进行限制。
由于金属催化剂层的作用是使氟代石墨烯在低温下生长，故在上述生长 环境下，只会在金属催化剂层的表面才会生长氟代石墨烯保护层。
在本发明实施例中，氟代石墨烯保护层的厚度可以为1-10层单原子氟代石墨烯的厚度。氟代石墨烯保护层的厚度不能太厚，也不能太薄。氟代石墨烯保护层太厚，透光性就会差，影响芯片的正常出光；氟代石墨烯保护层太薄，则防水性能不佳。因此，选用上述厚度的氟代石墨烯保护层既可以避免影响芯片的正常出光，又可以保证氟代石墨烯保护层有良好的防水性能。
优选地，氟代石墨烯保护层的厚度为5层单原子氟代石墨烯的厚度。
本发明实施例通过在形成有N电极和P电极的发光二极管芯片上生长一层金属催化剂层和一层氟代石墨烯保护层，在本发明中金属催化剂层和氟代石墨烯保护层构成整个芯片的保护层；本发明中的保护层覆盖发光二极管芯片的表面除N电极和P电极的顶面的中心区域及台阶面之外的区域，即仅露出N电极和P电极的顶面的中心区域和台阶面，使得保护层对整个芯片进行保护面积足够大；氟代石墨烯不透水，因此该保护层的防水效果好；金属和氟代石墨烯的导热系数高，导热性能好，可以很好的帮助芯片在工作时进行散热。故上述采用金属催化剂层和氟代石墨烯保护层作为保护层的芯片具有良好的防水和散热性能。
图2提供了一种发光二极管芯片的结构示意图，可以采用图1提供的发光二极管芯片制备方法制成，参见图2，该发光二极管芯片包括：衬底201、依次层叠在衬底201上的N型半导体层202、有源层203和P型半导体层204，依次层叠的N型半导体层202、有源层203、P型半导体层204共同刻蚀有一台阶200，台阶200包括上水平端面、下水平端面及连接上水平端面和下水平端面的台阶面，台阶200的下水平端面设有N电极206，台阶200的上水平端面上覆盖有一层透明导电层205，透明导电层205的中部设有蚀孔，透明导电层205的蚀孔内设有P电极207。
该发光二极管芯片还包括金属催化剂层208和氟代石墨烯保护层209，金属催化剂层208覆盖在发光二极管芯片的表面除N电极206和P电极207的顶面的中心区域及台阶面之外的区域，N电极206和P电极207的顶面的中心区域裸露，氟代石墨烯保护层209覆盖在金属催化剂层208上。
图3提供了一种发光二极管芯片的俯视图，其中，氟代石墨烯保护层209覆盖了除N电极206、P电极207中心区域外的整个芯片的表面。
在本发明实施例中，金属催化剂层由Ni、In、Ti、Rh或Zn构成；或者，金属催化剂层由Ni、In、Ti、Rh和Zn中的至少两种构成的合金构成；或者，金属催化剂层由Mo源构成，Mo源含Ni、In、Ti、Rh或Zn，如三甲基铟。上述金属催化剂层的材料仅为举例，本发明实施例中的金属材料还可以由其他金属材料构成，本发明对此不做限制。
在本发明实施例中，金属催化剂层的厚度为1-15nm。金属催化剂层的厚度不能太厚，也不能太薄。金属催化剂层太厚则会吸收光的能力强；金属催化剂层太薄则会使得催化效果不理想，无法保证后续氟代石墨烯保护层的正常生长。因此，选用上述厚度的金属催化剂层，使得金属催化剂厚度小，透光性好，而氟代石墨烯在可见光波段具有极高的透过率，因此使得芯片整体的的透光性好；另外，选用上述厚度的金属催化剂层，又可以保证金属催化剂层的催化效果。
在本发明实施例中，氟代石墨烯保护层的厚度可以为1-10层单原子氟代石墨烯的厚度。氟代石墨烯保护层的厚度不能太厚，也不能太薄。氟代石墨烯保护层太厚，透光性就会差，影响芯片的正常出光；氟代石墨烯保护层太薄，则防水性能不佳。因此，选用上述厚度的氟代石墨烯保护层既可以避免影响芯片的正常出光，又可以保证氟代石墨烯保护层有良好的防水性能。
优选地，氟代石墨烯保护层的厚度为5层单原子氟代石墨烯的厚度。
其中，衬底201包括但不限于蓝宝石衬底或者硅衬底。
图2提供的发光二极管芯片的结构示意图，只是本发明实施例对于发光二极管芯片的举例，发光二极管芯片中的膜层顺序可以有很多种变化，发光二极管芯片也可以包括更多或者更少的膜层(如在衬底和N型半导体层之间设置缓冲层)，只要制作出发光二极管芯片必要的元素，确保发光二极管芯片可以正常工作即可。
本发明实施例通过在形成有N电极和P电极的发光二极管芯片上生长一层金属催化剂层和一层氟代石墨烯保护层，在本发明中金属催化剂层和氟 代石墨烯保护层构成整个芯片的保护层；本发明中的保护层覆盖发光二极管芯片的表面除N电极和P电极的顶面的中心区域及台阶面之外的区域，即仅露出N电极和P电极的顶面的中心区域和台阶面，使得保护层对整个芯片进行保护面积足够大；氟代石墨烯不透水，因此该保护层的防水效果好；金属和氟代石墨烯的导热系数高，导热性能好，可以很好的帮助芯片在工作时进行散热。故该采用上述金属催化剂层和氟代石墨烯保护层作为保护层的芯片具有良好的防水和散热性能。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种发光二极管芯片制备方法，其特征在于，所述发光二极管芯片制备方法包括：
    提供一衬底；
    在所述衬底上依次生长N型半导体层、有源层和P型半导体层；
    在所述N型半导体层、有源层和P型半导体层上形成台阶，所述台阶包括上水平端面、下水平端面及连接所述上水平端面和所述下水平端面的台阶面；
    在所述上水平端面上生长透明导电层，并在所述透明导电层中部形成蚀孔；
    在所述下水平端面上设置N电极，在所述蚀孔内设置P电极；
    在形成有所述N电极和所述P电极的所述发光二极管芯片上生长一层金属催化剂层，所述金属催化剂层覆盖在所述发光二极管芯片的表面除所述N电极和所述P电极的顶面的中心区域及所述台阶面之外的区域；
    在所述金属催化剂层上形成氟代石墨烯保护层。
  2. 根据权利要求1所述的方法，其特征在于，所述在形成有所述N电极和所述P电极的所述发光二极管芯片上生长一层金属催化剂层，包括：
    在所述N电极和所述P电极的顶面的中心区域及所述台阶面上涂一层光刻胶；
    采用磁控溅射法、热蒸发法、溶液法或电子束蒸发法在形成有所述N电极和所述P电极的所述发光二极管芯片的表面沉积一层金属；
    利用负胶剥离法除去所述N电极和所述P电极的顶面的中心区域及所述台阶面上的金属，并除去光刻胶，形成所述金属催化剂层。
  3. 根据权利要求1或2所述的方法，其特征在于，所述金属催化剂层由Ni、In、Ti、Rh或Zn构成；或者，所述金属催化剂层由Ni、In、Ti、Rh 和Zn中的至少两种构成的合金构成；或者，所述金属催化剂层由Mo源构成，所述Mo源含Ni、In、Ti、Rh或Zn。
  4. 根据权利要求1或2所述的方法，其特征在于，所述金属催化剂层的厚度为1-15nm。
  5. 根据权利要求1所述的方法，其特征在于，所述在所述金属催化剂层上形成氟代石墨烯保护层包括：
    将形成有所述金属催化剂层的所述发光二极管芯片放置于表面波等离子体化学气相沉积腔体中；
    将所述表面波等离子体化学气相沉积腔体内的压强控制在1000Pa以下，温度控制在500-750℃，通入H2、CH4和F2并开启微波源5-20min，在所述发光二极管芯片表面生成所述氟代石墨烯保护层。
  6. 根据权利要求1或5所述的方法，其特征在于，所述氟代石墨烯保护层的厚度为1-10层单原子氟代石墨烯的厚度。
  7. 一种发光二极管芯片，所述发光二极管芯片包括：衬底、依次层叠在所述衬底上的N型半导体层、有源层和P型半导体层，依次层叠的所述N型半导体层、所述有源层、所述P型半导体层共同刻蚀有一台阶，所述台阶包括上水平端面、下水平端面及连接所述上水平端面和所述下水平端面的台阶面，所述下水平端面设有N电极，所述上水平端面上覆盖有一层透明导电层，所述透明导电层中部设有蚀孔，所述蚀孔内设有P电极，其特征在于，
    所述该发光二极管芯片还包括金属催化剂层和氟代石墨烯保护层，所述金属催化剂层覆盖在所述发光二极管芯片的表面除所述N电极和所述P电极的顶面的中心区域及所述台阶面之外的区域，所述氟代石墨烯保护层覆盖在所述金属催化剂层上。
  8. 根据权利要求7所述的发光二极管芯片，其特征在于，所述金属催化剂层由Ni、In、Ti、Rh或Zn构成；或者，所述金属催化剂层由Ni、In、Ti、Rh和Zn中的至少两种构成的合金构成；或者，所述金属催化剂层由Mo源构成，所述Mo源含Ni、In、Ti、Rh或Zn。
  9. 根据权利要求7或8所述的发光二极管芯片，其特征在于，所述金属催化剂层的厚度为1-15nm。
  10. 根据权利要求7所述的发光二极管芯片，其特征在于，所述氟代石墨烯保护层的厚度为1-10层单原子氟代石墨烯的厚度。
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