WO2016144434A1 - Réseau compact de portes à champ programmable (fpga) basé sur une mémoire vive résistive (reram) - Google Patents

Réseau compact de portes à champ programmable (fpga) basé sur une mémoire vive résistive (reram) Download PDF

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Publication number
WO2016144434A1
WO2016144434A1 PCT/US2016/015756 US2016015756W WO2016144434A1 WO 2016144434 A1 WO2016144434 A1 WO 2016144434A1 US 2016015756 W US2016015756 W US 2016015756W WO 2016144434 A1 WO2016144434 A1 WO 2016144434A1
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WO
WIPO (PCT)
Prior art keywords
programming
transistors
push
random access
access memory
Prior art date
Application number
PCT/US2016/015756
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English (en)
Inventor
John L. Mccollum
Fethi Dhaoui
Original Assignee
Microsemi SoC Corporation
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Filing date
Publication date
Application filed by Microsemi SoC Corporation filed Critical Microsemi SoC Corporation
Priority to JP2017566605A priority Critical patent/JP2018513569A/ja
Priority to CN201680015229.XA priority patent/CN107431487B/zh
Priority to DE112016001160.1T priority patent/DE112016001160B4/de
Publication of WO2016144434A1 publication Critical patent/WO2016144434A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H10B63/34—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the vertical channel field-effect transistor type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/74—Array wherein each memory cell has more than one access device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/78—Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/82—Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials

Definitions

  • Push-pull resistive random access memory (ReRAM) cells such as the ones disclosed in United States Patent No. 8,415,650, are attractive for use in configuration memory for configurable logic integrated circuits such as field programmable gate arrays (FPGAs).
  • FPGAs field programmable gate arrays
  • This transition region can range from 0.2um to lum or more and can be a significant disadvantage in designing a configurable logic integrated circuit employing ReRAM push-pull configuration memory cell circuits that has a compact efficient layout.
  • An FPGA requires logic, routing switches, and programming transistors to be intermingled. To eliminate the transition region which is required by photolithography processing requirements, all the above listed devices must have the same pitch, including channel length pitch. Normally this requirement is not compatible with devices that are operated at different voltages.
  • the transistor devices used to program them will be subjected to higher drain and gate biases, and will switch at a higher gate bias during programming and operation as compared to other transistors employed in the integrated circuit.
  • An objective of the present invention is to provide ReRAM push-pull configuration memory cell circuits that eliminate this transition region.
  • a push-pull ReRAM cell circuit employs two programming transistors that are cascaded in series and have the same pitch and channel length.
  • a switch transistor used in the push-pull ReRAM cell circuit has the same pitch and channel length as the two programming transistors in order to maintain the same pitch and channel length for both the programming devices and the switch transistors that are used to configure and/or interconnect the logic cells.
  • the switch transistor whose state is configured by the ReRAM will use the same thick dielectric that is used in the programming transistors to mitigate elevated gate stress during programming.
  • Use of a thicker dielectric also allows the gate of the configuration switch to be overdriven at higher Vcc during operation, thus allowing the passage of the full Vcc logic signal.
  • a push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line.
  • a first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line.
  • a first programming transistor has a gate connected to the word line, a drain connected to the output node, and a source.
  • a second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source.
  • the first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.
  • At least one switch transistor has a gate connected to the output node, a drain connected to a first logic net node and a source connected to a second logic net node.
  • the switch transistor has the same pitch, channel length, and gate dielectric thickness as the first and second programming transistors.
  • FIG. 1 is a schematic diagram of a push-pull ReRAM cell in accordance with one aspect of the present invention
  • FIG. 2 is a cross-sectional view of an exemplary layout of the push-pull ReRAM cell of the present invention
  • FIG. 3 is a top view of an exemplary layout of the push-pull ReRAM cell of the present invention.
  • FIG. 1 a schematic diagram shows an illustrative push-pull ReRAM cell circuit 10 in accordance with one aspect of the present invention.
  • a first ReRAM device 12 is coupled in series with a second ReRAM device 14 to form a ReRAM cell 16.
  • a first end of the series connected ReRAM devices 12, 14, at one terminal of ReRAM device 12 is coupled to a first bit line (BL) 18 and a second end of the series connected ReRAM devices 12, 14, at one terminal of ReRAM device 14, is coupled to a second bit line (Bl_bar) 20.
  • the ReRAM cell 16 depicted in FIG.l is a front-to-back ReRAM cell, particularly useful for biasing a switch as shown, but persons of ordinary skill in the art will appreciate that back-to-back ReRAM cells could also be employed in the present invention.
  • ReRAM devices 12 and 14 together comprise a push-pull ReRAM cell 16.
  • the common output node 22 between ReRAM devices 12 and 14 is connected to the gate of one or more switch transistors.
  • FIG. 1 shows the common output node 22 connected to the gates of two switch transistsors 24a and 24b.
  • Switch transistor 24a is shown connected between two logic net nodes 26a and 28a.
  • switch transistor 24b is shown connected between two logic net nodes 26b and 28b.
  • logic net nodes 26a, 26b, 28a, and 28b can represent logic gates or other devices in a programmable integrated circuit that are connected together by the switch transistors 24a and 24b, respectively, and can also represent circuit nets in a single logic device in such an integrated circuit that define the function of the logic device, or can represent a wiring interconnection in a programmable integrated circuit.
  • FIG. 1 shows multiple switch transistors 24a and 24b so that more than one logic circuit net can be activated by a single push-pull ReRAM cell 16
  • a single switch transistor could be connected to the common output node 22.
  • push-pull ReRAM cell 16 is programmed using a pair of n-channel programming transistors 30 and 32 cascaded in series.
  • N-channel programming transistor 30 has its drain connected to the common output node 22 of the push-pull ReRAM cell 16, and its source connected to the drain of the n-channel programming transistor 32.
  • a single n-i- region serves as the source of n-channel programming transistor 30 and the drain of n-channel programming transistor 32.
  • the source of n-channel programming transistor 32 is connected to a word line WLS.
  • both n-channel programming transistors 30 and 32 can be designed having the same pitch and channel length as the n-channel switch transistors 24a and 24b.
  • the same pitch and channel length used for switch transistors 24a and 24b are used for the logic devices in the integrated circuit.
  • n-channel programming transistors 30 and 32 and n-channel switch transistors 24a and 24b are fabricated having the same gate dielectric thicknesses.
  • N-channel programming transistors 30 and 32 have gate dielectric thicknesses selected to withstand the programming and erase potentials that the ReRAM push-pull memory cell will be subjected to during its operation.
  • Most integrated circuits include input/output (I/O) transistors used to interface the integrated circuit with external components. Because these transistors interface with components that often operate at voltages higher than the voltages normally found internally in the integrated circuit, the I/O transistors are usually fabricated having gate dielectric thicknesses larger than other transistors used internally in the integrated circuit. It may therefore be convenient to employ n-channel programming transistors 30 and 32 having the same gate dielectric thicknesses as the I/O transistors.
  • bit line BL 18 is connected to a voltage source Vcc and BL_bar 20 is connected to a potential such as ground.
  • the WLS line can be connected to ground or to a slightly positive potential such as 0.9V to limit leakage in the n-channel programming transistors 30 and 32.
  • Push-pull ReRAM cell 16 is programmed so that only one of the ReRAM devices 12 and 14 is on at any one time, thus either pulling common node 22 up to the voltage on bitline BL 18 or pulling common node 22 down to the voltage on bitline BL_bar 20 (usually ground).
  • Push-pull ReRAM cell 16 is shown in FIG. 1 with ReRAM device 12 turned on and ReRAM device 14 turned off. The common node 22 is thus pulled up to the voltage on bit line BL 18 (Vcc), thus turning on switch transistors 24a and 24b (shown in FIG. 1 as n-channel transistors).
  • FIG. 2 is a cross-sectional view of an exemplary layout 40 of the push-pull ReRAM cell circuit 10 of the present invention.
  • FIG. 3 is a top view of an exemplary layout 40 of the push-pull ReRAM cell circuit 10 of the present invention.
  • Persons of ordinary skill in the art will observe that the layouts shown in FIGS. 2 and 3 are illustrative only and non-limiting.
  • Push-pull ReRAM cell circuit 10 (FIG. 1) is formed in a p-type substrate or well 42 in an integrated circuit.
  • N+ region 44 forms the drain of n-channel programming transistor 30 and n-i- region 46 forms its source, as well as acting as the drain of n-channel programming transistor 32.
  • Polysilicon or metal line 48 forms the gate of n-channel programming transistor 30.
  • N+ region 50 forms the source of n-channel programming transistor 32 and polysilicon or metal line 52 forms its gate.
  • Contacts 54 connect the polysilicon gates 48 and 52 of n-channel programming transistors 30 and 32 to word line 34, shown as being formed from a first metal interconnect layer (Ml).
  • Ml first metal interconnect layer
  • the switch transistor shown in FIG. 3 includes source region 56 and drain region 58, separated by gate 60. It is noted that the cross sectional view of FIG. 2 is partially taken through the source region of one of switch transistors 24a and 24b.
  • the switch transistors may be n-channel or p-channel devices.
  • ReRAM device 12 is formed between metal interconnect layers on the integrated circuit (for example between first and second metal layers Ml and M2). In FIGS. 2 and 3, ReRAM device 12 is shown formed between Ml metal segment 62 and M2 metal segment 64. ReRAM device 12 is formed over metal segment 62 and is connected to M2 metal segment 64 through contact 66. ReRAM device 12 is connected to bitline BL 18 through contact 68.
  • M2 segment 64 Contact to common node 22 is made from M2 segment 64 to an Ml metal segment 70 through contact 72.
  • a contact 74 connects Ml metal segment 70 to polysilicon gate 60 of the switch transistor.
  • ReRAM device 14 is shown formed between Ml metal segment 70 and the M2 metal segment forming second bitline Bl_bar 20.
  • a contact 76 connects Ml ReRAM device 14 to second bitline Bl_bar 20.
  • a contact 78 connects Ml metal segment 70 to the n+ region 44 forming the drain of n-channel programming transistor 30.
  • a metal segment 80 forms the word line WLS and is connected to n+ region 50 forming the source of programming transistor 32 through contact 82.
  • Push-pull ReRAM cell 16 is programmed by turning on the desired one of ReRAM devices 12 and 14 so as to either turn off, or turn on, switch transistors 24a and 24b.
  • both ReRAM devices 12 and 14 are erased.
  • To erase a ReRAM device means to turn it off so that it does not pass current.
  • To erase ReRAM device 12 bitline BL 18 is brought to a high voltage (e.g., 1.8V) and common node 22 is brought to ground.
  • second bit line Bl_bar 20 is also brought to ground so that there is no potential impressed across ReRAM device 14.
  • common node 22 is brought to a high voltage (e.g., 1.8V) and second bit line Bl_bar 20 is brought to ground.
  • bitline BL 18 is also brought to the high voltage so that there is no potential impressed across ReRAM device 12.
  • bitline BL 18 is brought to ground and common node 22 is brought to a high voltage (e.g., 1.8V).
  • second bit line Bl_bar 20 is also brought to the high voltage so that there is no potential impressed across ReRAM device 14.
  • bitline BL 18 is also brought to ground so that there is no potential impressed across ReRAM device 12.
  • two series connected n-channel programming transistors 30 and 32 are coupled between common node 22 and word line WLS.
  • the gates of n-channel transistors 30 and 32 are connected together to word line WL 34.
  • the present disclosure is directed to the application of a ReRAM memory device where the logic is switching at a first voltage and the programming and erasing of the ReRAM cell is performed at a second voltage, persons of ordinary skill in the art will appreciate that it is also applicable to other devices where it is desirable to switch two different voltages in different operating modes.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
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Abstract

L'invention concerne un circuit de cellule de mémoire vive résistive de type push-pull qui comprend un nœud de sortie, une ligne de mot ainsi que des première et seconde lignes de bits. Un premier dispositif de mémoire vive résistive est raccordé entre la première ligne de bits et le nœud de sortie et un second dispositif de mémoire vive résistive est raccordé entre le nœud de sortie et la seconde ligne de bits. Un premier transistor de programmation comporte une grille raccordée à la ligne de mot, un drain raccordé au nœud de sortie, et une source. Un second transistor de programmation comporte une grille raccordée à la ligne de mot, un drain raccordé à la source du premier transistor de programmation et une source. Les premier et second transistors de programmation présentent le même pas, la même longueur de canal et la même épaisseur de diélectrique de grille, l'épaisseur de diélectrique de grille étant choisie pour résister à des potentiels de programmation et d'effacement rencontrés pendant une opération du circuit de cellule de mémoire vive résistive (ReRAM pour Resistive Random Access Memory) de type push-pull.
PCT/US2016/015756 2015-03-12 2016-01-29 Réseau compact de portes à champ programmable (fpga) basé sur une mémoire vive résistive (reram) WO2016144434A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2017566605A JP2018513569A (ja) 2015-03-12 2016-01-29 コンパクトなＲｅＲＡＭベースのＦＰＧＡ
CN201680015229.XA CN107431487B (zh) 2015-03-12 2016-01-29 基于紧凑ReRAM的FPGA
DE112016001160.1T DE112016001160B4 (de) 2015-03-12 2016-01-29 Kompaktes ReRAM-basiertes FPGA

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201562132333P 2015-03-12 2015-03-12
US62/132,333 2015-03-12
US15/010,222 US9444464B1 (en) 2015-03-12 2016-01-29 Compact ReRAM based FPGA
US15/010,222 2016-01-29

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WO2016144434A1 true WO2016144434A1 (fr) 2016-09-15

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US (2) US9444464B1 (fr)
JP (1) JP2018513569A (fr)
DE (1) DE112016001160B4 (fr)
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WO2018063446A1 (fr) * 2016-09-29 2018-04-05 Microsemi Soc Corp. Cellule de mémoire résistive à accès aléatoire avec trois transistors et deux éléments de mémoire résistifs

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TWI765944B (zh) 2016-12-14 2022-06-01 成真股份有限公司 標準大宗商品化現場可編程邏輯閘陣列（ｆｐｇａ）積體電路晶片組成之邏輯驅動器
US10348306B2 (en) 2017-03-09 2019-07-09 University Of Utah Research Foundation Resistive random access memory based multiplexers and field programmable gate arrays
US10447274B2 (en) 2017-07-11 2019-10-15 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
US10957679B2 (en) 2017-08-08 2021-03-23 iCometrue Company Ltd. Logic drive based on standardized commodity programmable logic semiconductor IC chips
US10630296B2 (en) 2017-09-12 2020-04-21 iCometrue Company Ltd. Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
US10608642B2 (en) 2018-02-01 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells
US10623000B2 (en) 2018-02-14 2020-04-14 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10608638B2 (en) 2018-05-24 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10892011B2 (en) 2018-09-11 2021-01-12 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US10937762B2 (en) 2018-10-04 2021-03-02 iCometrue Company Ltd. Logic drive based on multichip package using interconnection bridge
US11616046B2 (en) 2018-11-02 2023-03-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
US10985154B2 (en) 2019-07-02 2021-04-20 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits
US11887930B2 (en) 2019-08-05 2024-01-30 iCometrue Company Ltd. Vertical interconnect elevator based on through silicon vias
US11637056B2 (en) 2019-09-20 2023-04-25 iCometrue Company Ltd. 3D chip package based on through-silicon-via interconnection elevator
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DE112016001160T5 (de) 2017-11-30
JP2018513569A (ja) 2018-05-24
US9444464B1 (en) 2016-09-13
US9520448B1 (en) 2016-12-13
DE112016001160B4 (de) 2023-12-28
US20160269031A1 (en) 2016-09-15
US20160351626A1 (en) 2016-12-01

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