WO2016138806A1 - 一种采用电流dac消除可变增益放大电路直流失调的方法 - Google Patents

一种采用电流dac消除可变增益放大电路直流失调的方法 Download PDF

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WO2016138806A1
WO2016138806A1 PCT/CN2016/072560 CN2016072560W WO2016138806A1 WO 2016138806 A1 WO2016138806 A1 WO 2016138806A1 CN 2016072560 W CN2016072560 W CN 2016072560W WO 2016138806 A1 WO2016138806 A1 WO 2016138806A1
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current
offset voltage
variable gain
analog
bit
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吴建辉
姚红燕
郭仲亚
陈超
黄成�
李红
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Southeast University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters

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  • the invention relates to a method for eliminating DC offset of a variable gain amplifier circuit by using a current DAC, and is an important technology applied in an intermediate frequency amplifier of a wireless transceiver, and relates to an intermediate frequency amplification technology and a digital baseband technology in the field of wireless communication.
  • CMOS processes noise and offset are major factors limiting the accuracy of analog integrated circuits.
  • the offset is the dominant factor limiting accuracy.
  • the offset is caused by a mismatch between the same placed transistors.
  • the offset voltage is caused by the mismatch of the transistor.
  • the gain of the amplifier is large, the dc offset voltage equivalent to the input of the amplifier is amplified, so that the high gain op amp is compared. Large errors, even when the offset is large, will be ineffective, causing blockage of the signal path.
  • the general circuit's loss of input input offset voltage is defined as the difference between the input voltages at both ends when the output voltage is zero.
  • the offset voltage In a double-ended amplifier, the offset voltage is often in the millivolt range. In a CMOS process, the offset voltage may increase by at least 10 times. Variable gain amplifiers usually have higher gains. Therefore, how to effectively eliminate the offset voltage of the variable gain amplifier is an important issue that must be considered in circuit design.
  • DC offset cancellation there are many methods for DC offset cancellation, such as feedback and feedforward, switched capacitors, and digital correction.
  • the performance of the DC offset cancellation technique can be evaluated from the following indicators: the settling time of the DC cancellation, that is, the time required for the DC component of the output signal to stabilize to a certain accuracy; the attenuation degree of the DC offset, that is, the DC component of the output signal and the input signal The ratio of the DC component; circuit power consumption, area, stability, etc.
  • the simplest method of DC offset cancellation is AC coupling: placing a large capacitor between two stages of circuits to achieve DC-blocking communication. This method is relatively simple to implement, but requires a large capacitance when the circuit operates in the low frequency state to achieve a lower attenuation of the AC signal.
  • a large DC blocking capacitor can occupy a large area if implemented in the chip.
  • MOS transistors are used in some circuits to achieve capacitance and resistance.
  • Another method is to use the feedback disappearance adjustment.
  • the basic principle is to connect a low-pass negative feedback loop in parallel to the forward amplification path to achieve the high-pass characteristic of the closed-loop transfer function.
  • the traditional analog DC offset cancellation technology requires large capacitance, and has a very slow settling time.
  • the feedback method is also easy to cause the stability of the circuit.
  • digitally assisted DC offset cancellation techniques are mainly used.
  • the basic process of the digitally assisted calibration method is to first short the differential input of the amplifier, detect the output offset voltage of the variable gain amplifier, and then calculate the offset calibration value through a successive comparison algorithm, and finally pass a calibration DAC. Eliminate the imbalance.
  • the dc offset cancellation circuit of this method occupies a small chip area and the offset of each gain stage can be calibrated.
  • the comparison output offset voltage is usually realized by a comparator, and the requirements of the comparator are relatively high, and a comparator with a small offset is required to obtain an accurate calibration.
  • the present invention provides a method for eliminating a DC offset of a variable gain amplifier circuit by using a current DAC, which can realize digital automatic DC offset calibration in a short time;
  • the invention adopts an improved step-by-step calibration algorithm to control the calibration DAC to eliminate the equivalent input offset voltage of the variable gain amplifier; the method of the invention can adjust the offset to a small order of magnitude, the calibration offset voltage range is large, the calibration accuracy is high, and the calibration is performed. high speed.
  • the obtained digital control words are respectively connected to control each current DAC; the working process is: shorting the differential input end of the variable gain amplifying circuit, and the output signal of the variable gain amplifying circuit is a DC offset voltage, using an analog to digital converter The DC offset voltage is sampled and detected, and the analog-to-digital conversion is performed to obtain the digital value of the DC offset voltage.
  • the improved bit-by-bit comparison algorithm is used to process the digital value of the DC offset voltage to obtain the control word of the control current DAC, and finally the current DAC pair is used.
  • variable gain amplifying circuit can also enter the normal amplification mode.
  • the current DAC has a total of (N+1) current branches, wherein the current of the second current branch to the (N+1)th current branch is increased by binary weighting, respectively, I 0 , 2 ⁇ I 0 , ..., 2 n ⁇ I 0 , ..., 2 (N-1) ⁇ I 0 , the current of the first current branch is I 0 ; the current output port of the current DAC has two, respectively connected to the corresponding variable gain amplifier The two ports of the differential input terminal, the current signals output by the two current output ports of the current DAC are I outn and I outp respectively ; the second current branch to the (N+1)th current branch are provided with one Switch, each switch consists of two parallel NMOS transistors.
  • control signals of the two NMOS transistors are B[n] and pass through the inverter. All current branches using the control signal B[n] are connected to the first current DC and output I outn , using an inverter All current branches are connected and output I outp , ie:
  • I outn 2 N I 0 -(B[0]I 0 +2B[1]I 0 +...+2 (N-1) B[N-1]I 0 )
  • B[0:N-1] is recorded as the control word of the current DAC; the calibration current of the current DAC flowing into the variable gain amplifier is I outn -I outp , and the calibration current varies by (-2 N I 0 , 2 N I 0 ), the accuracy of the change is I 0 .
  • the improved bitwise comparison algorithm is: adjusting the control word of the current DAC bit by bit according to the currently detected DC offset voltage value of the analog to digital converter and the DC offset voltage value of the previous state: when the currently detected DC offset voltage is not present
  • the first-stage variable gain amplifier is first adjusted. After the adjustment is completed, the second-stage variable gain amplifier is adjusted.
  • the third stage variable gain amplifier when the currently detected dc offset voltage is within the detection range of the analog to digital converter, the current detected dc offset voltage value and the current variable gain amplifier circuit gain value are directly converted
  • the control word of the current DAC realizes rapid adjustment of the DC offset voltage;
  • the calibration current of each variable gain amplifier is 0; according to the current detection
  • the dc offset voltage value and the dc offset voltage value of the previous state if the current dc offset voltage value and the previous state dc offset voltage value are within the detection range of the analog to digital converter, the dc offset voltage cancellation calibration stops, the current DAC The control word remains unchanged.
  • variable gain amplifier circuit can enter the normal amplification mode; if the current DC offset voltage value is lower than the detection range of the analog-to-digital converter, the DC offset voltage value of the previous state is higher than the modulus.
  • the detection range of the converter the current control bit of the current DAC becomes high; if the current dc offset voltage value is higher than the detection range of the analog-to-digital converter, the dc offset voltage value of the previous state is lower than that of the analog-to-digital converter Measurement range, the control current to a low bit DAC current; DC offset voltage when the current value is lower than the detection range of the ADC, DC offset voltage on a state below the detection range of the ADC, electrical The current control bit of the stream DAC goes high, and the previous control bit goes high; if the current DC offset voltage value is higher than the detection range of the analog-to-digital converter, the value of the DC offset voltage of the previous state is higher than that of the analog-to-digital converter.
  • the current control bit of the current DAC becomes low, and the last control bit becomes low; comparing the current state with the previous state by the above method, the method of gradually changing one bit or changing two bit control bits can effectively solve the DC Misalignment and redundancy issues that occur during offset voltage calibration allow the dc offset voltage to be accurately calibrated.
  • the present invention provides a method for eliminating DC offset of a variable gain amplifier circuit by using a current DAC, and improves a bit-by-bit calibration method in a conventional digital-assisted DC offset cancellation technique, and directly detects a DC offset voltage by using an analog-to-digital converter.
  • the speed of the calibration is improved; and the invention adopts the digital-assisted DC offset cancellation method, which can effectively reduce the area of the layout occupied by the chip; the DC offset cancellation method of the invention has accuracy and rapidity.
  • FIG. 1 is a structural block diagram and a circuit DAC circuit diagram of a variable gain amplifying circuit using the method of the present invention
  • Figure 2 is a flow chart for the bitwise comparison adjustment from the high to the low of the current DAC
  • 3 is a process waveform of DC offset voltage cancellation in different gain modes using a variable gain amplifying circuit of the method of the present invention.
  • the invention provides a method for eliminating DC offset of a variable gain amplifier circuit by using a current DAC, and adopts a digital assisted DC offset voltage cancellation technique.
  • the digitally assisted DC offset voltage cancellation technique uses a DC offset voltage output from a variable gain amplifier circuit, which is calibrated and eliminated by a current DAC at the input of the variable gain amplifier, and finally causes a DC offset voltage of the output signal of the variable gain amplifier circuit. In the acceptable range even reaches zero.
  • a bit-by-bit comparison method is needed in the process of eliminating the DC offset.
  • the invention improves the traditional bit-to-bit approximation algorithm for the digital DC offset cancellation technology, which can effectively prevent the loss and redundancy of the bits in the DC offset cancellation process, so that the DC offset voltage can be effectively eliminated.
  • variable gain amplifier circuit has three amplification stages, that is, three variable gain amplifiers are connected in series to form a variable gain amplification.
  • each variable gain amplifier is connected to a current DAC for dc offset adjustment (ie, a calibration DAC), the output of the variable gain amplifier circuit is connected to the input of the analog-to-digital converter, and the output terminal of the analog-to-digital converter is connected
  • the DC offset cancellation module performs digital processing, and the obtained digital control words are respectively connected to the respective current DACs; the working process is: shorting the differential input end of the variable gain amplifier, and the output signal of the variable gain amplifier circuit is the DC offset voltage ,
  • the analog-to-digital converter is used to sample and detect the DC offset voltage and obtain the digital value of the DC offset voltage.
  • the improved bit-by-bit comparison algorithm is used to process the digital value of the DC offset voltage to obtain the control word of the control current DAC.
  • the input of the variable gain amplifier is feedback-calibrated by the current DAC to eliminate the DC offset voltage; after the DC offset voltage is removed, the differential input of the variable gain amplifier circuit is disconnected, and the AC signal can be amplified.
  • the variable gain amplifier circuit can also enter the normal amplification mode.
  • the current DAC has a total of (N+1) current branches, wherein the current of the second current branch to the (N+1)th current branch is increased by binary weighting, respectively, I 0 , 2 ⁇ I 0 , ..., 2 n ⁇ I 0 , ..., 2 (N-1) ⁇ I 0 , the current of the first current branch is I 0 ; the current output port of the current DAC has two, respectively connected to the corresponding variable gain amplifier The two ports of the differential input terminal, the current signals output by the two current output ports of the current DAC are I outn and I outp respectively ; the second current branch to the (N+1)th current branch are provided with one Switch, each switch consists of two parallel NMOS transistors.
  • control signals of the two NMOS transistors are B[n] and pass through the inverter. All current branches using the control signal B[n] are connected to the first current DC and output I outn , using an inverter All current branches are connected and output I outp , ie:
  • I outn 2 N I 0 -(B[0]I 0 +2B[1]I 0 +...+2 (N-1) B[N-1]I 0 )
  • B[0:N-1] is recorded as the control word of the current DAC; the calibration current of the current DAC flowing into the variable gain amplifier is I outn -I outp , and the calibration current varies by (-2 N I 0 , 2 N I 0 ), the accuracy of the change is I 0 .
  • the improved bitwise comparison algorithm is: adjusting the control word of the current DAC bit by bit according to the currently detected DC offset voltage value of the analog to digital converter and the DC offset voltage value of the previous state: when the currently detected DC offset voltage is not present
  • the first-stage variable gain amplifier is first adjusted. After the adjustment is completed, the second-stage variable gain amplifier is adjusted.
  • the third stage variable gain amplifier when the currently detected dc offset voltage is within the detection range of the analog to digital converter, the current detected dc offset voltage value and the current variable gain amplifier circuit gain value are directly converted
  • the control word of the current DAC enables fast adjustment of the dc offset voltage.
  • the dc offset voltage value of the previous state is the dc offset of the previous state changed by the current DAC control word Voltage value;
  • the calibration current of each variable gain amplifier is 0; according to the currently detected DC offset voltage value and the DC offset voltage value of the previous state: if the current DC offset voltage value and The dc offset voltage value of one state is within the detection range of the analog-to-digital converter, the dc offset voltage cancellation calibration stops, and the control word of the current DAC remains unchanged.
  • the variable gain amplifier circuit can enter the normal amplification mode; The dc offset voltage value is lower than the detection range of the analog-to-digital converter.
  • the dc offset voltage value of the previous state is higher than the detection range of the analog-to-digital converter, and the current control bit of the current DAC becomes high; if the current dc offset voltage value Above the detection range of the analog-to-digital converter, the dc offset voltage value of the previous state is lower than the detection range of the analog-to-digital converter, and the current control bit of the current DAC becomes low; if the current dc offset voltage value is lower than the analog to digital converter
  • the detection range of the device the dc offset voltage value of the previous state is lower than the detection range of the analog-to-digital converter, the current control bit of the current DAC becomes high, the previous control bit becomes high; if the current dc offset voltage value is higher than The detection range of the analog-to-digital converter, the dc offset voltage value of the previous state is higher than the detection range of the analog-to-digital converter, the current control bit of the current DAC becomes low, and the previous control bit becomes low; the current state is
  • FIG. 3 is a process waveform of a DC offset voltage cancellation in a variable gain mode using the variable gain amplifier circuit of the present invention, and the circuit is gradually calibrated according to the value of the DC offset voltage, and the variable gain can be finally obtained by stepwise calibration from the figure.
  • the dc offset of the amplifying circuit is within an acceptable range, and the dc offset signal at both ends of the differential result can be calibrated to less than 15 mV.
  • the gain mode is switched, the dc offset is readjusted. Since the dc offset is adjusted according to the sampled value of the analog-to-digital converter, the calibration speed of the dc offset is related to the sampling rate of the analog-to-digital converter, where the sampling rate is 16 MHz. It can be seen from the simulation results that the calibration time of the DC offset can be controlled within 10us.
  • the invention adopts the technology that the current DAC eliminates the DC offset of the variable gain amplifier, and the traditional digital auxiliary DC offset cancellation technology is improved in that the error is relatively inaccurate, and the response is fast and accurate.
  • the binary-weighted current DAC features a large calibration range and high accuracy.

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Abstract

一种采用电流DAC消除可变增益放大器电路直流失调的方法，将可变增益放大器的差分输入端短接，可变增益放大电路的输出信号即为直流失调电压，使用模数转换器对直流失调电压进行采样检测和模数转换，得到直流失调电压的数字值，采用改进的逐位比较算法对直流失调电压的数字值进行处理，得到控制电流DAC的控制字，最后通过电流DAC对对应可变增益放大器的输入端进行反馈校准，以消除直流失调电压。该方法改进了传统的数字辅助直流失调消除技术中的逐位校准的方式，并采用模数转换器直接检测直流失调电压，提高了校准的速度。

Description

一种采用电流DAC消除可变增益放大电路直流失调的方法 技术领域
本发明涉及一种采用电流DAC消除可变增益放大电路直流失调的方法，是应用在无线收发机的中频放大器中的重要技术，涉及无线通信领域的中频放大技术和数字基带技术。
背景技术
在CMOS工艺中，噪声和失调是限制模拟集成电路精度的主要因素。事实上随着沟道长度变小失调会越加严重，因此失调是成为限制精度的主导因素。失调是由相同放置的晶体管间的不匹配所造成的。尤其在差分可变增益放大器的设计过程中，由于晶体管的不匹配造成失调电压，当放大器的增益较大时，等效在放大器输入的直流失调电压会被放大，从而使得高增益运放产生比较大的误差，甚至当失调较大的时候会湮没有效信号，造成信号通路的阻塞。一般电路的失调用输入失调电压来定义：使输出电压为零时的两端输入电压之差。在一个双端放大器中，失调电压常常是毫伏级的，在CMOS工艺中，失调电压有可能会增大到至少10倍以上。而可变增益放大器通常具有较高的增益，因此，如何有效的消除可变增益放大器的失调电压是在电路设计时必须考虑的一个重要问题。
直流失调消除的方法比较多，比如反馈和前馈、开关电容、数字校正等。评价直流失调消除技术的性能可以从如下几个指标进行：直流消除的建立时间，即输出信号直流分量稳定到一定的精度所需的时间；直流失调的衰减程度，即输出信号直流分量与输入信号直流分量的比值；电路功耗、面积、稳定性等。直流失调消除最简单的方法是交流耦合：将大电容放在两级电路之间，实现隔直流通交流的目的。这种方法实现相对简单，但是当电路工作在低频状态下需要很大的电容才能实现较低的交流信号的衰减，很大的隔直电容如果在片内实现会占用很大的面积。在一些采用具有高通特性的电路取代直接的交流耦合，另外考虑到大电阻和大电容占用的面积较大，在一些电路中采用MOS管来实现电容和电阻。另外的方法是采用反馈消失调，基本原理是在在正向放大通路上并联一个低通的负反馈回路，从而实现闭环传递函数的高通特性。传统的模拟直流失调消除技术都需要用到大电容，并且具有很慢的建立时间，另外采用反馈的方式也易引起电路的稳定性问题。
因此在现在的一些电路设计中，主要采用数字辅助的直流失调消除的技术。数字辅助的校准方法的基本过程是：首先将放大器的差分输入短接，检测可变增益放大器的输出失调电压，然后通过一个逐次比较的算法，计算失调校准值，最后通过一个校准DAC 将失调消除。这种方法的直流失调消除电路占用很小的芯片面积并且每个增益级的失调都能得到校准。其中比较输出失调电压通常是采用比较器实现，对比较器的要求比较高，需要自身失调很小的比较器才能得到准确的校准。在传统的数字辅助直流失调校准算法中，由于采用的校准DAC是二进制DAC，若有一位DAC的校准发生错误，则后面的校准难以将失调重新校准过来。在一些文献中，采用了亚二进制的DAC，即DAC每一位的加权小于二。这样可以有效防止校准出错，但是这样相同位数的DAC校准的失调电压较小。
发明内容
发明目的：为了消除直流失调电压对可变增益放大器性能的影响，本发明提供一种采用电流DAC消除可变增益放大电路直流失调的方法，能够在较短的时间内实现数字自动直流失调校准；本发明采用改进的逐步校准算法控制校准DAC，以消除可变增益放大器的等效输入失调电压；本发明方法能够将失调校准到很小的数量级，校准失调电压范围大，校准准确性高，校准速度快。
技术方案：为实现上述目的，本发明采用的技术方案为：
一种采用电流DAC消除可变增益放大电路直流失调的方法，该可变增益放大电路共有三个放大级，即由三个可变增益放大器串联构成可变增益放大电路，每个可变增益放大器均连接一个直流失调调节用的电流DAC(即校准DAC)，可变增益放大电路的输出端接入模数转换器的输入端，模数转换器的输出端接入直流失调消除模块进行数字处理，得到的数字控制字分别连接控制各个电流DAC；工作过程为：将可变增益放大电路的差分输入端短接，可变增益放大电路的输出信号即为直流失调电压，使用模数转换器对直流失调电压进行采样检测和模数转换，得到直流失调电压的数字值，采用改进的逐位比较算法对直流失调电压的数字值进行处理，得到控制电流DAC的控制字，最后通过电流DAC对对应可变增益放大器的输入端进行反馈校准，以消除直流失调电压；在直流失调电压消除后，将可变增益放大电路的差分输入端断开，即可进行交流信号的放大，也即可变增益放大电路进入正常的放大模式。
所述电流DAC共有(N+1)个电流支路，其中第二个电流支路到第(N+1)个电流支路的电流按二进制加权增加，分别为I0、2×I0、…、2n×I0、…、2(N-1)×I0，第一个电流支路的电流为I0；电流DAC的电流输出端口有两个，分别连接到对应可变增益放大器的差分输入端的两个端口，记电流DAC的两个电流输出端口输出的电流信号分别为 Ioutn和Ioutp；第二个电流支路到第(N+1)个电流支路上均设置有一个开关，每个开关均由两个并联的NMOS管构成，对于第(n+1)个电流支路，两个NMOS管的控制信号为B[n]和经过反相器的
Figure PCTCN2016072560-appb-000001
采用控制信号B[n]的所有电流支路和第一个电流直流相连后输出Ioutn，采用经过反相器的
Figure PCTCN2016072560-appb-000002
的所有电流支路相连后输出Ioutp，即：
Ioutn＝2NI0-(B[0]I0+2B[1]I0+…+2(N-1)B[N-1]I0)
Figure PCTCN2016072560-appb-000003
其中，B[0:N-1]记为电流DAC的控制字；电流DAC流入可变增益放大器的校准电流为Ioutn-Ioutp，校准电流的变化范围为(-2NI0,2NI0)，变化的精度为I0。
所述改进的逐位比较算法为：根据模数转换器的当前检测的直流失调电压值和上一状态的直流失调电压值来逐位调整电流DAC的控制字：当当前检测的直流失调电压不在模数转换器的检测范围内时，从电流DAC的高位到低位逐位比较调整，首先调整第一级的可变增益放大器，调整完成后调整第二级的可变增益放大器，调整完成后调整第三级的可变增益放大器；当当前检测的直流失调电压在模数转换器的检测范围内时，通过当前检测的直流失调电压值和当前可变增益放大电路的增益值进行换算，直接调节电流DAC的控制字，实现直流失调电压的快速调整；
其中，上一状态的直流失调电压值即电流DAC控制字改变的前一状态的直流失调电压值；从电流DAC的高位到低位逐位比较调整的基本过程是：电流DAC的初始控制字为B[N-1:0]＝<100…0>，即最高位为1，其余的(N-1)位均为低位，此时各级可变增益放大器的校准电流为0；根据当前检测的直流失调电压值和上一状态的直流失调电压值：若当前的直流失调电压值和上一状态的直流失调电压值均在模数转换器的检测范围内，直流失调电压消除校准停止，电流DAC的控制字保持不变，此时可变增益放大电路可以进入正常的放大模式；若当前的直流失调电压值低于模数转换器的检测范围，上一状态的直流失调电压值高于模数转换器的检测范围，电流DAC的当前控制位变为高；若当前的直流失调电压值高于模数转换器的检测范围，上一状态的直流失调电压值低于模数转换器的检测范围，电流DAC的当前控制位变为低；若当前的直流失调电压值低于模数转换器的检测范围，上一状态的直流失调电压值低于模数转换器的检测范围，电 流DAC的当前控制位变为高，上一控制位变为高；若当前的直流失调电压值高于模数转换器的检测范围，上一状态的直流失调电压值高于模数转换器的检测范围，电流DAC的当前控制位变为低，上一控制位变为低；通过上述方式比较当前状态和上一状态，采用逐步改变一位或改变两位控制位的方式，能够有效解决直流失调电压校准过程中发生的错位和冗余问题，使得直流失调电压得到准确的校准。
有益效果：本发明提供的采用电流DAC消除可变增益放大电路直流失调的方法，改进了传统的数字辅助直流失调消除技术中的逐位校准的方式，并采用模数转换器直接检测直流失调电压，提高了校准的速度；并且本发明采用采用的数字辅助的直流失调消除的方式，可以有效减小芯片占用的版图的面积；本发明的直流失调消除方法，具有准确性和快速性。
附图说明
图1为采用本发明方法的可变增益放大电路的结构框图和电路DAC电路图；
图2为从电流DAC的高位到低位逐位比较调整的流程图；
图3为采用本发明方法的可变增益放大电路在不同增益模式下的直流失调电压消除的过程波形。
具体实施方式
下面结合附图对本发明作更进一步的说明。
本发明提供的采用电流DAC消除可变增益放大器电路直流失调的方法，采用了数字辅助的直流失调电压消除技术。该数字辅助的直流失调电压消除技术采用可变增益放大电路输出的直流失调电压，通过电流DAC在可变增益放大器的输入端进行校准消除，最终使得可变增益放大电路的输出信号的直流失调电压在能接受的范围甚至是达到零。在校准过程中，若经过放大器后的直流失调过大，会超过模数转换器的检测范围，因此需要在直流失调消除的过程中采用逐位比较的方法。本发明改进了传统的数字直流失调消除技术逐位逼近算法，能有效防止直流失调消除过程中的位的丢失和冗余，使得直流失调电压能够得到有效的消除。
一种采用电流DAC消除可变增益放大器电路直流失调的方法，如图1和图2所示该可变增益放大电路共有三个放大级，即由三个可变增益放大器串联构成可变增益放大电路，每个可变增益放大器均连接一个直流失调调节用的电流DAC(即校准DAC)，可变增益放大电路的输出端接入模数转换器的输入端，模数转换器的输出端接入直流失调消除模块进行数字处理，得到的数字控制字分别连接到各个电流DAC；工作过程为：将可变增益放大器的差分输入端短接，可变增益放大电路的输出信号即为直流失调电压， 使用模数转换器对直流失调电压进行采样检测和模数转换，得到直流失调电压的数字值，采用改进的逐位比较算法对直流失调电压的数字值进行处理，得到控制电流DAC的控制字，最后通过电流DAC对对应可变增益放大器的输入端进行反馈校准，以消除直流失调电压；在直流失调电压消除后，将可变增益放大电路的差分输入端断开，即可进行交流信号的放大，也即可变增益放大电路进入正常的放大模式。
所述电流DAC共有(N+1)个电流支路，其中第二个电流支路到第(N+1)个电流支路的电流按二进制加权增加，分别为I0、2×I0、…、2n×I0、…、2(N-1)×I0，第一个电流支路的电流为I0；电流DAC的电流输出端口有两个，分别连接到对应可变增益放大器的差分输入端的两个端口，记电流DAC的两个电流输出端口输出的电流信号分别为Ioutn和Ioutp；第二个电流支路到第(N+1)个电流支路上均设置有一个开关，每个开关均由两个并联的NMOS管构成，对于第(n+1)个电流支路，两个NMOS管的控制信号为B[n]和经过反相器的
Figure PCTCN2016072560-appb-000004
采用控制信号B[n]的所有电流支路和第一个电流直流相连后输出Ioutn，采用经过反相器的
Figure PCTCN2016072560-appb-000005
的所有电流支路相连后输出Ioutp，即：
Ioutn＝2NI0-(B[0]I0+2B[1]I0+…+2(N-1)B[N-1]I0)
Figure PCTCN2016072560-appb-000006
其中，B[0:N-1]记为电流DAC的控制字；电流DAC流入可变增益放大器的校准电流为Ioutn-Ioutp，校准电流的变化范围为(-2NI0,2NI0)，变化的精度为I0。
所述改进的逐位比较算法为：根据模数转换器的当前检测的直流失调电压值和上一状态的直流失调电压值来逐位调整电流DAC的控制字：当当前检测的直流失调电压不在模数转换器的检测范围内时，从电流DAC的高位到低位逐位比较调整，首先调整第一级的可变增益放大器，调整完成后调整第二级的可变增益放大器，调整完成后调整第三级的可变增益放大器；当当前检测的直流失调电压在模数转换器的检测范围内时，通过当前检测的直流失调电压值和当前可变增益放大电路的增益值进行换算，直接调节电流DAC的控制字，实现直流失调电压的快速调整。
其中，上一状态的直流失调电压值即电流DAC控制字改变的前一状态的直流失调 电压值；从电流DAC的高位到低位逐位比较调整的基本过程是：电流DAC的初始控制字为B[N-1:0]＝<100…0>，即最高位为1，其余的(N-1)位均为低位，此时各级可变增益放大器的校准电流为0；根据当前检测的直流失调电压值和上一状态的直流失调电压值：若当前的直流失调电压值和上一状态的直流失调电压值均在模数转换器的检测范围内，直流失调电压消除校准停止，电流DAC的控制字保持不变，此时可变增益放大电路可以进入正常的放大模式；若当前的直流失调电压值低于模数转换器的检测范围，上一状态的直流失调电压值高于模数转换器的检测范围，电流DAC的当前控制位变为高；若当前的直流失调电压值高于模数转换器的检测范围，上一状态的直流失调电压值低于模数转换器的检测范围，电流DAC的当前控制位变为低；若当前的直流失调电压值低于模数转换器的检测范围，上一状态的直流失调电压值低于模数转换器的检测范围，电流DAC的当前控制位变为高，上一控制位变为高；若当前的直流失调电压值高于模数转换器的检测范围，上一状态的直流失调电压值高于模数转换器的检测范围，电流DAC的当前控制位变为低，上一控制位变为低；通过上述方式比较当前状态和上一状态，采用逐步改变一位或改变两位控制位的方式，能够有效解决直流失调电压校准过程中发生的错位和冗余问题，使得直流失调电压得到准确的校准。
如图3为采用本发明方法的可变增益放大电路在不同增益模式下的直流失调电压消除的过程波形，电路根据直流失调电压的值逐步校准，从图中通过逐步校准最终可以使得可变增益放大电路的直流失调在能接受的范围内，仿真的结果差分两端的直流失调信号最终能校准到小于15mV。当增益模式发生切换的时候，直流失调进行重新调整。由于直流失调是根据模数转换器的采样值进行调节，因此直流失调的校准速度与模数转换器的采样率有关，这里采样率为16MHz。从仿真结果可以看出直流失调的校准时间可以控制在10us之内。
本发明的采用电流DAC消除可变增益放大器直流失调的技术，改进了传统数字辅助直流失调消除技术易错误较不准的缺点，具有响应快速、准确的特点。采用二进制加权的电流DAC，具有校准范围大，精度高的特点。
以上所述仅是本发明的优选实施方式，应当指出：对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (3)

  1. 一种采用电流DAC消除可变增益放大电路直流失调的方法，其特征在于：该可变增益放大电路共有三个放大级，即由三个可变增益放大器串联构成可变增益放大电路，每个可变增益放大器均连接一个直流失调调节用的电流DAC，可变增益放大电路的输出端接入模数转换器的输入端，模数转换器的输出端接入直流失调消除模块进行数字处理，得到的数字控制字分别连接控制各个电流DAC；工作过程为：将可变增益放大电路的差分输入端短接，可变增益放大电路的输出信号即为直流失调电压，使用模数转换器对直流失调电压进行采样检测和模数转换，得到直流失调电压的数字值，采用改进的逐位比较算法对直流失调电压的数字值进行处理，得到控制电流DAC的控制字，最后通过电流DAC对对应可变增益放大器的输入端进行反馈校准，以消除直流失调电压；在直流失调电压消除后，将可变增益放大电路的差分输入端断开，即可进行交流信号的放大，也即可变增益放大电路进入正常的放大模式。
  2. 根据权利要求1所述的采用电流DAC消除可变增益放大电路直流失调的方法，其特征在于：所述电流DAC共有(N+1)个电流支路，其中第二个电流支路到第(N+1)个电流支路的电流按二进制加权增加，分别为I0、2×I0、…、2n×I0、…、2(N-1)×I0，第一个电流支路的电流为I0；电流DAC的电流输出端口有两个，分别连接到对应可变增益放大器的差分输入端的两个端口，记电流DAC的两个电流输出端口输出的电流信号分别为Ioutn和Ioutp；第二个电流支路到第(N+1)个电流支路上均设置有一个开关，每个开关均由两个并联的NMOS管构成，对于第(n+1)个电流支路，两个NMOS管的控制信号为B[n]和经过反相器的
    Figure PCTCN2016072560-appb-100001
    采用控制信号B[n]的所有电流支路和第一个电流直流相连后输出Ioutn，采用经过反相器的
    Figure PCTCN2016072560-appb-100002
    的所有电流支路相连后输出Ioutp，即：
    Ioutn＝2NI0-(B[0]I0+2B[1]I0+…+2(N-1)B[N-1]I0)
    Figure PCTCN2016072560-appb-100003
    其中，B[0:N-1]记为电流DAC的控制字；电流DAC流入可变增益放大器的校准电流为Ioutn-Ioutp，校准电流的变化范围为(-2NI0,2NI0)，变化的精度为I0。
  3. 根据权利要求2所述的采用电流DAC消除可变增益放大电路直流失调的方法， 其特征在于：所述改进的逐位比较算法为：根据模数转换器的当前检测的直流失调电压值和上一状态的直流失调电压值来逐位调整电流DAC的控制字：当当前检测的直流失调电压不在模数转换器的检测范围内时，从电流DAC的高位到低位逐位比较调整，首先调整第一级的可变增益放大器，调整完成后调整第二级的可变增益放大器，调整完成后调整第三级的可变增益放大器；当当前检测的直流失调电压在模数转换器的检测范围内时，通过当前检测的直流失调电压值和当前可变增益放大电路的增益值进行换算，直接调节电流DAC的控制字，实现直流失调电压的快速调整；
    其中，上一状态的直流失调电压值即电流DAC控制字改变的前一状态的直流失调电压值；从电流DAC的高位到低位逐位比较调整的基本过程是：电流DAC的初始控制字为B[N-1:0]＝<100…0>，即最高位为1，其余的(N-1)位均为低位，此时各级可变增益放大器的校准电流为0；根据当前检测的直流失调电压值和上一状态的直流失调电压值：若当前的直流失调电压值和上一状态的直流失调电压值均在模数转换器的检测范围内，直流失调电压消除校准停止，电流DAC的控制字保持不变，此时可变增益放大电路可以进入正常的放大模式；若当前的直流失调电压值低于模数转换器的检测范围，上一状态的直流失调电压值高于模数转换器的检测范围，电流DAC的当前控制位变为高；若当前的直流失调电压值高于模数转换器的检测范围，上一状态的直流失调电压值低于模数转换器的检测范围，电流DAC的当前控制位变为低；若当前的直流失调电压值低于模数转换器的检测范围，上一状态的直流失调电压值低于模数转换器的检测范围，电流DAC的当前控制位变为高，上一控制位变为高；若当前的直流失调电压值高于模数转换器的检测范围，上一状态的直流失调电压值高于模数转换器的检测范围，电流DAC的当前控制位变为低，上一控制位变为低；通过上述方式比较当前状态和上一状态，采用逐步改变一位或改变两位控制位的方式，能够有效解决直流失调电压校准过程中发生的错位和冗余问题，使得直流失调电压得到准确的校准。
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