WO2016119471A1 - 上电复位电路 - Google Patents

上电复位电路 Download PDF

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Publication number
WO2016119471A1
WO2016119471A1 PCT/CN2015/089877 CN2015089877W WO2016119471A1 WO 2016119471 A1 WO2016119471 A1 WO 2016119471A1 CN 2015089877 W CN2015089877 W CN 2015089877W WO 2016119471 A1 WO2016119471 A1 WO 2016119471A1
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Prior art keywords
field effect
effect transistor
resistor
reference current
gate
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PCT/CN2015/089877
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English (en)
French (fr)
Inventor
高云
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无锡华润上华半导体有限公司
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Priority to US15/731,768 priority Critical patent/US10340912B2/en
Publication of WO2016119471A1 publication Critical patent/WO2016119471A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Definitions

  • the present invention relates to the field of integrated circuit control, and more particularly to a power-on reset circuit.
  • the current chip basically has a built-in power-on reset circuit.
  • power-on reset circuits There are many types of power-on reset circuits. The most widely used ones are POR (Power On) using resistors, capacitors, Schmitt triggers or inverters. Reset, power-on reset) signal.
  • the conventional power-on reset circuit is used for level inversion using an inverter
  • the anti-interference ability of the power supply disturbance is relatively poor, that is, when the power supply is dithered near the inverter flip level, the inverter will not stop.
  • the flipping produces a series of unstable POR signals, a phenomenon known as false triggering that prevents the chip from functioning properly.
  • a circuit with a Schmitt trigger for level inversion has certain anti-interference ability, but the upper and lower threshold levels of the Schmitt trigger are difficult to set accurately, and the threshold level varies with the fluctuation of the power supply voltage. Therefore, it is difficult to precisely modulate the threshold level of the power-on reset, and eventually the resulting POR signal is unstable.
  • a power-on reset circuit includes a current bias circuit, a threshold level control circuit, and a capacitor charge and discharge circuit, wherein the current bias circuit is configured to provide a non-power supply for the threshold level control circuit and the capacitor charge and discharge circuit a threshold current control circuit for setting a threshold level value of the upper and lower electrical resets, wherein the capacitor charging and discharging circuit is configured to be configured according to the threshold level control circuit The threshold level value is output, and the power-on reset signal is output;
  • the current bias circuit includes a first reference current output terminal, a second reference current output terminal, and a third reference current output terminal, wherein the first reference current output terminal is used to The flat control circuit is connected, and the second reference current output terminal and the third reference current output terminal are connected to the capacitor charging and discharging circuit.
  • the current bias circuit provides three threshold currents that do not vary with the power supply for the threshold level control circuit and the capacitor charge and discharge circuit, such that the threshold level control circuit passes the current bias
  • the reference current provided by the circuit generates an accurate threshold level value
  • the capacitor charging and discharging circuit passes the reference current provided by the current bias circuit, so that the charging and discharging time of the capacitor can also be accurately calculated, whether the power supply is quickly powered on or slow.
  • the capacitor charging and discharging circuit can generate a stable power-on reset signal.
  • FIG. 1 is a block diagram of a power-on reset circuit in an embodiment
  • FIG. 2 is a circuit schematic diagram of a current bias circuit in the embodiment shown in FIG. 1;
  • FIG. 3 is a circuit schematic diagram of a threshold level control circuit in the embodiment shown in FIG. 1;
  • FIG. 4 is a circuit schematic diagram of a capacitor charging and discharging circuit in the embodiment shown in FIG. 1;
  • FIG. 5 is a waveform diagram of simulation of upper and lower power supply voltages in a normal state in an embodiment
  • FIG. 6 is a waveform diagram of a corresponding POR signal voltage simulation in the embodiment shown in FIG. 5;
  • Figure 7 is a simulation waveform diagram of the upper and lower power supply voltages when the power supply voltage fluctuates to 30%;
  • FIG. 8 is a waveform diagram of a corresponding POR signal voltage simulation in the embodiment shown in FIG. 7.
  • FIG. 8 is a waveform diagram of a corresponding POR signal voltage simulation in the embodiment shown in FIG. 7.
  • an embodiment of the power-on reset circuit includes a current bias circuit 110 , a threshold level control circuit 120 , and a capacitor charge and discharge circuit 130 .
  • the current bias circuit 110 is used to provide the threshold level control circuit 120 and the capacitor charge and discharge circuit 130 with a reference current that does not vary with the power supply.
  • the current bias circuit 110 includes a first path reference current output terminal Ibias1, a second path reference current output terminal Ibias2, and a third path reference current output terminal Ibias3.
  • the first reference current output terminal Ibias1 is used for connection with the threshold level control circuit 120
  • the second reference current output terminal Ibias2 and the third reference current output terminal Ibias3 are used for connection with the capacitor charge and discharge circuit 130.
  • the current bias circuit 110 includes a first field effect transistor MN1, a second field effect transistor MN2, a third field effect transistor MN3, a fourth field effect transistor MP1, a fifth field effect transistor MP2, and a sixth field effect transistor MP3.
  • the gate of the first field effect transistor MN1 is connected to its drain, and the drain of the first field effect transistor MN1 is externally connected to the reference current source Ibias.
  • the source of the first field effect transistor MN1, the second field effect transistor MN2 and the third field effect transistor MN3 is grounded to GND, and the gate of the second field effect transistor MN2 is connected to the gate of the first field effect transistor MN1, the second field effect
  • the drain of the tube MN2 is connected to the drain of the fourth field effect transistor MP1
  • the gate of the third field effect transistor MN3 is connected to the gate of the first field effect transistor MN1
  • the drain of the third field effect transistor MN3 is the third reference current. Output Ibias3.
  • the gate of the fourth field effect transistor MP1 is connected to the drain of the fourth field effect transistor MP1
  • the gate of the fifth field effect transistor MP2 is connected to the gate of the fourth field effect transistor MP1
  • the fourth field effect transistor MP1 the fifth field
  • the source of the effect transistor MP2 and the sixth FET MP3 is connected to the power supply VDD
  • the drain of the fifth FET MP2 is the second reference current output terminal Ibias2
  • the gate of the sixth FET MP3 is connected to the fourth FET.
  • the drain of the MP1 gate and the sixth FET MP3 is the first reference current output terminal Ibias1.
  • the first field effect transistor MN1, the second field effect transistor MN2, and the third field effect transistor MN3 are N-type field effect transistors; the fourth field effect transistor MP1, the fifth field effect transistor MP2, The six field effect transistor MP3 is a P-type field effect transistor.
  • the threshold level control circuit 120 is configured to set a threshold level value of the upper and lower power resets. Specifically, please refer to FIG. 3.
  • the threshold level control circuit 120 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first diode D1, and a second diode.
  • D2 third transistor D3, first comparator Comp1, second comparator Comp2, third comparator Comp3, first NOR gate Nor1 and second NOR gate Nor2.
  • the first resistor R1, the second resistor R2 and the third resistor R3 are connected in series between the first reference current output terminal Ibias1 and the ground GND, and the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6 are connected in series to the power source VDD and the ground. Between GND.
  • the non-inverting input terminal ip of the first comparator Comp1 is connected between the fourth resistor R4 and the fifth resistor R5, and the inverting input terminal in1 of the first comparator Comp1 is connected between the first resistor R1 and the second resistor R2.
  • the output terminal out of the first comparator Comp1 is connected to the first input terminal of the first NOR gate Nor1.
  • the non-inverting input terminal ip of the second comparator Comp2 is connected between the second resistor R2 and the third resistor R3, and the inverting input terminal in2 of the second comparator Comp2 is connected between the fourth resistor R4 and the fifth resistor R5.
  • the output end of the second comparator Comp2 is connected to the first input terminal of the second NOR gate Nor2.
  • the non-inverting input terminal ip of the third comparator Comp3 is connected to the first reference current output terminal Ibias1 together with the positive pole of the first diode D1, and the inverting input terminal in of the third comparator Comp3 is connected to the fifth resistor R5 and the first Between the six resistors R6, the output terminal out of the third comparator Comp3 is connected to the capacitor charging and discharging circuit 130.
  • the cathode of the first diode D1 is connected to the anode of the second diode D2, and the cathode of the second diode D2 is connected to the ground GND.
  • the third transistor D3 is connected between the inverting input terminal in the third comparator Comp3 and the ground GND.
  • the output of the first NOR gate Nor1 is connected to the second input terminal of the second NOR gate Nor2, and the output terminal of the second NOR gate Nor2 is connected to the second input terminal of the first NOR gate Nor1 and the capacitor charging and discharging circuit 130.
  • the reference current source Ibias externally connected to the current bias circuit 110 generally comes from the reference power supply circuit inside the chip, if the power supply VDD power-on speed is faster than the internal reference voltage power supply circuit of the chip, the circuit failure occurs, and the first two poles of the series are connected.
  • the tube D1 and the second diode D2 can ensure that the capacitor charging and discharging circuit 130 does not generate before the reference voltage source Ibias is established. POR signal.
  • the capacitor charging and discharging circuit 130 is configured to output a POR according to a threshold level value set by the threshold level control circuit 120. Specifically, please refer to FIG. 4.
  • the capacitor charging and discharging circuit includes a seventh field effect transistor MP4, an eighth field effect transistor MP5, a ninth field effect transistor MN4, a tenth field effect transistor MN5, a first capacitor C1, and an inverter INV.
  • the source of the seventh field effect transistor MP4 is connected to the power supply VDD, and the drain of the seventh field effect transistor MP4 is respectively connected to the drain of the eighth field effect transistor MP5, the drain of the ninth field effect transistor MN4, and the tenth field effect transistor MN5.
  • the sources of the eighth field effect transistor MP5 and the ninth field effect transistor MN4 are respectively connected to the second reference current input terminal Ibias2 and the third reference current input terminal Ibias3, and the source and the drain of the tenth field effect transistor MN5 are both Ground GND, the negative pole of the first capacitor C1 is grounded, and the output of the inverter INV outputs POR.
  • the external reference current source Ibias passes through the current bias circuit 110 to provide three reference currents that do not fluctuate with the power supply VDD. After the first reference current output terminal Ibias1 is connected to the first resistor R1, the second resistor R2 and the third resistor R3 connected in series, a relatively accurate upper and lower threshold levels are generated.
  • the current value outputted by the first reference current output terminal Ibias1 is I 1
  • the resistance values of the first resistor R1, the second resistor R2 and the third resistor R3 are R 1 , R 2 and R 3 , respectively
  • the upper threshold level is For I 1 ⁇ (R 2 + R 3 )
  • the lower threshold level is I 1 ⁇ R 3 , that is, the difference between the upper and lower threshold levels is I 1 ⁇ R 2 .
  • the second resistor R2 and the third resistor R3 connected in series may be replaced by N (not less than 2) resistors in series with a small resistance value, and the number of series resistors may be finely adjusted to obtain more.
  • N not less than 2 resistors in series with a small resistance value
  • the number of series resistors may be finely adjusted to obtain more.
  • the difference between the threshold levels can also be flexibly adjusted to achieve the anti-interference ability of the power supply under different chip applications.
  • the power supply VDD can generate a POR signal at different voltage values.
  • the resistance values of the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 are equal, the corresponding power supply voltages when the upper and lower threshold levels generate POR are 1.5 ⁇ I 1 ⁇ (R 2 + R 3 ), respectively. , 1.5 ⁇ I 1 ⁇ R 3 . Therefore, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 can realize a coarse adjustment of the voltage value when the power supply VDD generates a POR signal, and the first resistor R1, the second resistor R2, and the third resistor R3 can realize the voltage value. Fine adjustment.
  • the currents outputted by the second reference current output terminal Ibias2 and the third reference current output terminal Ibias3 provided by the current bias circuit 110 are the charging current and the discharging current in the capacitor charging and discharging circuit 130, respectively.
  • the current values of the two current sources can be set according to the actual application environment of the chip.
  • the current value output by the second reference current output terminal Ibias2 is twice the current value output by the third reference current output terminal Ibias3. It can be understood that in other embodiments, only the second reference is guaranteed.
  • the current value outputted by the current output terminal Ibias2 is an integral multiple of the current value outputted by the third reference current output terminal Ibias3.
  • V 1 is the voltage value of the gate of the tenth field effect transistor MN5
  • C 1 is the sum of the capacitance value of the tenth field effect transistor MN5 and the capacitance value of the first capacitor C1
  • I 2 is the second reference current output.
  • the current value output by the terminal Ibias2, V 2 is the flip level value corresponding to the inverter INV.
  • the output of the first comparator Comp1 is “0”.
  • the output of the second comparator Comp2 is “0”, the output of the second NOR gate Nor2 is “0”, and the output current of the second reference current output terminal IBIs2 continues to charge the first capacitor C1, and the output of the inverter INV is still “0”.
  • FIG. 5-8 The waveform diagram of the power-on reset circuit on and off is shown in Figures 5-8.
  • Figure 5 and Figure 6 are the simulated waveforms of the upper and lower power supply voltages and their corresponding POR signal voltage simulation waveforms.
  • Figure 7 and Figure 8 show the upper and lower voltages when the power supply voltage fluctuates at 30%.
  • the circuit When the power supply VDD voltage rises to the upper threshold level of 2.807V, the circuit generates a POR signal. When the power supply VDD voltage drops to the lower threshold level of 1.567V, the POR signal immediately drops to 0, which greatly increases the power supply voltage VDD. Anti-interference ability.
  • the current bias circuit provides three threshold currents that do not vary with the power supply for the threshold level control circuit and the capacitor charge and discharge circuit, such that the threshold level control circuit is biased by current
  • the reference current provided by the circuit generates an accurate threshold level value
  • the capacitor charging and discharging circuit passes the reference current provided by the current bias circuit, so that the charging and discharging time of the capacitor can be accurately calculated, whether the power supply is quickly powered on or slow.
  • the capacitor charging and discharging circuit can generate a stable power-on reset signal.

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Abstract

一种上电复位电路，包括电流偏置电路（110）、门限电平控制电路（120）及电容充放电电路（130）；电流偏置电路（110）用于为门限电平控制电路（120）和电容充放电电路（130）提供不随电源变化的基准电流；门限电平控制电路（120）用于设定上、下电复位的门限电平值；电容充放电电路（130）用于根据门限电平控制电路（120）设定的门限电平值，输出上电复位信号；其中，电流偏置电路（110）包括第一路基准电流输出端、第二路基准电流输出端和第三路基准电流输出端，所述第一路基准电流输出端用于与门限电平控制电路（120）连接，所述第二路基准电流输出端和第三路基准电流输出端用于与电容充放电电路（130）连接。

Description

上电复位电路
【技术领域】
本发明涉及集成电路控制领域，特别是涉及一种上电复位电路。
【背景技术】
目前的芯片中基本都内置上电复位电路。上电复位电路种类很多，目前应用最广的是利用电阻电容、施密特触发器或反相器产生POR (Power On Reset，上电复位) 信号。
然而，传统的上电复位电路在采用反相器做电平翻转使用时，其电源扰动的抗干扰能力比较差，即当电源在反相器翻转电平附近抖动时，反相器会不停的翻转而产生一系列不稳定的POR信号，这种现象被称之为误触发，使得芯片无法正常工作。采用施密特触发器做电平翻转的电路具有一定的抗干扰能力，但施密特触发器的上下门限电平难以精确的设置，且其门限电平会随电源电压的波动而变化，所以很难精确调制上电复位的门限电平，最终导致产生的POR信号不稳定。
【发明内容】
基于此，有必要提供一种能产生稳定上电复位信号的上电复位电路。
一种上电复位电路，包括电流偏置电路、门限电平控制电路及电容充放电电路，所述电流偏置电路用于为所述门限电平控制电路和电容充放电电路提供不随电源变化的基准电流，所述门限电平控制电路用于设定上、下电复位的门限电平值，所述电容充放电电路用于根据所述门限电平控制电路设定的所述门限电平值，输出上电复位信号；
其中，所述电流偏置电路包括第一路基准电流输出端、第二路基准电流输出端和第三路基准电流输出端，所述第一路基准电流输出端用于与所述门限电平控制电路连接，所述第二路基准电流输出端和第三路基准电流输出端用于与所述电容充放电电路连接。
根据上述上电复位电路，所述电流偏置电路为所述门限电平控制电路和电容充放电电路提供了三路不随电源变化的基准电流，这样所述门限电平控制电路通过电流偏置电路提供的基准电流产生精确的门限电平值，所述电容充放电电路通过电流偏置电路提供的基准电流，使得电容充放电时间也可以精确计算出来，无论在电源快速上电还是慢速上电的情况下，电容充放电电路都能产生稳定的上电复位信号。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一实施例中上电复位电路的模块图；
图2为图1所示实施例中电流偏置电路的电路原理图；
图3为图1所示实施例中门限电平控制电路的电路原理图；
图4为图1所示实施例中电容充放电电路的电路原理图；
图5为一实施例中正常情况的上、下电电源电压仿真波形图；
图6为图5所示实施例中对应的POR信号电压仿真波形图；
图7为电源电压波动为30%时的上、下电电源电压仿真波形图；
图8为图7所示实施例中对应的POR信号电压仿真波形图。
【具体实施方式】
请参照图1，一实施例中上电复位电路包括电流偏置电路110、门限电平控制电路120及电容充放电电路130。
电流偏置电路110用于为门限电平控制电路120和电容充放电电路130提供不随电源变化的基准电流。在本实施例中，电流偏置电路110包括第一路基准电流输出端Ibias1、第二路基准电流输出端Ibias2和第三路基准电流输出端Ibias3。第一路基准电流输出端Ibias1用于与门限电平控制电路120连接，第二路基准电流输出端Ibias2和第三路基准电流输出端Ibias3用于与电容充放电电路130连接。
具体地，请结合图2。电流偏置电路110包括第一场效应管MN1、第二场效应管MN2、第三场效应管MN3、第四场效应管MP1、第五场效应管MP2、第六场效应管MP3。
第一场效应管MN1的栅极与其漏极相连，第一场效应管MN1的漏极外接参考电流源Ibias。第一场效应管MN1、第二场效应管MN2和第三场效应管MN3的源极接地GND，第二场效应管MN2的栅极接第一场效应管MN1的栅极，第二场效应管MN2的漏极接第四场效应管MP1的漏极，第三场效应管MN3的栅极接第一场效应管MN1的栅极，第三场效应管MN3的漏极为第三路基准电流输出端Ibias3。第四场效应管MP1的栅极接第四场效应管MP1的漏极，第五场效应管MP2的栅极接第四场效应管MP1的栅极，第四场效应管MP1、第五场效应管MP2和第六场效应管MP3的源极接电源VDD，第五场效应管MP2的漏极为第二路基准电流输出端Ibias2，第六场效应管MP3的栅极接第四场效应管MP1栅极，第六场效应管MP3的漏极为第一路基准电流输出端Ibias1。
在本实施例中，第一场效应管MN1、第二场效应管MN2、第三场效应管MN3为N型场效应管；所述第四场效应管MP1、第五场效应管MP2、第六场效应管MP3为P型场效应管。
门限电平控制电路120用于设定上、下电复位的门限电平值。具体地，请结合图3。
门限电平控制电路120包括第一电阻R1、第二电阻R2、第三电阻R3、第四电阻R4、第五电阻R5、第六电阻R6、第一二极管D1、第二二极管D2、第三三极管D3、第一比较器Comp1、第二比较器Comp2、第三比较器Comp3、第一或非门Nor1及第二或非门Nor2。
第一电阻R1、第二电阻R2和第三电阻R3串联在第一路基准电流输出端Ibias1与地GND之间，第四电阻R4、第五电阻R5和第六电阻R6串联在电源VDD与地GND之间。
第一比较器Comp1的同向输入端ip连接在第四电阻R4与第五电阻R5之间，第一比较器Comp1的反向输入端in连接在第一电阻R1与第二电阻R2之间，第一比较器Comp1的输出端out接第一或非门Nor1的第一输入端。
第二比较器Comp2的同向输入端ip连接在第二电阻R2与第三电阻R3之间，第二比较器Comp2的反向输入端in连接在第四电阻R4与第五电阻R5之间，第二比较器Comp2的输出端out接第二或非门Nor2的第一输入端。
第三比较器Comp3的同向输入端ip和第一二极管D1的正极一起连接第一路基准电流输出端Ibias1，第三比较器Comp3的反向输入端in连接在第五电阻R5与第六电阻R6之间，第三比较器Comp3的输出端out接电容充放电电路130。
第一二极管D1的负极接第二二极管D2的正极，第二二极管D2的负极接地GND。第三三极管D3连接在第三比较器Comp3的反向输入端in与地GND之间。第一或非门Nor1的输出端接第二或非门Nor2的第二输入端，第二或非门Nor2的输出端接第一或非门Nor1的第二输入端和电容充放电电路130。
由于电流偏置电路110外接的参考电流源Ibias一般来自于芯片内部的参考电源电路，若电源VDD上电速度比芯片内部参考电压电源电路建立时间快就会造成电路失效，串联的第一二极管D1和第二二极管D2可以确保参考电压源Ibias没有建立好之前，电容充放电电路130不会产生 POR信号。
电容充放电电路130用于根据门限电平控制电路120设定的门限电平值，输出POR。 具体地，请结合图4。
电容充放电电路包括第七场效应管MP4、第八场效应管MP5、第九场效应管MN4、第十场效应管MN5、第一电容C1以及反相器INV。
第七场效应管MP4的源极接电源VDD，第七场效应管MP4的漏极分别接第八场效应管MP5的漏极、第九场效应管MN4的漏极、第十场效应管MN5的栅极、第一电容C1的正极以及反相器INV的输入端。第八场效应管MP5、第九场效应管MN4的源极分别接第二路基准电流输入端Ibias2和第三路基准电流输入端Ibias3，第十场效应管MN5的源极及其漏极都接地GND，第一电容C1的负极接地，反相器INV的输出端输出POR。
以下结合图1～图4说明上电复位电路的工作原理。
外接的参考电流源Ibias经过电流偏置电路110后，提供出了三路不随电源VDD波动的基准电流。第一路基准电流输出端Ibias1接至串联的第一电阻R1、第二电阻R2和第三电阻R3后，产生了较为精准的上、下门限电平。设第一路基准电流输出端Ibias1输出的电流值为I1，第一电阻R1、第二电阻R2和第三电阻R3的电阻值分别为R1、R2和R3，则上门限电平为I1×(R2+ R3)，下门限电平为I1×R3，即上、下门限电平之差为I1×R2。
可以理解，在其他实施例中，还可以将串联的第二电阻R2、第三电阻R3替换为N（不小于2）个小电阻值的电阻串联，通过微调串联电阻的个数，可以获得更为精准的上、下门限电平，同时门限电平之差也可以灵活的调整，可以实现不同芯片应用场合下电源的抗干扰能力。
进一步地，配合串联的第四电阻R4、第五电阻R5及第六电阻R6，可以实现电源VDD在不同电压值时产生POR信号。如当第四电阻R4、第五电阻R5及第六电阻R6的电阻值相等时，上、下门限电平产生POR时对应的电源电压分别为1.5×I1×(R2+ R3)、1.5×I1×R3。因此，第四电阻R4、第五电阻R5及第六电阻R6可以实现电源VDD产生POR信号时电压值的粗调，而第一电阻R1、第二电阻R2及第三电阻R3可以实现此电压值的精细调节。
电流偏置电路110提供的第二路基准电流输出端Ibias2、第三路基准电流输出端Ibias3输出的电流分别为电容充放电电路130中的充电电流和放电电流。此两路电流源的电流值可根据芯片实际应用环境设置。
在本实施例中，第二路基准电流输出端Ibias2输出的电流值是第三路基准电流输出端Ibias3输出的电流值的两倍，可以理解，在其他实施例中，只要保证第二路基准电流输出端Ibias2输出的电流值是第三路基准电流输出端Ibias3输出的电流值的整数倍即可。
由于偏置电流不会随电源VDD波动，则可以精确计算出充电时间为：T1=（V1×C1）/I2。同理，放电时间也可以精确计算出来为：T2=2×（V1-V2）×C1/I2。其中，V1为第十场效应管MN5的栅极的电压值，C1为第十场效应管MN5的电容值和第一电容C1的电容值的和，I2为第二路基准电流输出端Ibias2输出的电流值，V2为反相器INV所对应的翻转电平值。
当电源VDD上电时，第四电阻R4和第五电阻R5间电压V3成比例跟随上升，第一比较器Comp1输出为“0”, 第二比较器Comp2输出为“1”，第二或非门Nor2输出为“0”，第八场效应管MP5导通，第二路基准电流输出端IBias2输出电流对第一电容C1充电，第十场效应管MN5的栅极电压上升，反向器INV输出为“0”。
当第四电阻R4和第五电阻R5间电压V3上升至下门限电平时，第一比较器Comp1输出为“0”, 第二比较器Comp2输出为“0”，第二或非门Nor2输出为“0”，第二路基准电流输出端IBias2输出电流继续对第一电容C1充电，反向器INV输出依然为“0”；当第四电阻R4和第五电阻R5间电压V3上升至上门限电平时，第一比较器Comp1输出为“1”, 第二比较器Comp2输出为“0”，第二或非门Nor2输出为“1”， 第一电容C1开始放电，反向器INV输出为“1”，产生POR信号。
当电源VDD下电时，第四电阻R4和第五电阻R5间电压V3开始下降， 当V3电压下降至上门限电平时，第一比较器Comp1输出为“0”, 第二比较器Comp2输出为“0”，第二或非门Nor2输出为“1”，反向器 INV输出依然为“1”；当第四电阻R4和第五电阻R5间电压V3下降至下门限电平时，第一比较器Comp1输出为“0”, 第二比较器Comp2输出为“1”，第二或非门Nor2输出为“0”，反向器INV输出为“0”。
该上电复位电路上、下电仿真波形图如图5～图8所示。其中，图5和图6分别为正常情况的上、下电电源电压仿真波形图及其对应的POR信号电压仿真波形图；图7、图8分别为电源电压波动为30%时的上、下电电源电压仿真波形图及其对应的POR信号电压仿真波形图。
当电源VDD电压升高至上门限电平2.807V时，电路产生POR信号，当电源VDD电压下降至下门限电平1.567V时，POR信号立即下降为0，这就大大提高了电源电压VDD的抗干扰能力。
如图8所示，即使电源电压VDD波动30%时，也不会产生POR信号的误触发。
上述上电复位电路，所述电流偏置电路为所述门限电平控制电路和电容充放电电路提供了三路不随电源变化的基准电流，这样所述门限电平控制电路通过电流偏置电路提供的基准电流产生精确的门限电平值，所述电容充放电电路通过电流偏置电路提供的基准电流，使得电容充放电的时间也可以精确计算出来，无论在电源快速上电还是慢速上电的情况下，电容充放电电路都能产生稳定的上电复位信号。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种上电复位电路，其特征在于，包括电流偏置电路、门限电平控制电路及电容充放电电路，所述电流偏置电路用于为所述门限电平控制电路和电容充放电电路提供不随电源变化的基准电流，所述门限电平控制电路用于设定上、下电复位的门限电平值，所述电容充放电电路用于根据所述门限电平控制电路设定的所述门限电平值，输出上电复位信号；
    其中，所述电流偏置电路包括第一路基准电流输出端、第二路基准电流输出端和第三路基准电流输出端，所述第一路基准电流输出端用于与所述门限电平控制电路连接，所述第二路基准电流输出端和第三路基准电流输出端用于与所述电容充放电电路连接。
  2. 根据权利要求1所述的上电复位电路，其特征在于，所述电流偏置电路包括第一场效应管、第二场效应管、第三场效应管、第四场效应管、第五场效应管、第六场效应管；
    所述第一场效应管的栅极与其漏极相连，所述第一场效应管的漏极外接参考电流源，所述第一场效应管、第二场效应管和第三场效应管的源极接地；所述第二场效应管的栅极接第一场效应管的栅极，所述第二场效应管的漏极接所述第四场效应管的漏极，所述第三场效应管的栅极接所述第一场效应管的栅极，所述第三场效应管的漏极为所述第三路基准电流输出端，所述第四场效应管、第五场效应管和第六场效应管的源极接电源，所述第四场效应管的栅极接第四场效应管的漏极, 所述第五场效应管的栅极接第四场效应管的栅极，所述第五场效应管的漏极为所述第二路基准电流输出端，所述第六场效应管的栅极接第四场效应管的栅极，所述第六场效应管的漏极为所述第一路基准电流输出端。
  3. 根据权利要求2所述的上电复位电路，其特征在于，所述第一场效应管、第二场效应管、第三场效应管为N型场效应管；所述第四场效应管、第五场效应管、第六场效应管为P型场效应管。
  4. 根据权利要求1所述的上电复位电路，其特征在于，所述门限电平控制电路包括串联的第一二极管和第二二极管，所述第一二极管的正极连接所述第一路基准电流输出端，所述第一二极管的负极接所述第二二极管的正极，所述第二二极管的负极接地。
  5. 根据权利要求4所述的上电复位电路，其特征在于，所述门限电平控制电路还包括第一电阻、第二电阻、第三电阻、第四电阻、第五电阻、第六电阻、第三三极管、第一比较器、第二比较器、第三比较器、第一或非门及第二或非门；
    所述第一电阻、第二电阻和第三电阻串联在所述第一路基准电流输出端与地之间，所述第四电阻、第五电阻和第六电阻串联在电源与地之间；
    所述第一比较器的同向输入端连接在所述第四电阻与第五电阻之间；所述第一比较器的反向输入端连接在所述第一电阻与第二电阻之间，所述第一比较器的输出端接所述第一或非门的第一输入端；
    所述第二比较器的同向输入端连接在所述第二电阻与第三电阻之间，所述第二比较器的反向输入端连接在所述第四电阻与第五电阻之间，所述第二比较器的输出端接所述第二或非门的第一输入端；
    所述第三比较器的同向输入端连接所述第一路基准电流输出端，所述第三比较器的反向输入端连接在所述第五电阻与第六电阻之间，所述第三比较器的输出端接所述电容充放电电路；
    所述第三三极管连接在所述第三比较器的反向输入端与地之间；所述第一或非门的输出端接所述第二或非门的第二输入端，所述第二或非门的输出端接所述第一或非门的第二输入端和所述电容充放电电路。
  6. 根据权利要求1所述的上电复位电路，其特征在于，所述电容充放电电路包括第七场效应管、第八场效应管、第九场效应管、第十场效应管、第一电容以及反相器；
    所述第七场效应管的源极接电源，所述第七场效应管的漏极分别接所述第八场效应管的漏极、所述第九场效应管的漏极、所述第十场效应管的栅极、所述第一电容的正极以及所述反相器的输入端，所述第八场效应管、第九场效应管的源极分别接所述第二路基准电流输入端和第三路基准电流输入端，所述第十场效应管的源极及其漏极都接地，所述第一电容的负极接地，所述反相器的输出端输出上电复位信号。
  7. 根据权利要求6所述的上电复位电路，其特征在于，所述第七场效应管、第八场效应管为P型场效应管，所述第九场效应管、第十场效应管为N型场效应管。
  8. 根据权利要求6所述的上电复位电路，其特征在于，所述第一电容为MIM电容。
  9. 根据权利要求1所述的上电复位电路，其特征在于，所述第二路基准电流输出端输出的电流值是第三路基准电流输出端输出的电流值的整数倍。
  10. 根据权利要求9所述的上电复位电路，其特征在于，所述第二路基准电流输出端输出的电流值是第三路基准电流输出端输出的电流值的两倍。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109004922A (zh) * 2018-06-26 2018-12-14 珠海市杰理科技股份有限公司 复位电路

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107547074B (zh) * 2017-08-04 2020-08-04 广东顺德中山大学卡内基梅隆大学国际联合研究院 一种上电复位电路
CN110429930B (zh) * 2019-08-29 2024-05-14 广东华芯微特集成电路有限公司 下电复位电路及电源装置
KR20210037309A (ko) 2019-09-27 2021-04-06 삼성전자주식회사 컨트롤 ic의 리셋을 제어하는 전자 장치 및 방법
CN117930949A (zh) * 2022-10-25 2024-04-26 荣耀终端有限公司 复位电路及电子设备
CN117749150B (zh) * 2024-02-19 2024-04-19 北京中天星控科技开发有限公司成都分公司 一种快慢上电复位电路

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013037617A (ja) * 2011-08-10 2013-02-21 Denso Corp バンドギャップ基準電圧回路及びこれを用いたパワーオンリセット回路
CN103019295A (zh) * 2011-09-24 2013-04-03 创杰科技股份有限公司 启动重置信号产生装置及方法
CN103427812A (zh) * 2012-05-25 2013-12-04 国家电网公司 一种上电复位电路及其方法
CN103633974A (zh) * 2013-12-04 2014-03-12 安徽理工大学 一种具有固定阻容时间延迟特性的上电复位电路
CN103997323A (zh) * 2014-06-09 2014-08-20 上海华力微电子有限公司 一种低功耗高稳定性的复位电路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6137324A (en) * 1998-06-02 2000-10-24 Advanced Micro Devices, Inc. Precision power-on reset circuit with improved accuracy
US6515523B1 (en) * 2001-05-23 2003-02-04 National Semiconductor Corporation Method and apparatus for generating a power-on reset with an adjustable falling edge for power management
KR100492801B1 (ko) * 2002-11-14 2005-06-07 주식회사 하이닉스반도체 리셋신호 발생회로 및 이를 이용한 불휘발성 강유전체메모리 장치
US7348814B2 (en) * 2004-08-24 2008-03-25 Macronix International Co., Ltd. Power-on reset circuit
JP2008048298A (ja) * 2006-08-21 2008-02-28 Renesas Technology Corp 半導体集積回路装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013037617A (ja) * 2011-08-10 2013-02-21 Denso Corp バンドギャップ基準電圧回路及びこれを用いたパワーオンリセット回路
CN103019295A (zh) * 2011-09-24 2013-04-03 创杰科技股份有限公司 启动重置信号产生装置及方法
CN103427812A (zh) * 2012-05-25 2013-12-04 国家电网公司 一种上电复位电路及其方法
CN103633974A (zh) * 2013-12-04 2014-03-12 安徽理工大学 一种具有固定阻容时间延迟特性的上电复位电路
CN103997323A (zh) * 2014-06-09 2014-08-20 上海华力微电子有限公司 一种低功耗高稳定性的复位电路

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109004922A (zh) * 2018-06-26 2018-12-14 珠海市杰理科技股份有限公司 复位电路
CN109004922B (zh) * 2018-06-26 2022-03-04 珠海市杰理科技股份有限公司 复位电路

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