WO2016112744A1 - 抗闩锁效应微处理器复位电路 - Google Patents

抗闩锁效应微处理器复位电路 Download PDF

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WO2016112744A1
WO2016112744A1 PCT/CN2015/095370 CN2015095370W WO2016112744A1 WO 2016112744 A1 WO2016112744 A1 WO 2016112744A1 CN 2015095370 W CN2015095370 W CN 2015095370W WO 2016112744 A1 WO2016112744 A1 WO 2016112744A1
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capacitor
reset circuit
microprocessor
order
resistor
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PCT/CN2015/095370
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English (en)
French (fr)
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侯立功
刘全胜
陈天娥
吴伟
肖颖
侯正昌
陆秋俊
王欣
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无锡职业技术学院
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Publication of WO2016112744A1 publication Critical patent/WO2016112744A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means

Definitions

  • the anti-latch effect microprocessor reset circuit of the invention relates to the field of electronic technology application, in particular to a reset circuit, which can effectively avoid the risk of latch-up triggering of the reset signal to the microprocessor.
  • CMOS complementary metal-oxide-semiconductor
  • parasitic bipolar transistor inherent in the CMOS structure is activated under certain conditions, forming positive feedback, causing latch-up, causing the IC circuit to malfunction, causing data or logic state changes, data loss, and severely burning the chip. Causes permanent failure of the circuit.
  • the current IC layout process design can basically avoid the probability of the chip itself latching. It is currently recognized in the industry that the generation of the latch mainly comes from the triggering of external conditions, that is, the circuit application.
  • the recognized external trigger conditions that are prone to IC latching are: external signal or noise interference, especially signal flipping at the chip I/O pin, I/O pin voltage exceeding the device supply voltage or below ground, I/ The voltage or current on the O pin changes too fast, and there are surges or drops on the power supply pins of the device.
  • the object of the present invention is to provide an anti-latch effect microprocessor resetting power for the above-mentioned deficiencies
  • the anti-latch effect microprocessor reset circuit comprises a first-order reset circuit, a power-down detection circuit and a drain channel, and the power-down detection circuit and the first-order reset circuit are connected by an optocoupler;
  • the first-order reset circuit is composed of a resistor and a first capacitor connected in series;
  • the power-down detection circuit is composed of a diode, a second capacitor and a light-emitting diode inside the optocoupler.
  • the anode of the diode and the cathode of the LED are respectively connected to the power source, and the cathode of the second capacitor and the cathode of the diode are respectively connected to the anode of the LED, and the second The negative pole of the capacitor is grounded;
  • the drain channel is composed of a phototransistor inside the photocoupler and an element in the first order reset circuit; the component is a first capacitor or resistor.
  • the drain channel is composed of a phototransistor inside the photocoupler and a first capacitor in the first-order reset circuit
  • the collector of the phototransistor is connected to the anode of the first capacitor, the emitter of the phototransistor is grounded
  • the resistor in the first-order reset circuit One end is connected to the power source, the other end of the resistor is connected to the anode of the first capacitor, and the cathode of the first capacitor is grounded
  • the first-order reset circuit forms a first-order integral reset circuit, which is suitable for resetting the microprocessor at a low level.
  • the bleed passage is composed of a phototransistor inside the photocoupler and a resistor in the first-order reset circuit
  • the emitter of the phototransistor is grounded
  • the anode of the first capacitor in the first-order reset circuit is connected to the power source, and the anode and the resistor of the first capacitor One end is connected and connected to the collector of the phototransistor, and the other end of the resistor is grounded
  • the first-order reset circuit forms a first-order differential reset circuit, which is suitable for resetting the microprocessor at a high level.
  • the circuit of the invention designs a new leakage path for the first capacitor, and can quickly discharge the first capacitor when the power is turned off, and avoids impact on the reset pin of the microprocessor, and does not affect the stability of the normal reset signal. And reliability.
  • the microprocessor reset pin can avoid the reset capacitor, that is, the impact when the first capacitor stores the power release, and effectively avoids the risk of the microprocessor latch trigger caused by the reset signal.
  • Figure 1 is a conventional microprocessor reset circuit diagram a
  • Figure 2 is a conventional microprocessor reset circuit diagram b
  • Figure 3 is a simulation waveform of a conventional microprocessor reset circuit
  • FIG. 4 is a schematic diagram of an anti-latch microprocessor reset circuit (for a low level reset microprocessor) of the present invention
  • FIG. 5 is a schematic diagram of the anti-latch microprocessor reset circuit (applicable to a high level reset microprocessor) of the present invention.
  • C1 first capacitor, R1, resistor, VCC, power supply, RST, microprocessor reset pin, T1, phototransistor, VD1, LED, D1, diode, C2, second capacitor, U1, optocoupler .
  • the reset circuit in the conventional reset circuit diagram a, is connected in series by the resistor R1 and the first capacitor C1. One end of the resistor R1 is connected to the power source, and the other end of the resistor R1 is connected to the anode of the first capacitor C1. The first capacitor C1 The negative pole is grounded; referring to the operating waveform diagram of Figure 3, when the power is turned off, the voltage change on the microprocessor reset pin RST conforms to the external trigger condition that causes the microprocessor to latch.
  • the power supply VCC When the power supply VCC is energized, the power supply VCC mainly charges the first capacitor C1 through the resistor R1 to generate a reset signal, and the microprocessor has not yet entered the working state; and when the power supply VCC is powered off, the discharge of the first capacitor C1 directly impacts the micro Processor reset pin RST.
  • the diode discharge circuit is added, but due to the falling characteristics of the power supply, the discharge to the microprocessor reset pin RST cannot be avoided.
  • the impact becomes frequent and becomes an important trigger for the latching of the microprocessor.
  • the anti-latch microprocessor reset circuit of the present invention designs a new drain path for the first capacitor C1, which enables the first capacitor C1 to be quickly discharged when the power supply is powered down, while avoiding the microprocessor.
  • the reset pin RST forms an impact and does not affect the stability and reliability of the normal reset signal.
  • the anti-latch effect microprocessor reset circuit of the present invention comprises a first-order reset circuit, a power-down detection circuit and a drain channel, and the brown-out detection circuit and the first-order reset circuit are connected by an optocoupler U1;
  • the first-order reset circuit is composed of a resistor R1 and a first capacitor C1 connected in series;
  • the power-down detection circuit is composed of a diode D1, a second capacitor C2 and a light-emitting diode VD1 inside the photocoupler U1.
  • the anode of the diode D1 and the cathode of the light-emitting diode VD1 are respectively connected to the power source VCC, and the cathode of the second capacitor C2 and the cathode of the diode D1 are respectively Connected to the anode of the light emitting diode VD1, and the negative pole of the second capacitor C2 is grounded;
  • the drain channel is composed of a phototransistor T1 inside the photocoupler U1 and an element in the first-order reset circuit; the component is a first capacitor C1 or a resistor R1.
  • the drain channel is composed of the phototransistor T1 inside the photocoupler U1 and the first capacitor C1 in the first-order reset circuit
  • the collector of the phototransistor T1 is connected to the anode of the first capacitor C1, and the emitter of the phototransistor T1 is grounded
  • the first-order reset circuit one end of the resistor R1 is connected to the power source VCC, the other end of the resistor R1 is connected to the anode of the first capacitor C1, and the cathode of the first capacitor C1 is grounded;
  • the first-order reset circuit forms a first-order integral reset circuit, which is suitable for low Level reset microprocessor.
  • the emitter of the phototransistor T1 is grounded;
  • the anode of the first capacitor C1 in the first-order reset circuit is connected to the power source VCC,
  • the negative pole of a capacitor C1 is connected to one end of the resistor R1, and is connected to the collector of the phototransistor T1, and the other end of the resistor R1 is grounded;
  • the first-order reset circuit forms a first-order differential reset circuit, which is suitable for resetting the microprocessor at a high level.
  • the anti-latch microprocessor reset circuit shown in Figure 4 is suitable for a low level reset microprocessor comprising three parts: a first order integral reset circuit, a brownout detection circuit and a drain channel.
  • the above partial circuits are connected by signal lines. The function of each component of the present invention will be specifically described below with reference to FIG. 4:
  • the first capacitor C1 is mainly composed of a resistor R1 and a first capacitor C1. One end of the resistor R1 is connected to the power source VCC, the other end is connected to the anode of the first capacitor C1, and the cathode of the first capacitor C1 is grounded.
  • the power source VCC is connected to the anode of the diode D1 and the cathode of the light-emitting diode VD1; the anode of the second capacitor C2, the cathode of the diode D1 and the anode of the light-emitting diode VD1 are connected together; and the cathode of the second capacitor C2 is connected to the power ground.
  • the diode D1 When the power is turned on, the diode D1 is forwardly turned on, and the light-emitting diode VD1 inside the optocoupler U1 is reversely energized, and is not turned on at this time, and the power source VCC charges and stores the second capacitor C2 through the diode D1. After the charging is completed, the positive voltage of the second capacitor C2 is equal to VCC.
  • the collector of the phototransistor T1 is connected to the positive pole of the first capacitor C1
  • the emitter of the phototransistor T1 is connected to the power ground.
  • the light-emitting diode VD1 in the power-down detection circuit is reversely energized, so the phototransistor T1 is not turned on, and the drain channel is in an open state, which does not affect the reset circuit operation.
  • the anti-latch microprocessor reset circuit shown in Figure 5 is suitable for a high level reset microprocessor comprising three parts: a first order differential reset circuit, a brownout detection circuit and a drain channel.
  • the above partial circuits are connected by signal lines. The function of each component of the present invention will be specifically described below with reference to FIG. 5:
  • the first capacitor C1 is connected to the power source VCC, the cathode of the first capacitor C1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the power source.
  • the power source VCC is connected to the anode of the diode D1 and the cathode of the light-emitting diode VD1; the anode of the second capacitor C2, the cathode of the diode D1 and the anode of the light-emitting diode VD1 are connected together; and the cathode of the second capacitor C2 is connected to the power ground.
  • the diode D1 When the power is turned on, the diode D1 is forwardly turned on, and the light-emitting diode VD1 inside the optocoupler U1 is reversely energized, and is not turned on at this time, and the power source VCC charges and stores the second capacitor C2 through the diode D1. After the charging is completed, the positive voltage of the second capacitor C2 is equal to VCC.
  • the VCC voltage is lowered.
  • the positive voltage of the second capacitor C2 is higher than the VCC voltage, and the diode D1 is reversely energized and not turned on; the light-emitting diode VD1 inside the optocoupler is forward-conducting, and the capacitor C2 is stored.
  • the electric energy is discharged to the power source VCC through the light-emitting diode VD1 to form a current I F , thereby triggering the phototransistor T1 inside the photocoupler U1 to be turned on.
  • the phototransistor T1 is mainly composed of a phototransistor T1 and a resistor R1 inside the optocoupler.
  • the collector of the phototransistor T1 is connected to the connection point of the resistor R1 and the cathode of the first capacitor C1, and the emitter of the phototransistor T1 is connected to the power source.
  • the light-emitting diode VD1 in the power-down detection circuit is reversely energized, so the phototransistor T1 is not turned on, and the drain channel is in an open state, which does not affect the reset circuit operation.
  • the phototransistor T1 When the power is off, the phototransistor T1 is turned on and the drain channel is closed under the trigger of the power-down detection circuit. Since the reset pin RST is low when the microprocessor is working normally, the drain channel will be directly processed. The reset pin RST is pulled down to the ground potential through the turned-on phototransistor T1 to avoid the influence of the discharge of the first capacitor C1 on the microprocessor reset pin RST.

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Abstract

一种抗闩锁效应微处理器复位电路，包括一阶复位电路、掉电检测电路和泄流通道，掉电检测电路和一阶复位电路之间通过光耦（U1）连接；所述一阶复位电路由电阻（R1）和第一电容（C1）串接组成；掉电检测电路由二极管（D1）、第二电容（C2）和光耦（U1）内部的发光二极管（VD1）组成；泄流通道由光耦（U1）内部的光敏三极管（T1）和一阶复位电路中的元件组成。上述抗闩锁效应微处理器复位电路能够有效避免复位信号对微处理器带来的闩锁触发风险。

Description

抗闩锁效应微处理器复位电路 技术领域
本发明抗闩锁效应微处理器复位电路涉及电子技术应用领域，具体为一种复位电路，能够有效避免复位信号对微处理器带来的闩锁触发风险。
背景技术
CMOS工艺的低功耗、无比例逻辑设计以及较大的噪声容限等优点使得其成为数字电路、模拟电路以及在同一芯片上构成模拟、数字混合电路的首选技术。但CMOS结构所固有的寄生双极型晶体管在某些条件触发下会被激活，形成正反馈，产生闩锁，导致IC电路出现故障，造成数据或逻辑状态改变、数据丢失，严重时烧毁芯片，导致电路永久失效。
目前的IC版图工艺设计已基本可以避免芯片自身闩锁发生的几率,当前业界公认为，闩锁的产生主要还是来自于外部条件的触发，即电路应用方面。公认的容易引起IC闩锁的外部触发条件主要有：外界信号或者噪声干扰特别是芯片I/O引脚处的信号翻转、I/O引脚电压超过器件供电电压或低于地电压、I/O管脚上的电压或电流变化太快、器件电源管脚上出现浪涌或跌落等因素。
现代CMOS电路，尤其是以嵌入式控制为代表的各类微处理器应用呈几何式增长，在样机调试和系统应用过程中，经常会出现软件跑飞、数据丢失、参数改变等各类错误现象。排除软件本身Bug，由于实际应用电路和外部环境的多样化和复杂性，在某些特殊情况下(比如频繁通断电)，在采取了上述各种抗干扰措施后仍未能解决问题时，需要考虑由复位电路触发导致微处理器进入闩锁的可能性。但由于复位信号工作的特殊性，很多工程师在解决问题时容易忽视由复位信号触发的微处理器闩锁，学术界和市场上还未发现有关于复位和闩锁关联方向的研究成果。
发明内容
本发明的目的是针对上述不足之处提供一种抗闩锁效应微处理器复位电 路，通过该复位电路，有效避免复位信号对微处理器带来的闩锁触发风险。
本发明抗闩锁效应微处理器复位电路是采取以下技术方案实现的：
抗闩锁效应微处理器复位电路包括一阶复位电路、掉电检测电路和泄流通道，掉电检测电路和一阶复位电路之间通过光耦连接；
所述一阶复位电路由电阻和第一电容串接组成；
掉电检测电路由二极管、第二电容和光耦内部的发光二极管组成，二极管的阳极以及发光二极管的阴极分别与电源相连，第二电容的正极、二极管的阴极分别与发光二极管的阳极相连，第二电容的负极接地；
泄流通道由光耦内部的光敏三极管和一阶复位电路中的元件组成；所述元件为第一电容或电阻。
当泄流通道由光耦内部的光敏三极管和一阶复位电路中的第一电容组成时，光敏三极管的集电极和第一电容的正极相连，光敏三极管的发射极接地；一阶复位电路中电阻的一端与电源相连，电阻的另一端与第一电容的正极相连，第一电容的负极接地；一阶复位电路形成一阶积分复位电路，适用于低电平复位微处理器。
当泄流通道由光耦内部的光敏三极管和一阶复位电路中的电阻组成时，光敏三极管的发射极接地；一阶复位电路中第一电容的正极与电源相连，第一电容的负极与电阻一端连接，并和光敏三极管集电极相连，电阻另一端接地；一阶复位电路形成一阶微分复位电路，适用于高电平复位微处理器。
本发明电路为第一电容设计了一条新的泄流路径，在电源掉电时，能够让第一电容快速放电，同时避免对微处理器复位引脚形成冲击，不影响正常复位信号的稳定性和可靠性。通过所述泄流通道使微处理器复位引脚能够避开复位电容即第一电容储存的电量释放时的冲击，有效避免由复位信号引起的微处理器闩锁触发风险。
附图说明
以下将结合附图对本发明作进一步说明：
图1是传统微处理器复位电路图a；
图2是传统微处理器复位电路图b；
图3是传统微处理器复位电路仿真波形；
图4为本发明抗闩锁微处理器复位电路(适用于低电平复位微处理器)的原理图；
图5为本发明抗闩锁微处理器复位电路(适用于高电平复位微处理器)的原理图。
图中：C1、第一电容，R1、电阻，VCC、电源，RST、微处理器复位引脚，T1、光敏三极管，VD1、发光二极管，D1、二极管，C2、第二电容，U1、光耦。
具体实施方式
参照附图1～3，传统复位电路图a中，复位电路由电阻R1和第一电容C1串接，电阻R1的一端接电源，电阻R1另一端与第一电容C1的正极相连，第一电容C1的负极接地；参考图3的工作波形图，电源通断电时，微处理器复位引脚RST上的电压变化，符合引起微处理器闩锁的外部触发条件特征。当电源VCC通电时，电源VCC通过电阻R1主要对第一电容C1充电，产生复位信号，此时微处理器尚未进入工作状态；而在电源VCC掉电时，第一电容C1的放电直接冲击微处理器复位引脚RST。
传统复位电路图b中，增加了二极管放电回路，但受制于电源的下降特性，仍然不能避开针对微处理器复位引脚RST的放电。当系统连续快速通断电时，这种冲击就会变得频繁起来，成为导致微处理器闩锁的重要触发因素。
为解决此问题，本发明抗闩锁微处理器复位电路为第一电容C1设计了一条新的泄流路径，在电源掉电时，能够让第一电容C1快速放电，同时避免对微处理器复位引脚RST形成冲击，不影响正常复位信号的稳定性和可靠性。
参照附图4～5，本发明抗闩锁效应微处理器复位电路包括一阶复位电路、掉电检测电路和泄流通道，掉电检测电路和一阶复位电路之间通过光耦U1连接；所述一阶复位电路由电阻R1和第一电容C1串接组成；
掉电检测电路由二极管D1、第二电容C2和光耦U1内部的发光二极管VD1组成，二极管D1的阳极以及发光二极管VD1的阴极分别与电源VCC相连，第二电容C2的正极、二极管D1的阴极分别与发光二极管VD1的阳极相连，第二电容C2的负极接地；
泄流通道由光耦U1内部的光敏三极管T1和一阶复位电路中的元件组成；所述元件为第一电容C1或电阻R1。
当泄流通道由光耦U1内部的光敏三极管T1和一阶复位电路中的第一电容C1组成时，光敏三极管T1的集电极和第一电容C1的正极相连，光敏三极管T1的发射极接地；一阶复位电路中电阻R1的一端与电源VCC相连，电阻R1的另一端与第一电容C1的正极相连，第一电容C1的负极接地；一阶复位电路形成一阶积分复位电路，适用于低电平复位微处理器。
当泄流通道由光耦U1内部的光敏三极管T1和一阶复位电路中的电阻R1组成时，光敏三极管T1的发射极接地；一阶复位电路中第一电容C1的正极与电源VCC相连，第一电容C1的负极与电阻R1一端连接，并和光敏三极管T1的集电极相连，电阻R1的另一端接地；一阶复位电路形成一阶微分复位电路，适用于高电平复位微处理器。
图4中所示的抗闩锁微处理器复位电路适用于低电平复位微处理器，其包括三个部分：一阶积分复位电路、掉电检测电路和泄流通道。上述各部分电路之间通过信号线相连。下面结合附图4具体描述一下本发明各组成部分的作用：
(1)一阶积分复位电路
①主要由电阻R1和第一电容C1组成，电阻R1一端连接电源VCC，另一端连接第一电容C1的正极，第一电容C1的负极接地。
②当电源VCC上电时，由于第一电容C1充电时的暂态效应，在第一电容C1正极的电压UR初始电位等于电源地，经过一定时间的延迟，第一电容C1充电完成。在此过程中，UR逐渐变为高电平。利用这个过程为微处理器提供复位信号。在此过程中，微处理器未进入工作状态。延迟时间的长短取决于电阻R1 和第一电容C1的取值，根据设计对象的功能要求来确定延迟时间。电阻R1的阻值乘以第一电容C1的电容值被称为时间常数。
(2)掉电检测电路
①主要由二极管D1、第二电容C2和光耦内部的发光二极管VD1组成。电源VCC接二极管D1的阳极和发光二极管VD1的阴极；第二电容C2的正极、二极管D1的阴极和发光二极管VD1的阳极连接在一起；第二电容C2的负极接电源地。
②通电时，二极管D1正向导通，光耦U1内部的发光二极管VD1由于是反向通电，此时不导通，电源VCC通过二极管D1对第二电容C2充电蓄能。充电完成后，第二电容C2正极电压等于VCC。
③电源VCC掉电时，VCC电压降低，此时第二电容C2正极电压高于VCC电压，二极管D1成了反向通电，不导通；光耦U1内部的发光二极管VD1正向导通，第二电容C2储存的电能通过发光二极管VD1向电源VCC释放，形成电流IF，从而触发光耦U1内部的光敏三极管T1导通。
(3)泄流通道
①主要由光耦U1内部的光敏三极管T1和第一电容C1组成，光敏三极管T1集电极接第一电容C1正极，光敏三极管T1发射极接电源地。
②通电时，在掉电检测电路中所述的发光二极管VD1反向通电，所以光敏三极管T1不导通，此时泄流通道处于断路状态，不影响复位电路工作。
③掉电时，在掉电检测电路触发下，光敏三极管T1导通，泄流通道闭合，第一电容C1储存的电能通过光敏三极管T1形成近乎直接对地的放电，从而避免了第一电容C1放电对微处理器复位引脚RST的冲击。
图5中所示的抗闩锁微处理器复位电路适用于高电平复位微处理器，其包括三个部分：一阶微分复位电路、掉电检测电路和泄流通道。上述各部分电路之间通过信号线相连。下面结合附图5具体描述一下本发明各组成部分的作用：
(1)一阶微分复位电路
①主要由电阻R1和第一电容C1组成，第一电容C1正极连接电源VCC，第一电容C1负极连接电阻R1一端，电阻R1另一端接电源地。
②当电源VCC上电时，由于第一电容C1充电时的暂态效应，在第一电容C1负极的电压UR瞬间为高电平，随着充电进程，电路中电流逐渐减小，UR变小。经过一定时间的延迟，第一电容C1充电完成，电路中没有电流产生，UR电位等于电源地。在此过程中，UR从高电平渐变为低电平。利用这个过程为微处理器提供复位信号。在此过程中，微处理器未进入工作状态。延迟时间的长短取决于电阻R1和第一电容C1的取值，根据设计对象的功能要求来确定延迟时间。电阻R1的阻值乘以第一电容C1的电容值被称为时间常数。
(2)掉电检测电路
①主要由二极管D1、第二电容C2和光耦内部的发光二极管VD1组成。电源VCC接二极管D1的阳极和发光二极管VD1的阴极；第二电容C2的正极、二极管D1的阴极和发光二极管VD1的阳极连接在一起；第二电容C2的负极接电源地。
②通电时，二极管D1正向导通，光耦U1内部的发光二极管VD1由于是反向通电，此时不导通，电源VCC通过二极管D1对第二电容C2充电蓄能。充电完成后，第二电容C2正极电压等于VCC。
③电源VCC掉电时，VCC电压降低，此时第二电容C2正极电压高于VCC电压，二极管D1成了反向通电，不导通；光耦内部的发光二极管VD1正向导通，电容C2储存的电能通过发光二极管VD1向电源VCC释放，形成电流IF，从而触发光耦U1内部的光敏三极管T1导通。
(3)泄流通道
①主要由光耦内部的光敏三极管T1和电阻R1组成，光敏三极管T1的集电极接电阻R1与第一电容C1负极的连接点，光敏三极管T1的发射极接电源地。
②通电时，在掉电检测电路中所述的发光二极管VD1反向通电，所以光敏三极管T1不导通，此时泄流通道处于断路状态，不影响复位电路工作。
③掉电时，在掉电检测电路触发下，光敏三极管T1导通，泄流通道闭合，由于微处理器正常工作时复位引脚RST为低电平，此时，泄流通道直接将微处理器复位引脚RST通过导通的光敏三极管T1下拉为地电位，避免第一电容C1放电对微处理器复位引脚RST的影响。

Claims (3)

  1. 一种抗闩锁效应微处理器复位电路，其特征在于：包括一阶复位电路、掉电检测电路和泄流通道，掉电检测电路和一阶复位电路之间通过光耦连接；
    所述一阶复位电路由电阻和第一电容串接组成；
    掉电检测电路由二极管、第二电容和光耦内部的发光二极管组成，二极管的阳极以及发光二极管的阴极分别与电源相连，第二电容的正极、二极管的阴极分别与发光二极管的阳极相连，第二电容的负极接地；
    泄流通道由光耦内部的光敏三极管和一阶复位电路中的元件组成；所述元件为第一电容或电阻。
  2. 根据权利要求1所述的抗闩锁效应微处理器复位电路，其特征在于：当泄流通道由光耦内部的光敏三极管和一阶复位电路中的第一电容组成时，光敏三极管的集电极和第一电容的正极相连，光敏三极管的发射极接地；一阶复位电路中电阻的一端与电源相连，电阻的另一端与第一电容的正极相连，第一电容的负极接地；一阶复位电路形成一阶积分复位电路，适用于低电平复位微处理器。
  3. 根据权利要求1所述的抗闩锁效应微处理器复位电路，其特征在于：当泄流通道由光耦内部的光敏三极管和一阶复位电路中的电阻组成时，光敏三极管的发射极接地；一阶复位电路中第一电容的正极与电源相连，第一电容的负极与电阻一端连接，并和光敏三极管集电极相连，电阻另一端接地；一阶复位电路形成一阶微分复位电路，适用于高电平复位微处理器。
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