WO2016101667A1 - 一种用于δ-σ模数转换器的可配置电容阵列 - Google Patents

一种用于δ-σ模数转换器的可配置电容阵列 Download PDF

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WO2016101667A1
WO2016101667A1 PCT/CN2015/090313 CN2015090313W WO2016101667A1 WO 2016101667 A1 WO2016101667 A1 WO 2016101667A1 CN 2015090313 W CN2015090313 W CN 2015090313W WO 2016101667 A1 WO2016101667 A1 WO 2016101667A1
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capacitor
branch
node
control switch
voltage
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PCT/CN2015/090313
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French (fr)
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郑宇亮
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深圳市中兴微电子技术有限公司
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Publication of WO2016101667A1 publication Critical patent/WO2016101667A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters

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  • the present invention relates to the field of integrated circuit design technology, and in particular to a configurable capacitor array for a delta-sigma analog-to-digital converter.
  • each module constituting the communication system needs to have a configuration capability.
  • the receiver since different digital basebands are divided by communication in different carrier frequency bands, the receiver also needs to provide hardware support at different bandwidths and precisions.
  • the ⁇ - ⁇ analog-to-digital converter can be configured as a popular solution with small area, high precision and low power consumption.
  • FIG 1 is a schematic diagram of a configurable delta-sigma analog-to-digital converter.
  • a configurable capacitor array such as C1, C2
  • the branch of the configurable capacitor array is usually composed of a capacitor and a metal oxide semiconductor (MOS) switch in series. Pass or disconnect can be implemented through the configuration register. Normally, some of the configurable capacitor array branches are turned on, and some of the branches are disconnected (refer to Figure 2). For the broken branch, the connection point of the capacitor plate and the MOS switch is floating. Due to the uncontrollability of the floating point voltage, the equivalent capacitance values of the differential two-way of the analog-to-digital converter are inconsistent, resulting in deterioration of circuit performance.
  • MOS metal oxide semiconductor
  • the switches S1 and S2 are turned on, the p1 and p2 nodes are in the same voltage as the Vn node; since the switches S3 and S4 are disconnected, p3 and p4 are in a floating state, and the node voltage has the same tendency as the signal of the Vp node due to the coupling effect of the capacitance. , but the common mode level status is unknown.
  • Figure 3 is a schematic diagram of a parasitic transistor triggered by a floating node in a configurable capacitor array.
  • the node voltages of the floating nodes p3 and p4 A condition greater than the supply voltage or lower than the ground voltage may occur, causing parasitic NPN conduction (path 1) of the N-type MOS (NMOS) switch or parasitic PNP conduction (path 2) of the P-type MOS (PMOS) switch, resulting in
  • the RC time constant variation of the delta-sigma analog-to-digital converter causes the propagation delay (Propagation Delay) on the signal path to be inconsistent.
  • Embodiments of the present invention are directed to providing a configurable capacitor array for a delta-sigma analog-to-digital converter that can improve the performance of a delta-sigma analog-to-digital converter circuit.
  • Embodiments of the present invention provide a configurable capacitor array for a delta-sigma analog-to-digital converter, including at least two capacitor branches, each capacitor branch including a capacitor and a branch control switch in series, One end of the capacitor is connected to the output of the operational amplifier, and the other end of the capacitor is connected to the branch control a switch, the other end of the branch control switch is connected to an input end of the operational amplifier;
  • the configurable capacitor array further includes a node voltage control unit, and the node voltage control unit is configured to control when the branch control switch is turned on The node voltage between the capacitor in the capacitor branch to which it belongs and the branch control switch is not higher than the power supply voltage and not lower than the ground voltage.
  • the node voltage control unit is configured to connect a node between a capacitor in the capacitor branch and the branch control switch to a fixed potential node or when the branch control switch is turned on
  • the controllable node, the voltage of the fixed potential node or the controllable node is not higher than the power supply voltage and not lower than the ground voltage.
  • the node voltage control unit is configured to limit a range of variation of a node voltage between a capacitor in the capacitor branch and the branch control switch when the branch control switch is turned on, so that The node voltage is not higher than the power supply voltage and not lower than the ground voltage.
  • the node voltage control unit includes at least two bypass switches
  • a bypass switch is respectively connected to both ends of the capacitor in each capacitor branch, and the bypass switch is opened when the branch control switch in the capacitor branch is closed, and is closed when the branch control switch in the capacitor branch is opened.
  • the node voltage control unit includes at least two bypass switches
  • a bypass switch is respectively connected to both ends of the capacitor in each capacitor branch, and the bypass switch is opened when the branch control switch in the capacitor branch is closed or opened.
  • a configurable capacitor array for a delta-sigma analog-to-digital converter comprising at least two capacitor branches, each capacitor branch comprising a capacitor and a series connected in series a branch control switch, one end of the capacitor is connected to the output of the operational amplifier, the other end of the capacitor is connected to the branch control switch, and the other end of the branch control switch is connected to the input end of the operational amplifier; the configurable capacitor array A node voltage control unit is further configured to control, when the branch control switch is turned on, a node voltage between a capacitor in the capacitive branch to which the capacitor branch and the branch control switch are not higher than a power supply voltage And not lower than the ground voltage.
  • the configurable capacitor array according to the embodiment of the invention is used for the delta-sigma analog-to-digital converter, which ensures that the voltage of the floating node is not higher than the power supply voltage of the circuit and not lower than the circuit ground voltage, thereby avoiding the differential capacitance branch
  • the even harmonics caused by the mismatch of floating nodes in the road improve the performance of the delta-sigma analog-to-digital converter circuit.
  • Figure 1 is a schematic diagram of a configurable delta-sigma analog-to-digital converter
  • FIG. 2 is a schematic diagram of a configurable capacitor array
  • FIG. 3 is a schematic diagram of a parasitic transistor triggered by a floating node in a configurable capacitor array
  • FIG. 4 is a schematic diagram of a configurable capacitor array for a delta-sigma analog-to-digital converter according to an embodiment of the present invention
  • FIG. 5 is a schematic structural diagram of a configurable capacitor array for a delta-sigma analog-to-digital converter according to Embodiment 1 of the present invention
  • FIG. 6 is a schematic structural diagram of a configurable capacitor array for a delta-sigma analog-to-digital converter according to Embodiment 2 of the present invention.
  • the configurable capacitor array includes at least two capacitor branches, each of which has a capacitor branch. Included in the series is a capacitor and a way control switch, one end of the capacitor is connected to the output of the operational amplifier, the other end of the capacitor is connected to the branch control switch, and the other end of the branch control switch is connected to the input end of the operational amplifier
  • the configurable capacitor array further includes a node voltage control unit, and the node voltage control unit is configured to control the capacitance and the branch in the capacitor branch to which the branch control switch is turned on when the branch control switch is turned on Control the node voltage between the switches not Higher than the supply voltage and not lower than the ground voltage.
  • the node voltage control unit is configured to connect a node between a capacitor in the capacitor branch and the branch control switch to a fixed potential node or when the branch control switch is turned on
  • the controllable node the voltage of the fixed potential node or the controllable node is not higher than the power supply voltage and not lower than the ground voltage.
  • its floating node can be set to a fixed potential or connected to a controllable node to eliminate the influence of the floating node on the performance of the delta-sigma analog-to-digital converter. .
  • the node voltage control unit may be configured to include at least two bypass switches, and a bypass switch is respectively connected at both ends of the capacitor in each of the capacitor branches, and the bypass switch is in a branch of the associated capacitor branch.
  • the road control switch is opened when it is closed, and is closed when the branch control switch in the associated capacitor branch is opened.
  • the node voltage control unit is configured to limit a range of variation of a node voltage between a capacitor in the capacitor branch and the branch control switch when the branch control switch is turned on, so that The node voltage is not higher than the power supply voltage and not lower than the ground voltage.
  • the node voltage control unit limits the voltage variation range of the floating node, it can be ensured that the highest or lowest voltage value does not exceed the power supply voltage of the circuit or the ground voltage of the circuit to eliminate the floating node. The effect on the performance of the delta-sigma analog-to-digital converter.
  • the node voltage control unit may be configured to include at least two bypass switches, and a bypass switch is respectively connected at both ends of the capacitor in each of the capacitor branches, and the bypass switch is in a branch of the associated capacitor branch. When the road control switch is closed or opened, it is turned on.
  • the embodiment of the invention can ensure that the voltage variation range of the floating node of the configurable array does not exceed the operating voltage range of the circuit, thereby avoiding the parasitic NPN or PNP of the triggering MOS tube, and eliminating the ⁇ - ⁇ analog-to-digital conversion of the floating node. The impact of device performance.
  • the node voltage control unit includes at least two bypass switches, and the node is electrically When the branch control switch is turned on, the voltage control unit connects the node between the capacitor in the capacitor branch and the branch control switch to a fixed potential node or a controllable node, and the fixed potential node or the controllable node The voltage is not higher than the power supply voltage and not lower than the ground voltage.
  • Both ends of C1; S6 is connected to two points of Vp and P2, across the two ends of capacitor C2; S7 is connected to two points of Vp and P3, across the two ends of capacitor C3; S8 is connected to two points of Vp and P4, across capacitor C4 end.
  • S1 and S2 branches since S1 and S2 are turned on, S5 and S6 are disconnected to avoid affecting the normal operation of the circuit; for the C3 and C4 branches, the P3 and P4 nodes become floating due to the disconnection of S3 and S4.
  • Nodes, conducting S7 and S8, P3 and P4 are connected to the Vp node, shorting capacitors C3 and C4, eliminating the effects of floating nodes P3 and P4 on the performance of the delta-sigma analog-to-digital converter.
  • the node voltage control unit includes at least two bypass switches, and the node voltage control unit limits the node voltage between the capacitor in the capacitor branch and the branch control switch when the branch control switch is turned on.
  • the range of variation is such that the node voltage is not higher than the power supply voltage and not lower than the ground voltage.
  • the embodiment of the present invention includes a configurable capacitor array including at least two capacitor branches, each of the capacitor branches includes a capacitor and a branch control switch connected in series, one end of the capacitor is connected to an output of the operational amplifier, and the capacitor is The other end is connected to the branch control switch, and the other end of the branch control switch is connected to the input end of the operational amplifier;
  • the configurable capacitor array further includes a node voltage control unit, and the node voltage control unit is configured to be in the branch When the control switch is turned on, the node voltage between the capacitor in the capacitor branch to which it belongs and the branch control switch is controlled to be no higher than the power supply voltage and not lower than the ground voltage.
  • the configurable capacitor array is used in the delta-sigma analog-to-digital converter to ensure that the voltage of the floating node is not higher than the power supply voltage of the circuit and not lower than the circuit ground voltage, thereby avoiding the difference in the differential capacitor branch.
  • the even harmonics caused by the mismatch of floating nodes improve the performance of the delta-sigma analog-to-digital converter circuit.

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  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

一种用于Δ-Σ模数转换器的可配置电容阵列，包括至少两条电容支路，每条电容支路包括串联的一电容和一支路控制开关，电容的一端连接运算放大器输出端，所述电容的另一端连接支路控制开关，所述支路控制开关的另一端连接运算放大器的输入端；所述可配置电容阵列还包括节点电压控制单元，所述节点电压控制单元配置为在所述支路控制开关打开时，控制其所属电容支路中电容与支路控制开关之间的节点电压不高于电源电压且不低于地电压。

Description

一种用于Δ-Σ模数转换器的可配置电容阵列 技术领域
本发明涉及集成电路设计技术领域，具体涉及一种用于Δ-Σ模数转换器的可配置电容阵列。
背景技术
随着无线通信领域的迅速兴起，为降低功耗，提高系统集成度，减少设计成本，大量的信号处理功能从模拟域转移到数字域完成，因此需要高性能的模数转换器实现从模拟域到数字域的转换。
为了支持多种通信标准的中频可编程数字接入能力，构成通信系统的各个模块都需要具有配置能力。另外，在各种通信协议中，由于在不同的载波频段通信而划分不同的数字基带，因此接收机也需要在不同带宽和精度上提供硬件支持。针对上述应用背景，可配置Δ-Σ模数转换器以其面积小，精度高，功耗低而成为热门的解决方案。
图1为可配置Δ-Σ模数转换器示意图，如图1所示，在可配置的Δ-Σ模数转换器中，可配置电容阵列(如C1、C2)是其中重要的组成部分，与电阻阵列和运算放大器一起构成积分器形式。图2为一种具体的可配置电容阵列框图，如图2所示，可配置的电容阵列的支路通常由电容和金属氧化物半导体(MOS，Metal Oxide Semiconductor)开关串联组成，MOS开关的导通或者断开可以通过配置寄存器实现。通常情况下，可配置电容阵列部分支路导通，部分支路断开(参考图2)，对于断开的支路，电容极板和MOS开关的连接点处于浮空状态。由于浮空点电压的不可控性，会导致模数转换器的差分两路的等效电容值不一致，导致电路性能的恶化。
具体来说，如果两个完全相同的电容阵列(参考图2)分别连接在Δ- Σ模数转换器差分通路上，形成通路1和通路2。在Δ-Σ模数转换器中，两个电容阵列的Vn节点都连接到运算放大器的输入端，由于运放的虚地特性，两个Vn节点电压近似相等；两个电容阵列的Vp节点都连接到运算放大器的输出端，两个Vp节点的信号幅度相等，相位相反。因为开关S1和S2导通，p1和p2节点与Vn节点电压一致；因为开关S3和S4断开，p3和p4处于浮空状态，其节点电压由于电容的耦合效应与Vp节点的信号变化趋势相同，但共模电平状态未知。
图3为由可配置电容阵列中浮空节点触发的寄生三极管示意图，如图3所示，当Δ-Σ模数转换器的信号幅度变化较大时，浮空节点p3和p4的节点电压极可能出现大于电源电压或者低于地电压的情况，从而造成N型MOS(NMOS)开关的寄生NPN导通(通路1)或者P型MOS(PMOS)开关的寄生PNP导通(通路2)，造成Δ-Σ模数转换器的RC时间常数变化(RC Time Constant Variation)，引起信号通路上的传输延迟(Propagation Delay)不一致，参考图3，由于NPN和PNP都是寄生器件，无法达到对称性要求，会使积分器的等效电容值不相等，进而造成偶次谐波的出现，恶化Δ-Σ模数转换器电路性能；并且，在电容阵列中，如果断开的支路的电容值(如C3和C4)大于导通的支路的电容值(如C1和C2)，偶次谐波现象会更加明显、Δ-Σ模数转换器电路性能更差。
发明内容
本发明实施例期望提供一种用于Δ-Σ模数转换器的可配置电容阵列，能够提高Δ-Σ模数转换器电路性能。
本发明实施例的技术方案是这样实现的：
本发明实施例提供了一种用于Δ-Σ模数转换器的可配置电容阵列，包括至少两条电容支路，每条电容支路包括串联的一电容和一支路控制开关，所述电容的一端连接运算放大器输出端，所述电容的另一端连接支路控制 开关，所述支路控制开关的另一端连接运算放大器的输入端；所述可配置电容阵列还包括节点电压控制单元，所述节点电压控制单元配置为在所述支路控制开关打开时，控制其所属电容支路中电容与所述支路控制开关之间的节点电压不高于电源电压且不低于地电压。
一具体实施例中，所述节点电压控制单元，配置为在所述支路控制开关打开时，将其所属电容支路中电容与所述支路控制开关之间的节点连接至固定电位节点或可控节点，所述固定电位节点或所述可控节点的电压不高于电源电压且不低于地电压。
一具体实施例中，所述节点电压控制单元，配置为在所述支路控制开关打开时，限制其所属电容支路中电容与所述支路控制开关之间节点电压的变化范围，使得所述节点电压不高于电源电压且不低于地电压。
一具体实施例中，所述节点电压控制单元包括至少两个旁路开关，
每个电容支路中的电容两端分别并联一旁路开关，所述旁路开关在所属电容支路中的支路控制开关闭合时打开，在所属电容支路中的支路控制开关打开时闭合。
一具体实施例中，所述节点电压控制单元包括至少两个旁路开关，
每个电容支路中的电容两端分别并联一旁路开关，所述旁路开关在所属电容支路中的支路控制开关闭合或打开时，均打开。
本发明实施例所述的一种用于Δ-Σ模数转换器的可配置电容阵列，所述可配置电容阵列包括至少两条电容支路，每条电容支路包括串联的一电容和一支路控制开关，所述电容的一端连接运算放大器输出端，所述电容的另一端连接支路控制开关，所述支路控制开关的另一端连接运算放大器的输入端；所述可配置电容阵列还包括节点电压控制单元，所述节点电压控制单元配置为在所述支路控制开关打开时，控制其所属电容支路中电容与所述支路控制开关之间的节点电压不高于电源电压且不低于地电压。将 本发明实施例所述的可配置电容阵列用于Δ-Σ模数转换器，保证了浮空节点的电压不高于电路的电源电压且不低于电路地电压，从而避免了由于差分电容支路中浮空节点不匹配造成的偶次谐波，提高了Δ-Σ模数转换器电路性能。
附图说明
图1为可配置Δ-Σ模数转换器示意图；
图2为可配置的电容阵列示意图；
图3为由可配置电容阵列中浮空节点触发的寄生三极管示意图；
图4为本发明实施例一种用于Δ-Σ模数转换器的可配置电容阵列示意图；
图5为本发明实施例1所述用于Δ-Σ模数转换器的可配置电容阵列结构示意图；
图6为本发明实施例2所述用于Δ-Σ模数转换器的可配置电容阵列结构示意图。
具体实施方式
本发明实施例的目的在于提供一种用于Δ-Σ模数转换器的可配置电容阵列，避免电容阵列中的浮空节点对于Δ-Σ模数转换器电路性能影响。
图4为本发明实施例一种用于Δ-Σ模数转换器的可配置电容阵列示意图，如图4所示，所述可配置电容阵列包括至少两条电容支路，每条电容支路包括串联的一电容和一支路控制开关，所述电容的一端连接运算放大器输出端，所述电容的另一端连接支路控制开关，所述支路控制开关的另一端连接运算放大器的输入端；本实施例中，所述可配置电容阵列还包括节点电压控制单元，所述节点电压控制单元配置为在所述支路控制开关打开时，控制其所属电容支路中电容与所述支路控制开关之间的节点电压不 高于电源电压且不低于地电压。
一具体实施例中，所述节点电压控制单元，配置为在所述支路控制开关打开时，将其所属电容支路中电容与所述支路控制开关之间的节点连接至固定电位节点或可控节点，所述固定电位节点或所述可控节点的电压不高于电源电压且不低于地电压。这样，对于电容阵列中断开的支路，便可将其浮空节点设置到某一固定电位或者连接到某一可控节点，以消除浮空节点对于Δ-Σ模数转换器性能的影响。为了实现上述方案，可以设置所述节点电压控制单元包括至少两个旁路开关，每个电容支路中的电容两端分别并联一旁路开关，所述旁路开关在所属电容支路中的支路控制开关闭合时打开，在所属电容支路中的支路控制开关打开时闭合。
一具体实施例中，所述节点电压控制单元，配置为在所述支路控制开关打开时，限制其所属电容支路中电容与所述支路控制开关之间节点电压的变化范围，使得所述节点电压不高于电源电压且不低于地电压。这样，对于电容阵列中断开的支路，通过限制其浮空节点的电压变化范围，即可保证其最高或最低电压值不会超出电路的电源电压或者电路的地电压，以消除浮空节点对于Δ-Σ模数转换器性能的影响。为了实现上述方案，可以设置所述节点电压控制单元包括至少两个旁路开关，每个电容支路中的电容两端分别并联一旁路开关，所述旁路开关在所属电容支路中的支路控制开关闭合或打开时，均打开。
本发明实施例可保证可配置阵列的浮空节点的电压变化范围不会超出电路的工作电压范围，从而能够避免触发MOS管的寄生NPN或者PNP，消除了浮空节点对Δ-Σ模数转换器性能的影响。
下面通过具体实施例对本发明的技术方案作进一步详细说明。
实施例1
本实施例中，节点电压控制单元包括至少两个旁路开关，所述节点电 压控制单元在支路控制开关打开时，将其所属电容支路中电容与所述支路控制开关之间的节点连接至固定电位节点或可控节点，所述固定电位节点或可控节点的电压不高于电源电压且不低于地电压。
图5为本发明实施例1所述用于Δ-Σ模数转换器的可配置电容阵列结构示意图，如图5所示，电容Ci与MOS开关Si(i＝1，2，3，4)串联构成电容阵列的可配置支路，Si(i＝5，6，7，8)分别连接于每路可配置电容支路的电容两端，即S5连接到Vp和P1两点，横跨电容C1两端；S6连接到Vp和P2两点，横跨电容C2两端；S7连接到Vp和P3两点，横跨电容C3两端；S8连接到Vp和P4两点，横跨电容C4两端。对于C1和C2支路，由于S1和S2导通，S5和S6断开，避免影响到电路的正常工作；对于C3和C4支路，由于S3和S4断开，P3和P4节点变为浮空节点，导通S7和S8，P3和P4连接到Vp节点，将电容C3和C4短路，可消除浮空节点P3和P4对于Δ-Σ模数转换器性能的影响。Si(i＝1，2，3，4，5，6，7，8)的控制方式为S1⊕S5＝1，S2⊕S6＝1，S3⊕S7＝1，S4⊕S8＝1。
实施例2
本实施例中，节点电压控制单元包括至少两个旁路开关，所述节点电压控制单元在支路控制开关打开时，限制其所属电容支路中电容与所述支路控制开关之间节点电压的变化范围，使得所述节点电压不高于电源电压且不低于地电压。
图6为本发明实施例2所述用于Δ-Σ模数转换器的可配置电容阵列结构示意图，如图6所示，电容Ci与MOS开关Si(i＝1，2，3，4)串联构成电容阵列的可配置支路，Si(i＝5，6，7，8)分别连接于每路可配置电容支路的电容两端，即S5连接到Vp和P1两点，横跨电容C1两端；S6连接到Vp和P2两点，横跨电容C2两端；S7连接到Vp和P3两点，横跨电容C3两端；S8连接到Vp和P4两点，横跨电容C4两端。与实施例1 不同的是，无论电路处于何种工作状态，均保证Si(i＝5，6，7，8)断开。Si(i＝5，6，7，8)为MOS管开关，在其关断状态下，有nA级别漏电流，可以等效为一个大电阻，限制了浮空节点的共模电平范围，保证浮空节点的电压变化范围不会超过电路的工作电压范围。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
本发明实施例通过包括至少两条电容支路的可配置电容阵列，每条电容支路包括串联的一电容和一支路控制开关，所述电容的一端连接运算放大器输出端，所述电容的另一端连接支路控制开关，所述支路控制开关的另一端连接运算放大器的输入端；所述可配置电容阵列还包括节点电压控制单元，所述节点电压控制单元配置为在所述支路控制开关打开时，控制其所属电容支路中电容与所述支路控制开关之间的节点电压不高于电源电压且不低于地电压。如此，将所述可配置电容阵列用于Δ-Σ模数转换器，保证了浮空节点的电压不高于电路的电源电压且不低于电路地电压，从而避免了由于差分电容支路中浮空节点不匹配造成的偶次谐波，提高了Δ-Σ模数转换器电路性能。

Claims (5)

  1. 一种用于Δ-Σ模数转换器的可配置电容阵列，包括至少两条电容支路，每条电容支路包括串联的一电容和一支路控制开关，所述电容的一端连接运算放大器输出端，所述电容的另一端连接支路控制开关，所述支路控制开关的另一端连接运算放大器的输入端；
    所述可配置电容阵列还包括节点电压控制单元，所述节点电压控制单元配置为在所述支路控制开关打开时，控制其所属电容支路中电容与所述支路控制开关之间的节点电压不高于电源电压且不低于地电压。
  2. 根据权利要求1所述的可配置电容阵列，其中，
    所述节点电压控制单元，配置为在所述支路控制开关打开时，将其所属电容支路中电容与所述支路控制开关之间的节点连接至固定电位节点或可控节点，所述固定电位节点或所述可控节点的电压不高于电源电压且不低于地电压。
  3. 根据权利要求1所述的可配置电容阵列，其中，
    所述节点电压控制单元，配置为在所述支路控制开关打开时，限制其所属电容支路中电容与所述支路控制开关之间节点电压的变化范围，使得所述节点电压不高于电源电压且不低于地电压。
  4. 根据权利要求2所述的可配置电容阵列，其中，所述节点电压控制单元包括至少两个旁路开关，
    每个电容支路中的电容两端分别并联一旁路开关，所述旁路开关在所属电容支路中的支路控制开关闭合时打开，在所属电容支路中的支路控制开关打开时闭合。
  5. 根据权利要求3所述的可配置电容阵列，其中，所述节点电压控制单元包括至少两个旁路开关，
    每个电容支路中的电容两端分别并联一旁路开关，所述旁路开关在所 属电容支路中的支路控制开关闭合或打开时，均打开。
PCT/CN2015/090313 2014-12-22 2015-09-22 一种用于δ-σ模数转换器的可配置电容阵列 WO2016101667A1 (zh)

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CN101859107A (zh) * 2009-04-07 2010-10-13 西门子（中国）有限公司 一种可配置混合信号控制系统及方法
CN102629874A (zh) * 2011-02-04 2012-08-08 索尼公司 δ-σ调制器与信号处理系统

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