WO2016101402A1 - 低温多晶硅薄膜晶体管及其制造方法 - Google Patents

低温多晶硅薄膜晶体管及其制造方法 Download PDF

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WO2016101402A1
WO2016101402A1 PCT/CN2015/072595 CN2015072595W WO2016101402A1 WO 2016101402 A1 WO2016101402 A1 WO 2016101402A1 CN 2015072595 W CN2015072595 W CN 2015072595W WO 2016101402 A1 WO2016101402 A1 WO 2016101402A1
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layer
thin film
light shielding
film transistor
convex portion
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French (fr)
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李金明
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3454—Amorphous
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a low temperature polysilicon thin film transistor and a method of fabricating the same.
  • a flat panel display device is the most commonly used display device.
  • the active matrix flat panel display device controls the input of data signals through a Thin Film Transistor (TFT) to control the picture. display.
  • TFT Thin Film Transistor
  • the current display technology is developing in the direction of high resolution.
  • the resolution of mobile phones has reached the level of 1080P (1080 ⁇ 1920), and the resolution of TVs has reached the level of 4K (4096 ⁇ 2160), accompanied by resolution.
  • the continuous improvement of the rate requires continuous improvement of the driving capability of TFT devices. Therefore, low temperature poly-silicon (LTPS) thin film transistor display devices having high resolution, fast response speed, high brightness, high aperture ratio and the like are also attracting more and more attention, in order to satisfy high resolution display devices.
  • LTPS low temperature poly-silicon
  • the driving capability requires that the on-state current of the pixel area and the driving area of the display device be increased, and the method of increasing the on-state current is to increase the aspect ratio of the TFT device channel.
  • the on-state current I D and the TFT device are required.
  • Channel width to length ratio The relevant formula is: linear region: Saturated area: From the above formula, it can be determined that there are two ways to increase the on-state current for both the linear region and the saturation region. One is to increase the channel width W, but as the channel width W increases, the aperture ratio of the display device will also increase. This is reduced, thereby reducing the space of the panel design. Second, the channel length L is reduced. However, if the channel length L is too small, the risk of channel breakdown is increased, and thus the range of the channel length L is very limited.
  • the aspect ratio increases the on-state current, which in turn improves the drive capability and device performance of the low temperature polysilicon thin film transistor.
  • the polysilicon thin film transistor has excellent driving ability and device performance.
  • the present invention firstly provides a low temperature polysilicon thin film transistor, comprising: a substrate, a light shielding layer disposed on the substrate, a liner layer disposed on the light shielding layer, and disposed on the liner layer a dielectric layer, an active layer disposed on the dielectric layer, a gate insulating layer disposed on the active layer, and a gate layer disposed on the gate insulating layer;
  • the light shielding layer includes a flat portion disposed on the substrate, and a convex portion disposed on the flat portion;
  • the projection of the active layer covers at least a partial region of the upper surface of the raised portion and a sidewall of the raised portion.
  • the material of the light shielding layer is molybdenum.
  • the light shielding layer has a thickness of 800 to 2500 angstroms at the convex portion, and the height of the convex portion is 300 to 800 angstroms, and an angle between the side walls of the convex portion and the lining layer It is 35° to 70°.
  • the material of the liner layer is silicon nitride and has a thickness of 400 to 500 angstroms; the dielectric layer is made of silicon dioxide and has a thickness of 1000 to 2000 angstroms.
  • the active layer has a thickness of 400 to 500 angstroms.
  • the invention also provides a method for manufacturing a low temperature polysilicon thin film transistor, comprising the following steps:
  • Step 1 providing a substrate, depositing a light shielding layer on the substrate by a physical vapor deposition process, forming a flat portion and a convex portion of the light shielding layer by gray scale exposure and etching;
  • Step 2 sequentially forming a liner layer and a dielectric layer on the light shielding by a plasma enhanced chemical vapor deposition process
  • Step 3 depositing an amorphous silicon layer on a portion of the dielectric layer corresponding to the convex portion of the light shielding layer, the projection of the amorphous silicon layer covering the entire convex portion, and then converting the amorphous silicon layer a polysilicon layer;
  • Step 4 etching the polysilicon layer to form an active layer, the active layer covering at least a partial region of the upper surface of the convex portion and a sidewall of the convex portion;
  • Step 5 sequentially depositing and etching a gate insulating layer and a gate over the active layer Floor.
  • the material of the light shielding layer in the step 1 is molybdenum.
  • the light shielding layer in the step 1 has a thickness of 800 to 2500 angstroms at the convex portion, and the height of the convex portion is 300 to 800 angstroms, both side walls of the convex portion and the spacer The angle between the layers is 35° to 70°.
  • the material of the liner layer in the step 2 is silicon nitride and has a thickness of 400 to 500 angstroms; the dielectric layer is made of silicon dioxide and has a thickness of 1000 to 2000 angstroms.
  • the thickness of the active layer in the step 4 is 400 to 500 angstroms.
  • the present invention also provides a low temperature polysilicon thin film transistor, comprising: a substrate, a light shielding layer disposed on the substrate, a liner layer disposed on the light shielding layer, a dielectric layer disposed on the liner layer, and a device An active layer on the dielectric layer, a gate insulating layer disposed on the active layer, and a gate layer disposed on the gate insulating layer;
  • the light shielding layer includes a flat portion disposed on the substrate, and a convex portion disposed on the flat portion;
  • the projection of the active layer covers at least a partial region of the upper surface of the convex portion and a sidewall of the convex portion;
  • the material of the light shielding layer is molybdenum
  • the material of the liner layer is silicon nitride and has a thickness of 400 to 500 angstroms; the material of the dielectric layer is silicon dioxide and has a thickness of 1000 to 2000 angstroms.
  • the present invention provides a low-temperature polysilicon thin film transistor and a method of fabricating the same, which is provided by providing a light-shielding layer having a protrusion on a substrate and then providing a remaining portion on the light-shielding layer, thereby effectively increasing the low-temperature polysilicon film
  • the channel width of the transistor and the aspect ratio of the channel improve the on-state current, improve the driving capability and device performance of the low-temperature polysilicon thin film transistor, and do not affect the aperture ratio of the display device, and the manufacturing method is simple and easy to operate.
  • 1 is a schematic plan view of a low temperature polysilicon thin film transistor
  • FIG. 2 is a cross-sectional view of the low temperature polysilicon thin film transistor of the present invention taken along line A-A;
  • FIG. 3 is a flow chart of a method of fabricating a low temperature polysilicon thin film transistor of the present invention.
  • the low temperature polysilicon thin film transistor includes a gate 100, a source 200, a drain 300, and an active layer 400, the source 200 and the drain
  • the poles 300 are in contact with the active layer 400 through the vias 500, respectively.
  • the present invention provides a low temperature polysilicon thin film transistor comprising: a substrate 1, a light shielding layer 2 disposed on the substrate 1, and a liner layer 3 on the light shielding layer 2, a dielectric layer 4 disposed on the liner layer 3, an active layer 5 disposed on the dielectric layer 4, and the active layer 5 a gate insulating layer 6, a gate layer 7 provided on the gate insulating layer 6;
  • the light shielding layer 2 includes a flat portion 21 provided on the substrate 1 and a convex portion 22 provided on the flat portion 21; the material of the light shielding layer 2 is molybdenum.
  • the light shielding layer 2 has a thickness of 800 to 2500 angstroms at the convex portion 22, the height of the convex portion 22 is 300 to 800 angstroms, and the side walls 224 of the convex portion 22 and the spacer The angle between the layers 3 is 35° to 70°.
  • the material of the liner layer 3 is silicon nitride and has a thickness of 400 to 500 angstroms; the dielectric layer 4 is made of silicon dioxide and has a thickness of 1000 to 2000 angstroms.
  • the backing layer 3 and the dielectric layer 4 together form a buffer layer.
  • the projection of the active layer 5 covers at least a partial area of the upper surface of the raised portion 22 and a side wall 224 of the raised portion 22.
  • the active layer 5 has a thickness of 400 to 500 angstroms.
  • the present invention further provides a method for manufacturing a low temperature polysilicon thin film transistor, comprising the following steps:
  • Step 1 providing a substrate 1, depositing a light shielding layer 2 on the substrate 1 by a physical vapor deposition process, forming a flat portion 21 and a raised portion 22 of the light shielding layer 2 by gray scale exposure and etching;
  • the material of the light shielding layer 2 is molybdenum or other similar metal or organic material
  • the light shielding layer 2 has a thickness of 800 to 2500 angstroms at the convex portion 22, and the height of the convex portion 22 is 300. Up to 800 angstroms, the angle between the side walls 224 of the raised portion 22 and the backing layer 3 is 35 to 70.
  • the flat portion 21 and the convex portion 22 of the light shielding layer 2 are formed by dry etching using a semi-transparent mask process.
  • Step 2 using a plasma enhanced chemical vapor deposition process on the light shielding layer 2 sequentially deposited to form a liner layer 3, and a dielectric layer 4;
  • the deposition temperature is 400 to 450 degrees
  • the material of the liner layer 3 is silicon nitride
  • the thickness is 400 to 500 angstroms
  • the dielectric layer 4 is made of silicon dioxide and has a thickness of 1000 to 2000. Ai.
  • the backing layer 3 and the dielectric layer 4 together form a buffer layer.
  • Step 3 depositing an amorphous silicon layer on the dielectric layer 2 corresponding to the convex portion 22 of the light shielding layer 2, the projection of the amorphous silicon layer covering the entire convex portion 22, and then the non- Converting the crystalline silicon layer into a polysilicon layer;
  • the amorphous silicon layer is deposited by a chemical vapor deposition process at a temperature of 400 ° C to 500 ° C, and the deposited amorphous silicon layer has a thickness of 400 to 500 ⁇ .
  • the amorphous silicon layer is converted into a polysilicon layer by excimer laser annealing (ELA) or solid phase crystallization (SPC).
  • Step 4 etching the polysilicon layer to form an active layer 5, the active layer 5 covers at least a partial region of the upper surface of the raised portion 22 and a sidewall 224 of the raised portion 22;
  • the active layer 5 has a thickness of 400 to 500 angstroms.
  • Step 5 sequentially depositing and etching a gate insulating layer 6 and a gate layer 7 over the active layer 5.
  • the manufacturing method of the low temperature polysilicon thin film transistor may further include:
  • Step 6 On the surface of the substrate 1 having the gate layer 7, a dielectric layer is deposited, and the material of the dielectric layer may be silicon oxide or silicon nitride; then the ohmic contact region is used in the source by photolithography and etching processes. And a dielectric layer above the drain ohmic region and a contact hole in the gate insulating layer 6 forming a direct source and a contact hole directly reaching the drain;
  • Step 7 finally depositing a second metal layer on the surface of the substrate 1, such as an aluminum layer, a tungsten layer, a chromium layer or other metal single layer or a composite multilayer conductive layer; and then forming a source by photolithography and etching processes And the drain, so that the signal can be electrically connected from the source to the drain to complete the fabrication process of the entire low temperature polysilicon thin film transistor.
  • a second metal layer such as an aluminum layer, a tungsten layer, a chromium layer or other metal single layer or a composite multilayer conductive layer
  • the present invention provides a low-temperature polysilicon thin film transistor and a method of fabricating the same, which can effectively increase the low-temperature polysilicon thin film transistor by disposing a light-shielding layer having a bump on the substrate and then providing the remaining portion on the light-shielding layer.
  • the width of the channel and the aspect ratio of the channel increase the on-state current, thereby improving the driving capability and device performance of the low-temperature polysilicon thin film transistor without affecting the aperture ratio of the display device, and the manufacturing method is simple and easy to operate. .

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal (AREA)

Abstract

一种低温多晶硅薄膜晶体管及其制造方法，包括：基板(1)、设于基板(1)上的遮光层(2)、设于遮光层(2)上的衬垫层(3)、设于衬垫层上的介质层(4)、设于介质层上的有源层(5)、设于有源层(5)上的栅极绝缘层(6)、设于栅极绝缘层(6)上的栅极层(7)；其中，遮光层(2)包括设于基板(1)上的平坦部(21)、及设于平坦部(21)上的凸起部(22)；有源层(5)的投影至少覆盖所述凸起部(22)的上表面局部区域及所述凸起部(22)的一个侧壁(224)，能够在不改变显示装置开口率的前提下，有效地增加沟道宽度，增加沟道的宽长比，提高了开态电流，提升低温多晶硅薄膜晶体管的驱动能力及器件性能。

Description

低温多晶硅薄膜晶体管及其制造方法 技术领域
本发明涉及显示技术领域，尤其涉及一种低温多晶硅薄膜晶体管及其制造方法。
背景技术
随着显示技术的发展，平板显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
主动矩阵式(Active Matrix，AM)平板显示装置是目前最常用的显示装置，所述主动矩阵式平板显示装置通过一薄膜晶体管开关(Thin Film Transistor，TFT)来控制数据信号的输入，进而控制画面显示。
目前的显示技术朝着高分辨率的方向不断发展，例如手机的分辨率已经达到1080P的水准(1080×1920)，而电视的分辨率更是达到4K(4096×2160)的级别，伴随着分辨率的不断提升，需要不断提高TFT器件的驱动能力。因而，具有高分辨率、反应速度快、高亮度、高开口率等优点的低温多晶硅(Low Temperature Poly-silicon，LTPS)薄膜晶体管显示装置也越来越受关注，为了满足高分辨率的显示装置的驱动能力要求，需要提高显示装置像素区和驱动区的开态电流，提高开态电流的方法为增大TFT器件沟道的宽长比，具体的，所述开态电流ID与TFT器件沟道的宽长比
Figure PCTCN2015072595-appb-000001
的相关公式为：线性区:
Figure PCTCN2015072595-appb-000002
饱和区：
Figure PCTCN2015072595-appb-000003
从上述公式可确定，无论是对于线性区还是饱和区，提高开态电流都有两种方法，一是增加沟道宽度W，但是随着沟道宽度W的增加，显示装置的开口率也会随之降低，从而降低面板设计的空间；二是减小沟道长度L，但是沟道长度L过小会增加沟道被击穿风险，因此在沟道长度L的变化上范围十分有限。
发明内容
本发明的目的在于提供一种低温多晶硅薄膜晶体管，用于驱动主动矩阵式显示器件，该低温多晶硅薄膜晶体管能够在不改变显示装置开口率的前提下，有效地增加沟道宽度，增加沟道的宽长比，提高了开态电流，进而提升了低温多晶硅薄膜晶体管的驱动能力及器件性能。
本发明的目的还在于提供一种低温多晶硅薄膜晶体管的制造方法，采用该法能够制造具有较大的沟道宽度与沟道的宽长比低温多晶硅薄膜晶体管，进而提高开态电流，使得该低温多晶硅薄膜晶体管具有优异的驱动能力及器件性能。
为实现上述目的，本发明首先提供一种低温多晶硅薄膜晶体管，包括:基板、设于所述基板上的遮光层、设于所述遮光层上的衬垫层、设于所述衬垫层上的介质层、设于所述介质层上的有源层、设于所述有源层上的栅极绝缘层、设于所述栅极绝缘层上的栅极层；
其中，所述遮光层包括设于所述基板上的平坦部、及设于所述平坦部上的凸起部；
所述有源层的投影至少覆盖所述凸起部的上表面局部区域及所述凸起部的一个侧壁。
所述遮光层的材料为钼。
所述遮光层位于凸起部处的厚度为800至2500埃，所述凸起部的高度为300至800埃，所述凸起部的两侧侧壁与所述衬垫层之间的角度为35°至70°。
所述衬垫层的材料为氮化硅，厚度为400至500埃；所述介质层的材料为二氧化硅，厚度为1000至2000埃。
所述有源层的厚度为400至500埃。
本发明还提供一种低温多晶硅薄膜晶体管的制造方法，包括如下步骤：
步骤1、提供一基板，在所述基板上通过物理气相沉积工艺沉积一遮光层，通过灰阶曝光和刻蚀形成所述遮光层的平坦部与凸起部；
步骤2、采用等离子增强化学气相沉积工艺在所述遮光上依次沉积形成衬垫层、及介质层；
步骤3、在介质层上与所述遮光层的凸起部相对应的区域沉积一非晶硅层，所述非晶硅层的投影覆盖整个凸起部，然后将所述非晶硅层转化为多晶硅层；
步骤4、刻蚀所述多晶硅层形成一有源层，所述有源层至少覆盖在所述凸起部上表面的局部区域及所述凸起部的一个侧壁上；
步骤5、在所述有源层的上方依次沉积并刻蚀形成栅极绝缘层及栅极 层。
所述步骤1中所述遮光层的材料为钼。
所述步骤1中所述遮光层位于凸起部处的厚度为800至2500埃，所述凸起部的高度为300至800埃，所述凸起部的两侧侧壁与所述衬垫层之间的角度为35°至70°。
所述步骤2中所述衬垫层的材料为氮化硅，厚度为400至500埃；所述介质层的材料为二氧化硅，厚度为1000至2000埃。
所述步骤4中所述有源层的厚度为400至500埃。
本发明还提供一种低温多晶硅薄膜晶体管，包括:基板、设于所述基板上的遮光层、设于所述遮光层上的衬垫层、设于所述衬垫层上的介质层、设于所述介质层上的有源层、设于所述有源层上的栅极绝缘层、设于所述栅极绝缘层上的栅极层；
其中，所述遮光层包括设于所述基板上的平坦部、及设于所述平坦部上的凸起部；
所述有源层的投影至少覆盖所述凸起部的上表面局部区域及所述凸起部的一个侧壁；
其中，所述遮光层的材料为钼；
其中，所述衬垫层的材料为氮化硅，厚度为400至500埃；所述介质层的材料为二氧化硅，厚度为1000至2000埃。
本发明的有益效果：本发明提供一种低温多晶硅薄膜晶体管及其制造方法，通过在基板上设置一具有凸起的遮光层，再在遮光层上设置其余部分，有效地增加了该低温多晶硅薄膜晶体管沟道宽度和沟道的宽长比，提高了开态电流，提升了低温多晶硅薄膜晶体管的驱动能力及器件性能，且不影响显示器件的开口率，采用的制造方法工艺简单，易于操作。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为一种低温多晶硅薄膜晶体管的平面示意图；
图2为本发明的低温多晶硅薄膜晶体管沿A-A线截面图；
图3为本发明的低温多晶硅薄膜晶体管的制造方法的流程图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
图1为一种低温多晶硅薄膜晶体管的平面示意图；如图1所示，所述低温多晶硅薄膜晶体管包括栅极100、源极200、漏极300及有源层400，所述源极200与漏极300分别通过过孔500与有源层400相接触。
图2为本发明的低温多晶硅薄膜晶体管沿A-A线截面图，如图2所示，本发明提供一种低温多晶硅薄膜晶体管，包括:基板1、设于所述基板1上的遮光层2、设于所述遮光层2上的衬垫层3、设于所述衬垫层3上的介质层4、设于所述介质层4上的有源层5、设于所述有源层5上的栅极绝缘层6、设于所述栅极绝缘层6上的栅极层7；
具体的，所述遮光层2包括设于所述基板1上的平坦部21、及设于所述平坦部21上的凸起部22；所述遮光层2的材料为钼。所述遮光层2位于凸起部22处的厚度为800至2500埃，所述凸起部22的高度为300至800埃，所述凸起部22的两侧侧壁224与所述衬垫层3之间的角度为35°至70°。通过在所述遮光层2上制备凸起部22，可以在不改变显示装置开口率的前提下，有效地增加沟道宽度。
进一步的，所述衬垫层3的材料为氮化硅，厚度为400至500埃；所述介质层4的材料为二氧化硅，厚度为1000至2000埃。所述衬垫层3和介质层4共同构成缓冲层。
此外，所述有源层5的投影至少覆盖所述凸起部22的上表面局部区域及所述凸起部22的一个侧壁224。所述有源层5的厚度为400至500埃。
请参阅图2及图3，本发明还提供了一种低温多晶硅薄膜晶体管的制造方法，包括如下步骤：
步骤1、提供一基板1，在所述基板1上通过物理气相沉积工艺沉积一遮光层2，通过灰阶曝光和刻蚀形成所述遮光层2的平坦部21与凸起部22；
具体的，所述遮光层2的材料为钼或其他类似的金属或有机材料，所述遮光层2位于凸起部22处的厚度为800至2500埃，所述凸起部22的高度为300至800埃，所述凸起部22的两侧侧壁224与所述衬垫层3之间的角度为35°至70°。通过在所述遮光层2上制备凸起部22，然后在所述凸起部22上形成有源层，可以在不改变显示装置开口率的前提下，有效地增加的沟道宽度。
具体的，采用半透掩模工艺，利用干刻蚀形成所述遮光层2的平坦部21和的凸起部22。
步骤2、采用等离子增强化学气相沉积工艺在所述遮光层2上依次沉积形成衬垫层3、及介质层4；
具体的，沉积的温度为400度至450度，所述衬垫层3的材料为氮化硅，厚度为400至500埃；所述介质层4的材料为二氧化硅，厚度为1000至2000埃。所述衬垫层3与介质层4共同构成缓冲层。
步骤3、在介质层2上与所述遮光层2的凸起部22相对应的区域沉积一非晶硅层，所述非晶硅层的投影覆盖整个凸起部22，然后将所述非晶硅层转化为多晶硅层；
具体的，采用化学气相沉积工艺沉积所述非晶硅层，沉积的温度为400℃至500℃，沉积的非晶硅层的厚度为400至500埃。采用准分子激光退火(ELA)或固相结晶(SPC)的方法将非晶硅层转化为多晶硅层。
步骤4、刻蚀所述多晶硅层形成一有源层5，所述有源层5至少覆盖在所述凸起部22上表面的局部区域及所述凸起部22的一个侧壁224；
具体的，所述有源层5的厚度为400至500埃。
步骤5、在所述有源层5的上方依次沉积并刻蚀形成栅极绝缘层6及栅极层7。
此外，该低温多晶硅薄膜晶体管的制造方法还可以包括：
步骤6、在具有栅极层7的基板1表面上，再沉积一介电层，该介电层的材料可以为氧化硅或氮化硅；接着利用光刻和蚀刻工序在源极欧姆接触区域以及漏极欧姆区域的上方的介电层以及栅极绝缘层6内分别形成直达源极的接触孔以及直达漏极的接触孔；
步骤7、最后在基板1表面上沉积第二金属层，如一铝层、一钨层、一铬层或其他金属单层或复合多层导电层；接着利用光刻及刻蚀工序，形成源极和漏极，这样就可以把信号从源极电连接至漏极，完成整个低温多晶硅薄膜晶体管的制造过程。
综上所述，本发明提供一种低温多晶硅薄膜晶体管及其制造方法，通过在基板上设置一具有凸起的遮光层，再在遮光层上设置其余部分，可以有效地增加该低温多晶硅薄膜晶体管的沟道宽度和沟道的宽长比，提高了开态电流，进而提升了低温多晶硅薄膜晶体管的驱动能力及器件性能，且不影响显示器件的开口率，采用的制造方法工艺简单，易于操作。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形 都应属于本发明权利要求的保护范围。

Claims (13)

  1. 一种低温多晶硅薄膜晶体管，包括:基板、设于所述基板上的遮光层、设于所述遮光层上的衬垫层、设于所述衬垫层上的介质层、设于所述介质层上的有源层、设于所述有源层上的栅极绝缘层、设于所述栅极绝缘层上的栅极层；
    其中，所述遮光层包括设于所述基板上的平坦部、及设于所述平坦部上的凸起部；
    所述有源层的投影至少覆盖所述凸起部的上表面局部区域及所述凸起部的一个侧壁。
  2. 如权利要求1所述的低温多晶硅薄膜晶体管，其中，所述遮光层的材料为钼。
  3. 如权利要求2所述的低温多晶硅薄膜晶体管，其中，所述遮光层位于凸起部处的厚度为800至2500埃，所述凸起部的高度为300至800埃，所述凸起部的两侧侧壁与所述衬垫层之间的角度为35°至70°。
  4. 如权利要求1所述的低温多晶硅薄膜晶体管，其中，所述衬垫层的材料为氮化硅，厚度为400至500埃；所述介质层的材料为二氧化硅，厚度为1000至2000埃。
  5. 如权利要求1所述的低温多晶硅薄膜晶体管，其中，所述有源层的厚度为400至500埃。
  6. 一种低温多晶硅薄膜晶体管的制造方法，包括如下步骤：
    步骤1、提供一基板，在所述基板上通过物理气相沉积工艺沉积一遮光层，通过灰阶曝光和刻蚀形成所述遮光层的的平坦部与凸起部；
    步骤2、采用等离子增强化学气相沉积工艺在所述遮光层上依次沉积形成衬垫层、及介质层；
    步骤3、在介质层上与所述遮光层的凸起部相对应的区域沉积一非晶硅层，所述非晶硅层的投影覆盖整个凸起部，然后将所述非晶硅层转化为多晶硅层；
    步骤4、刻蚀所述多晶硅层形成一有源层，所述有源层至少覆盖在所述凸起部上表面的局部区域及所述凸起部的一个侧壁上；
    步骤5、在所述有源层的上方依次沉积并刻蚀形成栅极绝缘层及栅极层。
  7. 如权利要求6所述的低温多晶硅薄膜晶体管的制造方法，其中，所 述步骤1中所述遮光层的材料为钼。
  8. 如权利要求6所述的低温多晶硅薄膜晶体管的制造方法，其中，所述步骤1中所述遮光层位于凸起部处的厚度为800至2500埃，所述凸起部的高度为300至800埃，所述凸起部的两侧侧壁与所述衬垫层之间的角度为35°至70°。
  9. 如权利要求6所述的低温多晶硅薄膜晶体管的制造方法，其中，所述步骤2中所述衬垫层的材料为氮化硅，厚度为400至500埃；所述介质层的材料为二氧化硅，厚度为1000至2000埃。
  10. 如权利要求6所述的低温多晶硅薄膜晶体管的制造方法，其中，所述步骤4中所述有源层的厚度为400至500埃。
  11. 一种低温多晶硅薄膜晶体管，包括:基板、设于所述基板上的遮光层、设于所述遮光层上的衬垫层、设于所述衬垫层上的介质层、设于所述介质层上的有源层、设于所述有源层上的栅极绝缘层、设于所述栅极绝缘层上的栅极层；
    其中，所述遮光层包括设于所述基板上的平坦部、及设于所述平坦部上的凸起部；
    所述有源层的投影至少覆盖所述凸起部的上表面局部区域及所述凸起部的一个侧壁；
    其中，所述遮光层的材料为钼；
    其中，所述衬垫层的材料为氮化硅，厚度为400至500埃；所述介质层的材料为二氧化硅，厚度为1000至2000埃。
  12. 如权利要求11所述的低温多晶硅薄膜晶体管，其中，所述遮光层位于凸起部处的厚度为800至2500埃，所述凸起部的高度为300至800埃，所述凸起部的两侧侧壁与所述衬垫层之间的角度为35°至70°。
  13. 如权利要求11所述的低温多晶硅薄膜晶体管，其中，所述有源层的厚度为400至500埃。
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