WO2016090694A1 - 一种阵列基板的掺杂方法和掺杂设备 - Google Patents

一种阵列基板的掺杂方法和掺杂设备 Download PDF

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WO2016090694A1
WO2016090694A1 PCT/CN2014/095559 CN2014095559W WO2016090694A1 WO 2016090694 A1 WO2016090694 A1 WO 2016090694A1 CN 2014095559 W CN2014095559 W CN 2014095559W WO 2016090694 A1 WO2016090694 A1 WO 2016090694A1
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doped
region
photoresist
doping
channel region
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PCT/CN2014/095559
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English (en)
French (fr)
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薛景峰
陈归
郝思坤
张鑫
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深圳市华星光电技术有限公司
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Priority to US14/426,251 priority Critical patent/US20160343746A1/en
Publication of WO2016090694A1 publication Critical patent/WO2016090694A1/zh

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
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Definitions

  • the present invention relates to the field of substrate manufacturing technology, and in particular, to a doping method and a doping device for an array substrate.
  • Thin film transistor is a basic circuit component for controlling the brightness of each pixel in a liquid crystal display. It is generally made of amorphous silicon structure. With the advancement of technology, more and more low-temperature polysilicon structures are used. The electrical properties of the thin film transistor are improved.
  • Thin film transistors are formed using low temperature polysilicon (LTPS) technology.
  • LTPS low temperature polysilicon
  • the standard low temperature polysilicon thin film transistor has an N-type heavily doped region as a source and a drain on the polysilicon layer, because the doping concentration of the two N heavily doped regions is higher. High, and the distance from the gate electrode conductor is small, resulting in too strong electric field near the drain, resulting in hot carrier effect, causing leakage current of the polysilicon thin film transistor in the off state, and component stability is seriously affected.
  • the channel region, the heavily doped region, and the lightly doped region are doped three times to reduce the leakage current.
  • FIG. 1a is a schematic diagram of a process for first doping a channel region, a heavily doped region, and a lightly doped region in the prior art
  • FIG. 1b is a prior art pair.
  • FIG. 1c is a third doping of a channel region, a heavily doped region, and a lightly doped region in the prior art.
  • polysilicon 102 is formed on the substrate 101, and the polysilicon 102 defines a region 103 to be heavily doped (a desired doping concentration is a), a region to be lightly doped 104 (a desired doping concentration is b), and a trench to be doped. Channel region 105 (the desired doping concentration is c).
  • the heavily doped region 103, the lightly doped region 104, and the channel region 105 to be doped are simultaneously doped, and the first doping concentration is c; in FIG. 1b, the polysilicon 102 is formed with a coating to be doped.
  • the gate 106 of the hetero-channel region 105 first forms a photoresist 108 through the photomask 107, and the photoresist 108 covers the light-doped region 104 and the gate 106, the light-doped region 104, and the channel region to be doped.
  • the photoresist 108 and the gate 106 covered on the 105 are uniformly uniform in thickness, and then the doped region 103 is doped a second time, and the second doping concentration is abc; the photoresist 108 is removed in FIG. 1c, and the heavily doped
  • the impurity region 103 and the lightly doped region 104 are doped for a third time, and the third doping concentration is b.
  • the doping process in the prior art is complicated, and three times of doping is required, which increases the cost and the production cycle, and is also prone to the problem of process error.
  • the invention provides a doping method and a doping device for an array substrate, which realizes primary doping of a channel region, a heavily doped region and a lightly doped region of a substrate, which simplifies the process and reduces the cost.
  • the present invention provides a method for doping an array substrate, comprising: providing a substrate, the substrate comprising a substrate body and a polysilicon layer disposed on the substrate body, wherein the polysilicon layer defines a region to be heavily doped, to be a lightly doped region and a channel region to be doped; a photoresist layer is formed on the substrate by a photolithography process, wherein the photoresist layer forms a first photoresist portion corresponding to the region to be heavily doped, corresponding to the region to be lightly doped.
  • the second photoresist portion forms a third photoresist portion corresponding to the channel region to be doped, the first photoresist portion is thinner than the second photoresist portion, and the second photoresist portion is thinner than the third photoresist portion;
  • the heavily doped region, the lightly doped region, and the channel region to be doped are doped once to form a heavily doped corresponding to the heavily doped region, the lightly doped region,
  • the step of forming a photoresist layer on the substrate by a photolithography process comprises: providing a uniform thickness on the region to be heavily doped, the region to be lightly doped, and the region to be doped Photoresist; exposure of the photoresist through a photomask, wherein the photomask The first light transmitting portion, the second light transmitting portion, and the third light transmitting portion are included, and the light transmittances of the first light transmitting portion, the second light transmitting portion, and the third light transmitting portion are sequentially increased or decreased sequentially; And exposing the exposed photoresist to form a first photoresist portion corresponding to the first light transmitting portion, a second photoresist portion corresponding to the second light transmitting portion, and a third photoresist portion corresponding to the third light transmitting portion unit.
  • the photomask is a halftone mask or a gray scale mask
  • the second light transmissive portion of the halftone mask corresponding to the second photoresist portion is a semi-transparent film, and the transmittance of the semi-transmissive film is 0 to Between 100%
  • the second light transmitting portion of the gray scale mask corresponding to the second photoresist portion has at least one slit to block a part of the light source to achieve a semi-transparent effect, and the slit control transmittance is between 0% and 100%.
  • the step of performing doping of the heavily doped region, the lightly doped region, and the channel region to be doped by the photoresist layer includes: using a diffusion method or an ion implantation process to treat the heavily doped region through the photoresist layer,
  • the lightly doped region and the channel region to be doped are doped once to form a heavily doped region and a lightly doped region corresponding to the region to be heavily doped, the region to be lightly doped, and the channel region to be doped, respectively. And channel area.
  • the present invention further provides a method for doping an array substrate, comprising: providing a substrate on which a region to be heavily doped, a region to be lightly doped, and a channel region to be doped are defined; Forming a photoresist layer on the substrate, wherein the photoresist layer forms a first photoresist portion corresponding to the region to be heavily doped, a second photoresist portion corresponding to the region to be lightly doped, and a third region corresponding to the channel region to be doped Photoresist, first photoresist The portion is thinner than the second photoresist portion, and the second photoresist portion is thinner than the third photoresist portion; the doped region to be lightly doped, the region to be lightly doped, and the region to be doped are doped once by the photoresist layer to A heavily doped region, a lightly doped region, and a channel region respectively corresponding to the region to be heavily doped, the region to be lightly doped, and
  • the substrate includes a substrate body and a polysilicon layer disposed on the substrate body, wherein the polysilicon layer defines a region to be heavily doped, a region to be lightly doped, and a channel region to be doped.
  • the step of forming a photoresist layer on the substrate by a photolithography process includes: providing a photoresist having a uniform thickness on the region to be heavily doped, the region to be lightly doped, and the channel region to be doped; passing the photomask The plate exposes the photoresist, wherein the photomask comprises a first light transmitting portion, a second light transmitting portion and a third light transmitting portion, the first light transmitting portion, the second light transmitting portion and the third light transmitting portion The light transmittance is sequentially increased or decreased sequentially; the exposed photoresist is developed by a developing solution to form a first photoresist portion corresponding to the first light transmitting portion, and a second light corresponding to the second light transmitting portion a resisting portion and a third photoresist portion corresponding to the third light transmitting portion.
  • the photomask is a halftone mask or a gray scale mask
  • the second light transmissive portion of the halftone mask corresponding to the second photoresist portion is a semi-transparent film, and the transmittance of the semi-transmissive film is 0 to Between 100%
  • the second light transmitting portion of the gray scale mask corresponding to the second photoresist portion has at least one slit to block a part of the light source to achieve a semi-transparent effect, and the slit control transmittance is between 0% and 100%.
  • the step of performing doping of the heavily doped region, the lightly doped region, and the channel region to be doped by the photoresist layer includes: using a diffusion method or an ion implantation process to treat the heavily doped region through the photoresist layer,
  • the lightly doped region and the channel region to be doped are doped once to form a heavily doped region and a lightly doped region corresponding to the region to be heavily doped, the region to be lightly doped, and the channel region to be doped, respectively. And channel area.
  • the present invention further provides a doping device for an array substrate, comprising: a lithographic apparatus for forming a photoresist layer on a substrate, wherein a region to be heavily doped and a region to be lightly doped are defined on the substrate And a channel region to be doped; the photoresist layer forms a first photoresist portion corresponding to the region to be heavily doped, a second photoresist portion is formed corresponding to the region to be lightly doped, and a third photoresist portion is formed corresponding to the channel region to be doped
  • the first photoresist portion is thinner than the second photoresist portion, the second photoresist portion is thinner than the third photoresist portion, and the doping device is configured to treat the heavily doped region, the lightly doped region, and the photoresist layer through the photoresist layer.
  • the doped channel region is doped once to form a heavily doped region, a lightly doped region, and a channel region corresponding to the
  • the substrate includes a substrate body and a polysilicon layer disposed on the substrate body, wherein the polysilicon layer defines a region to be heavily doped, a region to be lightly doped, and a channel region to be doped.
  • the lithography apparatus comprises a photoresist, a photomask, a developing solution and an exposure light source; wherein the photoresist is disposed in a uniform thickness to be heavily doped, to be lightly doped, and to be doped
  • the photomask plate includes a first light transmitting portion, a second light transmitting portion, and a third light transmitting portion, and the first light transmitting portion and the second light transmitting portion And the light transmittance of the third light transmitting portion is sequentially increased or decreased sequentially;
  • the exposure light source exposes the photoresist through the photomask;
  • the developing solution develops the exposed photoresist to form a corresponding first through
  • the first photoresist portion of the light portion corresponds to the second photoresist portion of the second light transmitting portion and the third photoresist portion corresponding to the third light transmitting portion.
  • the photomask is a halftone mask or a gray scale mask
  • the second light transmissive portion of the halftone mask corresponding to the second photoresist portion is a semi-transparent film, and the transmittance of the semi-transmissive film is 0 to Between 100%
  • the second light transmitting portion of the gray scale mask corresponding to the second photoresist portion has at least one slit to block a part of the light source to achieve a semi-transparent effect, and the slit control transmittance is between 0% and 100%.
  • the doping device adopts a diffusion method or an ion implantation process to do the doping of the heavily doped region, the region to be lightly doped, and the region to be doped by the photoresist layer, to form a doping region to be heavily doped at a time. a lightly doped region and a heavily doped region, a lightly doped region, and a channel region corresponding to the channel region to be doped.
  • the beneficial effects of the present invention are: different from the prior art, the present invention forms a photoresist layer on the substrate by a photolithography process, and the photoresist layer formed has three photoresist portions of different thicknesses, and the light passes through the light.
  • the resist layer is doped, and the dopant passes through the photoresist portions of different thicknesses to reach the substrate.
  • the doping power is the same, and the thickness of the photoresist portion is different. Therefore, the amount of the dopant reaching the substrate through the photoresist portions of different thicknesses is also different, so that the doping can form a weight with different doping concentrations.
  • the doped region, the lightly doped region, and the channel region simplifies the process and reduces the cost.
  • 1a is a schematic view showing a process of first doping a channel region, a heavily doped region, and a lightly doped region in the prior art
  • 1b is a schematic view showing a process of performing second doping of a channel region, a heavily doped region, and a lightly doped region in the prior art
  • 1c is a schematic view showing a process of performing third doping of a channel region, a heavily doped region, and a lightly doped region in the prior art
  • FIG. 2 is a schematic flow chart of a first embodiment of a doping method of an array substrate of the present invention
  • FIG. 3 is a schematic view showing a process corresponding to the first embodiment of the doping method shown in FIG. 2;
  • FIG. 4 is a schematic view showing a nanoimprint lithography process in a first embodiment of the doping method shown in FIG. 2;
  • FIG. 5 is a schematic flow chart of a second embodiment of a doping method of an array substrate of the present invention.
  • FIG. 6 is a schematic view showing a process corresponding to the second embodiment of the doping method shown in FIG. 5;
  • FIG. 7 is a schematic structural view of a gray scale reticle in a second embodiment of the doping method shown in FIG. 5;
  • FIG. 8 is a partial structural schematic view of a thin film transistor fabricated by the doping method of the array substrate of the present invention.
  • FIG. 9 is a schematic view showing the manner of use of the first embodiment of the doping device of the array substrate of the present invention in a process flow.
  • FIG. 2 is a schematic flow chart of a first embodiment of a doping method of the array substrate of the present invention
  • FIG. 3 is a schematic view of a process corresponding to the first embodiment of the doping method of FIG.
  • the method provides a doping method, including the steps:
  • S201 Providing a substrate on which a region to be heavily doped, a region to be lightly doped, and a channel region to be doped are defined.
  • processes such as hole processing, plating, etching, and setting of electronic components on the substrate 301 can perform functions such as electrical, magnetic, or optical.
  • the addition of a small amount of other elements or compounds to the substrate 301 can cause the substrate 301 to produce specific properties.
  • incorporation of phosphorus P or gallium Ga into a semiconductor silicon substrate can respectively obtain an n-type or p-type semiconductor material; and incorporation of a metal ion ⁇ Eu in an inorganic solid compound yttrium oxide Y 2 O 3 substrate can be obtained. Red fluorescent material.
  • a lightly doped drain region (LDD) structure in a thin film transistor the structure includes an N-type heavily doped region and an N-type lightly doped region, and carriers generated in the heavily doped region diffuse toward the lightly doped region to Reduce the problem of leakage current.
  • LDD lightly doped drain region
  • three regions to be doped that require different doping concentrations are defined on the substrate 301: a region to be heavily doped 302 having a desired doping concentration h, and a desired doping concentration of 1 to be lightly doped
  • the impurity region 303 and the channel region 304 to be doped having a desired doping concentration c, wherein h>l>c.
  • different numbers of regions having different doping concentrations may be set according to actual needs, and the positional relationship of each region is not limited to the positional relationship in FIG.
  • S202 forming a photoresist layer on the substrate by a photolithography process, wherein the photoresist layer forms a first photoresist portion corresponding to the region to be heavily doped, and forms a second photoresist portion corresponding to the region to be lightly doped, corresponding to the trench to be doped
  • the track region forms a third photoresist portion, the first photoresist portion is thinner than the second photoresist portion, and the second photoresist portion is thinner than the third photoresist portion.
  • the photoresist layer 305 is formed on the substrate 301 before the substrate 301 is doped, and the photoresist layer 305 forms the first photoresist portion 3051 corresponding to the heavily doped region 302, corresponding to the lightly doped region.
  • 303 is formed with a second photoresist portion 3052, and a third photoresist portion 3053 is formed corresponding to the channel region 304 to be doped, and the first photoresist portion 3051 has a thickness p 1 and the second photoresist portion 3052 has a thickness p 2 and a third portion.
  • the photoresist portion 3053 has a thickness of p 3 , where p 1 < p 2 < p 3 .
  • the photoresist layer 305 can be formed by using a nanoimprint lithography process.
  • FIG. 4 is a schematic diagram of a nanoimprint lithography process in the first embodiment of the doping method shown in FIG. First, a uniform thickness of the photoresist 401 is laid on the substrate 301, and then the nano-mold 402 is pressed down, so that the photoresist 401 flows and fills the pattern of the nano-mold 402, and then the nano-mold 402 is pressed down.
  • the photoresist 401 After the thickness of the photoresist 401 reaches the required range, the photoresist is cured to form a photoresist layer, and by designing the nano-mold 402, the photoresist layer can be formed to have thicknesses p 1 , p 2 and p 3 , respectively. Three photoresist sections.
  • the photoresist layer 305 can also be formed by a conventional optical lithography process.
  • a uniform thickness of photoresist is deposited on the substrate 301, and the strong light is irradiated onto the photoresist through the photomask, and the photoresist irradiated by the strong light is deteriorated, and then the substrate 301 is cleaned by using a corrosive liquid. The deteriorated photoresist is removed.
  • the amount of deterioration of the photoresist can be controlled.
  • S203 doping the heavily doped region, the lightly doped region, and the channel region to be doped through the photoresist layer to form a doping region to be heavily doped, a region to be lightly doped, and a region to be doped.
  • the channel region corresponds to a heavily doped region, a lightly doped region, and a channel region.
  • a photoresist layer 305 having three photoresist portions is formed, and the photoresist layer 305 is overlaid on the substrate 301, and then passes through the photoresist layer 305 to be heavily doped region 302, to be lightly doped region 303, and to be
  • the doped channel region 304 is doped once, and a heavily doped region, a lightly doped region, and a channel region are formed on the substrate 301 at a time.
  • Different materials do not have different doping methods.
  • diffusion or ion implantation is generally used.
  • luminescent materials chemical methods such as high temperature solid phase method and sol gel method are used.
  • the first photoresist portion having a thickness of p 1 has the least hindrance effect
  • the second photoresist portion having a thickness of p 2 is generally hindered, and the corresponding doping concentration is 1.
  • the third photoresist portion having a thickness of p 3 has the greatest hindrance effect, corresponding to the channel region 304 to be doped having a doping concentration of c.
  • a photoresist layer is formed on the substrate by a photolithography process, and the photoresist layer has photoresist portions with different thicknesses, and the limitation of the doping hindrance effect is achieved by controlling the thickness of the photoresist portion. Then, the limitation of the doping concentration on the substrate is realized, so that after the primary doping, the heavily doped region, the lightly doped region and the channel region having different doping concentrations can be formed on the substrate, thereby simplifying the doping process and reducing cost.
  • FIG. 5 is a schematic flow chart of a second embodiment of a doping method of the array substrate of the present invention
  • FIG. 6 is a schematic diagram of a process corresponding to the second embodiment of the doping method shown in FIG.
  • a doping method is provided, including the steps:
  • S501 providing a substrate, the substrate comprising a substrate body and a polysilicon layer disposed on the substrate body, wherein the polysilicon layer defines a region to be heavily doped, a region to be lightly doped, and a channel region to be doped.
  • the substrate 601 in this embodiment includes a substrate body 6011 and a polysilicon layer 6012.
  • the polysilicon layer 6012 defines a region to be heavily doped 6013, a region to be lightly doped 6014, and a channel region 6015 to be doped.
  • the polysilicon layer 6012 in the present embodiment is formed by low temperature polysilicon technology.
  • an amorphous silicon layer is formed on the substrate main body 6011 by a chemical vapor deposition process or a plasma enhanced chemical vapor deposition process, wherein the substrate body 6011 may be glass or quartz, and then the excimer laser is used as a heat source, and the laser passes through the transmission system. A laser beam having uniform energy distribution is generated and transmitted on the amorphous silicon layer.
  • the amorphous silicon layer absorbs the energy of the excimer laser, it is converted into a polysilicon layer 6012.
  • the process is completed at 500-600 degrees Celsius, and the ordinary glass substrate is completed. It can also withstand, so low-temperature polysilicon technology enables low-cost polysilicon for LCD display.
  • the substrate body 6011 in the present embodiment is a glass substrate, and the polysilicon layer 6012 is a low temperature polysilicon layer and is used for manufacturing a low temperature polysilicon thin film transistor.
  • the source and the drain on the polysilicon layer are N-type heavily doped. Zone, and corresponding to the gate distance is small, so a strong battery is generated near the drain, which in turn generates a hot carrier effect, so that the thin film transistor has a leakage current problem in the off state, so the source and the drain A heavily doped region, a lightly doped region, and a channel region are formed between the electrodes to reduce leakage current.
  • the heavily doped region 6013, the region to be lightly doped 6014, and the region to be doped 6015 need to be defined on the polysilicon layer 6012.
  • S502 providing a photoresist of uniform thickness on the to-be-doped region, the lightly doped region, and the channel region to be doped.
  • the photoresist (not shown) includes a photosensitive resin, a sensitizer, and a solvent, wherein the photosensitive resin undergoes a photocuring reaction after being irradiated, and then the physical properties of the photoresist, particularly solubility and affinity, change.
  • the photoresist is divided into two types: a positive gel and a negative gel.
  • the negative gel is formed after the light is formed into an insoluble matter.
  • a positive gel is formed after the light is formed into a soluble substance.
  • the photoresist is a positive glue.
  • the photoresist is coated on the substrate 601 by spin coating.
  • spin coating There are two main methods, one is static coating, the substrate 601 is glued at rest, then the substrate 601 is accelerated to rotate the silicone, and finally the solvent is evaporated; Dynamic coating, the substrate 601 is dispensed at a low speed rotation, then the rubber is rotated at a high speed, and finally the solvent is evaporated.
  • the present embodiment adopts dynamic coating, and controls the time point of the rotation acceleration, and tries to glue at a higher speed.
  • S503 exposing the photoresist through the photomask, wherein the photomask comprises a first transparent portion, a second transparent portion, and a third transparent portion, the first transparent portion, the second transparent portion, and The third light transmitting portion is sequentially increased or decreased sequentially.
  • the ultimate goal of the present embodiment is to form heavily doped regions, lightly doped regions, and channel regions of different doping concentrations on the polysilicon 6012.
  • the doping concentration determines the thickness of the photoresist layer 602 and the power of the first doping.
  • the thickness of the photoresist layer 602 determines the thickness of the photoresist and the corresponding exposure rate, and then can determine the exposure light source, the exposure speed, the light transmittance of the photomask plate 603, and the photoresist in the glue coating process in the exposure process. thickness of.
  • the present embodiment uses an exposure light source of ultraviolet light is a positive photoresist and the photoresist, and therefore the choice of a first photomask having a light transmitting plate portion 603 6031 light transmittance of t 1, a second light-transmitting light-transmissive portion 6032
  • the transmittance of t 2 and the third light transmitting portion 6033 is t 3
  • the light transmittances of the first light transmitting portion 6031, the second light transmitting portion 6032, and the third light transmitting portion 6033 are sequentially decreased, that is, t 1 > t 2 > t 3 ;
  • a negative photoresist is used, the transmittances of the first light transmitting portion 6031, the second light transmitting portion 6032, and the third light transmitting portion 6033 are sequentially increased, that is, t 1 ⁇ t 2 ⁇ t 3 .
  • the following descriptions have been made on the corresponding photomask of the positive photoresist, and the relevant parameters of the corresponding photomask of
  • the ultraviolet light is exposed to the photoresist through the photomask plate 603.
  • the photomask plate 603 has three positional relationships with the photoresist. First, the photomask plate 603 is placed on the photoresist and directly contacted, and the exposure precision is achieved. High, but the photoresist is easy to contaminate the photomask plate 603, causing loss of the photomask plate 603; second, the photomask plate 603 is slightly separated from the photoresist by a certain distance, and the life of the photomask plate 603 can be ensured.
  • the third is to provide a lens between the photomask plate 603 and the photoresist, which solves the problems of the first two, but the corresponding manufacturing cost of the multiple lenses is relatively high.
  • the photomask plate 603 is slightly separated from the photoresist by a certain distance, that is, the second mode described above.
  • the photomask plate 603 in the embodiment may be a halftone photomask, wherein the first light transmitting portion 6031 is a light transmitting portion, the second light transmitting portion 6032 is a semi-light transmitting portion, and the third light transmitting portion 6033.
  • the second light transmitting portion 6032 is a semi-transmissive portion
  • the third light transmitting portion 6033 is an opaque portion
  • the second light transmitting portion 6032 has at least one slit to block a part of the light source to achieve a semi-transmissive effect.
  • the slit controls the transmittance between 0 and 100%.
  • FIG. 7 is a schematic structural diagram of a gray scale reticle in a second embodiment of the doping method shown in FIG. 5.
  • the slit of the first light transmitting portion 6031 is the smallest, and the slit of the third light transmitting portion 6033 is the largest.
  • S504 developing the exposed photoresist by using a developing solution to form a photoresist layer, wherein the photoresist layer comprises a first photoresist portion corresponding to the first light transmitting portion, corresponding to the second light transmitting portion a second photoresist portion of the portion and a third photoresist portion corresponding to the third light transmitting portion.
  • the photoresist After the photoresist is exposed through the light transmitting portions having different light transmittances, the photoresists in the corresponding regions of the different light transmitting portions transmit different curing reactions. Then, the photoresist is developed by using a developing solution to form a photoresist layer 602.
  • the first light-transmissive portion 6031 is formed with a first photoresist portion 6021 having a thickness p 1 and the second light-transmitting portion 6032 is formed with a second portion.
  • the thickness of the photoresist portion 6022 is p 2
  • the thickness of the third photoresist portion 6023 is p 3 corresponding to the third light transmissive portion 6033. Since the light transmittance t 1 >t 2 >t 3 , the thickness of the photoresist portion is corresponding to p. 1 ⁇ p 2 ⁇ p 3 .
  • the developer 605 is correspondingly selected from tetramethylammonium hydroxide (TMAOH), the photoresist generates a carboxylic acid during exposure, and the alkali and acid in the developer 605 are neutralized.
  • TMAOH tetramethylammonium hydroxide
  • the exposed photoresist was dissolved in the developer 605, and no exposure was observed.
  • the specific development process may adopt immersion development or continuous spray development. The immersion development immerses the entire substrate 601 in the developer 605.
  • This method consumes more developer 605 and has poor development uniformity; continuous spray development Then, the developer 605 is sprayed on the surface of the substrate 601 using one or more nozzles, while the substrate 601 is rotated at a low speed while achieving the dissolution rate of the photoresist and the uniformity of development.
  • continuous spray development is employed.
  • S505 doping the heavily doped region, the to-be-lightly doped region, and the channel region to be doped through the photoresist layer to form a doping region to be heavily doped, a region to be lightly doped, and a region to be doped
  • the channel region corresponds to a heavily doped region, a lightly doped region, and a channel region.
  • a photoresist layer 602 is formed on the polysilicon layer 6012, and the first photoresist portion 6021 having a thickness p 1 in the photoresist layer 602 corresponds to the to-be-doped region 6013, and the second photoresist portion 6022 having a thickness p 2 is corresponding to The lightly doped region 6014, the first photoresist portion 6021 of p 1 corresponds to the region 4013 to be heavily doped.
  • the doping is started once, and nitrogen (nitrogen N 2 + or nitrogen N + ) is doped into the polysilicon layer 6012 via the photoresist layer 602.
  • the doping may be performed by an ion implantation process or a diffusion method, and the ion implantation process is to ionize the impurities.
  • the ionized impurities are directly driven into the polysilicon layer 6012 by magnetic field acceleration to achieve the purpose of doping; the diffusion method is to drive the dopant from the high concentration region to the low concentration region under high temperature driving.
  • an ion implantation process is employed, and the amount of energy used for implantation is determined by the thickness of the photoresist layer 602 and the doping concentration of the polysilicon layer 6012.
  • the ions pass through the photoresist layer 602 with a certain energy and are injected into the polysilicon layer 6012. Due to the different thickness of the photoresist layer 602, the number of the implanted polysilicon layers 6012 is different, and then the heavily doped regions can be formed and lightly doped. Miscellaneous and channel regions.
  • the first embodiment first coats a layer of photoresist on the polysilicon layer, exposes the photoresist through the photomask, and then develops the exposed photoresist with a developing solution to A photoresist layer having three different thicknesses is formed. Limiting the doping barrier effect by controlling the thickness of the photoresist layer, and then limiting the doping concentration on the polysilicon layer, so that after primary doping, heavy doping with different doping concentrations can be formed on the substrate. The region, the lightly doped region, and the channel region simplify the doping process and reduce cost.
  • FIG. 8 is a partial structural diagram of a thin film transistor fabricated by the doping method of the array substrate of the present invention.
  • the thin film transistor 800 includes a glass substrate 801, a polysilicon layer 802, a gate insulating layer 803, and a gate layer 804.
  • the polysilicon layer 802 is disposed on the glass substrate 801 , and includes a heavily doped region 8021 , a lightly doped region 8022 , and a channel region 8023 .
  • the heavily doped region 8021 serves as a source of the thin film transistor 800 .
  • the gate insulating layer 803 is disposed on the polysilicon layer 802, and the gate layer 804 is disposed on the gate insulating layer 803.
  • the gate layer 804 is disposed on the glass substrate 801, the gate insulating layer 803 covers the gate layer 804, and then the polysilicon layer 802 is disposed on the gate insulating layer 803.
  • FIG. 9 is a schematic diagram showing the manner of use of the first embodiment of the doping apparatus of the array substrate of the present invention in a process flow.
  • the present embodiment provides a doping apparatus 900 including a lithographic apparatus 901 and a doping apparatus 902.
  • the lithographic apparatus 901 further includes a photoresist 903, a photomask 904, a developing solution (not shown), and an exposure light source. 905.
  • the lithographic apparatus 901 is configured to form a photoresist layer on the substrate, wherein the substrate is defined with a region to be heavily doped, a region to be lightly doped, and a channel region to be doped; the photoresist layer corresponds to the Forming a first photoresist portion in the heavily doped region, and forming a second photoresist portion corresponding to the to-be-lightly doped region, corresponding to the channel to be doped.
  • the region forms a third photoresist portion, the first photoresist portion is thinner than the second photoresist portion, and the second photoresist portion is thinner than the third photoresist portion.
  • the specific working process of the lithography apparatus 901 is as follows:
  • S901 disposing the photoresist in the uniform thickness to the heavily doped region, the region to be lightly doped, and the channel region to be doped.
  • This step S901 is similar to the step S502 in the second embodiment of the doping method of the array substrate, and details are not described herein again.
  • the exposure light source 905 exposes the photoresist 903 through the photomask 904.
  • the photoresist 903 is a positive glue; the photomask 904 includes a first light transmissive portion 9041, a second light transmissive portion 9042, and a third light transmissive portion 9043.
  • the transmittance of the first light transmissive portion 9041 is greater than
  • the light transmittance of the second light transmitting portion 9042 is greater than the light transmittance of the third light transmitting portion 9043; this step S902 is similar to the doping method of the array substrate. Step S503 in the second embodiment is not described here.
  • S903 developing the exposed photoresist using a developing solution to form a photoresist layer.
  • the photoresist portion includes a first photoresist portion corresponding to the first light transmitting portion, a second photoresist portion corresponding to the second light transmitting portion, and a third photoresist portion corresponding to the third light transmitting portion.
  • This step S903 is similar to the step S504 in the second embodiment of the doping method of the array substrate, and details are not described herein again.
  • the doping device 902 is configured to perform doping once to be heavily doped, to be lightly doped, and to be doped through the photoresist layer, to form a region to be heavily doped, a region to be lightly doped, and The heavily doped region, the lightly doped region, and the channel region corresponding to the doped channel region.
  • the specific working process of the doping device 902 is similar to the step S505 in the second embodiment of the doping method of the array substrate, and details are not described herein again.
  • a photoresist is coated on the substrate by using a lithography apparatus, and the photoresist is subjected to an exposure and development operation through the photomask and the developer to form three different thicknesses on the substrate. Photoresist layer.
  • the doping device is used to dope the substrate once through the photoresist layer, so that the heavily doped region, the lightly doped region and the channel region having different doping concentrations can be formed on the substrate at one time, which simplifies the complexity of the doping device. Degree, reduce doping equipment running time, reduce costs.

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Abstract

一种阵列基板的掺杂方法及掺杂设备，掺杂方法包括提供定义有待重掺杂区（302）、待轻掺杂区（303）以及待掺杂沟道区（304）的基板（301）；通过光刻工艺在基板上形成光阻层（305），该光阻层（305）对应待重掺杂区（302）形成第一光阻部（3051），对应待轻掺杂区（303）形成第二光阻部（3052），对应待掺杂沟道区（304）形成第三光阻部（3053），第一光阻部（3051）比第二光阻部（3052）薄，第二光阻部（3052）比第三光阻部（3053）薄；经光阻层（305）对待重掺杂区（302）、待轻掺杂区（303）以及待掺杂沟道区（304）进行一次掺杂，以一次形成分别与待重掺杂区（302）、待轻掺杂区（303）以及待掺杂沟道区（304）对应的重掺杂区、轻掺杂区和沟道区。能够实现对基板的沟道区、重掺杂区以及轻掺杂区的一次掺杂，简化工艺，降低成本。

Description

一种阵列基板的掺杂方法和掺杂设备 【技术领域】
本发明涉及基板制造技术领域，特别是涉及一种阵列基板的掺杂方法和掺杂设备。
【背景技术】
薄膜晶体管(TFT)是液晶显示器中控制每个像素亮度的基本电路组件，一般由非晶硅结构制造而成，随着技术的进步，越来越多的使用低温多晶硅结构，这种结构大大的改善了薄膜晶体管的电性能。
使用低温多晶硅(LTPS)技术形成薄膜晶体管，一般标准低温多晶硅薄膜晶体管在多晶硅层上有作为源极和漏极的N型重掺杂区，由于两个N性重掺杂区的掺杂浓度较高，且与栅电极导体间的距离较小，导致漏极附近电场太强，而产生热载流子效应，使多晶硅薄膜晶体管在关闭状态下会有漏电流的问题，组件稳定性受到严重影响。为解决这个问题，现有技术中对沟道区、重掺杂区以及轻掺杂区进行三次掺杂以减少漏电流的问题。
请参阅图1a、图1b以及图1c，图1a是现有技术中对沟道区、重掺杂区以及轻掺杂区进行第一次掺杂的工艺示意图，图1b是现有技术中对沟道区、重掺杂区以及轻掺杂区进行第二次掺杂的工艺示意图，图1c是现有技术中对沟道区、重掺杂区以及轻掺杂区进行第三次掺杂的工艺示意图。其中，在基板101上形成多晶硅102，多晶硅102上定义有待重掺杂区103(所需掺杂浓度为a)、待轻掺杂区104(所需掺杂浓度为b)以及待掺杂沟道区105(所需掺杂浓度为c)。图1a中即对待重掺杂区103、待轻掺杂区104以及待掺杂沟道区105同时进行掺杂，第一次掺杂浓度为c；图1b中多晶硅102上形成有覆盖待掺杂沟道区105的栅极106，首先通过光掩膜板107形成光阻108，光阻108覆盖待轻掺杂区104以及栅极106，待轻掺杂区104以及待掺杂沟道区105上所覆盖的光阻108以及栅极106整体厚度均匀，然后对待重掺杂区103进行第二次掺杂，第二次掺杂浓度为a-b-c；图1c中除去光阻108，对重掺杂区103以及轻掺杂区104进行第三次掺杂，第三次掺杂浓度为b。
根据以上描述可知，现有技术中掺杂工艺较为复杂，且需要进行三次掺杂，增加了成本和生产周期，同时也容易导致工艺误差的问题。
【发明内容】
本发明提供一种阵列基板的掺杂方法和掺杂设备，实现对基板的沟道区、重掺杂区以及轻掺杂区的一次掺杂，简化工艺，降低成本。
为解决上述问题，本发明提供一种阵列基板的掺杂方法，其包括：提供基板，该基板包括基板主体以及设置在基板主体上的多晶硅层，其中多晶硅层上定义有待重掺杂区、待轻掺杂区以及待掺杂沟道区；通过光刻工艺在基板上形成光阻层，其中，光阻层对应待重掺杂区形成第一光阻部，对应待轻掺杂区形成第二光阻部，对应待掺杂沟道区形成第三光阻部，第一光阻部比第二光阻部薄，第二光阻部比第三光阻部薄；经光阻层对待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂，以一次形成分别与待重掺杂区、待轻掺杂区以及待掺杂沟道区对应的重掺杂区、轻掺杂区和沟道区；通过光刻工艺在基板上形成光阻层的步骤包括：在待重掺杂区、待轻掺杂区以及待掺杂沟道区上设置有均匀厚度的光刻胶；通过光掩膜板对光刻胶进行曝光，其中，光掩膜板包括第一透光部、第二透光部以及第三透光部，第一透光部、第二透光部以及第三透光部的透光率依次增大或依次减小；利用显影液对曝光后的光刻胶进行显影，以形成对应第一透光部的第一光阻部，对应第二透光部的第二光阻部以及对应第三透光部的第三光阻部。
其中，光掩膜板为半色调光罩或灰阶光罩；半色调光罩对应第二光阻部的第二透光部为半透光膜，半透光膜的透过率在0～100％之间；灰阶光罩对应第二光阻部的第二透光部具有至少一条狭缝，以遮挡部分光源实现半透光效果，狭缝控制透过率在0～100％之间。
其中，经光阻层对待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂的步骤包括：采用扩散法或离子注入工艺经光阻层对待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂，以一次形成分别与待重掺杂区、待轻掺杂区以及待掺杂沟道区对应的重掺杂区、轻掺杂区和沟道区。
为解决上述问题，本发明还提供一种阵列基板的掺杂方法，其包括：提供基板，该基板上定义有待重掺杂区、待轻掺杂区以及待掺杂沟道区；通过光刻工艺在基板上形成光阻层，其中，光阻层对应待重掺杂区形成第一光阻部，对应待轻掺杂区形成第二光阻部，对应待掺杂沟道区形成第三光阻部，第一光阻 部比第二光阻部薄，第二光阻部比第三光阻部薄；经光阻层对待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂，以一次形成分别与待重掺杂区、待轻掺杂区以及待掺杂沟道区对应的重掺杂区、轻掺杂区和沟道区。
其中，基板包括基板主体以及设置在基板主体上的多晶硅层，其中多晶硅层上定义有待重掺杂区、待轻掺杂区以及待掺杂沟道区。
其中，通过光刻工艺在基板上形成光阻层的步骤包括：在待重掺杂区、待轻掺杂区以及待掺杂沟道区上设置有均匀厚度的光刻胶；通过光掩膜板对光刻胶进行曝光，其中，光掩膜板包括第一透光部、第二透光部以及第三透光部，第一透光部、第二透光部以及第三透光部的透光率依次增大或依次减小；利用显影液对曝光后的光刻胶进行显影，以形成对应第一透光部的第一光阻部，对应第二透光部的第二光阻部以及对应第三透光部的第三光阻部。
其中，光掩膜板为半色调光罩或灰阶光罩；半色调光罩对应第二光阻部的第二透光部为半透光膜，半透光膜的透过率在0～100％之间；灰阶光罩对应第二光阻部的第二透光部具有至少一条狭缝，以遮挡部分光源实现半透光效果，狭缝控制透过率在0～100％之间。
其中，经光阻层对待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂的步骤包括：采用扩散法或离子注入工艺经光阻层对待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂，以一次形成分别与待重掺杂区、待轻掺杂区以及待掺杂沟道区对应的重掺杂区、轻掺杂区和沟道区。
为解决上述问题，本发明又提供一种阵列基板的掺杂设备，其包括：光刻装置，用于在基板上形成光阻层，其中基板上定义有待重掺杂区、待轻掺杂区以及待掺杂沟道区；光阻层对应待重掺杂区形成第一光阻部，对应待轻掺杂区形成第二光阻部，对应待掺杂沟道区形成第三光阻部，第一光阻部比第二光阻部薄，第二光阻部比第三光阻部薄；以及掺杂装置，用于经光阻层对待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂，以一次形成分别与待重掺杂区、待轻掺杂区以及待掺杂沟道区对应的重掺杂区、轻掺杂区和沟道区。
其中，基板包括基板主体以及设置在基板主体上的多晶硅层，其中多晶硅层上定义有待重掺杂区、待轻掺杂区以及待掺杂沟道区。
其中，光刻装置包括光刻胶、光掩膜板、显影液以及曝光光源；其中，光刻胶以均匀的厚度设置在待重掺杂区、待轻掺杂区以及待掺杂沟道区上；光掩膜板包括第一透光部、第二透光部以及第三透光部，第一透光部、第二透光部 以及第三透光部的透光率依次增大或依次减小；曝光光源通过光掩膜板对光刻胶进行曝光；显影液对曝光后的光刻胶进行显影，以形成对应第一透光部的第一光阻部，对应第二透光部的第二光阻部以及对应第三透光部的第三光阻部。
其中，光掩膜板为半色调光罩或灰阶光罩；半色调光罩对应第二光阻部的第二透光部为半透光膜，半透光膜的透过率在0～100％之间；灰阶光罩对应第二光阻部的第二透光部具有至少一条狭缝，以遮挡部分光源实现半透光效果，狭缝控制透过率在0～100％之间。
其中，掺杂装置采用采用扩散法或离子注入工艺经光阻层对待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂，以一次形成分别与待重掺杂区、待轻掺杂区以及待掺杂沟道区对应的重掺杂区、轻掺杂区和沟道区。
通过上述方案，本发明的有益效果是：区别于现有技术，本发明通过光刻工艺在基板上形成光阻层，所形成的光阻层上具有三个不同厚度的光阻部，通过光阻层对进行掺杂，掺杂物经过不同厚度的光阻部，到达基板。在进行一次掺杂时，掺杂功率相同，光阻部厚度不同，因此掺杂物经过不同厚度的光阻部到达基板的量也不同，因此一次掺杂即能够形成具有不同掺杂浓度的重掺杂区、轻掺杂区以及沟道区，相应的简化了工艺，降低了成本。
【附图说明】
图1a是现有技术中对沟道区、重掺杂区以及轻掺杂区进行第一次掺杂的工艺示意图；
图1b是现有技术中对沟道区、重掺杂区以及轻掺杂区进行第二次掺杂的工艺示意图；
图1c是现有技术中对沟道区、重掺杂区以及轻掺杂区进行第三次掺杂的工艺示意图；
图2是本发明阵列基板的掺杂方法的第一实施方式的流程示意图；
图3是图2所示掺杂方法的第一实施方式对应的工艺示意图；
图4是图2所示掺杂方法的第一实施方式中纳米压印光刻工艺示意图；
图5是本发明阵列基板的掺杂方法的第二实施方式的流程示意图；
图6是图5所示掺杂方法的第二实施方式对应的工艺示意图；
图7是图5所示掺杂方法的第二实施方式中灰阶光罩的结构示意图；
图8是结合本发明阵列基板的掺杂方法制造出的薄膜晶体管的部分结构示意图；
图9是本发明阵列基板的掺杂装置的第一实施方式在工艺流程中使用方式示意图。
【具体实施方式】
请参阅图2和图3，图2是本发明阵列基板的掺杂方法的第一实施方式的流程示意图，图3是图2所示掺杂方法的第一实施方式对应的工艺示意图，本实施方式提供一种掺杂方法，包括步骤：
S201：提供基板，基板上定义有待重掺杂区、待轻掺杂区以及待掺杂沟道区。
一般来说，对基板301进行孔加工、电镀、蚀刻以及设置电子元件等工艺可以实现电学、磁学或光学等方面的功能。在基板301中掺入少量的其他元素或化合物，可以使基板301产生特定的性能。具体而言，例如在半导体硅基板中掺入磷P或镓Ga可以分别得n型或p型半导体材料；在无机固体化合物氧化钇Y2O3基板中掺入金属离子铕Eu，可以得到发红光的荧光材料。
掺杂物的浓度对基板301性能的影响很大，因此具有不同浓度掺杂物的基板301对应有不同的性能，且对具有不同浓度掺杂物的基板301组合使用可实现特定功能。例如薄膜晶体管中的轻掺杂漏区域(LDD)结构，此结构包括N型重掺杂区和N型轻掺杂区，重掺杂区中产生的载流子向轻掺杂区扩散，以减小漏电流的问题。
本实施方式中，在基板301上定义有需要不同掺杂浓度的三个待掺杂区域：所需掺杂浓度为h的待重掺杂区302、所需掺杂浓度为1的待轻掺杂区303以及所需掺杂浓度为c的待掺杂沟道区304，其中h＞l＞c。在其他实施方式中，可以根据实际需求设置不同数量具有不同掺杂浓度的区域，且各区域的位置关系也并不仅限于图3中的位置关系。
S202：通过光刻工艺在基板上形成光阻层，其中，光阻层对应待重掺杂区形成第一光阻部，对应待轻掺杂区形成第二光阻部，对应待掺杂沟道区形成第三光阻部，第一光阻部比第二光阻部薄，第二光阻部比第三光阻部薄。
本实施方式中，在对基板301进行掺杂之前先在基板301上形成光阻层305， 且光阻层305对应待重掺杂区302形成第一光阻部3051，对应待轻掺杂区303形成第二光阻部3052，对应待掺杂沟道区304形成第三光阻部3053，且第一光阻部3051厚度为p1、第二光阻部3052厚度为p2、第三光阻部3053厚度为p3，其中p1＜p2＜p3。
本实施方式可以使用纳米压印光刻工艺来形成光阻层305，请参阅图4，图4是图2所示掺杂方法的第一实施方式中纳米压印光刻工艺示意图。首先在基板301上铺设一层厚度均匀的光刻胶401，然后将纳米模具402下压，使光刻胶401流动并填充致纳米模具402的图型中，随后增大纳米模具402下压载荷，使其光刻胶401厚度达到要求的范围后固化光刻胶以形成光阻层，且通过对纳米模具402的设计，可以使光阻层形成分别具有厚度p1、p2和p3的三个光阻部。
本实施方式也可以采用传统光学光刻工艺来形成光阻层305。在基板301上铺设一层厚度均匀的光刻胶，强光通过光掩膜板照射在光刻胶上，被强光照射到的光刻胶会发生变质，然后再使用腐蚀性液体清洗基板301，使变质的光刻胶被除去。通过控制光刻胶被强光照射的程度，可以光刻胶发生变质的量得到控制，因此对三个区域的光刻胶采用三种程度的光照，可以使三个区域的光刻胶具有三种不同的变质的量，然后通过腐蚀性液体的清洗，最后在基板上形成光阻层305，且相应的在三个区域形成有不同的厚度p1、p2和p3的三个光阻部。
S203：经光阻层对待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂，以一次形成分别与待重掺杂区、待轻掺杂区以及待掺杂沟道区对应的重掺杂区、轻掺杂区和沟道区。
步骤S202后形成了具有三个光阻部的光阻层305，且光阻层305覆盖在基板301上，然后再经过光阻层305对待重掺杂区302、待轻掺杂区303以及待掺杂沟道区304进行一次掺杂，在基板301上一次形成重掺杂区、轻掺杂区和沟道区。
不同的材料的基板所采用的掺杂方法不同，对于半导体硅基板一般采用扩散法或离子注入法；而对于发光材料基板则多采用化学方法，如高温固相法、溶胶凝胶法等。当将掺杂物通过光阻层305注入到基板上时，由于光阻层305有一定的阻碍作用，且不同厚度光阻部的阻碍作用不同，由于本实施方式中三个区域的掺杂过程一次完成，即对于三个区域来说，掺杂过程中除了对应光阻部的厚度不同，即p1＜p2＜p3，其他条件完全相同。因此p1厚度的第一光阻部阻碍作用最小，则对应掺杂浓度为h的待重掺杂区302；p2厚度的第二光阻部阻 碍作用一般，则对应掺杂浓度为1的待轻掺杂区303；且p3厚度的第三光阻部阻碍作用最大，则对应掺杂浓度为c的待掺杂沟道区304。
区别于现有技术，本实施方式中通过光刻工艺在基板上形成光阻层，光阻层具有不同厚度的光阻部，通过对光阻部厚度的控制实现对掺杂阻碍作用的限制，继而实现对基板上掺杂浓度的限制，从而使得在一次掺杂后，基板上能够形成具有不同掺杂浓度的重掺杂区、轻掺杂区以及沟道区，简化了掺杂工艺，降低成本。
请参阅图5和图6，图5是本发明阵列基板的掺杂方法第二实施方式的流程示意图，图6是图5所示掺杂方法的第二实施方式对应的工艺示意图，本实施方式提供了一种掺杂方法，包括步骤：
S501：提供基板，基板包括基板主体以及设置在基板主体上的多晶硅层，其中多晶硅层上定义有待重掺杂区、待轻掺杂区以及待掺杂沟道区。
本实施方式中的基板601包括基板主体6011和多晶硅层6012，多晶硅层6012上定义了待重掺杂区6013、待轻掺杂区6014以及待掺杂沟道区6015。
为了实现LCD轻薄化设计以及减小功耗，越来越多的使用多晶硅液晶材料，多晶硅结构一般是对非晶硅结构进行处理得到的，本实施方式中的多晶硅层6012的形成采用低温多晶硅技术，首先是在基板主体6011上利用化学气相沉积制程或等离子体加强化学气相沉积制程形成非晶硅层，其中基板主体6011可以为玻璃或石英，然后将准分子激光作为热源，激光经过透射系统后，产生能量均匀分布的激光束并透射在非晶硅层上，当非晶硅层吸收准分子激光的能量后，转变为多晶硅层6012，此过程在500-600摄氏度以下完成，普通的玻璃基板也能够承受，因此低温多晶硅技术实现了低成本的将多晶硅用于LCD显示领域。
本实施方式中的基板主体6011为玻璃基板，多晶硅层6012为低温多晶硅层，并将其用于制造低温多晶硅薄膜晶体管，对于NMOS管，多晶硅层上的源极和漏极是N型重掺杂区，且相应的于栅极距离较小，因此漏极附近产生较强的电池，继而产生热载流子效应，使得薄膜晶体管在关闭状态下会有漏电流的问题，因此在源极和漏极之间形成重掺杂区、轻掺杂区以及沟道区以减小漏电流的问题。相应的在S501步骤中，需要在多晶硅层6012上定义待重掺杂区6013、待轻掺杂区6014以及待掺杂沟道区6015。
S502：在待重掺杂区、待轻掺杂区以及待掺杂沟道区上设置均匀厚度的光刻胶。
光刻胶(图未示)包括感光树脂、增感剂以及溶剂，其中感光树脂经光照后会发生光固化反应，继而光刻胶的物理性能，特别是溶解性和亲和性发生变化。光刻胶分为正性胶和负性胶两种，光照后形成不可溶物质的是负性胶，反之，光照后形成可溶物质的是正性胶。本实施方式中光刻胶为正性胶。
通过旋转涂胶的方法将光刻胶涂覆在基板601上，主要有两种方式，一是静态涂胶，基板601静止时滴胶，然后基板601加速旋转甩胶，最后挥发溶剂；二是动态涂胶，基板601低速旋转时滴胶，然后高速旋转甩胶，最后挥发溶剂。为得到较为均匀的光刻胶层，本实施方式采用动态涂胶，并控制旋转加速的时间点，且尽量以较高的速度甩胶。
S503：通过光掩膜板对光刻胶进行曝光，其中光掩膜板包括第一透光部、第二透光部以及第三透光部，第一透光部、第二透光部以及第三透光部是依次增大或依次减小的。
本实施方式最终目的是为了在多晶硅6012上形成不同掺杂浓度的重掺杂区、轻掺杂区以及沟道区，掺杂浓度决定了光阻层602的厚度以及一次掺杂的功率，而光阻层602的厚度则决定了光刻胶的厚度及相应的曝光率，继而可以确定曝光工艺中的曝光光源、曝光速度、光掩膜板603的透光率以及涂胶工艺中光刻胶的厚度。
本实施方式中曝光光源采用紫外光源，且光刻胶为正性胶，因此所选用的光掩膜板603具有第一透光部6031透光率为t1、第二透光部6032透光率为t2以及第三透光部6033透光率为t3，第一透光部6031、第二透光部6032以及第三透光部6033的透光率是依次减小的，即t1＞t2＞t3；若是采用负性光刻胶，则第一透光部6031、第二透光部6032以及第三透光部6033的透光率是依次增大的，即t1＜t2＜t3。以下均已正性光刻胶相应的光掩膜板进行描述，负性光刻胶相应光掩膜板的相关参数可作对应的调整。
紫外光通过光掩膜板603对光刻胶进行曝光，光掩膜板603与光刻胶有三种位置关系，一是光掩膜板603放置在光刻胶上且直接接触，曝光的精确度高，但光刻胶容易污染光掩膜板603，造成光掩膜板603的损耗；二是光掩膜板603与光刻胶以一定距离略微分开，可保证光掩膜板603的寿命，但是由于衍射效应，曝光的精确度不高；三是在光掩膜板603和光刻胶之间设置透镜，解决了前面两种的问题，但多设置透镜相应的制造成本较高。在本实施方式中光掩膜板603与光刻胶以一定距离略微分开，即上述第二种方式。
具体的，本实施方式中的光掩膜板603可以为半色调光罩，其第一透光部6031为透光部分，第二透光部6032为半透光部分，第三透光部6033为不透光部分；其中，第二透光部6032半透光部分的透过率在0～100％之间；光掩膜板603也可以为灰阶光罩；其第一透光部6031为透光部分，第二透光部6032为半透光部分，第三透光部6033为不透光部分；第二透光部6032具有至少一条狭缝，以遮挡部分光源实现半透光效果，所述狭缝控制透过率在0～100％之间。具体请参阅图7，图7是图5所示掺杂方法的第二实施方式中灰阶光罩的结构示意图。其中第一透光部6031的狭缝最少，第三透光部6033的狭缝最多。
S504：利用显影液对曝光后的所述光刻胶进行显影，以形成光阻层，其中光阻层包括对应所述第一透光部的第一光阻部，对应所述第二透光部的第二光阻部以及对应所述第三透光部的第三光阻部。
在通过不同透光率的透光部对光刻胶进行曝光后，不同透光部对应区域的光刻胶发送不同的固化反应。然后使用显影液对光刻胶进行显影，最终形成光阻层602，且对应第一透光部6031形成有第一光阻部6021厚度为p1，对应第二透光部6032形成有第二光阻部6022厚度为p2，对应第三透光部6033形成有第三光阻部6023厚度为p3，由于透光率t1＞t2＞t3，因此光阻部厚度相应的p1＜p2＜p3。
由于本实施方式中采用正性光刻胶，因此显影液605相应的选择四甲基氢氧化铵(TMAOH)，光刻胶在曝光过程中产生羧酸，显影液605中的碱和酸中和使得曝光的光刻胶溶于显影液605，而未曝光的没有影响。具体显影过程可采用浸没式显影或连续喷雾式显影，浸没式显影是将整个基板601浸没在显影液605中，此方式消耗的显影液605较多，且显影均匀性较差；连续喷雾式显影则是使用一个或多个喷嘴将显影液605喷洒在基板601表面，同时基板601低速旋转，同时实现光刻胶的溶解率以及显影的均匀性。本实施方式中采用连续喷雾式显影。
S505：经光阻层对待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂，以一次形成分别与待重掺杂区、待轻掺杂区以及待掺杂沟道区对应的重掺杂区、轻掺杂区和沟道区。
在多晶硅层6012上形成了光阻层602，且光阻层602中厚度为p1的第一光阻部6021对应待重掺杂区6013，厚度为p2的第二光阻部6022对应待轻掺杂区6014，p1的第一光阻部6021对应待重掺杂区6013。
开始进行一次掺杂，将氮气(氮气N2 +或者氮N+)经光阻层602掺杂注入多晶硅层6012，掺杂的可以采用离子注入工艺或扩散法，离子注入工艺是将杂质离化，通过磁场加速，将这些离化的杂质直接打入多晶硅层6012，以达到掺杂的目的；扩散法是在高温驱动下使掺杂物从高浓度区向低浓度区运动。本实施方式中采用离子注入工艺，且注入所使用能量的大小由光阻层602的厚度以及多晶硅层6012的掺杂浓度所决定。离子以一定能量经过光阻层602，并注入多晶硅层6012，由于光阻层602中不同厚度的阻碍作用，使得注入多晶硅层6012的数量也不一样，继而能够相应形成重掺杂区、轻掺杂区和沟道区。
区别于现有技术，本实施方式首先在多晶硅层上涂覆一层光刻胶，并通过光掩膜板对光刻胶进行曝光，然后利用显影液对曝光后的光刻胶进行显影，以形成具有三个不同厚度的光阻层。通过对光阻层厚度的控制实现对掺杂阻碍作用的限制，继而实现对多晶硅层上掺杂浓度的限制，从而使得在一次掺杂后，基板上能够形成具有不同掺杂浓度的重掺杂区、轻掺杂区以及沟道区，简化了掺杂工艺，降低成本。
请参阅图8，图8是结合本发明阵列基板的掺杂方法制造出的薄膜晶体管的部分结构示意图。
薄膜晶体管800包括玻璃基板801、多晶硅层802、栅极绝缘层803以及栅极层804。
请参考图8中的A部分，多晶硅层802设置于玻璃基板801上的，包括重掺杂区8021、轻掺杂区8022以及沟道区8023，重掺杂区8021作为薄膜晶体管800的源极和漏极。栅极绝缘层803设置在多晶硅层802上，栅极层804设置在栅极绝缘层803上。
另一种结构请参考图8中的B部分，将栅极层804设置在玻璃基板801上，栅极绝缘层803覆盖栅极层804，继而将多晶硅层802设置在栅极绝缘层803上。
请参阅图9，图9是本发明阵列基板的掺杂装置的第一实施方式在工艺流程中使用方式示意图。本实施方式提供一种掺杂设备900，其包括光刻装置901和掺杂装置902，光刻装置901还包括光刻胶903、光掩膜板904、显影液(未图示)以及曝光光源905。
其中，光刻装置901用于在基板上形成光阻层，其中，所述基板上定义有待重掺杂区、待轻掺杂区以及待掺杂沟道区；所述光阻层对应所述待重掺杂区形成第一光阻部，对应所述待轻掺杂区形成第二光阻部，对应所述待掺杂沟道 区形成第三光阻部，所述第一光阻部比所述第二光阻部薄，所述第二光阻部比所述第三光阻部薄。
光刻装置901具体工作过程如下：
S901：将光刻胶以均匀的厚度设置在所述待重掺杂区、待轻掺杂区以及待掺杂沟道区上。
此步骤S901类似于阵列基板的掺杂方法第二实施方式中的步骤S502，在此不再赘述。
S902：曝光光源905通过光掩膜板904对光刻胶903进行曝光。
光刻胶903为正性胶；光掩膜板904包括第一透光部9041、第二透光部9042以及第三透光部9043，所述第一透光部9041的透光率大于所述第二透光部9042的透光率，所述第二透光部9042的透光率大于所述第三透光部9043的透光率；此步骤S902类似于阵列基板的掺杂方法第二实施方式中的步骤S503，在此不再赘述。
S903：使用显影液对曝光后的光刻胶进行显影，以形成光阻层。
光阻部包括对应所述第一透光部的第一光阻部，对应所述第二透光部的第二光阻部以及对应所述第三透光部的第三光阻部。此步骤S903类似于阵列基板的掺杂方法第二实施方式中的步骤S504，在此不再赘述。
掺杂装置902用于经光阻层对待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂，以一次形成分别与待重掺杂区、待轻掺杂区以及待掺杂沟道区对应的重掺杂区、轻掺杂区和沟道区。掺杂装置902的具体工作过程类似于阵列基板的掺杂方法第二实施方式中的步骤S505，在此不再赘述。
区别于现有技术，本实施方式中使用光刻装置在基板上涂覆光刻胶，并通过光掩膜板及显影液对光刻胶进行曝光显影操作，使基板上形成具有三个不同厚度的光阻层。然后再利用掺杂装置通过光阻层对基板进行一次掺杂，使得基板上能够一次形成具有不同掺杂浓度的重掺杂区、轻掺杂区以及沟道区，简化了掺杂设备的复杂度，减小掺杂设备运行时间，降低成本。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种阵列基板的掺杂方法，其中，所述掺杂方法包括：
    提供基板，所述基板包括基板主体以及设置在基板主体上的多晶硅层，其中所述多晶硅层上定义有所述待重掺杂区、待轻掺杂区以及待掺杂沟道区；
    通过光刻工艺在所述基板上形成光阻层，其中，所述光阻层对应所述待重掺杂区形成第一光阻部，对应所述待轻掺杂区形成第二光阻部，对应所述待掺杂沟道区形成第三光阻部，所述第一光阻部比所述第二光阻部薄，所述第二光阻部比所述第三光阻部薄；
    经所述光阻层对所述待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂，以一次形成分别与所述待重掺杂区、待轻掺杂区以及待掺杂沟道区对应的重掺杂区、轻掺杂区和沟道区；
    所述通过光刻工艺在所述基板上形成光阻层的步骤包括：
    在所述待重掺杂区、待轻掺杂区以及待掺杂沟道区上设置均匀厚度的光刻胶；
    通过光掩膜板对所述光刻胶进行曝光，其中，所述光掩膜板包括第一透光部、第二透光部以及第三透光部，所述第一透光部、第二透光部以及第三透光部的透光率依次增大或依次减小；
    利用显影液对曝光后的所述光刻胶进行显影，以形成对应所述第一透光部的第一光阻部，对应所述第二透光部的第二光阻部以及对应所述第三透光部的第三光阻部。
  2. 根据权利要求1所述的掺杂方法，其中，所述光掩膜板为半色调光罩或灰阶光罩；所述半色调光罩对应所述第二光阻部的第二透光部为半透光膜，所述半透光膜的透过率在0～100％之间；所述灰阶光罩对应所述第二光阻部的第二透光部具有至少一条狭缝，以遮挡部分光源实现半透光效果，所述狭缝控制透过率在0～100％之间。
  3. 根据权利要求1所述的掺杂方法，其中，所述经所述光阻层对所述待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂的步骤包括：
    采用扩散法或离子注入工艺经所述光阻层对所述待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂，以一次形成分别与所述待重掺杂区、待轻掺 杂区以及待掺杂沟道区对应的重掺杂区、轻掺杂区和沟道区。
  4. 根据权利要求2所述的掺杂方法，其中，所述经所述光阻层对所述待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂的步骤包括：
    采用扩散法或离子注入工艺经所述光阻层对所述待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂，以一次形成分别与所述待重掺杂区、待轻掺杂区以及待掺杂沟道区对应的重掺杂区、轻掺杂区和沟道区。
  5. 一种阵列基板的掺杂方法，其中，所述掺杂方法包括：
    提供基板，所述基板上定义有待重掺杂区、待轻掺杂区以及待掺杂沟道区；
    通过光刻工艺在所述基板上形成光阻层，其中，所述光阻层对应所述待重掺杂区形成第一光阻部，对应所述待轻掺杂区形成第二光阻部，对应所述待掺杂沟道区形成第三光阻部，所述第一光阻部比所述第二光阻部薄，所述第二光阻部比所述第三光阻部薄；
    经所述光阻层对所述待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂，以一次形成分别与所述待重掺杂区、待轻掺杂区以及待掺杂沟道区对应的重掺杂区、轻掺杂区和沟道区。
  6. 根据权利要求5所述的掺杂方法，其中，所述基板包括基板主体以及设置在基板主体上的多晶硅层，其中所述多晶硅层上定义有所述待重掺杂区、待轻掺杂区以及待掺杂沟道区。
  7. 根据权利要求5所述的掺杂方法，其中，所述通过光刻工艺在所述基板上形成光阻层的步骤包括：
    在所述待重掺杂区、待轻掺杂区以及待掺杂沟道区上设置均匀厚度的光刻胶；
    通过光掩膜板对所述光刻胶进行曝光，其中，所述光掩膜板包括第一透光部、第二透光部以及第三透光部，所述第一透光部、第二透光部以及第三透光部的透光率依次增大或依次减小；
    利用显影液对曝光后的所述光刻胶进行显影，以形成对应所述第一透光部的第一光阻部，对应所述第二透光部的第二光阻部以及对应所述第三透光部的第三光阻部。
  8. 根据权利要求7所述的掺杂方法，其中，所述光掩膜板为半色调光罩或灰阶光罩；所述半色调光罩对应所述第二光阻部的第二透光部为半透光膜，所述半透光膜的透过率在0～100％之间；所述灰阶光罩对应所述第二光阻部的第二 透光部具有至少一条狭缝，以遮挡部分光源实现半透光效果，所述狭缝控制透过率在0～100％之间。
  9. 根据权利要求5所述的掺杂方法，其中，所述经所述光阻层对所述待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂的步骤包括：
    采用扩散法或离子注入工艺经所述光阻层对所述待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂，以一次形成分别与所述待重掺杂区、待轻掺杂区以及待掺杂沟道区对应的重掺杂区、轻掺杂区和沟道区。
  10. 根据权利要求6所述的掺杂方法，其中，所述经所述光阻层对所述待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂的步骤包括：
    采用扩散法或离子注入工艺经所述光阻层对所述待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂，以一次形成分别与所述待重掺杂区、待轻掺杂区以及待掺杂沟道区对应的重掺杂区、轻掺杂区和沟道区。
  11. 根据权利要求7所述的掺杂方法，其中，所述经所述光阻层对所述待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂的步骤包括：
    采用扩散法或离子注入工艺经所述光阻层对所述待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂，以一次形成分别与所述待重掺杂区、待轻掺杂区以及待掺杂沟道区对应的重掺杂区、轻掺杂区和沟道区。
  12. 根据权利要求8所述的掺杂方法，其中，所述经所述光阻层对所述待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂的步骤包括：
    采用扩散法或离子注入工艺经所述光阻层对所述待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂，以一次形成分别与所述待重掺杂区、待轻掺杂区以及待掺杂沟道区对应的重掺杂区、轻掺杂区和沟道区。
  13. 一种阵列基板的掺杂设备，其中，所述掺杂设备包括：
    光刻装置，用于在基板上形成光阻层，其中，所述基板上定义有待重掺杂区、待轻掺杂区以及待掺杂沟道区；所述光阻层对应所述待重掺杂区形成第一光阻部，对应所述待轻掺杂区形成第二光阻部，对应所述待掺杂沟道区形成第三光阻部，所述第一光阻部比所述第二光阻部薄，所述第二光阻部比所述第三光阻部薄；
    以及掺杂装置，用于经所述光阻层对所述待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂，以一次形成分别与所述待重掺杂区、待轻掺杂区以及待掺杂沟道区对应的重掺杂区、轻掺杂区和沟道区。
  14. 根据权利要求13所述的掺杂设备，其中，所述基板包括基板主体以及设置在基板主体上的多晶硅层，其中所述多晶硅层上定义有所述待重掺杂区、待轻掺杂区以及待掺杂沟道区。
  15. 根据权利要求13所述的掺杂设备，其中，所述光刻装置包括光刻胶、光掩膜板、显影液以及曝光光源；
    其中，所述光刻胶以均匀的厚度设置在所述待重掺杂区、待轻掺杂区以及待掺杂沟道区上；
    所述光掩膜板包括第一透光部、第二透光部以及第三透光部，所述第一透光部、第二透光部以及第三透光部的透光率依次增大或依次减小；
    所述曝光光源通过所述光掩膜板对所述光刻胶进行曝光；
    所述显影液对曝光后的所述光刻胶进行显影，以形成对应所述第一透光部的第一光阻部，对应所述第二透光部的第二光阻部以及对应所述第三透光部的第三光阻部。
  16. 根据权利要求15所述的掺杂设备，其中，所述光掩膜板为半色调光罩或灰阶光罩；所述半色调光罩对应所述第二光阻部的第二透光部为半透光膜，所述半透光膜的透过率在0～100％之间；所述灰阶光罩对应所述第二光阻部的第二透光部具有至少一条狭缝，以遮挡部分光源实现半透光效果，所述狭缝控制透过率在0～100％之间。
  17. 根据权利要求13所述的掺杂设备，其中，所述掺杂装置采用扩散法或离子注入工艺经所述光阻层对所述待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂，以一次形成分别与所述待重掺杂区、待轻掺杂区以及待掺杂沟道区对应的重掺杂区、轻掺杂区和沟道区。
  18. 根据权利要求14所述的掺杂设备，其中，所述掺杂装置采用扩散法或离子注入工艺经所述光阻层对所述待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂，以一次形成分别与所述待重掺杂区、待轻掺杂区以及待掺杂沟道区对应的重掺杂区、轻掺杂区和沟道区。
  19. 根据权利要求15所述的掺杂设备，其中，所述掺杂装置采用扩散法或离子注入工艺经所述光阻层对所述待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂，以一次形成分别与所述待重掺杂区、待轻掺杂区以及待掺杂沟道区对应的重掺杂区、轻掺杂区和沟道区。
  20. 根据权利要求16所述的掺杂设备，其中，所述掺杂装置采用扩散法或 离子注入工艺经所述光阻层对所述待重掺杂区、待轻掺杂区以及待掺杂沟道区进行一次掺杂，以一次形成分别与所述待重掺杂区、待轻掺杂区以及待掺杂沟道区对应的重掺杂区、轻掺杂区和沟道区。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104916584A (zh) * 2015-04-30 2015-09-16 京东方科技集团股份有限公司 一种制作方法、阵列基板及显示装置
CN104900708B (zh) * 2015-05-28 2017-11-17 福州大学 一种改善漏极电流的薄膜晶体管
CN105097552A (zh) * 2015-08-14 2015-11-25 京东方科技集团股份有限公司 薄膜晶体管及阵列基板的制备方法、阵列基板及显示装置
CN106449518A (zh) * 2016-10-14 2017-02-22 武汉华星光电技术有限公司 Ltps阵列基板的制造方法及阵列基板
CN107393953B (zh) 2017-07-27 2020-04-10 武汉华星光电半导体显示技术有限公司 低温多晶硅薄膜晶体管及其制作方法、有机发光显示器
US11764062B2 (en) * 2017-11-13 2023-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor structure
SE541515C2 (en) * 2017-12-22 2019-10-22 Graphensic Ab Assembling of molecules on a 2D material and an electronic device
JP7024626B2 (ja) * 2018-06-27 2022-02-24 三菱電機株式会社 半導体装置、半導体装置の製造方法
CN109411411A (zh) * 2018-12-07 2019-03-01 深圳市华星光电半导体显示技术有限公司 Goa阵列基板的制作方法及液晶显示器
WO2020154981A1 (zh) * 2019-01-30 2020-08-06 深圳市柔宇科技有限公司 阵列基板及其制造方法、显示面板
CN109904076A (zh) * 2019-03-25 2019-06-18 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、基板及其制备方法、显示装置
CN110047800B (zh) * 2019-04-18 2021-01-15 武汉华星光电技术有限公司 阵列基板及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002009288A (ja) * 2000-06-20 2002-01-11 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2004146474A (ja) * 2002-10-23 2004-05-20 Sharp Corp 薄膜トランジスタを備えた装置およびその製造方法
CN1564313A (zh) * 2004-03-19 2005-01-12 友达光电股份有限公司 薄膜晶体管及其制作方法
JP2008177457A (ja) * 2007-01-22 2008-07-31 Seiko Epson Corp 半導体装置の製造方法、電気光学装置の製造方法、およびハーフトーンマスク

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW579604B (en) * 2002-12-17 2004-03-11 Ind Tech Res Inst Method of forming a top-gate type thin film transistor device
TWI222227B (en) * 2003-05-15 2004-10-11 Au Optronics Corp Method for forming LDD of semiconductor devices
JP5398228B2 (ja) * 2008-10-30 2014-01-29 株式会社アルバック 膜製造方法
CN102903649A (zh) * 2011-07-28 2013-01-30 中芯国际集成电路制造(上海)有限公司 一种选择离子注入的光刻胶厚度方法
CN102881571B (zh) * 2012-09-28 2014-11-26 京东方科技集团股份有限公司 有源层离子注入方法及薄膜晶体管有源层离子注入方法
CN103165529B (zh) * 2013-02-20 2015-04-29 京东方科技集团股份有限公司 一种阵列基板的制备方法
CN203826346U (zh) * 2014-04-25 2014-09-10 鄂尔多斯市源盛光电有限责任公司 一种掩膜板及离子注入设备

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002009288A (ja) * 2000-06-20 2002-01-11 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2004146474A (ja) * 2002-10-23 2004-05-20 Sharp Corp 薄膜トランジスタを備えた装置およびその製造方法
CN1564313A (zh) * 2004-03-19 2005-01-12 友达光电股份有限公司 薄膜晶体管及其制作方法
JP2008177457A (ja) * 2007-01-22 2008-07-31 Seiko Epson Corp 半導体装置の製造方法、電気光学装置の製造方法、およびハーフトーンマスク

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