WO2016090680A1 - Goa型显示面板及其驱动电路结构和驱动方法 - Google Patents

Goa型显示面板及其驱动电路结构和驱动方法 Download PDF

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WO2016090680A1
WO2016090680A1 PCT/CN2014/094857 CN2014094857W WO2016090680A1 WO 2016090680 A1 WO2016090680 A1 WO 2016090680A1 CN 2014094857 W CN2014094857 W CN 2014094857W WO 2016090680 A1 WO2016090680 A1 WO 2016090680A1
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Prior art keywords
scan lines
control circuit
switching transistors
control
signal line
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French (fr)
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许哲豪
姚晓慧
张天豪
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/416,736 priority Critical patent/US20160163276A1/en
Publication of WO2016090680A1 publication Critical patent/WO2016090680A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a GOA type display panel, a driving circuit structure thereof and a driving method thereof.
  • the driving circuit in the liquid crystal display is mainly completed by connecting an integrated circuit (IC) outside the liquid crystal panel.
  • IC integrated circuit
  • GOA Gate Driver on Array
  • GOA technology directly mounts gate driver circuits (Gate Driver ICs) on the array substrate instead of the driver chip fabricated by the external silicon chip.
  • GOA circuit can be directly fabricated around the panel, the process process is simplified, and the product cost can be reduced, and the integration of the liquid crystal panel can be improved, so that the panel tends to be thinner.
  • the mainstream 3D display technologies on the market include color difference type, polarized type, 3D shutter glass type and naked eye 3D.
  • the 3D shutter glasses technology has been widely recognized by the market for its outstanding stereoscopic effect, high resolution of the screen and low cost of the liquid crystal module.
  • BLU Backlight Unit
  • One of the technical problems to be solved by the present invention is to provide a driving circuit structure of a GOA type display panel, which can reduce the crosstalk phenomenon in the shutter type 3D display technology by inserting black technology, and can reduce the high frequency to LC. The charging effect of the panel.
  • a GOA type display panel and a driving method thereof are also provided.
  • the present invention provides a driving circuit structure of a GOA type display panel, comprising: a plurality of scanning lines; a first control circuit configured to control all odd scanning in the plurality of scanning lines Turning on or off a line or all even scan lines; a second control circuit configured to implement different connections between all pairs of odd and even scan lines in the plurality of scan lines in different display modes, the display mode The two-dimensional display mode and the three-dimensional display mode are included, wherein the dual scan lines are simultaneously turned on in the three-dimensional display mode.
  • the first control circuit and the second control circuit are disposed between the GOA circuit area and the effective display area, wherein the first control circuit
  • the method includes: a first set number of switching transistors, each of the switching transistors being respectively connected to each of the odd scanning lines or the respective even scanning lines; and a first control signal line configured to control opening and closing of the respective switching transistors, a first control signal line is coupled to a gate of each of the first set number of switching transistors;
  • the second control circuit includes: a second set number of switching transistors, each switching transistor being coupled to the Between each of the plurality of scan lines; a second control signal line configured to control the turning on and off of the respective switching transistors, the second control signal line and the second set number of switches The gates of each of the transistors are connected.
  • the first control circuit and the The ends of the second control circuit are disposed in two empty pins of the source driver chip.
  • a GOA type display panel comprising the drive circuit structure as described above.
  • a driving method of a GOA type display panel comprising a plurality of scanning lines, and disposed between a GOA circuit area of the GOA type display panel and an effective display area a first control circuit and a second control circuit, the method comprising: in a display phase of different display modes, the first control circuit controls opening of all odd scan lines or all even scan lines in the plurality of scan lines And closing; the second control circuit implements different connection manners between all pairs of parity scan lines in the plurality of scan lines, wherein the display mode comprises a two-dimensional display mode and a three-dimensional display mode, wherein, in the three-dimensional display mode Enable dual scan lines to be turned on at the same time.
  • the method further includes: in a display phase of the two-dimensional display mode, the first control signal line of the first control circuit is supplied to the first set number of switches Turning on a voltage of each of the transistors to turn on all odd scan lines or all even scan lines, wherein a gate of each of the first set number of switch transistors is connected to the first control signal line; a second control signal line of the second control circuit is supplied to a turn-off voltage of each of the second set number of switching transistors, thereby implementing disconnection between all pairs of parity scan lines in the plurality of scan lines, wherein the second A gate of each of the set number of switching transistors is connected to the second control signal line; and a scan signal for controlling each of the plurality of scan lines is controlled to be transmitted step by step by using a precharge scanning mode.
  • each odd scan line or each even scan line in the plurality of scan lines is In the on state, the first control signal line is supplied to a turn-off voltage of each of the first set number of switching transistors to turn off all odd scan lines or all even scan lines; during the entire scan period, the second control The signal line is supplied to an opening voltage of each of the second set number of switching transistors, thereby implementing shorting between all pairs of odd-numbered scanning lines of the plurality of scanning lines; and controlling a plurality of scanning lines by using a pre-charge scanning mode The progressive transmission of the scan signal of each scan line in the middle.
  • the pre-charge scanning mode is a four-stage pre-charge scanning.
  • One or more embodiments of the present invention may have the following advantages over the prior art.
  • the invention adds two control circuits between the GOA circuit area and the AA (active area) area, one of which is to add a TFT control switch on each odd scan line or each even scan line, and the other is to each pair of parity scan lines. Add TFT control switch between them, use these two control circuits to realize 2D normal display, and realize 3D display
  • the dual gates of the SG black insertion technology (frame rate is 240 Hz) are simultaneously turned on.
  • the circuit can be realized by simply using two empty pins of the source driver IC, without adding additional design and reducing the cost.
  • FIG. 1 is an equivalent circuit diagram of a structural portion of a driving circuit of a display panel according to an embodiment of the present invention
  • FIG. 2 is a timing chart when the display panel to which the driving circuit shown in FIG. 1 is applied performs 2D display and 3D display.
  • FIG. 1 is an equivalent circuit diagram of a structural portion of a driving circuit of a GOA type display panel according to an embodiment of the present invention.
  • the driving circuit includes a plurality of scanning lines, such as Gate_1, Gate_2, Gate_3, Gate_4, and the like as shown in the figure.
  • a first control circuit and a second control circuit disposed between the GOA circuit area and the effective display area (AA area) are also included.
  • a first control circuit configured to control the turning on and off of all odd scan lines (eg, Gate_1 and Gate_3, etc.) or all even scan lines (eg, Gate_2 and Gate_4, etc.) in the plurality of scan lines.
  • a second control circuit configured to implement different connections between all pairs of parity scan lines (eg, Gate_1 and Gate_2, Gate_3, and Gate_4) in the plurality of scan lines in different display modes, the display mode including two-dimensional The display mode and the three-dimensional display mode, wherein the dual scan lines are simultaneously turned on in the three-dimensional display mode.
  • all pairs of parity scan lines eg, Gate_1 and Gate_2, Gate_3, and Gate_4
  • the first control circuit controls all of the odd scan lines.
  • the first control circuit includes a plurality of (first set number) switching transistors (eg, TFT_1 and TFT_3 are illustrated) and a first control signal line SW1.
  • Each of the switching transistors is connected to each of the odd scan lines of the plurality of scan lines.
  • TFT_1 and TFT_3 are respectively connected to the odd scan lines Gate_1 and Gate_3.
  • First control signal line SW1 It is configured to control the opening and closing of respective switching transistors in the first control circuit, and the first control signal line SW1 is connected to the gates of the respective switching transistors in the first control circuit.
  • the second control circuit includes a plurality of (second set number) switching transistors (for example, TFT_2 and TFT_4 as illustrated) and a second control signal line SW2.
  • Each of the switching transistors is connected between each pair of parity scan lines, for example, TFT_2 is connected between the first pair of parity scan lines Gate_1 and Gate_2, and TFT_4 is connected between the second pair of parity scan lines Gate_3 and Gate_4.
  • the second control signal line SW2 is configured to control the turning on and off of the respective switching transistors in the second control circuit, and the second control signal line SW2 is connected to the gates of the respective switching transistors in the second control circuit.
  • the switching circuit in the GOA circuit area of FIG. 1 adopts a 4-stage pre-charge scan mode, and the two control circuits (SW1 and SW2) are used to realize compatibility between two-dimensional display and three-dimensional display. Please refer to FIG. 2 at the same time.
  • FIG. 2 is a timing chart when the display panel of the driving circuit shown in FIG. 1 is used for 2D display and 3D display.
  • the first control circuit controls all odd scan line transmissions in the plurality of scan lines; and the second control circuit controls to turn off all of the pair of odd scan lines among the plurality of scan lines.
  • the first control signal line SW1 is supplied to each of the switching transistor turn-on voltages connected thereto (high level as shown). , and then turn on each odd scan line.
  • the second control signal line SW2 is supplied to the off voltages of the respective switching transistors connected thereto (low level as shown), thereby achieving the disconnection between all the parity scan lines.
  • the GOA driving circuit of this embodiment adopts a four-stage pre-charge scanning mode, as shown in FIG. 1, four gate driving circuits 31, 32, 33, 34 are included, which are respectively connected to four scanning lines Gate_1, Gate_2, Gate_3, and Gate_4. connection.
  • the input terminal ST1 of the first gate drive circuit 31 receives the first start pulse signal ST1, the pulse signal duration being the gate open time, during which the clock signals CK1, CK2 CK3 and CK4 have no action.
  • the first gate driving circuit 31 outputs the scan voltage to the Gate_1 scan line connected thereto, and turns on the gate of the switch of the row of the Gate_1 scan line in the AA area, the data driver (not shown) Out) charging the pixels of the row.
  • the Gate_3 scan line also turns on the gate of the switch to receive the source signal from the data driver, precharging the pixels in the row of the Gate_3 scan line in the AA area.
  • the input terminal ST2 of the second gate drive circuit 32 After being delayed by a set time (preferably 1/2 of the gate-on time) with respect to the first start pulse signal ST1, the input terminal ST2 of the second gate drive circuit 32 receives the second start pulse signal ST2, the pulse The signal duration is the gate turn-on time.
  • the second gate driving circuit 32 outputs the scan voltage to the Gate_2 scan line connected thereto, and turns on the gate of the switch of the row of the Gate_2 scan line in the AA area, and the data driver drives the pixel of the row. Charge it.
  • the Gate_4 scan line also turns on the gate of the switch of the row of the Gate_4 scan line in the AA area to receive the source signal, and precharges the pixel of the row of the Gate_4 scan line in the AA area.
  • each of the plurality of scanning lines can be scanned step by step to realize normal two-dimensional display.
  • the first control circuit controls the transmission of the scan signals of all the odd scan lines in the plurality of scan lines; and the second control circuit controls all the pairs of the odd-even scan lines among the plurality of scan lines to be connected to each other by the control, That is, the connection method is a short connection method.
  • the first control signal line SW1 is supplied to the turn-off voltage of each of the switching transistors connected thereto when the odd-numbered scan lines are turned on.
  • the transmission of the scan signals of the odd-numbered scan lines is turned off, and the output of each even-numbered scan signal is not turned off at this time, that is, when the first control signal line SW1 is supplied to the odd-numbered scan line turn-off potential, the even-numbered scan lines are turned on.
  • the second control signal line SW2 is supplied to the respective switching transistor turn-on voltages connected thereto, thereby realizing short-circuiting between all the odd-numbered scan lines among the plurality of scan lines, thereby realizing each pair of parity scans.
  • the simultaneous switching of the wires enables simultaneous opening of the double gate (double scan line).
  • the scanning line is scanned step by step by using a precharge scanning method such as two-dimensional display to achieve better 3D display.
  • a precharge scanning method such as two-dimensional display to achieve better 3D display.
  • the double gates which are set to reduce the influence of the high frequency on the charging of the LC panel can be simultaneously turned on, that is, the parity scan lines are simultaneously turned on, thus reducing the scanning direction. Resolution, increase charging time, and achieve better 3D display.
  • all the odd scan lines are controlled by the first control circuit as an example, but in other embodiments, the first control circuit may be configured to control all even scan lines, and the present invention can also be implemented. Purpose, no longer repeat here.
  • the GOA driving circuit of the four-stage precharge scanning mode is employed, other GOA driving circuits of the precharge scanning mode may be employed.
  • two control circuits are added in the GOA circuit area and the AA area of the GOA type display panel, one of which is to add a TFT control switch on each odd scan line or each even scan line, and the other is in each pair of parity scans.
  • a TFT control switch is added between the lines, and the two control circuits are used to realize the 2D normal display, and the dual-gate simultaneous opening required for the 3D black insertion technology is realized.
  • the two control circuits can be realized by using only two empty pins of the source driver IC, and no additional design is required, which improves the display effect and reduces the cost.

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
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  • Liquid Crystal Display Device Control (AREA)
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Abstract

一种GOA型显示面板及其驱动电路结构和驱动方法，该驱动电路结构包括：多条扫描线（Gate_1, Gate_2, Gate_3, Gate_4）；一第一控制电路（TFT_1，TFT_3，SW1）；以及一第二控制电路（TFT_2，TFT_4，SW2）。通过在GOA电路区和AA区之间增加两条控制电路，利用这两条电路来实现2D正常显示，并实现3D显示中的双栅同时开启。另外，该电路只需利用源驱动IC的两个空管脚即可实现，不需新增额外设计，降低了成本。

Description

GOA型显示面板及其驱动电路结构和驱动方法
相关申请的交叉引用
本申请要求享有2014年12月8日提交的名称为“GOA型显示面板及其驱动电路结构和驱动方法”的中国专利申请CN201410748472.5的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种GOA型显示面板及其驱动电路结构和驱动方法。
背景技术
在现有技术中，液晶显示器中的驱动电路主要是通过在液晶面板外部连接集成电路(Integrated Circuit，IC)来完成的。相比之下，阵列基板行驱动(Gate Driver on Array)技术，简称GOA技术，其是直接将栅极驱动电路(Gate Driver ICs)制作在阵列基板上，以替代外接硅芯片制作的驱动芯片的一种技术。由于GOA电路可直接制作在面板周围，简化了制程工艺，而且还可降低产品成本，提高液晶面板的集成度，从而使面板趋向于更加薄型化。
目前，市场上主流的3D显示技术有色差式、偏光式、3D快门眼镜(3D shutter glass)式及裸眼3D。其中，3D快门眼镜式技术以其立体效果突出、画面分辨率高、液晶模组成本较低等优势得到了市场的广泛认可。
然而，由于受液晶响应速度的影响，因此会出现串扰(cross-talk)现象，例如左眼在观看左眼图像时，会同时看到上一场残留的部分右眼图像，导致左右眼图像重叠，形成重影，任何基于液晶显示的快门式3D电视都存在这种现象。为了降低3D显示时出现的串扰现象，背光(Back Light Unit，简称BLU)常采用扫描开关(Scanning)或动态区域开关(Local Dimming)技术。
由于扫描开关技术和动态区域开关技术所需的控制电路较复杂，成本较高，因此提出了在左右眼信号间采用插黑技术来降低串扰的解决方案。但是由于快门式3D技术是左右眼交替接收信号，所以对帧频(Frame rate)要求较高，一般在120Hz，而采用插黑技术后，帧频又要加倍，如此的高频要求对液晶面板充电影响较重，因此又提出了在3D显示时采用双栅(dual-gate)同时开启，来降低扫描方向上的分辨率，提高充电时间的解决方案，但这种方式又需要在PCB和栅极电路(Gate IC)上增加新的复杂设计，来实现上述功能。
因此，如何解决上述问题，在不增加新的复杂设计的情况下，对于GOA型面板来讲，既能通过插黑技术来减少快门式3D显示技术中的串扰现象，又能降低高频对液晶面板的充电影响，乃业界所致力的课题之一。
发明内容
本发明所要解决的技术问题之一是需要提供一种GOA型显示面板的驱动电路结构，该结构既能通过插黑技术来减少快门式3D显示技术中的串扰现象，又能降低高频对LC面板的充电影响。另外，还提供了GOA型显示面板及其驱动方法。
1)为了解决上述技术问题，本发明提供了一种GOA型显示面板的驱动电路结构，包括：多条扫描线；一第一控制电路，其配置以控制所述多条扫描线中所有奇数扫描线或所有偶数扫描线的开启和关闭；一第二控制电路，其配置以在不同显示模式下，实现所述多条扫描线中所有对奇偶扫描线之间的不同连接方式，所述显示模式包括二维显示模式和三维显示模式，其中，在三维显示模式下实现双扫描线同时开启。
2)在本发明的第1)项的一个优选实施方式中，所述第一控制电路和所述第二控制电路设置在GOA电路区和有效显示区之间，其中，所述第一控制电路包括：第一设定数量的开关晶体管，各个开关晶体管分别与各条奇数扫描线或各条偶数扫描线连接；一第一控制信号线，其配置以控制各个开关晶体管的开启和关闭，所述第一控制信号线与所述第一设定数量的开关晶体管中的每个的栅极连接；所述第二控制电路包括：第二设定数量的开关晶体管，各个开关晶体管分别连接至所述多条扫描线中的各对奇偶扫描线之间；一第二控制信号线，其配置以控制各个开关晶体管的开启和关闭，所述第二控制信号线与所述第二设定数量的开关晶体管中的每个的栅极连接。
3)在本发明的第1)项或第2)项中的一个优选实施方式中，所述第一控制电路和所 述第二控制电路的端部设置在源驱动芯片的两个空管脚内。
4)根据本发明的另一方面，还提供了一种GOA型显示面板，包括如上所述的驱动电路结构。
5)根据本发明的另一方面，还提供了一种GOA型显示面板的驱动方法，该液晶显示面板包括多条扫描线、以及设置在GOA型显示面板的GOA电路区和有效显示区之间的一第一控制电路和一第二控制电路，该方法包括：在不同显示模式的显示阶段，所述第一控制电路控制所述多条扫描线中所有奇数扫描线或所有偶数扫描线的开启和关闭；所述第二控制电路实现所述多条扫描线中所有对奇偶扫描线之间的不同连接方式，所述显示模式包括二维显示模式和三维显示模式，其中，在三维显示模式下实现双扫描线同时开启。
6)在本发明的第5)项的一个优选实施方式中，进一步包括：在二维显示模式的显示阶段，所述第一控制电路的第一控制信号线提供给第一设定数量的开关晶体管中每个的开启电压以开启所有奇数扫描线或所有偶数扫描线，其中，所述第一设定数量的开关晶体管中的每个的栅极与所述第一控制信号线连接；所述第二控制电路的第二控制信号线提供给第二设定数量的开关晶体管中每个的关闭电压，进而实现多条扫描线中的所有对奇偶扫描线之间断开，其中，所述第二设定数量的开关晶体管中的每个的栅极与所述第二控制信号线连接；利用预充电扫描方式控制多条扫描线中的每条扫描线的扫描信号逐级传输。
7)在本发明的第5)项或第6)项中的一个优选实施方式中，在三维显示模式的显示阶段，在所述多条扫描线中的各奇数扫描线或各偶数扫描线是开启状态时，所述第一控制信号线提供给第一设定数量的开关晶体管中每个的关闭电压以关闭所有奇数扫描线或所有偶数扫描线；在整个扫描周期中，所述第二控制信号线提供给第二设定数量的开关晶体管中每个的开启电压，进而实现所述多条扫描线中的所有对奇偶扫描线之间的短接；利用预充电扫描方式控制多条扫描线中的每条扫描线的扫描信号的逐级传输。
8)在本发明的第5)项-第7)项中任一项的一个优选实施方式中，
所述预充电扫描方式为四级预充电扫描。
与现有技术相比，本发明的一个或多个实施例可以具有如下优点。
本发明通过在GOA电路区域和AA(active area)区之间增加两条控制电路，其中一条是在各奇数扫描线或各偶数扫描线上增加TFT控制开关，另一条是在各对奇偶扫描线之间增加TFT控制开关，利用这两条控制电路来实现2D正常显示，并实现3D显示时 SG插黑技术(帧频为240Hz)的双栅极同时开启。另外，该电路只需利用源驱动IC的两个空管脚(pin)即可实现，不需新增额外设计，降低了成本。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。在附图中：
图1是根据本发明一实施例的显示面板的驱动电路结构部分的等效电路图；
图2是应用图1所示驱动电路的显示面板在进行2D显示和3D显示时的时序图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，以下结合附图对本发明作进一步地详细说明。
请参考图1，图1是根据本发明一实施例的GOA型显示面板的驱动电路结构部分的等效电路图。
该驱动电路包括多条扫描线，如图中所示的Gate_1、Gate_2、Gate_3、Gate_4等。还包括设置在GOA电路区和有效显示区(AA区)之间的一第一控制电路和一第二控制电路。第一控制电路，其配置以控制多条扫描线中所有奇数扫描线(例如，图示Gate_1和Gate_3等)或所有偶数扫描线(例如，图示Gate_2和Gate_4等)的开启和关闭。第二控制电路，其配置以在不同显示模式下，实现多条扫描线中所有对奇偶扫描线(例如，图示Gate_1和Gate_2、Gate_3和Gate_4)之间的不同连接方式，显示模式包括二维显示模式和三维显示模式，其中，在三维显示模式下实现双扫描线同时开启。
在本实施例中，第一控制电路控制所有奇数扫描线。请进一步参考图1，第一控制电路包括多个(第一设定数量)开关晶体管(例如，图示TFT_1和TFT_3)和一第一控制信号线SW1。其中，各个开关晶体管与多条扫描线中的各奇数扫描线一一连接，如图1所示，TFT_1和TFT_3分别与奇数扫描线Gate_1和Gate_3连接。第一控制信号线SW1， 其配置以控制第一控制电路中的各个开关晶体管的开启和关闭，第一控制信号线SW1与该第一控制电路中的各个开关晶体管的栅极连接。
第二控制电路包括多个(第二设定数量)开关晶体管(例如，图示的TFT_2和TFT_4)和第二控制信号线SW2。各个开关晶体管分别连接至各对奇偶扫描线之间，例如TFT_2连接在第一对奇偶扫描线Gate_1和Gate_2之间，TFT_4连接在第二对奇偶扫描线Gate_3和Gate_4之间。第二控制信号线SW2，其配置以控制第二控制电路中的各个开关晶体管的开启和关闭，第二控制信号线SW2与该第二控制电路中的各个开关晶体管的栅极连接。
下面来详细说明本实施例的应用该驱动电路的显示面板在进行二维显示和三维显示时的驱动过程。
图1中的GOA电路区中的开关电路采用的是4级预充电扫描(pre-charge scan)方式，利用上述两条控制电路(SW1和SW2)实现二维显示和三维显示的兼容。请同时参考图2，图2是应用图1所示驱动电路的显示面板在进行2D显示和3D显示时的时序图。
在二维显示模式的显示阶段，第一控制电路控制多条扫描线中所有奇数扫描线传输；第二控制电路通过控制使多条扫描线中所有对奇偶扫描线之间是断开的。
具体地，如图2的上图(2D时序图)所示，在扫描时间周期内，第一控制信号线SW1提供给与之连接的各个开关晶体管开启电压(如图所示的高电平)，进而开启各奇数扫描线。同时，在这个阶段，第二控制信号线SW2提供给与之连接的各个开关晶体管的关闭电压(如图所示的低电平)，进而实现所有对奇偶扫描线之间的断开。
由于本实施例的GOA驱动电路采用四级预充电扫描模式，如图1所示，包括四个栅极驱动电路31、32、33、34，它们分别与四条扫描线Gate_1、Gate_2、Gate_3和Gate_4连接。
在扫描时间周期内，第一栅极驱动电路31的输入端ST1接收第一启始脉冲信号ST1，该脉冲信号持续时间为栅极(Gate)开启时间，在此期间，时钟信号CK1、CK2、CK3和CK4没有任何动作。在时钟信号CK1的上升沿时刻，第一栅极驱动电路31输出扫描电压到与之连接的Gate_1扫描线，打开AA区中Gate_1扫描线所在行的开关的栅极，数据驱动器(图中未示出)对该行的像素进行充电。在CK3的上升沿时刻，Gate_3扫描线也将开关的栅极开启接收来自数据驱动器的源极信号，对AA区中Gate_3扫描线所在行的像素进行预充电。
在相对于第一启始脉冲信号ST1延迟了设定时间(优选为栅极开启时间的1/2)后，第二栅极驱动电路32输入端ST2接收第二启始脉冲信号ST2，该脉冲信号持续时间为栅极开启时间。在时钟信号CK2的上升沿时刻，第二栅极驱动电路32输出扫描电压到与之连接的Gate_2扫描线，打开AA区中Gate_2扫描线所在行的开关的栅极，数据驱动器对该行的像素进行充电。在时钟信号CK4的上升沿时刻，Gate_4扫描线也将AA区中Gate_4扫描线所在行的开关的栅极开启以接收源极信号，对AA区中Gate_4扫描线所在行的像素进行预充电。
那么，通过上述驱动，使得多条扫描线中的各个扫描线可以逐级扫描，实现正常的二维显示。
在三维显示模式的显示阶段，第一控制电路控制多条扫描线中所有奇数扫描线的扫描信号的传输；第二控制电路通过控制使多条扫描线中所有对奇偶扫描线之间彼此连接，即连接方式是短接方式。
具体地，如图2的下图(3D时序图)所示，在扫描时间周期内，第一控制信号线SW1在奇数扫描线是开启状态时，提供给与之连接的各个开关晶体管的关闭电压，关闭各奇数扫描线的扫描信号的传输，而此时未关闭各偶数扫描信号的输出，即第一控制信号线SW1提供给奇数扫描线关闭电位时，各偶数扫描线是开启状态。同时，在此阶段，在第二控制信号线SW2提供给与之连接的各个开关晶体管开启电压，实现多条扫描线中的所有对奇偶扫描线之间的短接，进而可以实现各对奇偶扫描线的同时开关，实现双栅(双扫描线)同时开启。
然后，利用如二维显示时的预充电扫描方式实现扫描线逐级扫描，实现较佳的3D显示。需要说明的是，这两条控制电路在空白时间和扫描时间所给的电压是相反的，这样会使得开关晶体管的性能更加稳定。
而且，通过上述驱动，在三维显示阶段进行插黑过程中，能够实现为了降低高频对LC面板充电的影响而设置的双栅同时开启，即奇偶扫描线同时开启，这样降低了扫描方向上的分辨率，提高充电时间，实现较佳的3D显示。
需要说明的是，本实施例中以第一控制电路控制所有奇数扫描线为例进行说明，但是在其他实施例中第一控制电路可以被设置为控制所有偶数扫描线，也能实现本发明的目的，在此不再赘述。另外，虽然以四级预充电扫描模式的GOA驱动电路，但是也可以采取其他预充电扫描模式的GOA驱动电路。
综上，通过在GOA型显示面板的GOA电路区和AA区增加两条控制电路，其中一条是在各奇数扫描线或各偶数扫描线上增加了TFT控制开关，另一条是在各对奇偶扫描线之间增加了TFT控制开关，利用这两条控制电路来实现2D正常显示，并实现3D插黑技术所需的双栅(dual-gate)同时开启。另外，这两条控制电路只需利用源驱动IC的两个空管脚即可实现，不需新增额外设计，在提高了显示效果的同时，还降低了成本。
以上所述，仅为本发明较佳的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉该技术的人员在本发明所揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。

Claims (10)

  1. 一种GOA型显示面板的驱动电路结构，包括：
    多条扫描线；
    一第一控制电路，其配置以控制所述多条扫描线中所有奇数扫描线或所有偶数扫描线的开启和关闭；
    一第二控制电路，其配置以在不同显示模式下，实现所述多条扫描线中所有对奇偶扫描线之间的不同连接方式，所述显示模式包括二维显示模式和三维显示模式，其中，在三维显示模式下实现双扫描线同时开启。
  2. 根据权利要求1所述的驱动电路结构，其中，所述第一控制电路和所述第二控制电路设置在GOA电路区和有效显示区之间，其中，
    所述第一控制电路包括：
    第一设定数量的开关晶体管，各个开关晶体管分别与所述多条扫描线中的各条奇数扫描线或各条偶数扫描线连接；
    一第一控制信号线，其配置以控制各个开关晶体管的开启和关闭，所述第一控制信号线与所述第一设定数量的开关晶体管中的每个的栅极连接；
    所述第二控制电路包括：
    第二设定数量的开关晶体管，各个开关晶体管分别连接至所述多条扫描线中的各对奇偶扫描线之间；
    一第二控制信号线，其配置以控制各个开关晶体管的开启和关闭，所述第二控制信号线与所述第二设定数量的开关晶体管中的每个的栅极连接。
  3. 根据权利要求2所述的驱动电路结构，其中，
    所述第一控制电路和所述第二控制电路的端部设置在源驱动芯片的两个空管脚内。
  4. 一种GOA型显示面板，包括驱动电路结构，
    所述驱动电路结构，包括：
    多条扫描线；
    一第一控制电路，其配置以控制所述多条扫描线中所有奇数扫描线或所有偶数扫描线的开启和关闭；
    一第二控制电路，其配置以在不同显示模式下，实现所述多条扫描线中所有对奇偶扫描线之间的不同连接方式，所述显示模式包括二维显示模式和三维显示模式，其中，在三维显示模式下实现双扫描线同时开启。
  5. 根据权利要求4所述的GOA型显示面板，其中，所述第一控制电路和所述第二控制电路设置在GOA电路区和有效显示区之间，其中，
    所述第一控制电路包括：
    第一设定数量的开关晶体管，各个开关晶体管分别与所述多条扫描线中的各条奇数扫描线或各条偶数扫描线连接；
    一第一控制信号线，其配置以控制各个开关晶体管的开启和关闭，所述第一控制信号线与所述第一设定数量的开关晶体管中的每个的栅极连接；
    所述第二控制电路包括：
    第二设定数量的开关晶体管，各个开关晶体管分别连接至所述多条扫描线中的各对奇偶扫描线之间；
    一第二控制信号线，其配置以控制各个开关晶体管的开启和关闭，所述第二控制信号线与所述第二设定数量的开关晶体管中的每个的栅极连接。
  6. 根据权利要求5所述的GOA型显示面板，其中，
    所述第一控制电路和所述第二控制电路的端部设置在源驱动芯片的两个空管脚内。
  7. 一种GOA型显示面板的驱动方法，该液晶显示面板包括多条扫描线、以及设置在GOA型显示面板的GOA电路区和有效显示区之间的一第一控制电路和一第二控制电路，该方法包括：
    在不同显示模式的显示阶段，
    所述第一控制电路控制所述多条扫描线中所有奇数扫描线或所有偶数扫描线的开启和关闭；
    所述第二控制电路实现所述多条扫描线中所有对奇偶扫描线之间的不同连接方式，所述显示模式包括二维显示模式和三维显示模式，其中，在三维显示模式下实现双扫描线同时开启。
  8. 根据权利要求7所述的驱动方法，其中，进一步包括：
    在二维显示模式的显示阶段，
    所述第一控制电路的第一控制信号线提供给第一设定数量的开关晶体管中每个的开启电压以开启所有奇数扫描线或所有偶数扫描线，其中，所述第一设定数量的开关晶体管中的每个的栅极与所述第一控制信号线连接；
    所述第二控制电路的第二控制信号线提供给第二设定数量的开关晶体管中每个的关闭电压，进而实现多条扫描线中的所有对奇偶扫描线之间断开，其中，所述第二设定数量的开关晶体管中的每个的栅极与所述第二控制信号线连接；
    利用预充电扫描方式控制多条扫描线中的每条扫描线的扫描信号逐级传输。
  9. 根据权利要求8所述的驱动方法，其中，
    在三维显示模式的显示阶段，
    在所述多条扫描线中的各奇数扫描线或各偶数扫描线是开启状态时，所述第一控制信号线提供给第一设定数量的开关晶体管中每个的关闭电压以关闭所有奇数扫描线或所有偶数扫描线；
    在整个扫描周期中，所述第二控制信号线提供给第二设定数量的开关晶体管中每个的开启电压，进而实现所述多条扫描线中的所有对奇偶扫描线之间的短接；
    利用预充电扫描方式控制多条扫描线中的每条扫描线的扫描信号的逐级传输。
  10. 根据权利要求8或9所述的驱动方法，其中，
    所述预充电扫描方式为四级预充电扫描。
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CN104880874A (zh) * 2015-05-20 2015-09-02 深圳市华星光电技术有限公司 一种液晶显示面板及装置
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