WO2016080670A1 - Test tray for test handler and interface board for tester - Google Patents

Test tray for test handler and interface board for tester Download PDF

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Publication number
WO2016080670A1
WO2016080670A1 PCT/KR2015/011433 KR2015011433W WO2016080670A1 WO 2016080670 A1 WO2016080670 A1 WO 2016080670A1 KR 2015011433 W KR2015011433 W KR 2015011433W WO 2016080670 A1 WO2016080670 A1 WO 2016080670A1
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WO
WIPO (PCT)
Prior art keywords
calibration
insert
hole
pin
test
Prior art date
Application number
PCT/KR2015/011433
Other languages
French (fr)
Korean (ko)
Inventor
나윤성
황정우
최희준
Original Assignee
(주)테크윙
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020150146230A external-priority patent/KR102489549B1/en
Application filed by (주)테크윙 filed Critical (주)테크윙
Priority to CN201580063135.5A priority Critical patent/CN106999988B/en
Priority to JP2017519886A priority patent/JP6375059B2/en
Publication of WO2016080670A1 publication Critical patent/WO2016080670A1/en

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/04Housings; Supporting members; Arrangements of terminals
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/06Measuring leads; Measuring probes
    • G01R1/067Measuring probes
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26Testing of individual semiconductor devices
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26Testing of individual semiconductor devices
    • G01R31/27Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer

Definitions

  • the present invention relates to an interface board electrically connected to a semiconductor device in a test tray and a tester capable of loading a semiconductor device in a test handler.
  • the test handler moves semiconductor devices manufactured through a predetermined manufacturing process from a customer tray to a test tray, and then the semiconductor devices loaded in the test tray are simultaneously tested by a tester (TESTER).
  • TEST which is a device that moves semiconductor devices from test trays to customer trays by classifying semiconductor devices according to test results.
  • the test tray has a structure in which inserts (INSERTs) having a seating space in which a semiconductor device is inserted are formed in an installation frame.
  • inserts INERTs
  • the insert has a supporting portion for supporting the semiconductor element seated in the seating space.
  • the support portion may be injection molded integrally with the body of the insert as referred to in Republic of Korea Patent No. 10-0801927, etc., may be provided in a thin film form as in Republic of Korea Patent Publication No. 10-2010-0081131.
  • the semiconductor device is fixed in a state of being seated in the seating space of the insert.
  • the semiconductor device is electrically connected to the test socket provided on the tester's interface board in the seating space of the insert. Therefore, there is a need to correct the position of the insert for accurate electrical connection between the semiconductor element in the insert and the test socket.
  • the insert is thus more or less fluidly coupled to the mounting frame.
  • the insert is formed with a calibration hole, and the interface board is provided with a socket guider having a calibration pin inserted into the calibration hole (see Korean Patent Publication No. 10-2013-0059485, etc., hereinafter referred to as 'prior art').
  • the number of terminals increases while the size of the semiconductor device is reduced.
  • the spacing between the terminals of the ball type and the size of the terminals are also reduced, resulting in the necessity of more precise and stable electrical connection between the terminals of the semiconductor device and the tester.
  • manufacturing tolerances of the calibration pin and the calibration hole should be considered so that the calibration pin can be properly inserted into the calibration hole. It should also be taken into account that there is a manufacturing tolerance between the socket guider and the test socket. Therefore, by making the inner diameter of the calibration hole larger than the diameter of the calibration pin, the calibration pin can be inserted into the calibration hole even if the center of the calibration pin is slightly away from the center of the calibration hole. If manufacturing tolerances are not taken into consideration, a failure may occur in the insertion of the calibration pins into the calibration holes, resulting in malfunction or damage to the inserts, and proper electrical connection between the semiconductor device and the test socket may not be achieved. If the calibration pin is inserted into the calibration hole by interference fit, it may be difficult for the calibration pin to come out of the calibration hole later.
  • the prior art has reached the limit of precisely correcting the position of the insert as much as the spacing between terminals that are miniaturized and the size of the terminals that decrease.
  • a second object of the present invention is to provide a technique capable of minimizing reflection of manufacturing tolerances.
  • the insert is formed with a seating space on which the semiconductor device can be seated; And an installation frame in which the insert is installed to be movable. It includes, The insert, The seating body is formed body; A support part formed integrally with the main body or coupled to the main body to support the semiconductor device seated in the seating space; And a fixing device for fixing the semiconductor device to prevent detachment of the semiconductor device seated in the seating space, wherein the first calibration pin of the socket guider provided in the interface board of the tester is inserted into the main body. A first calibration hole and a second calibration hole into which the second calibration pin of the socket guider can be inserted are formed.
  • the first calibration pin is first inserted into the first calibration hole and the second calibration pin is inserted later into the second calibration hole, thereby providing the first calibration hole.
  • the position of the insert is firstly corrected by the action of the first calibration pin and the position of the insert is secondarily precisely corrected by the action of the second calibration hole and the second calibration pin.
  • the first calibration pin Since the first calibration pin has a higher height than the second calibration pin, the first calibration pin may be inserted into the first calibration hole, and then the second calibration pin may be inserted into the second calibration hole.
  • the second calibration hole is in the form of a long hole in one side direction.
  • the second calibration hole is in the form of a longer hole in a straight direction passing through the center of the second calibration hole and the center of the insert.
  • An interface board for a tester for achieving the above object, the test socket electrically connected to the semiconductor element in the insert of the test tray; A socket guider for calibrating the position of the insert for electrical connection between the test socket and the semiconductor device; And a mounting board on which the test socket and the socket guider are installed, wherein the socket guider includes: a first calibration pin inserted into a first calibration hole formed in the insert to primarily calibrate the position of the insert; And a second calibration pin inserted into a second calibration hole formed in the insert to secondly correct the position of the insert. It includes.
  • the first calibration pin is first inserted into the first calibration hole, thereby first calibrating the position of the insert and the second calibration pin is later inserted into the second calibration hole.
  • the position of the insert is secondarily precisely calibrated.
  • the first calibration pin Since the first calibration pin has a higher height than the second calibration pin, the first calibration pin may be inserted into the first calibration hole, and then the second calibration pin may be inserted into the second calibration hole.
  • An alignment hole is formed in the test socket, and the socket guider has an alignment pin that can be inserted into the alignment hole.
  • the second calibration pin and the alignment pin may be provided on the same axis.
  • the second calibration pin has an elliptic shape with a flat cross section long in one direction.
  • the insert is formed with a seating space on which the semiconductor device can be seated; And an installation frame to which the insert is fixedly installed. It includes, The insert, The seating body is formed body; A support part formed integrally with the main body or coupled to the main body to support the semiconductor device seated in the seating space; And a fixing device for fixing the semiconductor device to prevent detachment of the semiconductor device seated in the seating space, wherein the body includes a calibration hole into which the calibration pin of the socket guider is inserted into the interface board of the tester. The wall surface forming the calibration hole is formed at least partially cut to reduce the contact portion with the calibration pin inserted into the calibration hole.
  • the main body When the calibration pin is inserted into the calibration hole, the main body has a plurality of circumferential directions on the outer side of the calibration hole so that the portion of the wall that forms the calibration hole in contact with the calibration pin is retracted outward and then elastically restored. An incision hole is formed.
  • the position of the insert is roughly calibrated first, and then the position of the insert is finely calibrated later, so that precise insert position calibration can be made without causing damage to the insert.
  • the assembly tolerances (manufacturing tolerances) generated in the process of assembling the test socket and the socket guider can be reduced as much as possible, thereby making the insert position more precise.
  • the wall surface constituting the calibration hole can be elastically resilient to flow, the calibration pin can be more easily exited from the calibration hole.
  • FIG. 1 is a plan view of a test tray for a test handler according to a first embodiment of the present invention.
  • FIG. 2 is a plan view of an interface board for a tester according to a first embodiment of the present invention.
  • FIG. 3 is a side view illustrating a coupled state of a test socket and a socket guider applied to the interface board of FIG. 2.
  • 4 to 6 are exaggerated diagrams conceptually extracting main parts of the test tray of FIG. 1 and the interface board of FIG. 2 to explain the operation of the main parts of the first embodiment of the present invention.
  • FIG. 3 is a perspective view illustrating the mutual structure of an insert installed in the test tray of FIG. 1 and a socket guider and a test socket installed in the interface board of FIG.
  • 4 to 6 is a schematic side view for explaining the operation of the main portion of the test tray and the interface board according to the present invention.
  • Fig. 7 is a reference diagram showing the formation positions of second calibration holes formed in various kinds of inserts.
  • FIG. 8 is a plan view of a test tray for a test handler according to a second embodiment of the present invention.
  • FIG. 9 is an enlarged perspective view of the main part of FIG. 8;
  • test tray 100 for a test handler (hereinafter, abbreviated as 'test tray') according to a first embodiment of the present invention.
  • the test tray 100 includes a plurality of inserts 110 and the installation frame 120.
  • the insert 110 includes a main body 111, a support portion 112, and a fixture 113.
  • the main body 111 has a seating space SS on which the semiconductor device is mounted.
  • two first calibration holes CH1 and four second calibration holes CH2 are formed in the main body 111.
  • the first calibration hole CH1 is formed to have an inner diameter in consideration of the manufacturing tolerances described in the section “Technology Background of the Invention”.
  • the first calibration hole CH1 serves to primarily correct the position of the insert 110.
  • the second straightening hole CH2 is formed to more precisely and secondarily correct the position of the insert 110 that is primarily straightened by the action of the first straightening hole CH1. Therefore, after the position of the insert 110 is firstly corrected by the first calibration hole CH1, the position of the insert 110 is secondarily more precisely corrected by the second calibration hole CH2.
  • the second calibration hole CH2 is formed on the crosshair CL based on the center O 1 of the insert 110, and is formed of a longer hole having a longer shape in the crosshair CL direction.
  • the second calibration hole CH2 on the X-axis line of the crosshair CL is a long hole in the X-axis direction
  • the second calibration hole CH2 on the Y-axis line of Fig. 3 is a long hole in the Y-axis direction.
  • the X axis and the Y axis are straight lines passing through the center of the second calibration hole CH2 and the center O 1 of the insert 110.
  • the second calibration hole CH2 is formed as a long hole, so that the function may be maintained even when the insert 110 itself is thermally expanded or cooled down based on the center O 1 of the insert 110.
  • the support part 112 supports the semiconductor device seated in the seating space SS.
  • the support portion 112 is provided with a thin film is coupled to the main body 111.
  • the support part 112 is provided with exposure holes EH that induce proper seating of the semiconductor device and allow terminals of the semiconductor device to be exposed to the test socket side.
  • the support portion 112 may be formed integrally with the main body 111.
  • the fixing unit 113 may also be referred to as a latch or a holding device, and is coupled to the main body 111 to be operable.
  • the fixture 113 fixes the semiconductor device supported by the support part 112 in a state of being seated in the seating space SS.
  • the fixing of the semiconductor device by the fixing unit 113 is performed by a separate opening device (refer to Republic of Korea Patent Application Publication No. 10-2011-0121063).
  • the insert frame 110 is coupled to the installation frame 120 by a coupler (not provided with a bolt and a nut) so as to be able to flow somewhat.
  • FIG. 2 is a plan view of the tester interface board 200 (hereinafter, abbreviated as 'interface board') according to the first embodiment of the present invention.
  • the interface board 200 includes a plurality of test sockets 210, a socket guider 220, and an installation board 230.
  • the test socket 210 has a socket portion 211 electrically connected to a semiconductor device in the insert 110 of the test tray 100.
  • four alignment holes AH are formed on the crosshair CL based on the bolt hole BH1 and the center O 2 of the test socket 210.
  • the socket guider 220 corrects the position of the insert 110 for electrical connection between the test socket 210 and the semiconductor device.
  • the socket guider 220 is provided with two first calibration pins CP1 at positions corresponding to two first calibration holes CH1, and positions corresponding to four second calibration holes CH2.
  • Four second calibration pins CP2 are provided.
  • four alignment pins AP are provided at positions corresponding to the four alignment holes AH as referred to in the conceptual side view of FIG. 3.
  • the first calibration pins CP1 are inserted into the first calibration holes CH1 to primarily correct the position of the insert 110.
  • the second calibration pins CP2 As the second calibration pins CP2 are inserted into the second calibration holes CH2, the second calibration pins CP2 are secondarily calibrated more precisely.
  • the second calibration pins CP2 have a shape corresponding to the second calibration hole CH2 having a long hole shape, and have a flat cross section having an elliptical shape.
  • the diameter of the short radius side of the second straightening pin CP2 in the cross section of the second straightening pin CP2 is substantially equal to the diameter of the short radius side of the second straightening hole CH2, and the diameter of the long radius side is the second straightening hole. It is rather shorter than the diameter of the long radius side of (CH2). This reason is taken into account the expansion of the insert 110 and the thermal expansion of the test socket 210 or the second calibration pin (CP2). That is, even if the second calibration pin CP2 expands or the second calibration pin CP2 does not expand due to thermal expansion, a free space must exist within the second calibration hole CH2 in consideration of movement in the thermal expansion direction. to be. By making the cross section elliptical in this way, the strength of the second calibration pin CP2, which is relatively thinner with respect to the first calibration pin CP1, may be reinforced.
  • the protruding height H 1 of the first straightening pins CP1 is higher than the height H 2 from which the second straightening pins CP2 protrude.
  • the first calibration pins CP1 are first inserted into the first calibration holes CH1 to align the position of the insert 110, and the second calibration pins CP2 are arranged to the second calibration holes CH2.
  • the first calibration pin and the second calibration pin have the same height while the first calibration pin is inserted into the first calibration hole first, and then the second calibration pin is inserted into the second calibration hole later.
  • the shape of the structure may be changed.
  • Alignment pins AP are inserted into the alignment holes AH.
  • the alignment pins AP and the alignment holes AH may be installed on the installation board 230 in a state where the socket guider 220 and the test socket 210 are precisely positioned.
  • the four second calibration pins CP2 and the four alignment pins AP are provided on the same axis SA 1 , SA 2 , SA 3 in the same form as shown in FIG. 3. Can be.
  • Four second calibration pins CP2 and four alignment pins AP may be integrally formed or separately.
  • the alignment pins are formed in a position different from the second calibration pins.
  • the socket guide 220 has a bolt hole BH2 formed at a position corresponding to the bolt hole BH1 of the test socket 210. Therefore, the test socket 210 and the socket guider 220 are installed on the installation board 230 by the bolt not shown.
  • the protruding height h 1 of the alignment pins AP may be equal to or smaller than the depth h 2 of the alignment hole AH of the test socket 210.
  • the operator by inserting the alignment pin (AP) in the alignment hole (AH) in advance during the bolt coupling operation test socket 210 and the socket guider 220 in a state that the test socket coupled to the test socket ( 210 and the socket guider 220 is coupled to the installation board (230).
  • the test socket and the socket guider are installed on the installation board by the alignment pins by forming a screw thread on one side of the alignment pins (the part facing the installation board side), no additional bolt holes or bolts may be required.
  • FIG. 4 (a) shows a state where the insert 110 and the test socket 210 are spaced apart from each other at a distance
  • FIG. 4 (b) shows the insert 110 of the insert 110 in the state (a) of FIG. 1
  • the first calibration pin CP1 is inserted into the first calibration hole CH1 as shown in FIG. While first inserted, the position of the insert 110 is primarily aligned as shown in FIG. Accordingly, in the state where the second calibration pin CP2 is greatly shifted from the second calibration hole CH2 as in FIG. 4B, the second calibration pin CP2 is second-calibrated as in FIG. 5B. It is corrected to a position that can be inserted into the hole CH2.
  • the second calibration pin CP2 is inserted into the second calibration hole CH2 as shown in FIG. 6, and thus the position of the insert 110 is improved. Secondly finely calibrated.
  • the present invention precisely positions the insert 110 in two steps by the first calibration hole CH1 / first calibration pin CP1 and the second calibration hole CH2 / second calibration pin CP2. It is a technique to correct. However, the present invention extends to applications in which the position of the insert is precisely corrected in three steps using the third calibration hole / third calibration pin, or the position of the insert is precisely corrected in four or more steps. Can be.
  • a second calibration hole CH2 is formed on the crosshair CL based on the center O 1 of the insert 110.
  • CL the direction
  • the inserts 110A, 110B, and 110C may have various types of shapes. Therefore, depending on the type of the inserts 110A, 110B, and 110C, it may be difficult to arrange the second calibration holes CH2 on the crosshairs CL, and it may be difficult to form long holes having different lengths. Therefore, various modifications as shown in FIG. 7 may be followed.
  • two second calibration holes CH2-a of the second calibration holes CH2-a and CH2-b are formed at corner portions facing each other diagonally, and two The other second straightening hole CH2-b is formed on the center line C dividing the insert 110A bilaterally.
  • the calibration hole of the sign CH2-a is in the form of a long hole in the left and right direction
  • the calibration hole of the sign CH2-b is in the form of a long hole in the front and rear direction on the drawing.
  • the second calibration hole CH2 is formed in both the front part and the rear part, divided on both sides of the center line C, which divides the insert 110B bilaterally. And all the second calibration holes (CH2) is in the form of a long hole in the front and rear direction on the drawing.
  • the second calibration hole CH2 is formed at the left side and the right side divided into both sides of the center line C dividing the insert 110C bilaterally. And all the second calibration holes (CH2) is in the form of a long hole in the left and right directions on the drawing.
  • the second calibration holes CH2 may have various arrangements according to the shapes of the inserts 100, 110A, 110B, and 110C.
  • the second calibration pins of the interface board should also be provided to correspond to the arrangement of the second calibration holes CH2-a, CH2-b, and CH2 according to various shapes of the inserts 110A, 110B, and 110C of FIG. 7. .
  • test tray 700 for a test handler according to a second embodiment of the present invention.
  • the test tray 700 includes a plurality of inserts 710 and an installation frame 720.
  • the insert 710 includes a body 711, a support portion 712 and a fixture 713.
  • the support part 712 and the fixing device 713 are the same as in the first embodiment, description thereof will be omitted.
  • the main body 711 has a mounting space SS on which a semiconductor device may be mounted.
  • the main body 711 is provided with the calibration hole CH and the cutting hole IH.
  • the wall surface W constituting the calibration hole CH has an incision portion IP to reduce the contact portion with the calibration pin inserted into the calibration hole CH.
  • the incision hole IH functions to allow a portion of the wall surface W constituting the calibration hole CH to be retracted outward when the calibration pin is inserted into the calibration hole CH.
  • the wall surface W which has been retracted by the elastic force of the material constituting the main body 711 of the insert 710, is restored and elastically advanced. That is, in the present embodiment, the inner diameter of the calibration hole CH before the calibration pin is inserted may be equal to or smaller than the diameter of the calibration pin by the elastic force.
  • the wall (W) constituting the calibration hole (CH) is retracted to the outside in the process of the calibration pin is inserted, the calibration hole (CH) is gradually opened to become large enough to insert the calibration pin sufficiently.
  • the phenomenon of being pinched in the state in which the calibration pins are inserted into the calibration holes CH is prevented, a malfunction of the calibration pins that do not escape from the calibration holes CH is eliminated.
  • the inner diameter of the calibration hole CH can be made smaller than the conventional one in consideration of the manufacturing tolerance to a minimum, more precise position correction of the insert 710 can be made.
  • the technique of forming the cutout hole IH on the outer side of the correction hole CH and having the cutout portion IP on the wall constituting the straightening hole CH according to the present embodiment has been described above in the first embodiment. It may be applied only to the first calibration hole CH1 which is present, or may be applied only to the second calibration hole CH2, and may be applied to both the first calibration hole CH1 and the second calibration hole CH2.
  • CP1 first calibration pin
  • CP3 second calibration pin

Abstract

The present invention relates to a test tray for a test handler and an interface board for a tester. According to the present invention, a secondary calibration hole is additionally formed in an insert of a test tray, and a secondary calibration pin is provided in a socket guider of an interface board. In addition, an alignment hole is additionally formed in a test socket of an interface board, and an alignment pin is provided in the interface board. Accordingly, the position of an insert can be calibrated in divided steps. Furthermore, a wall surface forming a calibration hole of an insert body is cut, and an incision hole is formed around the calibration hole. According to the present invention, the position of an insert is calibrated sequentially in divided steps, thereby enabling very accurate calibration of the position of an insert. In addition, a calibration pin is prevented from being fitted into a calibration hole, thereby enabling formation of a smaller calibration hole and finer calibration of the position of an insert.

Description

테스트핸들러용 테스트트레이와 테스터용 인터페이스보드Test tray for test handler and interface board for tester
본 발명은 테스트핸들러에서 반도체소자를 적재시킬 수 있는 테스트트레이와 테스터에서 반도체소자와 전기적으로 접속되는 인터페이스보드에 관한 것이다.The present invention relates to an interface board electrically connected to a semiconductor device in a test tray and a tester capable of loading a semiconductor device in a test handler.
테스트핸들러는 소정의 제조공정을 거쳐 제조된 반도체소자들을 고객트레이(CUSTOMER TRAY)로부터 테스트트레이(TEST TRAY)로 이동시킨 후, 테스트트레이에 적재되어 있는 반도체소자들이 동시에 테스터(TESTER)에 의해 테스트(TEST)될 수 있도록 지원하며, 테스트 결과에 따라 반도체소자를 등급별로 분류하면서 테스트트레이에서 고객트레이로 이동시키는 기기로서 이미 다수의 공개문서들을 통해 공개되어 있다.The test handler moves semiconductor devices manufactured through a predetermined manufacturing process from a customer tray to a test tray, and then the semiconductor devices loaded in the test tray are simultaneously tested by a tester (TESTER). TEST), which is a device that moves semiconductor devices from test trays to customer trays by classifying semiconductor devices according to test results.
테스트트레이는 반도체소자가 삽입되는 형태로 안착될 수 있는 안착공간이 형성된 인서트(INSERT)들이 설치프레임에 설치되는 구조를 가진다.The test tray has a structure in which inserts (INSERTs) having a seating space in which a semiconductor device is inserted are formed in an installation frame.
인서트는 안착공간에 안착된 반도체소자를 지지하는 지지부분을 가진다.The insert has a supporting portion for supporting the semiconductor element seated in the seating space.
지지부분은 대한민국 등록특허 10-0801927호 등에서 참조되는 바와 같이 인서트의 몸체와 일체로 사출 성형될 수도 있고, 대한민국 공개특허 10-2010-0081131호 등에서와 같이 얇은 필름 형태로 구비될 수도 있다.The support portion may be injection molded integrally with the body of the insert as referred to in Republic of Korea Patent No. 10-0801927, etc., may be provided in a thin film form as in Republic of Korea Patent Publication No. 10-2010-0081131.
반도체소자는 인서트의 안착공간에 안착된 상태로 고정된다. 그리고 인서트의 안착공간에 안착된 상태에서 반도체소자가 테스터의 인터페이스보드에 구비된 테스트소켓에 전기적으로 접속된다. 따라서 인서트에 있는 반도체소자와 테스트소켓 간의 정확한 전기적인 접속을 위해 인서트의 위치를 교정할 필요성이 있다. 그래서 인서트는 설치 프레임에 다소 유동 가능하게 결합되어 있다. 그리고 인서트에는 교정구멍을 형성하고, 인터페이스보드에는 교정구멍에 삽입되는 교정핀이 구비된 소켓가이더가 구비된다(대한민국 공개특허 10-2013-0059485호 등 참조, 이하 ‘종래기술’이라 함).The semiconductor device is fixed in a state of being seated in the seating space of the insert. The semiconductor device is electrically connected to the test socket provided on the tester's interface board in the seating space of the insert. Therefore, there is a need to correct the position of the insert for accurate electrical connection between the semiconductor element in the insert and the test socket. The insert is thus more or less fluidly coupled to the mounting frame. The insert is formed with a calibration hole, and the interface board is provided with a socket guider having a calibration pin inserted into the calibration hole (see Korean Patent Publication No. 10-2013-0059485, etc., hereinafter referred to as 'prior art').
한편, 집적기술의 발전 등으로 인해 반도체소자의 크기는 줄어들면서도 단자의 개수는 많아지게 되었다. 그리고 이로 인해 볼(BALL) 형태의 단자들 간의 간격과 단자들의 크기도 함께 줄어들게 되면서 반도체소자의 단자들과 테스터 간의 전기적 연결이 더욱 정교하면서도 안정적일 필요성이 대두되었다.Meanwhile, due to the development of integrated technology, the number of terminals increases while the size of the semiconductor device is reduced. As a result, the spacing between the terminals of the ball type and the size of the terminals are also reduced, resulting in the necessity of more precise and stable electrical connection between the terminals of the semiconductor device and the tester.
그런데, 종래기술의 경우, 교정핀이 교정구멍에 적절히 삽입될 수 있도록 교정핀과 교정구멍의 제작 공차를 고려해야 한다. 그리고 소켓가이더와 테스트소켓 간의 상호 위치도 제작 공차가 있다는 것을 고려해야만 한다. 따라서 교정핀의 직경보다 교정구멍의 내경을 좀 더 크게 함으로써 교정핀의 중심이 교정구멍의 중심에서 약간 비켜있더라도 교정핀이 교정구멍에 삽입될 수 있도록 구현한다. 만일 제작 공차를 고려하지 않는다면, 교정구멍에 교정핀이 삽입되는 것에 불량이 발생하여 작동 불량이나 인서트의 손상이 발생할 수 있고, 반도체소자와 테스트소켓 간의 적절한 전기적인 연결이 이루어지지 못할 수 있다. 그리고 교정핀이 억지 끼움식으로 교정구멍에 삽입되면, 차후에 교정핀이 교정구멍으로부터 빠져나오는 것이 곤란할 수 있다.However, in the prior art, manufacturing tolerances of the calibration pin and the calibration hole should be considered so that the calibration pin can be properly inserted into the calibration hole. It should also be taken into account that there is a manufacturing tolerance between the socket guider and the test socket. Therefore, by making the inner diameter of the calibration hole larger than the diameter of the calibration pin, the calibration pin can be inserted into the calibration hole even if the center of the calibration pin is slightly away from the center of the calibration hole. If manufacturing tolerances are not taken into consideration, a failure may occur in the insertion of the calibration pins into the calibration holes, resulting in malfunction or damage to the inserts, and proper electrical connection between the semiconductor device and the test socket may not be achieved. If the calibration pin is inserted into the calibration hole by interference fit, it may be difficult for the calibration pin to come out of the calibration hole later.
따라서 종래기술로서는 갈수록 미세화되는 단자들 간의 간격과 줄어드는 단자의 크기만큼 정교하게 인서트의 위치를 교정하는데 한계에 다다르게 되었다.Therefore, the prior art has reached the limit of precisely correcting the position of the insert as much as the spacing between terminals that are miniaturized and the size of the terminals that decrease.
본 발명의 제1 목적은 단계를 나누어 순차적으로 인서트의 위치를 교정할 수 있는 기술을 제공한다.It is a first object of the present invention to provide a technique capable of sequentially correcting the position of an insert in steps.
본 발명의 제2 목적은 제작 공차의 반영을 최소화시킬 수 있는 기술을 제공한다.A second object of the present invention is to provide a technique capable of minimizing reflection of manufacturing tolerances.
위와 같은 목적을 달성하기 위한 본 발명의 제1 관점에 따른 테스트핸들러용 테스트트레이는, 반도체소자가 안착될 수 있는 안착공간이 형성된 인서트; 및 상기 인서트가 유동 가능하게 설치되는 설치프레임; 을 포함하고, 상기 인서트는, 상기 안착공간이 형성된 본체; 상기 안착공간에 안착된 반도체소자를 지지하기 위해 상기 본체에 일체로 형성되거나 상기 본체에 결합되는 형태로 구비되는 지지부분; 및 상기 안착공간에 안착된 반도체소자의 이탈을 방지하기 위해 반도체소자를 고정시키는 고정기: 를 포함하며, 상기 본체에는 테스터의 인터페이스보드에 구비된 소켓가이더의 제1 교정핀이 삽입될 수 있는 제1 교정구멍과 상기 소켓가이더의 제2 교정핀이 삽입될 수 있는 제2 교정구멍이 형성되어 있다.The test tray for a test handler according to the first aspect of the present invention for achieving the above object, the insert is formed with a seating space on which the semiconductor device can be seated; And an installation frame in which the insert is installed to be movable. It includes, The insert, The seating body is formed body; A support part formed integrally with the main body or coupled to the main body to support the semiconductor device seated in the seating space; And a fixing device for fixing the semiconductor device to prevent detachment of the semiconductor device seated in the seating space, wherein the first calibration pin of the socket guider provided in the interface board of the tester is inserted into the main body. A first calibration hole and a second calibration hole into which the second calibration pin of the socket guider can be inserted are formed.
상기 인서트가 상기 인터페이스보드에 구비된 테스트소켓에 접근할 때 상기 제1 교정핀이 상기 제1 교정구멍에 먼저 삽입되고 상기 제2 교정핀이 상기 제2 교정구멍에 나중에 삽입됨으로써 상기 제1 교정구멍과 상기 제1 교정핀의 작용에 의해 상기 인서트의 위치가 1차적으로 교정되고, 상기 제2 교정구멍과 상기 제2 교정핀의 작용에 의해 상기 인서트의 위치가 2차적으로 정밀하게 교정된다.When the insert approaches the test socket provided on the interface board, the first calibration pin is first inserted into the first calibration hole and the second calibration pin is inserted later into the second calibration hole, thereby providing the first calibration hole. And the position of the insert is firstly corrected by the action of the first calibration pin and the position of the insert is secondarily precisely corrected by the action of the second calibration hole and the second calibration pin.
상기 제1 교정핀은 상기 제2 교정핀보다 돌출된 높이가 더 높아서 상기 제1 교정구멍에 상기 제1 교정핀이 삽입된 후 상기 제2 교정구멍에 상기 제2 교정핀이 삽입될 수 있다.Since the first calibration pin has a higher height than the second calibration pin, the first calibration pin may be inserted into the first calibration hole, and then the second calibration pin may be inserted into the second calibration hole.
상기 제2 교정구멍은 일 측 방향으로 긴 장공 형태이다.The second calibration hole is in the form of a long hole in one side direction.
상기 제2 교정구멍은 상기 제2 교정구멍의 중심과 상기 인서트의 중심을 지나는 직선 방향으로 더 긴 장공 형태이다.The second calibration hole is in the form of a longer hole in a straight direction passing through the center of the second calibration hole and the center of the insert.
위와 같은 목적을 달성하기 위한 본 발명의 제1 관점에 따른 테스터용 인터페이스보드는, 테스트트레이의 인서트에 있는 반도체소자와 전기적으로 연결되는 테스트소켓; 상기 테스트소켓과 반도체소자의 전기적인 연결을 위해 상기 인서트의 위치를 교정하는 소켓가이더; 및 상기 테스트소켓과 상기 소켓가이더가 설치되는 설치보드;를 포함하고, 상기 소켓가이더는, 상기 인서트에 형성된 제1 교정구멍에 삽입되어서 상기 인서트의 위치를 1차적으로 교정하는 제1 교정핀; 및 상기 인서트에 형성된 제2 교정구멍에 삽입되어서 상기 인서트의 위치를 2차적으로 교정하는 제2 교정핀; 을 포함한다.An interface board for a tester according to the first aspect of the present invention for achieving the above object, the test socket electrically connected to the semiconductor element in the insert of the test tray; A socket guider for calibrating the position of the insert for electrical connection between the test socket and the semiconductor device; And a mounting board on which the test socket and the socket guider are installed, wherein the socket guider includes: a first calibration pin inserted into a first calibration hole formed in the insert to primarily calibrate the position of the insert; And a second calibration pin inserted into a second calibration hole formed in the insert to secondly correct the position of the insert. It includes.
상기 인서트가 상기 테스트소켓으로 접근할 때 상기 제1 교정핀이 상기 제1 교정구멍에 먼저 삽입되면서 상기 인서트의 위치를 1차적으로 교정하고 상기 제2 교정핀이 상기 제2 교정구멍에 나중에 삽입되면서 상기 인서트의 위치를 2차적으로 정밀하게 교정한다.As the insert approaches the test socket, the first calibration pin is first inserted into the first calibration hole, thereby first calibrating the position of the insert and the second calibration pin is later inserted into the second calibration hole. The position of the insert is secondarily precisely calibrated.
상기 제1 교정핀은 상기 제2 교정핀보다 돌출된 높이가 더 높아서 상기 제1 교정구멍에 상기 제1 교정핀이 삽입된 후 상기 제2 교정구멍에 상기 제2 교정핀이 삽입될 수 있다.Since the first calibration pin has a higher height than the second calibration pin, the first calibration pin may be inserted into the first calibration hole, and then the second calibration pin may be inserted into the second calibration hole.
상기 테스트소켓에는 정렬구멍이 형성되어 있고, 상기 소켓가이더는 상기 정렬구멍에 삽입될 수 있는 정렬핀을 구비한다.An alignment hole is formed in the test socket, and the socket guider has an alignment pin that can be inserted into the alignment hole.
상기 제2 교정핀과 상기 정렬핀은 동일한 축 상에 구비될 수 있다.The second calibration pin and the alignment pin may be provided on the same axis.
상기 제2 교정핀은 평단면이 일 측 방향으로 긴 타원 형태이다. The second calibration pin has an elliptic shape with a flat cross section long in one direction.
위와 같은 목적을 달성하기 위한 본 발명의 제2 관점에 따른 테스트핸들러용 테스트트레이는, 반도체소자가 안착될 수 있는 안착공간이 형성된 인서트; 및 상기 인서트가 유동 가능하게 고정 설치되는 설치프레임; 을 포함하고, 상기 인서트는, 상기 안착공간이 형성된 본체; 상기 안착공간에 안착된 반도체소자를 지지하기 위해 상기 본체에 일체로 형성되거나 상기 본체에 결합되는 형태로 구비되는 지지부분; 및 상기 안착공간에 안착된 반도체소자의 이탈을 방지하기 위해 반도체소자를 고정시키는 고정기: 를 포함하며, 상기 본체에는 테스터의 인터페이스보드에 구비된 소켓가이더의 교정핀이 삽입될 수 있는 교정구멍이 형성되어 있고, 상기 교정구멍을 이루는 벽면은 상기 교정구멍에 삽입된 상기 교정핀과의 접촉부분을 줄이기 위해 적어도 일부분이 절개된 형태이다.The test tray for the test handler according to the second aspect of the present invention for achieving the above object, the insert is formed with a seating space on which the semiconductor device can be seated; And an installation frame to which the insert is fixedly installed. It includes, The insert, The seating body is formed body; A support part formed integrally with the main body or coupled to the main body to support the semiconductor device seated in the seating space; And a fixing device for fixing the semiconductor device to prevent detachment of the semiconductor device seated in the seating space, wherein the body includes a calibration hole into which the calibration pin of the socket guider is inserted into the interface board of the tester. The wall surface forming the calibration hole is formed at least partially cut to reduce the contact portion with the calibration pin inserted into the calibration hole.
상기 교정핀이 상기 교정구멍에 삽입될 때 상기 교정구멍을 이루는 벽면 중 상기 교정핀에 접하는 부분이 외측으로 후퇴된 후 탄성 복원될 수 있도록, 상기 본체에는 상기 교정구멍의 외측에 원주방향으로 복수의 절개구멍이 형성되어 있다.When the calibration pin is inserted into the calibration hole, the main body has a plurality of circumferential directions on the outer side of the calibration hole so that the portion of the wall that forms the calibration hole in contact with the calibration pin is retracted outward and then elastically restored. An incision hole is formed.
제1 관점에 따른 본 발명에 의하면 다음과 같은 효과가 있다.According to the present invention according to the first aspect, the following effects are obtained.
첫째, 먼저 대략적으로 인서트의 위치를 교정한 다음, 나중에 정교하게 인서트의 위치를 교정하기 때문에 인서트의 손상 등을 초래하지 않으면서도 정교한 인서트의 위치 교정이 이루어질 수 있다.First, the position of the insert is roughly calibrated first, and then the position of the insert is finely calibrated later, so that precise insert position calibration can be made without causing damage to the insert.
둘째, 테스트소켓과 소켓가이더를 조립하는 과정에서 발생되는 조립 공차(제작 공차)를 최대한 줄일 수 있어서 인서트의 위치 교정이 더욱 정교해질 수 있다.Second, the assembly tolerances (manufacturing tolerances) generated in the process of assembling the test socket and the socket guider can be reduced as much as possible, thereby making the insert position more precise.
셋째, 인서트의 열수축이나 열팽창과 무관하게 정교한 위치 교정이 이루어질 수 있다.Third, precise position calibration can be achieved regardless of the thermal contraction or thermal expansion of the insert.
그리고 제2 관점에 따른 본 발명에 의하면 다음과 같은 효과가 있다.And according to the present invention according to the second aspect has the following effects.
첫째, 교정핀이 교정구멍에 억지 끼움식으로 끼워지더라도 교정핀과 교정구멍을 이루는 벽면 간에 접촉 마찰이 줄기 때문에 차후에 교정핀이 교정구멍으로부터 손쉽게 빠져나올 수 있다.First, even if the calibration pin is inserted into the calibration hole by force, the contact friction between the calibration pin and the wall forming the calibration hole is reduced so that the calibration pin can be easily escaped from the calibration hole later.
둘째, 교정구멍을 이루는 벽면이 탄성 복원가능하게 유동될 수 있기 때문에 교정핀이 교정구멍으로부터 더욱 손쉽게 빠져나올 수 있다.Secondly, since the wall surface constituting the calibration hole can be elastically resilient to flow, the calibration pin can be more easily exited from the calibration hole.
도1은 본 발명의 제1 실시예에 따른 테스트핸들러용 테스트트레이에 대한 평면도이다.1 is a plan view of a test tray for a test handler according to a first embodiment of the present invention.
도2는 본 발명의 제1 실시예에 따른 테스터용 인터페이스보드에 대한 평면도이다.2 is a plan view of an interface board for a tester according to a first embodiment of the present invention.
도3은 도2의 인터페이스보드에 적용된 테스트소켓과 소켓가이더의 결합된 상태를 표현한 측면도이다.FIG. 3 is a side view illustrating a coupled state of a test socket and a socket guider applied to the interface board of FIG. 2.
도4 내지 도6은 본 발명의 제1 실시예의 주요 부위에 대한 작동을 설명하기 위해 도1의 테스트트레이와 도2의 인터페이스보드의 주요 부위를 개념적으로 발췌하여 도시한 과장도이다. 4 to 6 are exaggerated diagrams conceptually extracting main parts of the test tray of FIG. 1 and the interface board of FIG. 2 to explain the operation of the main parts of the first embodiment of the present invention.
도3은 도1의 테스트트레이에 설치된 인서트와 도2의 인터페이스보드에 설치된 소켓가이더 및 테스트소켓의 상호 구조를 설명하기 위한 사시도이다.FIG. 3 is a perspective view illustrating the mutual structure of an insert installed in the test tray of FIG. 1 and a socket guider and a test socket installed in the interface board of FIG.
도4 내지 도6은 본 발명에 따른 테스트트레이와 인터페이스보드의 주요 부위에 대한 작동을 설명하기 위한 개략적인 측면도이다.4 to 6 is a schematic side view for explaining the operation of the main portion of the test tray and the interface board according to the present invention.
도7은 다양한 종류의 인서트에 형성된 제2 교정구멍들의 형성 위치를 보여주기 한 참조도이다. Fig. 7 is a reference diagram showing the formation positions of second calibration holes formed in various kinds of inserts.
도8은 본 발명의 제2 실시예에 따른 테스트핸들러용 테스트트레이에 대한 평면도이다.8 is a plan view of a test tray for a test handler according to a second embodiment of the present invention.
도9는 도8의 주요 부위에 대한 확대 사시도이다.9 is an enlarged perspective view of the main part of FIG. 8;
이하 상기한 바와 같은 본 발명에 따른 바람직한 실시예를 첨부된 도면을 참조하여 설명하되, 설명의 간결함을 위해 중복되는 설명은 가급적 생략하거나 압축한다.Hereinafter, a preferred embodiment according to the present invention as described above with reference to the accompanying drawings, for the sake of brevity of description overlapping description is omitted or compressed as possible.
<제1 실시예><First Embodiment>
1. 테스트핸들러용 테스트트레이에 대한 설명1. Description of test tray for test handler
도1은 본 발명의 제1 실시예에 따른 테스트핸들러용 테스트트레이(100, 이하 ‘테스트트레이’로 약칭 함)에 대한 평면도이다.1 is a plan view of a test tray 100 for a test handler (hereinafter, abbreviated as 'test tray') according to a first embodiment of the present invention.
본 실시예에 따른 테스트트레이(100)는 다수의 인서트(110) 및 설치프레임(120)을 포함한다.The test tray 100 according to the present embodiment includes a plurality of inserts 110 and the installation frame 120.
인서트(110)는 본체(111), 지지부분(112) 및 고정기(113)를 포함한다.The insert 110 includes a main body 111, a support portion 112, and a fixture 113.
본체(111)에는 반도체소자가 안착될 수 있는 안착공간(SS)이 형성되어 있다. 또한, 본체(111)에는 2개의 제1 교정구멍(CH1)과 4개의 제2 교정구멍(CH2)이 형성되어 있다.The main body 111 has a seating space SS on which the semiconductor device is mounted. In addition, two first calibration holes CH1 and four second calibration holes CH2 are formed in the main body 111.
제1 교정구멍(CH1)은 ‘발명의 배경이 되는 기술’ 부분에서 설명한 제작 공차들을 고려한 내경을 가지도록 형성된다. 이러한 제1 교정구멍(CH1)은 인서트(110)의 위치를 1차적으로 교정하는 기능을 한다.The first calibration hole CH1 is formed to have an inner diameter in consideration of the manufacturing tolerances described in the section “Technology Background of the Invention”. The first calibration hole CH1 serves to primarily correct the position of the insert 110.
제2 교정구멍(CH2)은 제1 교정구멍(CH1)의 작용에 의해 1차적으로 교정된 인서트(110)의 위치를 더욱 정교하게 2차적으로 교정하기 위해 형성되어 있다. 따라서 제1 교정구멍(CH1)에 의해 인서트(110)의 위치가 1차적으로 교정된 후, 제2 교정구멍(CH2)에 의해 인서트(110)의 위치가 2차적으로 더욱 정교하게 교정된다. 이러한 제2 교정구멍(CH2)은 인서트(110)의 중심(O1)을 기준으로 하는 십자선(CL) 상에 형성되어 있고, 십자선(CL) 상 방향으로 더 긴 형태의 장공으로 형성되어 있다. 즉, 인서트의 중심(O1)에 십자선(CL)의 중심을 위치시킬 때, 십자선(CL)의 X축 선상에 있는 제2 교정구멍(CH2)은 X축 방향으로 긴 장공이고, 십자선(CL)의 Y축 선상에 있는 제2 교정구멍(CH2)은 Y축 방향으로 긴 장공이다. 여기서 X축과 Y축은 제2 교정구멍(CH2)의 중심과 인서트(110)의 중심(O1)을 지나는 직선이다. 이렇게 제2 교정구멍(CH2)이 장공으로 형성됨으로써 인서트(110)의 중심(O1)을 기준으로 인서트(110) 자체가 열팽창이나 냉각 수축되는 경우에도 그 기능이 유지될 수 있게 된다. The second straightening hole CH2 is formed to more precisely and secondarily correct the position of the insert 110 that is primarily straightened by the action of the first straightening hole CH1. Therefore, after the position of the insert 110 is firstly corrected by the first calibration hole CH1, the position of the insert 110 is secondarily more precisely corrected by the second calibration hole CH2. The second calibration hole CH2 is formed on the crosshair CL based on the center O 1 of the insert 110, and is formed of a longer hole having a longer shape in the crosshair CL direction. That is, when positioning the center of the crosshair CL in the center O 1 of the insert, the second calibration hole CH2 on the X-axis line of the crosshair CL is a long hole in the X-axis direction, and the crosshair CL The second calibration hole CH2 on the Y-axis line of Fig. 3) is a long hole in the Y-axis direction. Here, the X axis and the Y axis are straight lines passing through the center of the second calibration hole CH2 and the center O 1 of the insert 110. As such, the second calibration hole CH2 is formed as a long hole, so that the function may be maintained even when the insert 110 itself is thermally expanded or cooled down based on the center O 1 of the insert 110.
제1 교정구멍(CH1) 및 제2 교정구멍(CH2)과 관련하여 더 구체적인 설명은 차후에 설명한다.A more detailed description with respect to the first calibration hole CH1 and the second calibration hole CH2 will be described later.
지지부분(112)은 안착공간(SS)에 안착된 반도체소자를 지지한다. 이러한 지지부분(112) 얇은 필름으로 구비되어서 본체(111)에 결합된다. 그리고 지지부분(112)에는 반도체소자의 적절한 안착을 유도하고 반도체소자의 단자들이 테스트소켓 측으로 노출될 수 있게 하는 노출구멍(EH)들이 형성되어 있다. 물론, 실시하기에 따라서는 지지부분(112)이 본체(111)에 일체로 형성될 수도 있다.The support part 112 supports the semiconductor device seated in the seating space SS. The support portion 112 is provided with a thin film is coupled to the main body 111. In addition, the support part 112 is provided with exposure holes EH that induce proper seating of the semiconductor device and allow terminals of the semiconductor device to be exposed to the test socket side. Of course, depending on the implementation, the support portion 112 may be formed integrally with the main body 111.
고정기(113)는 래치나 홀딩장치 등으로도 불릴 수 있으며 작동 가능하게 본체(111)에 결합되어 있다. 이러한 고정기(113)는 안착공간(SS)에 안착된 상태에서 지지부분(112)에 의해 지지되는 반도체소자를 고정시킨다. 참고로, 고정기(113)에 의한 반도체소자의 고정 해제는 별도의 개방장치(대한민국 공개특허 10-2011-0121063호 참조)에 의해 이루어진다.The fixing unit 113 may also be referred to as a latch or a holding device, and is coupled to the main body 111 to be operable. The fixture 113 fixes the semiconductor device supported by the support part 112 in a state of being seated in the seating space SS. For reference, the fixing of the semiconductor device by the fixing unit 113 is performed by a separate opening device (refer to Republic of Korea Patent Application Publication No. 10-2011-0121063).
설치프레임(120)에는 미도시한 결합기(볼트와 너트로 구비될 수 있다)에 의해 인서트(110)가 다소 유동 가능하게 결합 설치된다.The insert frame 110 is coupled to the installation frame 120 by a coupler (not provided with a bolt and a nut) so as to be able to flow somewhat.
2. 2. 테스터용For tester 인터페이스보드에On interface board 대한 설명 Description of
도2는 본 발명의 제1 실시예에 따른 테스터용 인터페이스보드(200, 이하 ‘인터페이스보드’라 약칭함)에 대한 평면도이다.2 is a plan view of the tester interface board 200 (hereinafter, abbreviated as 'interface board') according to the first embodiment of the present invention.
본 실시예에 따른 인터페이스보드(200)는 다수의 테스트소켓(210), 소켓가이더(220) 및 설치보드(230)를 포함한다.The interface board 200 according to the present embodiment includes a plurality of test sockets 210, a socket guider 220, and an installation board 230.
테스트소켓(210)은 테스트트레이(100)의 인서트(110)에 있는 반도체소자와 전기적으로 연결되는 소켓부분(211)을 가진다. 그리고 테스트소켓(210)에는 볼트구멍(BH1)과 테스트소켓(210)의 중심(O2)을 기준으로 한 십자선(CL) 상에 4개의 정렬구멍(AH)이 형성되어 있다.The test socket 210 has a socket portion 211 electrically connected to a semiconductor device in the insert 110 of the test tray 100. In the test socket 210, four alignment holes AH are formed on the crosshair CL based on the bolt hole BH1 and the center O 2 of the test socket 210.
소켓가이더(220)는 테스트소켓(210)과 반도체소자의 전기적인 연결을 위해 인서트(110)의 위치를 교정한다. 이를 위해 소켓가이더(220)는 2개의 제1 교정구멍(CH1)들에 대응되는 위치에 2개의 제1 교정핀(CP1)들이 구비되고, 4개의 제2 교정구멍(CH2)들에 대응되는 위치에 4개의 제2 교정핀(CP2)들이 구비된다. 또한, 도3의 개념적인 측면도에서 참조되는 바와 같이 4개의 정렬구멍(AH)들에 대응되는 위치에 4개의 정렬핀(AP)이 구비된다.The socket guider 220 corrects the position of the insert 110 for electrical connection between the test socket 210 and the semiconductor device. To this end, the socket guider 220 is provided with two first calibration pins CP1 at positions corresponding to two first calibration holes CH1, and positions corresponding to four second calibration holes CH2. Four second calibration pins CP2 are provided. In addition, four alignment pins AP are provided at positions corresponding to the four alignment holes AH as referred to in the conceptual side view of FIG. 3.
제1 교정핀(CP1)들은 제1 교정구멍(CH1)에 삽입되면서 인서트(110)의 위치를 1차적으로 교정한다.The first calibration pins CP1 are inserted into the first calibration holes CH1 to primarily correct the position of the insert 110.
제2 교정핀(CP2)들은 제2 교정구멍(CH2)에 삽입되면서 1차적으로 교정된 인서트(110)의 위치를 더욱 정교하게 2차적으로 교정한다. 이러한 제2 교정핀(CP2)들은 장공 형태인 제2 교정구멍(CH2)에 대응되는 형상으로서 평단면이 타원형으로 형성되어 있다.As the second calibration pins CP2 are inserted into the second calibration holes CH2, the second calibration pins CP2 are secondarily calibrated more precisely. The second calibration pins CP2 have a shape corresponding to the second calibration hole CH2 having a long hole shape, and have a flat cross section having an elliptical shape.
그리고 제2 교정핀(CP2)의 단면에서 제2 교정핀(CP2)의 단반경 측의 직경은 제2 교정구멍(CH2)의 단반경 측의 직경과 거의 동일하고, 장반경 측의 직경은 제2 교정구멍(CH2)의 장반경 측의 직경보다 다소 짧다. 이러한 이유는 인서트(110)의 팽창과 테스트소켓(210)이나 제2 교정핀(CP2)의 열팽창을 고려한 것이다. 즉, 열팽창에 따라 제2 교정핀(CP2)이 팽창하거나 또는 제2 교정핀(CP2)이 팽창하지 않더라도 열팽창 방향으로의 이동을 고려하여 여유 공간이 제2 교정구멍(CH2) 내에 존재해야 하기 때문이다. 이렇게 단면을 타원형으로 함으로써 제1 교정핀(CP1)에 대하여 상대적으로 굵기가 많이 가는 편인 제2 교정핀(CP2)의 강도가 보강될 수 있는 효과도 있다.The diameter of the short radius side of the second straightening pin CP2 in the cross section of the second straightening pin CP2 is substantially equal to the diameter of the short radius side of the second straightening hole CH2, and the diameter of the long radius side is the second straightening hole. It is rather shorter than the diameter of the long radius side of (CH2). This reason is taken into account the expansion of the insert 110 and the thermal expansion of the test socket 210 or the second calibration pin (CP2). That is, even if the second calibration pin CP2 expands or the second calibration pin CP2 does not expand due to thermal expansion, a free space must exist within the second calibration hole CH2 in consideration of movement in the thermal expansion direction. to be. By making the cross section elliptical in this way, the strength of the second calibration pin CP2, which is relatively thinner with respect to the first calibration pin CP1, may be reinforced.
특히, 도3에서 참조되는 바와 같이 제1 교정핀(CP1)들의 돌출된 높이(H1)는 제2 교정핀(CP2)들이 돌출된 높이(H2)보다 더 높다. 이로 인해 제1 교정핀(CP1)들이 제1 교정구멍(CH1)들에 먼저 삽입되면서 1차적으로 인서트(110)의 위치를 정렬하고, 제2 교정핀(CP2)들이 제2 교정구멍(CH2)들에 나중에 삽입되면서 2차적으로 인서트(110)의 위치를 정교하게 정렬할 수 있게 된다. 물론, 실시하기에 따라서는 제1 교정핀과 제2 교정핀의 높이를 동일하게 하면서도 제1 교정핀이 제1 교정구멍에 먼저 삽입된 후 제2 교정핀이 제2 교정구멍에 나중에 삽입하도록 인서트의 형상 구조를 변경할 수도 있을 것이다.In particular, as shown in FIG. 3, the protruding height H 1 of the first straightening pins CP1 is higher than the height H 2 from which the second straightening pins CP2 protrude. As a result, the first calibration pins CP1 are first inserted into the first calibration holes CH1 to align the position of the insert 110, and the second calibration pins CP2 are arranged to the second calibration holes CH2. As later inserted into the field it is possible to finely align the position of the insert (110). Of course, according to the embodiment, the first calibration pin and the second calibration pin have the same height while the first calibration pin is inserted into the first calibration hole first, and then the second calibration pin is inserted into the second calibration hole later. The shape of the structure may be changed.
정렬핀(AP)들은 정렬구멍(AH)들에 삽입된다. 이러한 정렬핀(AP)들과 정렬구멍(AH)들에 의해 소켓가이더(220)와 테스트소켓(210)의 상호 위치가 정교하게 설정된 상태에서 설치보드(230)에 설치될 수 있다. 여기서 본 실시예에서처럼 4개의 제2 교정핀(CP2)들과 4개의 정렬핀(AP)들은 도3에서 참조되는 바와 같이 상호 동일한 형태로 동일한 축(SA1, SA2, SA3)상에 구비될 수 있다. 4개의 제2 교정핀(CP2)들과 4개의 정렬핀(AP)들은 일체로 형성될 수도 있고, 별개로 형성될 수도 있다. 물론, 실시하기에 따라서는 정렬핀들이 제2 교정핀들과는 다른 위치에 형성되는 것도 가능하다.Alignment pins AP are inserted into the alignment holes AH. The alignment pins AP and the alignment holes AH may be installed on the installation board 230 in a state where the socket guider 220 and the test socket 210 are precisely positioned. Here, as in this embodiment, the four second calibration pins CP2 and the four alignment pins AP are provided on the same axis SA 1 , SA 2 , SA 3 in the same form as shown in FIG. 3. Can be. Four second calibration pins CP2 and four alignment pins AP may be integrally formed or separately. Of course, according to the implementation it is also possible that the alignment pins are formed in a position different from the second calibration pins.
그리고 소켓가이더(220)에는 테스트소켓(210)의 볼트구멍(BH1)에 대응되는 위치에 볼트구멍(BH2)이 형성되어 있다. 따라서 미도시된 볼트에 의해 테스트소켓(210)과 소켓가이더(220)가 함께 설치보드(230)에 설치된다. 이를 위해 정렬핀(AP)들의 돌출된 높이(h1)는 테스트소켓(210)의 정렬구멍(AH)의 깊이(h2)와 동일하거나 작아야 할 것이다. 물론, 작업자는 볼트 결합 작업시에 미리 정렬핀(AP)을 정렬구멍(AH)에 삽입시킴으로써 테스트소켓(210)과 소켓가이더(220)를 가결합시킨 상태에서 볼트를 이용해 가결합된 테스트소켓(210)과 소켓가이더(220)를 설치보드(230)에 결합시킨다. 그런데, 만일 정렬핀들의 일 측 부분(설치보드 측으로 향하는 부분)에 나사선을 형성함으로써 정렬핀들에 의해 테스트소켓과 소켓가이더를 설치보드에 설치한다면 별도의 볼트구멍들이나 볼트가 필요하지 않을 수도 있다.The socket guide 220 has a bolt hole BH2 formed at a position corresponding to the bolt hole BH1 of the test socket 210. Therefore, the test socket 210 and the socket guider 220 are installed on the installation board 230 by the bolt not shown. For this purpose, the protruding height h 1 of the alignment pins AP may be equal to or smaller than the depth h 2 of the alignment hole AH of the test socket 210. Of course, the operator by inserting the alignment pin (AP) in the alignment hole (AH) in advance during the bolt coupling operation test socket 210 and the socket guider 220 in a state that the test socket coupled to the test socket ( 210 and the socket guider 220 is coupled to the installation board (230). However, if the test socket and the socket guider are installed on the installation board by the alignment pins by forming a screw thread on one side of the alignment pins (the part facing the installation board side), no additional bolt holes or bolts may be required.
3. 주요 3. Main 부분에 대한 작동 설명Description of operation of the part
테스트핸들러에 구비되는 푸싱유닛에 의해 테스트트레이(100)가 인터페이스보드(200) 측으로 접근하면, 테스트트레이(100)에 설치된 인서트(110)가 인터페이스보드(200)에 설치된 테스트소켓(210) 측으로 접근하게 된다(대한민국 특허공개 10- 참조).When the test tray 100 approaches the interface board 200 by the pushing unit provided in the test handler, the insert 110 installed in the test tray 100 approaches the test socket 210 installed in the interface board 200. (See Korean Patent Publication 10-).
도4 내지 도7은 본 발명의 주요 부위만을 발췌한 개념적인 과장도로서, 이들을 참조하여 주요 부위의 작동에 대하여 설명한다.4 to 7 are conceptual exaggerations extracting only the main parts of the present invention, with reference to them to explain the operation of the main parts.
도4의 (a)는 현재 인서트(110)와 테스트소켓(210)이 일정 간격 떨어져 있는 상태를 도시하고 있고, 도4의 (b)는 도4의 (a) 상태에서 인서트(110)의 제1 교정구멍(CH1)과 소켓가이더(220)의 제1 교정핀(CP1) 간의 위치 관계와, 인서트(110)의 제2 교정구멍(CH2)과 소켓가이더(220)의 제2 교정구멍(CH2) 간의 위치 관계를 도시하고 있다.4 (a) shows a state where the insert 110 and the test socket 210 are spaced apart from each other at a distance, and FIG. 4 (b) shows the insert 110 of the insert 110 in the state (a) of FIG. 1 Positional relationship between the calibration hole CH1 and the first calibration pin CP1 of the socket guider 220, the second calibration hole CH2 of the insert 110 and the second calibration hole CH2 of the socket guider 220. ) Shows the positional relationship between
도4의 상태에서 푸싱유닛이 작동하여 테스트트레이(100)를 인터페이스보드(200) 측으로 접근시키면, 도5의 (a)에서와 같이 제1 교정핀(CP1)이 제1 교정구멍(CH1)에 먼저 삽입되면서 도5의 (b)에서와 같이 인서트(110)의 위치를 1차적으로 정렬시킨다. 이에 따라 도4의 (b)에서처럼 제2 교정핀(CP2)이 제2 교정구멍(CH2)에서 크게 어긋나 있던 상태에서 도5의 (b)에서와 같이 제2 교정핀(CP2)이 제2 교정구멍(CH2)에 삽입될 수 있는 위치로 교정된다.When the pushing unit operates in the state of FIG. 4 to approach the test tray 100 toward the interface board 200, the first calibration pin CP1 is inserted into the first calibration hole CH1 as shown in FIG. While first inserted, the position of the insert 110 is primarily aligned as shown in FIG. Accordingly, in the state where the second calibration pin CP2 is greatly shifted from the second calibration hole CH2 as in FIG. 4B, the second calibration pin CP2 is second-calibrated as in FIG. 5B. It is corrected to a position that can be inserted into the hole CH2.
도5의 상태에서 인서트(110)가 지속적으로 테스트소켓(210)에 접근함으로써 도6에서와 같이 제2 교정핀(CP2)이 제2 교정구멍(CH2)에 삽입되면서 인서트(110)의 위치가 2차적으로 정교하게 교정된다.As the insert 110 continuously approaches the test socket 210 in the state of FIG. 5, the second calibration pin CP2 is inserted into the second calibration hole CH2 as shown in FIG. 6, and thus the position of the insert 110 is improved. Secondly finely calibrated.
위와 같이 본 발명은 제1 교정구멍(CH1)/제1 교정핀(CP1)과 제2 교정구멍(CH2)/제2 교정핀(CP2)에 의해 2단계에 걸쳐 인서트(110)의 위치를 정교하게 교정하는 기술이다. 그러나 본 발명은 제3 교정구멍/제3 교정핀을 이용하여 3단계를 거쳐 인서트의 위치를 정교하게 교정하거나, 4단계 이상의 단계들을 통해 순차적으로 인서트의 위치를 정교하게 교정하는 응용예들로 확장될 수 있다.As described above, the present invention precisely positions the insert 110 in two steps by the first calibration hole CH1 / first calibration pin CP1 and the second calibration hole CH2 / second calibration pin CP2. It is a technique to correct. However, the present invention extends to applications in which the position of the insert is precisely corrected in three steps using the third calibration hole / third calibration pin, or the position of the insert is precisely corrected in four or more steps. Can be.
4. 참고적인 사항4. References
위의 도1의 테스트트레이(100)에 적용된 인서트(110)에는 제2 교정구멍(CH2)이 인서트(110)의 중심(O1)을 기준으로 하는 십자선(CL) 상에 형성되어 있고, 십자선(CL) 방향으로 더 긴 장공인 예를 들고 있다.In the insert 110 applied to the test tray 100 of FIG. 1, a second calibration hole CH2 is formed on the crosshair CL based on the center O 1 of the insert 110. We are holding an example of a longer hole in the direction (CL).
그러나 도7의 (a), (b) 및 (c)에서와 같이 인서트(110A, 110B, 110C)는 다양한 종류의 형태를 가질 수 있다. 그래서 인서트(110A, 110B, 110C)의 종류에 따라서는 제2 교정구멍(CH2)을 십자선(CL) 상에 배치시키기가 곤란할 수 있으며, 긴 방향이 서로 다른 장공을 형성시키는 것도 곤란할 수 있다. 따라서 도7에서와 같은 다양한 변형예를 따를 수 있다.However, as shown in FIGS. 7A, 7B, and 7C, the inserts 110A, 110B, and 110C may have various types of shapes. Therefore, depending on the type of the inserts 110A, 110B, and 110C, it may be difficult to arrange the second calibration holes CH2 on the crosshairs CL, and it may be difficult to form long holes having different lengths. Therefore, various modifications as shown in FIG. 7 may be followed.
도7의 (a)에 따르면, 제2 교정구멍(CH2-a, CH2-b)들 중 2개의 제2 교정구멍(CH2-a)은 상호 대각선으로 마주보는 모서리 부분에 형성되어 있고, 2개의 다른 제2 교정구멍(CH2-b)은 인서트(110A)를 좌우 대칭되게 2분하는 중심선(C) 상에 형성되어 있다. 그리고 부호 CH2-a의 교정구멍은 좌우 방향으로 긴 장공의 형태이고, 부호 CH2-b의 교정구멍은 도면 상 전후 방향으로 긴 장공의 형태이다.According to Fig. 7A, two second calibration holes CH2-a of the second calibration holes CH2-a and CH2-b are formed at corner portions facing each other diagonally, and two The other second straightening hole CH2-b is formed on the center line C dividing the insert 110A bilaterally. And the calibration hole of the sign CH2-a is in the form of a long hole in the left and right direction, and the calibration hole of the sign CH2-b is in the form of a long hole in the front and rear direction on the drawing.
도7의 (b)에 따르면, 제2 교정구멍(CH2)은 인서트(110B)를 좌우 대칭되게 2분하는 중심선(C)의 양측에 나뉘어 전방 부분과 후방 부분에 형성되어 있다. 그리고 모든 제2 교정구멍(CH2)들이 도면상 전후 방향으로 긴 장공의 형태이다. According to Fig. 7B, the second calibration hole CH2 is formed in both the front part and the rear part, divided on both sides of the center line C, which divides the insert 110B bilaterally. And all the second calibration holes (CH2) is in the form of a long hole in the front and rear direction on the drawing.
도7의 (c)에 따르면, 제2 교정구멍(CH2)은 인서트(110C)를 좌우 대칭되게 2분하는 중심선(C)의 양측에 나뉘어 좌측 부분과 우측 부분에 형성되어 있다. 그리고 모든 제2 교정구멍(CH2)들이 도면상 좌우 방향으로 긴 장공의 형태이다. According to FIG. 7C, the second calibration hole CH2 is formed at the left side and the right side divided into both sides of the center line C dividing the insert 110C bilaterally. And all the second calibration holes (CH2) is in the form of a long hole in the left and right directions on the drawing.
즉, 제2 교정구멍(CH2)들은 인서트(100, 110A, 110B, 110C)의 형상에 따라서 다양한 배치를 가질 수 있다.That is, the second calibration holes CH2 may have various arrangements according to the shapes of the inserts 100, 110A, 110B, and 110C.
물론, 인터페이스보드의 제2 교정핀들도 도7의 인서트(110A, 110B, 110C)들의 다양한 형태에 따른 제2 교정구멍(CH2-a, CH2-b, CH2)의 배치에 대응되도록 구비되어야 할 것이다.Of course, the second calibration pins of the interface board should also be provided to correspond to the arrangement of the second calibration holes CH2-a, CH2-b, and CH2 according to various shapes of the inserts 110A, 110B, and 110C of FIG. 7. .
<제2 <Second 실시예Example >>
도8은 본 발명의 제2 실시예에 따른 테스트핸들러용 테스트트레이(700, 이하 ‘테스트트레이’로 약칭 함)에 대한 평면도이다.8 is a plan view of a test tray 700 (hereinafter, abbreviated as 'test tray') for a test handler according to a second embodiment of the present invention.
본 실시예에 따른 테스트트레이(700)는 다수의 인서트(710) 및 설치프레임(720)을 포함한다.The test tray 700 according to the present embodiment includes a plurality of inserts 710 and an installation frame 720.
인서트(710)는 본체(711), 지지부분(712) 및 고정기(713)를 포함한다. 여기서 지지부분(712) 및 고정기(713)는 제1 실시예와 동일하므로 그 설명을 생략한다.The insert 710 includes a body 711, a support portion 712 and a fixture 713. Here, since the support part 712 and the fixing device 713 are the same as in the first embodiment, description thereof will be omitted.
본체(711)에는 반도체소자가 안착될 수 있는 안착공간(SS)이 형성되어 있다. 또한, 본체(711)에는 교정구멍(CH) 및 절개구멍(IH)들이 형성되어 있다.The main body 711 has a mounting space SS on which a semiconductor device may be mounted. In addition, the main body 711 is provided with the calibration hole CH and the cutting hole IH.
교정구멍(CH)에는 인터페이스보드의 교정핀(제1 실시예에서의 제1 교정핀과 동일함)이 삽입되기 때문에, 이로 인해 인서트(710)의 위치가 교정된다. 여기서 도9의 사시도에서처럼 교정구멍(CH)을 이루는 벽면(W)은 교정구멍(CH)에 삽입되는 교정핀과의 접촉부분을 줄이기 위해 절개 부분(IP)이 있다.Since the calibration pin (same as the first calibration pin in the first embodiment) of the interface board is inserted into the calibration hole CH, the position of the insert 710 is thereby corrected. Here, as shown in the perspective view of FIG. 9, the wall surface W constituting the calibration hole CH has an incision portion IP to reduce the contact portion with the calibration pin inserted into the calibration hole CH.
절개구멍(IH)은 교정핀이 교정구멍(CH)에 삽입될 때 교정구멍(CH)을 이루는 벽면(W) 중 교정핀에 접하는 부분이 외측으로 후퇴될 수 있도록 기능한다. 또한, 교정핀이 교정구멍(CH)에서 빠져나오면, 인서트(710)의 본체(711)를 이루는 재질의 탄성력에 의해 후퇴되었던 벽면(W)이 전진하면서 탄성 복원된다. 즉, 본 실시예에서 교정핀이 삽입되기 전의 교정구멍(CH)의 내경은 탄성력에 의해 교정핀의 직경과 같거나 교정핀의 직경보다 다소 작을 수 있다. 그러나 교정핀이 삽입되는 과정에서 교정구멍(CH)을 이루는 벽면(W)이 외측으로 후퇴되기 때문에 교정구멍(CH)이 점차 벌어져서 교정핀이 충분히 삽입될 만큼 커지게 된다. 그리고 교정핀이 교정구멍(CH)에 억지 끼움으로 삽입된 상태에서 꽉 물리는 현상이 방지되기 때문에 교정핀이 교정구멍(CH)으로부터 빠져나오지 못하는 작동 불량이 해소된다.The incision hole IH functions to allow a portion of the wall surface W constituting the calibration hole CH to be retracted outward when the calibration pin is inserted into the calibration hole CH. In addition, when the calibration pin exits the calibration hole CH, the wall surface W, which has been retracted by the elastic force of the material constituting the main body 711 of the insert 710, is restored and elastically advanced. That is, in the present embodiment, the inner diameter of the calibration hole CH before the calibration pin is inserted may be equal to or smaller than the diameter of the calibration pin by the elastic force. However, since the wall (W) constituting the calibration hole (CH) is retracted to the outside in the process of the calibration pin is inserted, the calibration hole (CH) is gradually opened to become large enough to insert the calibration pin sufficiently. In addition, since the phenomenon of being pinched in the state in which the calibration pins are inserted into the calibration holes CH is prevented, a malfunction of the calibration pins that do not escape from the calibration holes CH is eliminated.
위와 같은 본 실시예에 의할 경우 제작 공차를 최소한으로 감안하여 기존보다 교정구멍(CH)의 내경을 더 작게 형성할 수 있기 때문에 더욱 정교한 인서트(710)의 위치 교정이 이루어질 수 있는 것이다.According to the present embodiment as described above, since the inner diameter of the calibration hole CH can be made smaller than the conventional one in consideration of the manufacturing tolerance to a minimum, more precise position correction of the insert 710 can be made.
그리고 본 실시예에 따른 교정구멍(CH)을 이루는 벽면에 절개부분(IP)이 있고, 교정구멍(CH)의 외측으로 절개구멍(IH)을 형성하는 기술은, 앞서 제1 실시예에서 설명한 바 있는 제1 교정구멍(CH1)에만 적용될 수도 있고, 제2 교정구멍(CH2)에만 적용될 수도 있으며, 제1 교정구멍(CH1) 및 제2 교정구멍(CH2)에 모두 적용될 수도 있다.In addition, the technique of forming the cutout hole IH on the outer side of the correction hole CH and having the cutout portion IP on the wall constituting the straightening hole CH according to the present embodiment has been described above in the first embodiment. It may be applied only to the first calibration hole CH1 which is present, or may be applied only to the second calibration hole CH2, and may be applied to both the first calibration hole CH1 and the second calibration hole CH2.
한편, 위에서 설명한 실시예들은 설명의 편의를 위해서 서로 분리하여 설명하였지만, 실시하기에 따라서는 제1 실시예와 제2 실시예가 제품에 함께 구현될 수도 있고, 제품에 별개로 적용될 수도 있다.On the other hand, the above-described embodiments are described separately from each other for convenience of description, but according to the implementation, the first embodiment and the second embodiment may be implemented together in the product, or may be separately applied to the product.
상술한 바와 같이, 본 발명에 대한 구체적인 설명은 첨부된 도면을 참조한 실시예들에 의해서 이루어졌지만, 상술한 실시예들은 본 발명의 바람직한 예를 들어 설명하였을 뿐이기 때문에, 본 발명이 상기의 실시예에만 국한되는 것으로 이해되어져서는 아니 되며, 본 발명의 권리범위는 후술하는 청구범위 및 그 등가개념으로 이해되어져야 할 것이다.As described above, the detailed description of the present invention has been made by the embodiments with reference to the accompanying drawings. However, since the above-described embodiments have only been described with reference to the preferred examples of the present invention, the present invention has been described above. It should not be understood to be limited only to the scope of the present invention will be understood by the claims and equivalent concepts described below.
(부호의 설명)(Explanation of the sign)
100, 700 : 인서트100, 700: Insert
110 : 인서트110: Insert
111 : 본체111: main body
CH1 : 제1 교정구멍 CH2 : 제2 교정구멍CH1: first calibration hole CH2: second calibration hole
112 : 지지부분112: support portion
113 : 고정기113: fixture
120 : 설치프레임120: installation frame
200 : 인터페이스보드200: interface board
210 : 테스트소켓210: test socket
AH : 정렬구멍AH: Alignment hole
220 : 소켓가이더220: Socket Guider
CP1 : 제1 교정핀 CP3 : 제2 교정핀CP1: first calibration pin CP3: second calibration pin
AP : 정렬핀AP: Alignment Pin
230 : 설치보드230: installation board

Claims (13)

  1. 반도체소자가 안착될 수 있는 안착공간이 형성된 인서트; 및An insert having a seating space in which the semiconductor device may be seated; And
    상기 인서트가 유동 가능하게 설치되는 설치프레임; 을 포함하고,An installation frame in which the insert is installed to be movable; Including,
    상기 인서트는,The insert is
    상기 안착공간이 형성된 본체;A main body in which the seating space is formed;
    상기 안착공간에 안착된 반도체소자를 지지하기 위해 상기 본체에 일체로 형성되거나 상기 본체에 결합되는 형태로 구비되는 지지부분; 및A support part formed integrally with the main body or coupled to the main body to support the semiconductor device seated in the seating space; And
    상기 안착공간에 안착된 반도체소자의 이탈을 방지하기 위해 반도체소자를 고정시키는 고정기: 를 포함하며,Fixing device for fixing the semiconductor device to prevent the separation of the semiconductor device seated in the seating space: includes;
    상기 본체에는 테스터의 인터페이스보드에 구비된 소켓가이더의 제1 교정핀이 삽입될 수 있는 제1 교정구멍과 상기 소켓가이더의 제2 교정핀이 삽입될 수 있는 제2 교정구멍이 형성되어 있는 것을 특징으로 하는The main body is provided with a first calibration hole into which the first calibration pin of the socket guider provided in the interface board of the tester and a second calibration hole into which the second calibration pin of the socket guider can be inserted. By
    테스트핸들러용 테스트트레이.Test tray for test handler.
  2. 제1항에 있어서,The method of claim 1,
    상기 인서트가 상기 인터페이스보드에 구비된 테스트소켓에 접근할 때 상기 제1 교정핀이 상기 제1 교정구멍에 먼저 삽입되고 상기 제2 교정핀이 상기 제2 교정구멍에 나중에 삽입됨으로써 상기 제1 교정구멍과 상기 제1 교정핀의 작용에 의해 상기 인서트의 위치가 1차적으로 교정되고, 상기 제2 교정구멍과 상기 제2 교정핀의 작용에 의해 상기 인서트의 위치가 2차적으로 정밀하게 교정되는 것을 특징으로 하는When the insert approaches the test socket provided on the interface board, the first calibration pin is first inserted into the first calibration hole and the second calibration pin is inserted later into the second calibration hole, thereby providing the first calibration hole. And the position of the insert is primarily corrected by the action of the first calibration pin and the position of the insert is precisely secondarily corrected by the action of the second calibration hole and the second calibration pin. By
    테스트핸들러용 테스트트레이.Test tray for test handler.
  3. 제2항에 있어서,The method of claim 2,
    상기 제1 교정핀은 상기 제2 교정핀보다 돌출된 높이가 더 높아서 상기 제1 교정구멍에 상기 제1 교정핀이 삽입된 후 상기 제2 교정구멍에 상기 제2 교정핀이 삽입될 수 있는 것을 특징으로 하는The first calibration pin has a higher protruding height than the second calibration pin so that the second calibration pin can be inserted into the second calibration hole after the first calibration pin is inserted into the first calibration hole. Characterized
    테스트핸들러용 테스트트레이. Test tray for test handler.
  4. 제1항에 있어서,The method of claim 1,
    상기 제2 교정구멍은 일 측 방향으로 긴 장공 형태인 것을 특징으로 하는The second calibration hole is characterized in that the long hole shape in one side direction
    테스트핸들르용 테스트트레이.Test tray for test handle.
  5. 제4항에 있어서,The method of claim 4, wherein
    상기 제2 교정구멍은 상기 제2 교정구멍의 중심과 상기 인서트의 중심을 지나는 직선 방향으로 더 긴 장공 형태인 것을 특징으로 하는The second calibration hole is characterized in that the long hole shape in the straight direction passing through the center of the second calibration hole and the center of the insert
    테스트핸들러용 테스트트레이.Test tray for test handler.
  6. 테스트트레이의 인서트에 있는 반도체소자와 전기적으로 연결되는 테스트소켓;A test socket electrically connected to the semiconductor element in the insert of the test tray;
    상기 테스트소켓과 반도체소자의 전기적인 연결을 위해 상기 인서트의 위치를 교정하는 소켓가이더; 및A socket guider for calibrating the position of the insert for electrical connection between the test socket and the semiconductor device; And
    상기 테스트소켓과 상기 소켓가이더가 설치되는 설치보드; 를 포함하고,An installation board on which the test socket and the socket guider are installed; Including,
    상기 소켓가이더는,The socket guider,
    상기 인서트에 형성된 제1 교정구멍에 삽입되어서 상기 인서트의 위치를 1차적으로 교정하는 제1 교정핀; 및A first calibration pin inserted into a first calibration hole formed in the insert to primarily correct the position of the insert; And
    상기 인서트에 형성된 제2 교정구멍에 삽입되어서 상기 인서트의 위치를 2차적으로 교정하는 제2 교정핀; 을 포함하는 것을 특징으로 하는A second calibration pin inserted into a second calibration hole formed in the insert to secondly correct the position of the insert; Characterized in that it comprises
    테스터용 인터페이스보드.Interface board for tester.
  7. 제6항에 있어서,The method of claim 6,
    상기 인서트가 상기 테스트소켓으로 접근할 때 상기 제1 교정핀이 상기 제1 교정구멍에 먼저 삽입되면서 상기 인서트의 위치를 1차적으로 교정하고 상기 제2 교정핀이 상기 제2 교정구멍에 나중에 삽입되면서 상기 인서트의 위치를 2차적으로 정밀하게 교정하는 것을 특징으로 하는As the insert approaches the test socket, the first calibration pin is first inserted into the first calibration hole, thereby first calibrating the position of the insert and the second calibration pin is later inserted into the second calibration hole. Characterized in that the position of the insert is secondarily precisely calibrated
    테스터용 인터페이스보드.Interface board for tester.
  8. 제7항에 있어서,The method of claim 7, wherein
    상기 제1 교정핀은 상기 제2 교정핀보다 돌출된 높이가 더 높아서 상기 제1 교정구멍에 상기 제1 교정핀이 삽입된 후 상기 제2 교정구멍에 상기 제2 교정핀이 삽입될 수 있는 것을 특징으로 하는The first calibration pin has a higher protruding height than the second calibration pin so that the second calibration pin can be inserted into the second calibration hole after the first calibration pin is inserted into the first calibration hole. Characterized
    테스트핸들러용 테스트트레이. Test tray for test handler.
  9. 제8항에 있어서,The method of claim 8,
    상기 테스트소켓에는 정렬구멍이 형성되어 있고,The test socket is formed with an alignment hole,
    상기 소켓가이더는 상기 정렬구멍에 삽입될 수 있는 정렬핀을 구비한 것을 특징으로 하는The socket guider is provided with an alignment pin that can be inserted into the alignment hole
    테스트용 인터페이스보드.Test interface board.
  10. 제9항에 있어서,The method of claim 9,
    상기 제2 교정핀과 상기 정렬핀은 동일한 축 상에 구비되는 것을 특징으로 하는The second calibration pin and the alignment pin is characterized in that provided on the same axis
    테스트용 인터페이스보드.Test interface board.
  11. 제6항에 있어서,The method of claim 6,
    상기 제2 교정핀은 평단면이 일 측 방향으로 긴 타원 형태인 것을 특징으로 하는The second calibration pin is characterized in that the flat cross-section is an ellipse long form in one direction
    테스트용 인터페이스보드.Test interface board.
  12. 반도체소자가 안착될 수 있는 안착공간이 형성된 인서트; 및An insert having a seating space in which the semiconductor device may be seated; And
    상기 인서트가 유동 가능하게 고정 설치되는 설치프레임; 을 포함하고,An installation frame in which the insert is fixedly movable; Including,
    상기 인서트는,The insert is
    상기 안착공간이 형성된 본체;A main body in which the seating space is formed;
    상기 안착공간에 안착된 반도체소자를 지지하기 위해 상기 본체에 일체로 형성되거나 상기 본체에 결합되는 형태로 구비되는 지지부분; 및A support part formed integrally with the main body or coupled to the main body to support the semiconductor device seated in the seating space; And
    상기 안착공간에 안착된 반도체소자의 이탈을 방지하기 위해 반도체소자를 고정시키는 고정기: 를 포함하며,Fixing device for fixing the semiconductor device to prevent the separation of the semiconductor device seated in the seating space: includes;
    상기 본체에는 테스터의 인터페이스보드에 구비된 소켓가이더의 교정핀이 삽입될 수 있는 교정구멍이 형성되어 있고,The main body is provided with a calibration hole that can be inserted into the calibration pin of the socket guider provided in the interface board of the tester,
    상기 교정구멍을 이루는 벽면은 상기 교정구멍에 삽입된 상기 교정핀과의 접촉부분을 줄이기 위해 적어도 일부분이 절개된 형태인 것을 특징으로 하는The wall surface constituting the calibration hole is characterized in that at least a portion is cut to reduce the contact portion with the calibration pin inserted into the calibration hole.
    테스트핸들러용 인서트.Insert for test handler.
  13. 제12항에 있어서,The method of claim 12,
    상기 교정핀이 상기 교정구멍에 삽입될 때 상기 교정구멍을 이루는 벽면 중 상기 교정핀에 접하는 부분이 외측으로 후퇴된 후 탄성 복원될 수 있도록, 상기 본체에는 상기 교정구멍의 외측에 원주방향으로 복수의 절개구멍이 형성되어 있는 것을 특징으로 하는When the calibration pin is inserted into the calibration hole, the main body has a plurality of circumferential directions on the outer side of the calibration hole so that the portion of the wall that forms the calibration hole in contact with the calibration pin is retracted outward and then elastically restored. Characterized in that the incision hole is formed
    테스트핸들러용 인서트.Insert for test handler.
PCT/KR2015/011433 2014-11-20 2015-10-28 Test tray for test handler and interface board for tester WO2016080670A1 (en)

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KR101706982B1 (en) * 2012-08-16 2017-02-16 (주)테크윙 Insert for test handler

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KR20070062085A (en) * 2005-12-12 2007-06-15 삼성전자주식회사 Insert for semiconductor package
KR20080044520A (en) * 2006-11-16 2008-05-21 주식회사 하이닉스반도체 Insert for semiconductor device test handling apparatus, tray and semiconductor device handling apparatus
KR20090010338A (en) * 2007-07-23 2009-01-30 (주)테크윙 Manufacturing method of insert body of test tray for test handler
KR20100071204A (en) * 2008-12-19 2010-06-29 삼성전자주식회사 Insert module for test handler and method of manufacturing the same
KR20140091797A (en) * 2013-01-09 2014-07-23 (주)테크윙 Insert for test handler

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