WO2016074218A1 - 一种模拟预失真器核心模块及模拟预失真器系统 - Google Patents

一种模拟预失真器核心模块及模拟预失真器系统 Download PDF

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Publication number
WO2016074218A1
WO2016074218A1 PCT/CN2014/091111 CN2014091111W WO2016074218A1 WO 2016074218 A1 WO2016074218 A1 WO 2016074218A1 CN 2014091111 W CN2014091111 W CN 2014091111W WO 2016074218 A1 WO2016074218 A1 WO 2016074218A1
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Prior art keywords
signal
module
output
envelope
radio frequency
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PCT/CN2014/091111
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English (en)
French (fr)
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叶四清
汪金铭
朱尔霓
王晨
尤览
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华为技术有限公司
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Priority to JP2017525978A priority Critical patent/JP6501323B2/ja
Priority to PCT/CN2014/091111 priority patent/WO2016074218A1/zh
Priority to KR1020177012682A priority patent/KR101954287B1/ko
Priority to CN201480083391.6A priority patent/CN107078980B/zh
Priority to EP14906131.9A priority patent/EP3197113B1/en
Publication of WO2016074218A1 publication Critical patent/WO2016074218A1/zh
Priority to US15/585,642 priority patent/US9893748B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B1/0475—Circuits with means for limiting noise, interference or distortion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
    • H03F1/3247—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits using feedback acting on predistortion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/102—A non-specified detector of a signal envelope being used in an amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2201/00—Indexing scheme relating to details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements covered by H03F1/00
    • H03F2201/32—Indexing scheme relating to modifications of amplifiers to reduce non-linear distortion
    • H03F2201/3233—Adaptive predistortion using lookup table, e.g. memory, RAM, ROM, LUT, to generate the predistortion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B2001/0408—Circuits with power amplifiers

Definitions

  • the present invention relates to the field of communications, and in particular, to an analog predistorter core module and an analog predistorter system.
  • PA Power Amplifier
  • PA Power Amplifier
  • PA Power Amplifier
  • the analog predistorter system includes a main delay module, an APD (Analog Predistorter) core module, and an APD training module.
  • the input end of the main delay module, the first input end of the APD core module and the first input end of the APD training module are all connected to the input end of the analog predistorter system, the output end of the main delay module and the output of the APD core module.
  • the terminals are respectively connected to the input end of the PA, the output end of the PA is connected to the second input end of the APD training module, and the output end of the APD training module is connected to the second input end of the APD core module.
  • the input end of the analog predistorter system receives an external radio frequency signal, and transmits the radio signal to the main delay module, the APD core module and the APD training module respectively, and the main delay module delays the radio frequency signal to obtain a main delay signal.
  • the main delay signal is output to the PA.
  • the PA couples the generated signal to the APD training module, and the APD training module calculates the pre-distortion coefficient according to the RF signal and the PA generated signal, and sends the pre-distortion coefficient to the APD core module, and the APD core module according to the
  • the radio frequency signal and the digital signal generate a predistortion signal that is transmitted to the PA.
  • the PA amplifies the mixed signal of the predistortion signal and the main delay signal to obtain a transmission signal.
  • the APD training module calculates and adjusts the pre-distortion coefficient according to the RF signal and the transmission signal output by the PA.
  • the predistortion coefficient generated by the APD training module is sufficiently accurate, the APD core module generates a predistortion signal to exactly cancel the distortion generated by the PA, so that the PA output signal is almost It is exactly the same as the RF signal.
  • an embodiment of the present invention provides an analog predistorter core module and an analog predistorter system.
  • the technical solution is as follows:
  • an analog predistorter APD core module includes:
  • the radio frequency delay module is configured to receive a feedforward radio frequency signal, generate multiple radio frequency delay signals with different delays according to the feedforward radio frequency signal, and output each radio frequency delay signal to the action matrix module;
  • the envelope module is configured to receive a feedforward radio frequency signal, perform envelope detection on the feedforward radio frequency signal to obtain multiple envelope signals with different delays, and output each envelope signal to the action matrix module;
  • the action matrix module is configured to receive each of the radio frequency delay signals, the each envelope signal, and an external predistortion coefficient, and each of the radio frequency delay signals and the location according to the predistortion coefficient Each envelope signal produces a predistortion signal.
  • the radio frequency delay module includes multiple radio frequency delay units RFD, which are RFD 0 , RFD 1 , . . . , RFD N-1 , N
  • the number of columns of the nonlinear model matrix is preset;
  • the RFD 0 is configured to receive a feedforward RF signal x(t), and delay the feedforward RF signal x(t) to obtain a first RF delay signal x(t- ⁇ RF1 ), where the 1 RF delay signal x(t- ⁇ RF1 ) is output to the action matrix module;
  • the envelope module includes an envelope generating unit ED and a plurality of envelope delay units BBD.
  • the plurality of BBDs are respectively BBD 1 , BBD 2 , ..., BBD M-1 , and M is the number of rows of the preset nonlinear model matrix;
  • the output terminal of the input terminal of the ED BBD 1 is connected to the BBD 1, BBD 2, ..., BBD M in series, and the BBD 1, BBD 2, ..., each of BBD M-1
  • the output end of the BBD is connected to the action matrix module;
  • the ED is configured to receive a feedforward radio frequency signal x(t), and perform envelope detection on the feedforward radio frequency signal x(t) to obtain a first envelope signal r(t- ⁇ BB1 ), where the first An envelope signal r(t- ⁇ BB1 ) is output to the BBD 1 and the action matrix module;
  • the BBD 1 is configured to delay the first envelope signal r(t- ⁇ BB1 ) to obtain a second envelope signal r(t- ⁇ BB2 ), and the second envelope signal r(t - ⁇ BB2 ) output to the BBD 2 and the action matrix module;
  • the BBD M-1 is configured to receive an M-1 envelope signal r(t- ⁇ BBM-1 ) output by the BBD M-2 , and to the M-1 envelope signal r(t- ⁇ BBM- 1 ) Performing a delay process to obtain an Mth envelope signal r(t- ⁇ BBM ), and outputting the Mth envelope signal r(t- ⁇ BBM ) to the action matrix module.
  • the envelope module includes a plurality of envelope generating units ED, respectively ED 0 , ED 1 , . . . , ED N-1 , N is Presetting the number of columns of the nonlinear model matrix;
  • the input end of the ED 0 is configured to receive the feedforward radio frequency signal, and the output end is connected to the action matrix module;
  • the enveloping module includes a plurality of envelope generating units ED and BBD, where the plurality of EDs are ED 0 , ED 1 , . ED N , N is the number of columns of the preset nonlinear model matrix;
  • the input end of the ED 0 is configured to receive the feedforward radio frequency signal, and the output end is connected to the action matrix module;
  • An input end of the BBD is connected to an output end of the ED N, and an output end is connected to the action matrix module;
  • the ED 0 is configured to receive a feedforward radio frequency signal x(t), and perform envelope detection on the feedforward radio frequency delay signal x(t) to obtain a first envelope signal r(t- ⁇ BB1 ), The first envelope signal r(t- ⁇ BB1 ) is output to the action matrix module;
  • the ED n is configured to receive an nth radio frequency delay signal x(t- ⁇ RFn ), and perform an envelope detection on the nth radio frequency delay signal x(t- ⁇ RFn ) to obtain an n+ 1th envelope signal.
  • the ED N is configured to receive an Nth radio frequency delay signal x(t- ⁇ RFN ), and perform an envelope detection on the Nth radio frequency delay signal x(t- ⁇ RFN ) to obtain an N+1th envelope signal.
  • r(t- ⁇ BBN+1 ) outputting the N+1th envelope signal r(t- ⁇ BBN+1 ) to the action matrix module and the BBD;
  • the BBD is configured to receive the N+ 1th envelope signal r(t- ⁇ BBN+1 ), and delay the N+1th envelope signal r(t- ⁇ BBN+1 ) to obtain a
  • the N+2 envelope signal r(t- ⁇ BBN+2 ) outputs the N+2 envelope signal r(t ⁇ BBN+2 ) to the action matrix module.
  • the action matrix module includes:
  • BSLs a plurality of BSLs and predistortion signal adders, wherein the plurality of BSLs are respectively BSL 1 , BSL 2 , ..., BSL N , and N is a preset integer value;
  • the BSL n receives an nth radio frequency delay signal x(t- ⁇ RFn ) output by the radio frequency delay module, an M path envelope signal output by the envelope module, and a predistortion coefficient output by the APD training module. Selecting at least one envelope signal from the M-path envelope signals, and performing the n-th radio frequency delay signal x(t- ⁇ according to the selected at least one envelope signal and the received pre-distortion coefficient RFn ) performing amplitude and phase transformation to obtain an nth tap signal, and outputting an nth tap signal to the predistortion signal adder;
  • the predistortion signal adder is configured to receive a tap signal outputted by each BSL, which is respectively the first The tap signal, the second tap signal, ..., the Nth tap signal add the first tap signal, the second tap signal, ..., the Nth tap signal to obtain a predistortion signal.
  • the BSL n includes an in-phase BLUT, an orthogonal BLUT, and an AVM; and an envelope input end of the in-phase BLUT And an envelope input end of the orthogonal BLUT is connected to the envelope module, and a coefficient input end of the in-phase BLUT and a coefficient input end of the orthogonal BLUT are connected to a coefficient input end of the BSL module,
  • the coefficients at the coefficient input of the in-phase BLUT are in-phase BLUT coefficients
  • the coefficients at the coefficient input of the orthogonal BLUT are orthogonal BLUT coefficients
  • the coefficients at the coefficient input of the BSL module are BSL coefficients
  • the BSL coefficients are from the in-phase BLUT And a coefficient of the two parts of the orthogonal BLUT coefficient, the output end of the in-phase BLUT and the output end of the orthogonal BLUT are respectively connected to
  • An envelope input of the in-phase BLUT and the orthogonal BLUT input includes at least one delayed envelope signal, including which envelope signals are determined by a nonlinear model matrix A, and correspondingly, the in-phase BLUT coefficients and The nonlinear predistortion coefficients included in the orthogonal BLUT coefficients are also determined by the nonlinear model matrix A;
  • the in-phase BLUT coefficient and the orthogonal BLUT coefficient include a linear pre-distortion coefficient determined by a linear model vector L; the in-phase BLUT receives a linear pre-distortion coefficient h n,i and a nonlinear pre-distortion coefficient input by the APD training module c m,n,1,i ⁇ c m,n,K,i and selecting at least one envelope signal according to the linear predistortion coefficient h n,i , the nonlinear predistortion coefficient c m,n,1,i ⁇ c m,n,K,i and said selected at least one envelope signal acquire an in-phase BLUT output signal w n,i (t), and output said in-phase BLUT output signal w n,i (t) to said In-phase modulation signal input of AVM;
  • the i in the coefficient subscript indicates that the radio frequency signal to which the coefficient acts is the nth radio frequency delay signal x(t- ⁇ RFn ), and the q in the coefficient subscript indicates that the radio frequency signal to which the coefficient acts is Hilbert transform of the nth radio frequency delay signal
  • the m in the coefficient subscript indicates that the envelope signal to which the coefficient acts is the mth envelope delay signal r(t- ⁇ BBm );
  • the orthogonal BLUT receives the linear predistortion coefficients h n,q input by the APD training module, the nonlinear predistortion coefficients c m,n,1,q ⁇ c m,n,K,q and select at least one envelope signal, Obtaining an orthogonal BLUT output signal according to the linear predistortion coefficient h n,q , the nonlinear predistortion coefficients c m,n,1,q ⁇ c m,n,K,q and the selected at least one envelope signal w n,q (t), outputting the orthogonal BLUT output signal w n,q (t) to the quadrature modulation signal input end of the AVM;
  • the AVM receives the in-phase BLUT output signal w n,i (t), the orthogonal BLUT output signal w n,q (t), and the radio frequency delay signal x(t- ⁇ output by the radio frequency delay module RFn), according to the in-phase output signal BLUT w n, i (t) and the quadrature output signal BLUT w n, q (t) to do the processing of the radio frequency signal delayed x (t- ⁇ RFn), to give
  • the AVM included in the BSL n includes a QPS, an in-phase multiplier, an orthogonal multiplier, and a subtraction Device
  • An input end of the QPS is connected to an output end of the radio frequency delay module, a first output end is connected to a first input end of the in-phase multiplier, and a second output end is connected to the orthogonal multiplier An input is connected;
  • the QPS is configured to receive an nth radio frequency delay signal x(t- ⁇ RFn ) sent by the radio frequency delay module, and divide the nth radio frequency delay signal x(t- ⁇ RFn ) into phase differences.
  • 90 degree 0 degree RF delay signal x(t- ⁇ RFn ) and -90 degree RF delay signal Outputting the 0-degree RF delay signal x(t- ⁇ RFn ) to the in-phase multiplier and the RF delay signal of the -90 degree path Output to the orthogonal multiplier;
  • the 0 degree path signal of the output of the QPS is x(t- ⁇ RFn ), but for convenience of description, it does not mean that the 0 degree path signal of the QPS output is the same as the QPS input radio frequency signal x(t- ⁇ RFn ).
  • the key technical feature of QPS is that the output of the 0-degree RF delay signal and the -90-degree RF delay signal have a 90-degree phase difference relationship, and it is not concerned whether one of them is the same as the input RF signal;
  • the in-phase multiplier is configured to receive the in-phase BLUT output signal and the 0-degree RF delay signal x(t- ⁇ RFn ), and output the in-phase BLUT output signal and the 0-degree path
  • the radio frequency delay signal x(t- ⁇ RFn ) is multiplied to obtain an in-phase modulated radio frequency signal, and the in-phase modulated radio frequency signal is output to the subtractor;
  • the second multiplier is configured to receive the orthogonal BLUT output signal and the RF delay signal of the -90 degree path Outputting the orthogonal BLUT output signal and the RF delay signal of the -90 degree path Multiplying, obtaining an orthogonal modulated radio frequency signal, and outputting the orthogonal modulated radio frequency signal to the subtractor;
  • the subtracter is configured to subtract the orthogonal modulated radio frequency signal from the in-phase modulated radio frequency signal, The nth tap signal is obtained.
  • the preset linear model vector L, L has N elements, the nth element of L is L n , and the value of L n is 0 or 1.
  • a first input end of the LUT m,n is connected to the envelope module, a second input end is connected to the APD training module, an output end is connected to the BLUT adder, and the BLUT adder is further connected to the APD training module.
  • the BLUT adder receives a LUT signal outputted by each LUT and a linear predistortion coefficient output by the APD training module, and adds the LUT signal and the linear predistortion coefficient to obtain an inphase modulation signal or a quadrature modulation. signal.
  • the LUT includes a LUT adder, a reference voltage generating module, a plurality of basis function generating units BFG, and a plurality of a multiplier, each of the plurality of BFGs corresponding to a multiplier;
  • each BFG is connected to the envelope module, and the second input end is connected to the reference voltage generating module, and the output end of each BFG is respectively corresponding to the multiplier of each BFG
  • the first input is connected;
  • a second input of each of the plurality of multipliers is coupled to the APD training module, and an output is coupled to the LUT adder;
  • the multiplier is configured to receive the basis function signal and a first pre-distortion coefficient output by the APD training module, and obtain a base contribution signal according to the base signal and the first pre-distortion coefficient, and the base contribution Signal output to the BLUT adder;
  • the LUT adder is configured to receive a base contribution signal output by each of the multipliers, and add a received LUT signal to each of the received base contribution signals.
  • the LUT includes a LUT adder, a plurality of basis function generating units BFG, and a plurality of multipliers, Each of the plurality of BFGs corresponds to one multiplier;
  • each BFG is connected to the envelope module, and the output end is respectively connected to the first input end of the multiplier corresponding to each BFG; the first of each of the plurality of multipliers The two input ends are connected to the APD training module, and the output ends are connected to the LUT adder;
  • the multiplier is configured to receive the basis function signal and a first pre-distortion coefficient output by the APD training module, and obtain a base contribution signal according to the base signal and the first pre-distortion coefficient, and the base contribution Signal output to the BLUT adder;
  • the LUT adder is configured to receive a base contribution signal output by each of the multipliers, and add a received LUT signal to each of the received base contribution signals.
  • the reference voltage generating module included in the LUT includes an amplifier, a third resistor, and a fourth resistor And a plurality of fifth resistors, wherein the plurality of fifth resistors are sequentially connected in series to form a series circuit;
  • An output end of the amplifier is connected to one end of the third resistor, one end of the series circuit, and one BFG, and the other end of the third resistor is connected to a negative input terminal of the amplifier and one end of the fourth resistor Connected, the other end of the fourth resistor is grounded;
  • a connection point of any two adjacent fifth resistors in the series circuit is connected to a BFG, and the other end of the series circuit is grounded.
  • the LUT includes K BFGs, which are BFG_1, BFG_2, ..., BFG_K, and K Preset integer value;
  • the gate of the first MOS transistor of the BFG_k is connected to the envelope module included in the APD core module, and the gate of the second MOS transistor is connected to the reference voltage generating module included in the APD core module, and the V1 output terminal of the BFG_k
  • the LUT includes K BFGs and K+1 LSs, where K is a preset integer value,
  • K is a preset integer value
  • the K BFGs are BFG_1, BFG_2, ..., BFG_K, respectively, and the K+1 LSs are LS0, LS1, ..., LSK;
  • a first input end of the LS0 is connected to a differential positive end of the output of the differential envelope module, a second input end receives an externally input constant voltage signal Vref0, and an output end is respectively connected to a differential positive input end of the BFG_k for
  • a first input end of the LSk is connected to a differential negative end of the output end of the envelope module, a second input end is connected to Vrefk outputted by the reference voltage generating module, and an output end is connected to a differential negative input end of the input end of the BFG_k.
  • the signal outputted from the V1 output of the BFG_k minus the signal outputted by the V2 output forms a differential downslope function signal, or the signal outputted by the V2 output of the BFG_k minus the signal outputted by the V1 output forms a differential upslope function signal.
  • the method further includes a first LS and multiple second LSs Each of the plurality of BFGs corresponds to a second LS;
  • a first input end of the first LS is connected to a differential positive output end of the differential envelope module, and an output end is respectively connected to a differential positive input end of each of the plurality of BFGs;
  • each of the plurality of second LSs is connected to a differential negative output end of the envelope module, a second input end is connected to the reference voltage generating module, and an output end is corresponding thereto
  • the differential negative inputs of the BFG are connected.
  • each of the BFGs of the K BFGs includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a first resistor, and a second resistor;
  • One end of the first resistor and one end of the second resistor are connected to a power source, and the other end of the first resistor is connected to a drain of the first MOS transistor, and the other end of the second resistor is The drains of the second MOS transistors are connected;
  • the base set of the first MOS transistor is connected to an external envelope module, and the source is connected to the drain of the third MOS transistor.
  • the base set of the second MOS transistor is connected to an external reference voltage generating module, and the source is connected to the drain of the third MOS transistor.
  • the source of the third MOS transistor is grounded.
  • an analog predistorter APD core module includes:
  • the linear filtering module is configured to receive a feedforward radio frequency signal, linearly filter the feedforward radio frequency signal according to a linear filter coefficient, and output the linearly filtered radio frequency signal to the ZMNL module, where the linear filtered radio frequency
  • the signal is called a linear preconditioning signal
  • the ZMNL module is configured to receive a linear preconditioning signal output by the linear filtering module, and perform nonlinear processing on the linear preconditioning signal according to a ZMNL coefficient to generate a predistortion signal.
  • the linear filtering module includes:
  • P-1 RF delay units P digital vector modulator units and linear adders, wherein P-1 RF delay units are RFD in1 , RFD in2 , ..., RFD inP-1 , P digital vector modulation
  • P-1 RF delay units are RFD in1 , RFD in2 , ..., RFD inP-1 , P digital vector modulation
  • the units are DVM in1 , DVM in2 , ..., DVM inP , and P is a preset integer value;
  • the RFD in1 , RFD in2 , ..., RFD inP-1 are connected in series, and the outputs of the RFD in1 , RFD in2 , ..., RFD inP-1 are respectively input to the DVM in2 , DVM in3 , ..., DVM inP Connected to the end, the output ends of the DVM in1 , DVM in2 , ..., DVM inP are connected to the linear adder;
  • the RFD in1 is configured to receive a feedforward RF signal x(t), and delay the feedforward RF signal x(t) to obtain a first RF delay signal x(t- ⁇ RF1 ), where the a radio frequency delay signal x(t- ⁇ RF1 ) is output to the RFD in2 and the DVM in2 ;
  • the RFD inP-1 is configured to receive a P-2 radio frequency delay signal x(t- ⁇ RFP-2 ) outputted by the RFD inP-2 , and to the P-2 radio frequency delay signal x(t- ⁇ RFP-2 ) delays to obtain the P-1 radio frequency delay signal x(t- ⁇ RFP-1 ), and outputs the P-1 radio frequency delay signal x(t- ⁇ RFP-1 ) to the DVM inP ;
  • the DVM in1 is configured to receive the feedforward radio frequency signal x(t) and an externally input predistortion coefficient, and perform amplitude and phase transformation on the feedforward radio frequency signal x(t) according to the predistortion coefficient. Outputting a signal u 1 (t), outputting the output signal u 1 (t) to the linear adder;
  • the DVM inp, p-1 for receiving a first radio frequency signal delayed x (t- ⁇ RFi-1 ), the first p-1 delay RF signal x (t- ⁇ RFp-1 ) amplitude and phase Transforming an output signal u p (t), and outputting the output signal u p (t) to the linear adder;
  • the linear adder is configured to receive output signals of the output outputs of the DVM in1 , DVM in2 , ..., DVM inP , and add u 1 (t), u 2 (t), ..., u P (t) Linear preconditioning signal.
  • the ZMNL module includes:
  • An envelope detecting unit ED and a signal lookup table unit SL the ZMNL module input end and the ED input end are connected to the RF input end x of the SL, and the ED output end and the envelope input end y of the SL Connected, the output end of the SL is the output end of the ZMNL;
  • the ED is used for performing envelope detection on the linear preconditioning signal outputted by the linear filter to generate an envelope signal, and outputting the envelope signal to the SL;
  • the SL is configured to receive a linear preconditioning signal output by the linear filter, an envelope signal of the ED output, and an externally input predistortion coefficient, according to the predistortion coefficient and the envelope signal,
  • the linear preconditioned signal is amplitude and phase transformed to obtain a predistorted signal.
  • the method further includes:
  • the broadband linear filtering module being connected to the ZMNL module;
  • the broadband linear filtering module is configured to process the linear preconditioning signal input by the ZMNL module under the action of a predistortion coefficient input by the APD training module, and output a predistortion signal.
  • an APD core module includes:
  • Linear filter module SBSL module and wideband linear filter module
  • the linear filtering module is operated by the linear filter coefficient input by the APD training module.
  • the RF signal is processed for processing, and the linear preconditioning signal is output;
  • the SBSL module processes the linear preconditioning signal under the action of the SBSL coefficient input by the APD training module C, and outputs an intermediate predistortion signal;
  • the wideband linear filtering module processes the intermediate predistortion signal input from the SBSL module under the action of the wideband linear filter coefficient input by the APD training module C, and outputs a predistortion signal.
  • an analog predistorter APD system comprising:
  • the analog predistorter system An input end is connected to an input end of the main delay module, and an input end of the analog predistorter system passes through a feedforward coupler and a first input of the APD core module and a first input of the APD training module
  • the terminals are connected to each other, and the output end of the main delay module and the output end of the APD core module are respectively connected to the first input end and the second input end of the combiner coupler, and the output end of the combined coupler is
  • the input end of the PA is connected, the second input end of the APD training module is connected to the output end of the PA through a feedback coupler, and the output end of the APD training module is connected to the second input end of the APD core module;
  • the main delay module is configured to receive a feedforward RF signal input from an input end of the analog predistorter system, delay a delay signal to obtain a main delay signal, and send the main delay signal Output to the combined coupler;
  • the APD training module is configured to receive a feedforward RF signal coupled by the feedforward coupler from an input end of the analog predistorter system and a transmit signal coupled by the feedback coupler from the PA a signal, calculating a pre-distortion coefficient according to the received feedforward RF signal and the transmit signal, and transmitting the pre-distortion coefficient to the APD core module;
  • the APD core module is configured to receive a feedforward radio frequency signal coupled by the feedforward coupler from an input end of the analog predistorter system and a predistortion coefficient sent by the APD training module, according to the received feedforward
  • the radio frequency signal and the pre-distortion coefficient generate a pre-distortion signal
  • the pre-distortion signal is output to the combining coupler
  • the pre-distortion signal and the main delay signal are mixed by the combining coupler to obtain a mixed signal
  • the mixed signal is output to the PA, and the mixed signal is amplified by the PA to output a transmission signal.
  • an analog predistorter APD system includes:
  • a main delay module, the APD core module and the APD training module according to any one of the first to third possible implementations of the second aspect or the second aspect, simulating the input of the predistorter system
  • An end of the analog predistorter system is coupled to a first input of the APD core module and a first input of the APD training module Connected to each other, the output end of the main delay module and the output end of the APD core module are respectively connected to the first input end and the second input end of the combiner coupler, the output end of the combined coupler and the
  • the input end of the APD training module is connected to the output end of the PA through a feedback coupler, and the output end of the APD training module is connected to the second input end of the APD core module;
  • the main delay module is configured to receive a feedforward RF signal input from an input end of the analog predistorter system, delay a delay signal to obtain a main delay signal, and send the main delay signal Output to the combined coupler;
  • the APD training module is configured to receive a feedforward RF signal coupled by the feedforward coupler from an input end of the analog predistorter system and a transmit signal coupled by the feedback coupler from the PA a signal, calculating a pre-distortion coefficient according to the received feedforward RF signal and the transmit signal, and transmitting the pre-distortion coefficient to the APD core module;
  • the APD core module is configured to receive a feedforward radio frequency signal coupled by the feedforward coupler from an input end of the analog predistorter system and a predistortion coefficient sent by the APD training module, according to the received feedforward
  • the radio frequency signal and the pre-distortion coefficient generate a pre-distortion signal
  • the pre-distortion signal is output to the combining coupler
  • the pre-distortion signal and the main delay signal are mixed by the combining coupler to obtain a mixed signal
  • the mixed signal is output to the PA, and the mixed signal is amplified by the PA to output a transmission signal.
  • the RF delay module is used to delay the feedforward RF signal to obtain multiple RF delay signals with different delays, and each RF delay signal is input to the action matrix module, so that the action matrix module is Each time-delayed RF delay signal generates a pre-distortion signal, so that when the PA has a distortion characteristic that does not correspond to the APD core module, the influence on the action matrix module can be eliminated, thereby effectively canceling the distortion generated by the PA.
  • FIG. 1 is a structural block diagram of an analog predistorter system according to an embodiment of the present invention
  • FIG. 2-1 is a thick block diagram of an APD core module of a matrix model according to an embodiment of the present invention
  • FIG. 2-2 is a detailed block diagram of a first embodiment of an APD core module envelope module of a matrix model according to an embodiment of the present invention
  • 2-3 is a detailed block diagram of a second embodiment of an APD core module envelope module of a matrix model according to an embodiment of the present invention
  • FIG. 2-4 is a detailed block diagram of a third embodiment of an APD core module envelope module of a matrix model according to an embodiment of the present invention
  • FIGS. 2-5 are internal block diagrams of a BSL module according to an embodiment of the present invention.
  • FIGS. 2-6 are internal block diagrams of an AVM module according to an embodiment of the present invention.
  • 2-7a are block diagrams of in-phase BLUTs provided by an embodiment of the present invention.
  • 2-7b are block diagrams of orthogonal BLUTs provided by an embodiment of the present invention.
  • 2-8a are block diagrams of an in-phase LUT using a polynomial basis function according to an embodiment of the present invention
  • 2-8b are block diagrams of orthogonal LUTs using a polynomial basis function according to an embodiment of the present invention
  • 3-1 is a thick block diagram of a first embodiment of an APD core module of a cascading model according to an embodiment of the present invention
  • FIG. 3-2 is a detailed block diagram of a first embodiment of an APD core module of a cascading model according to an embodiment of the present invention
  • 3-3 is an internal block diagram of a DVM module according to an embodiment of the present invention.
  • 3-4 are internal block diagrams of a SL (Signal LUT (Look Up Table), Block Signal Lookup Table) module according to an embodiment of the present invention
  • FIG. 3-5 are rough block diagrams of a second embodiment of an APD core module of a cascading model according to an embodiment of the present invention.
  • FIGS. 3-6 are detailed block diagrams of a second embodiment of an APD core module of a cascading model according to an embodiment of the present invention.
  • 3-7 are thick block diagrams of a third embodiment of an APD core module of a cascading model according to an embodiment of the present invention.
  • FIGS 3-8 are internal block diagrams of an SBSL module according to an embodiment of the present invention.
  • 4-1a is a block diagram of an in-phase LUT using the inventive ramp basis function according to an embodiment of the present invention
  • 4-1b is a block diagram of an orthogonal LUT using the ramp basis function of the present invention provided by an embodiment of the present invention
  • 4-2 is a reference voltage module of a ramp basis function according to an embodiment of the present invention.
  • 4-3 is a first structural block diagram of a level shifter of a ramp basis function according to an embodiment of the present invention.
  • 4-4 is a second structural block diagram of a level shifter of a ramp basis function according to an embodiment of the present invention.
  • 4-5 are basic units of a ramp basis function according to an embodiment of the present invention.
  • 4-6 are schematic diagrams showing a single-ended down-slope basis function generating circuit for a ramp-based function according to an embodiment of the present invention
  • 4-7 are single-end down-slope basis functions of a ramp-based function according to an embodiment of the present invention.
  • 4-8 are schematic diagrams of a single-ended up-slope basis function generating circuit for a ramp-based function according to an embodiment of the present invention
  • 4-9 are single-end up-slope basis functions of a ramp-based function according to an embodiment of the present invention.
  • 4-10 are schematic diagrams showing a ramp-based function differential down-slope basis function generating circuit according to an embodiment of the present invention.
  • 4-11 are schematic diagrams of a slope-based function differential down-slope basis function according to an embodiment of the present invention.
  • 4-12 are schematic diagrams of a ramp-based function differential up-slope basis function generating circuit according to an embodiment of the present invention.
  • 4-13 are differential basic slope function functions of a ramp basis function according to an embodiment of the present invention.
  • Part I Block diagram of the system of the invention.
  • the second part the first type of APD model of the present invention, namely a matrix model.
  • Part III The second type of APD model of the present invention, that is, a cascading model.
  • the fourth part the APD basis function of the present invention, that is, the slope basis function.
  • the distortion generated by the PA cannot be effectively corrected.
  • the prior art uses even polynomials as the APD basis function.
  • the problem of even polynomials is a series of problems between different basis functions, mainly the dynamic difference between high-order and low-order terms, resulting in circuit implementation and algorithm robustness.
  • the present invention proposes two types of APD models, namely a matrix model and a cascade model. Both types of models have strong memory distortion correction ability, when PA has strong memory In the case of sexual distortion, the distortion produced by the PA can be effectively corrected.
  • the present invention proposes a ramp basis function, and the dynamic difference between different basis functions is small, which is beneficial to circuit implementation and algorithm robustness.
  • the first part of the invention a block diagram of the system of the invention.
  • an analog predistorter system comprising:
  • the input of the analog predistorter system is connected to the input of the main delay module A.
  • the input of the analog predistorter system is coupled to the first input of the APD core module B and the first input of the APD training module C via a feedforward coupler.
  • the output end of the main delay module A and the output end of the APD core module B are respectively connected to the first input end and the second input end of the combiner coupler, and the output end of the combine coupler is connected to the input end of the PA.
  • the second input of the APD training module C is connected to the output of the PA through a feedback coupler, and the output of the APD training module C is connected to the second input of the APD core module B.
  • the input of the analog predistorter system receives the RF signal and outputs the RF signal to the main delay module A and the feedforward coupler.
  • the feedforward coupler is configured to couple a part of the radio frequency signal from the radio frequency signal as a feedforward radio frequency signal, and output the feedforward radio frequency signal to the APD core module B and the APD training module C.
  • the main delay module A is configured to receive the radio frequency signal, delay the radio frequency signal to obtain a main delay signal, and output the main delay signal to the combined coupler.
  • the feedback coupler is configured to couple a partial transmit signal from the transmit signal generated by the PA, and send the coupled partial transmit signal to the APD training module C.
  • the APD training module C is configured to receive the feedforward RF signal and the partial transmit signal sent by the feedback coupler, calculate a predistortion coefficient according to the feedforward RF signal and the partial transmit signal, and send the predistortion coefficient to the APD core module B.
  • the APD core module B is configured to receive the feedforward RF signal and the predistortion coefficient sent by the APD training module C, generate a predistortion signal according to the received feedforward RF signal and the predistortion coefficient, and output the predistortion signal to the combiner coupler .
  • the combining coupler is configured to mix the predistortion signal and the main delay signal to obtain a mixed signal, and output the mixed signal to the PA, and the PA mixes the mixed signal to output a transmitting signal.
  • the APD training module C calculates and based on the feedforward RF signal and the PA output signal. Adjust the predistortion coefficient. When the predistortion coefficient generated by the APD training module C is sufficiently accurate, the predistortion signal generated by the APD core module B can exactly cancel the distortion generated by the PA, so that the transmission signal of the PA output is almost identical to the feedforward RF signal.
  • the second part the first type of APD model of the present invention, namely a matrix model.
  • the first type of model of the APD core module B in the system block diagram of the present invention that is, the matrix model, see FIG. 2-1, the matrix model of the APD core module B includes:
  • the RF delay module 1, the envelope module 2 and the action matrix module 3, and the action matrix module 3 are respectively connected to the RF delay module 1 and the envelope module 2.
  • the RF delay module 1 is configured to receive a feedforward RF signal, generate multiple RF delay signals of different delays according to the feedforward RF signal, and output each RF delay signal to the action matrix module 3.
  • the envelope module 2 is configured to receive the feedforward RF signal, perform envelope detection on the feedforward RF signal to obtain multiple envelope signals of different delays, and output each envelope signal to the action matrix module 3.
  • the action matrix module 3 is configured to receive each RF delay signal, each envelope signal, and an external predistortion coefficient, and generate a predistortion signal according to the predistortion coefficient, each RF delay signal and each envelope signal.
  • the pre-distortion coefficient is outputted by the APD training module C to the action matrix module 3.
  • the feedforward RF signal is output from the analog predistorter system to the RF delay module 1, the envelope module 2, and the action matrix module 3.
  • the external part refers to a part other than the APD core module B, that is, the external signals received by the radio frequency delay module 1, the envelope module 2, and the action matrix module 3 are input to the APD from other parts except the APD core module B.
  • the signal of core module B is not limited to the APD core module B.
  • the RF delay module 1 includes multiple RF delay units RFD (RF (Radio Frequency) Delay, RF delay), which are RFD 0 , RFD 1 , ..., RFD N-1 , N, respectively. Is the default integer.
  • RFD Radio Frequency
  • RFD 0 , RFD 1 , ..., RFD N-1 are connected in series, and the output of each RFD of RFD 0 , RFD 1 , ..., RFD N-1 is connected to the action matrix module 3.
  • RFD 0 is used for receiving the feedforward RF signal x(t), delaying the feedforward RF signal x(t) to obtain the first RF delay signal x(t- ⁇ RF1 ), and the first RF delay signal x (t- ⁇ RF1 ) is output to the action matrix module 3, and ⁇ RF1 is the delay generated by RFD 0 .
  • RFD n is used to receive the nth radio frequency delay signal x(t- ⁇ RFn ) outputted by the RFD n-1 , and delay the nth radio frequency delay signal x(t- ⁇ RFn ) to obtain the n+ 1th radio frequency extension
  • the envelope module 2 includes an ED (Envelope Detector) and a plurality of BBD (Baseband Delay), and the plurality of BBDs are BBD 1 , BBD 2 , ..., respectively.
  • BBD M-1 , M is the default integer value.
  • ED is connected to the output terminal of the input terminal 1 of the BBD, BBD 1, BBD 2, ... , BBD M-1 in series, and a BBD, BBD 2, ..., an output terminal BBD M-1 in each of the BBD and Function
  • the matrix modules 3 are connected.
  • the ED is used to receive the feedforward RF signal x(t), and the envelope signal of the feedforward RF signal x(t) is detected to obtain a first envelope signal r(t- ⁇ BB1 ).
  • the envelope signal of x(t) is r(t) and the delay of the ED module is ⁇ BB1
  • the first envelope signal r(t- ⁇ BB1 ) is output to BBD 1 .
  • the ED may also output the square of the envelope of the RF signal, ie the ED output signal may also be r 2 (t- ⁇ BB1 ).
  • the design is ED output r(t- ⁇ BB1 ) and is made into the corresponding circuit, ED can only output r(t- ⁇ BB1 ), but not r 2 (t- ⁇ BB1 ).
  • the ED output r 2 (t- ⁇ BB1 ) is designed and made into the corresponding circuit, the ED can only output r 2 (t- ⁇ BB1 ), but not r(t- ⁇ BB1 ).
  • the ED output signal is r(t- ⁇ BB1 ).
  • the ED output signal is r 2 (t- ⁇ BB1 ), but the description will be modified accordingly, and will not be described again.
  • r(t) and r 2 (t) are baseband signals.
  • x(t- ⁇ BBm ) is not a signal appearing in the circuit, it is a hypothetical signal introduced to make the technical description more clear. That is to say, x(t- ⁇ BBm ) is a radio frequency signal obtained by imagining that the feedforward RF signal is delayed by an RF delay equal to ⁇ BBm .
  • BBD 1 is configured to delay the first envelope signal r(t- ⁇ BB1 ) to obtain a second envelope signal r(t- ⁇ BB2 ), and output the second envelope signal r(t- ⁇ BB2 ) to BBD 2 and action matrix module 3, ⁇ BB2 is the delay generated by BBD 1 .
  • BBD M-1 is used to receive the M-1 envelope signal r(t- ⁇ BBM-1 ) output by the BBD M-2 , and to delay the M-1 envelope signal r(t- ⁇ BBM-1 ) The time processing obtains the Mth envelope signal r(t- ⁇ BBM ), and outputs the Mth envelope signal r(t- ⁇ BBM ) to the action matrix module 3, and ⁇ BBM is BBD 1 , BBD 2 , ..., BBD M- 1 co-produced delay.
  • the action matrix module 3 includes:
  • BSL Block Signal LUT (Look Up Table), block signal lookup table
  • predistortion signal adder 31 which are respectively BSL 1 , BSL 2 , ..., BSL N .
  • the BSL n is respectively connected to the RF delay module 1, the envelope module 2, the predistortion signal adder 31 and the APD training module C.
  • the BSL n receives the nth radio frequency delay signal x(t- ⁇ RFn ) output by the radio frequency delay module 1, the M path envelope signal output by the envelope module 2, and the predistortion coefficient output by the APD training module C.
  • the BSL n receives the BSL n coefficients, that is, the predistortion coefficients associated with the BSL n among the predistortion coefficients output by the APD training module C to the action matrix module 3.
  • the BSL n selects at least one envelope signal from the M-path envelope signal, and performs amplitude and phase transformation on the n-th radio frequency delay signal x(t- ⁇ RFn ) according to the selected at least one envelope signal and the received BSL n coefficient.
  • the nth tap signal v n (t) is obtained, and the nth tap signal v n (t) is output to the predistortion signal adder 31.
  • the predistortion signal adder 31 receives the tap signals outputted by each BSL, and is a first tap signal, a second tap signal, ..., an Nth tap signal, and a first tap signal, a second tap signal, ..., The Nth tap signals are added to obtain a predistortion signal.
  • the APD training module C outputs a predistortion coefficient to the BSL n , that is, a BSL n coefficient
  • the BSL n coefficient includes an in-phase BLUT (Block LUT (Look Up Table), block lookup table) coefficient and an orthogonal BLUT coefficient
  • Both the in-phase BLUT coefficients and the orthogonal BLUT coefficients include linear pre-distortion coefficients and nonlinear pre-distortion coefficients.
  • the predistortion coefficients output by the APD training module C to the APD core module B include N BSL coefficients, that is, BSL 1 to BSL N coefficients.
  • Each BSL coefficient in BSL 1 - BSL N in turn includes an in-phase BLUT coefficient and an orthogonal BLUT coefficient.
  • the in-phase BLUT coefficients and the orthogonal BLUT coefficients both contain linear pre-distortion coefficients and nonlinear pre-distortion coefficients.
  • the linear model vector L is preset in advance, L has N elements, the nth element of L is L n , and the value of L n is 0 or 1.
  • the BSL n coefficients contain linear predistortion coefficients h n,i and h n,q .
  • the setting of the linear model vector L is related to the delay amount ⁇ RFmain of the main delay module in FIG. 1 .
  • n 1, 2, ..., N.
  • the nonlinear model matrix A is preset in advance, A has M rows and N columns, and the elements on the mth row and the nth column of A are A m, n , A m, and the value of n is 0 or 1.
  • BSL n selects at least one envelope signal from the M-path envelope signals according to the nonlinear model matrix A, and sets corresponding nonlinear pre-distortion coefficients.
  • a m,n 1
  • BSL n selects the mth envelope signal r(t- ⁇ BBm ) from the M envelope signal, and sets the corresponding nonlinear predistortion coefficient c m,n,k,i And c m,n,k,q .
  • BSL n does not select the mth envelope signal r(t- ⁇ BBm ) output from the envelope module 2 from the M-path envelope signal, and of course, does not set the corresponding nonlinear pre- Distortion coefficients c m,n,k,i and c m,n,k,q .
  • m 1, 2, ..., M
  • n 1, 2, ..., N
  • k 1, 2, ..., K.
  • K is the number of basis functions
  • k is the base number.
  • the nonlinear predistortion coefficient c m,n,k,i in the subscript indicates that the RF signal applied by the coefficient is the nth radio frequency delay signal x(t- ⁇ RFn ), and the nonlinear predistortion coefficient
  • the q in the subscript of c m,n,k,q indicates that the radio frequency signal to which the coefficient acts is the Hilbert transform of the nth radio frequency delay signal.
  • the radio frequency signal applied by h n,i is the nth radio frequency delay signal x(t- ⁇ RFn )
  • the radio frequency signal affected by h n,q is the Hilbert transform of the nth radio frequency delay signal. Said It is generated in the AVM (Analogue Vector Modulator).
  • the m in the coefficient subscript indicates that the envelope signal to which the coefficient acts is the mth envelope delay signal r(t- ⁇ BBm ).
  • the envelope signal affected by c m,n,1,i ⁇ c m,n,K,i is the mth envelope delay signal
  • ⁇ RF1 0ns
  • ⁇ RF2 2ns
  • ⁇ RF3 4ns
  • ⁇ BB1 0 ns
  • ⁇ BB2 2 ns
  • ⁇ BB3 4 ns
  • ⁇ RFmain is the delay amount of the main delay module in FIG. 1
  • L is a preset linear model vector
  • A is a preset nonlinear model matrix
  • the RF delay module 1 outputs three RF signals, which are the first RF delay signal x(t- ⁇ RF1 ), the second RF delay signal x(t- ⁇ RF2 ), and the third RF.
  • the envelope module 2 outputs three envelope signals, which are a first envelope signal r(t- ⁇ BB1 ), a second envelope signal r(t- ⁇ BB2 ), and a third envelope signal r(t- ⁇ BB3). ).
  • RF delay module 1 outputs x(t- ⁇ RF1 ) to BSL 1 and envelope module 2 outputs r(t- ⁇ BB1 ) to BSL 1 .
  • BSL 1 splits the input pre-distortion coefficients h 1,i , h 1,q as the BSL 1 linear pre-distortion coefficient, and BSL 1 will input c 1,1,k in the pre-distortion coefficient.
  • RF delay module 1 outputs x(t- ⁇ RF2 ) to BSL 2
  • envelope module 2 outputs r(t- ⁇ BB1 ), r(t- ⁇ BB2 ), r(t- ⁇ BB3 ) to BSL 2
  • BSL 2 will input c 1,2,k,i , c 1,2,k,q c 2,2,k,i ,c 2,2,k,q ,c 3 in the pre-distortion coefficients.
  • RF delay module 1 outputs x(t- ⁇ RF3 ) to BSL 3 and envelope module 2 outputs r(t- ⁇ BB3 ) to BSL 3 .
  • BSL 3 splits the input pre-distortion coefficients h 3,i , h 3,q as the BSL 1 linear pre-distortion coefficient, and BSL 3 will input c 3,3,k in the pre-distortion coefficient.
  • Figure 2-2 shows the first implementation of the envelope module 2.
  • the characteristic of this implementation is that there is only one envelope generating unit ED, all envelope delay signals are output signals of ED, or the ED output signals are obtained with different delays.
  • the envelope module 2 also has a second implementation, which is characterized by a plurality of envelope generation units ED.
  • a total of envelope signals for the M path are generated.
  • the delay of each envelope signal is different.
  • M is not less than N, and N is the number of ways of the RF delay signal.
  • each of the R EDs inputs an RF delay signal.
  • the remaining M-R road envelope signals by passing certain The output signal of the ED is delayed.
  • FIG. 2-3 a first embodiment of a second implementation of the envelope module 2 of the present invention is provided.
  • the envelope module 2 shown in FIG. 2-3 includes a plurality of envelope generating units ED, respectively ED 0 , ED 1 , . . . , ED N-1 , where N is the number of columns of the preset nonlinear model matrix;
  • the input end of the ED 0 is connected to the feedforward RF signal, and the output end is connected to the action matrix module 3;
  • ED n is used to receive the n+ 1th radio frequency delay signal x(t- ⁇ RFn+1 ), and perform envelope detection on the n+ 1th radio frequency delay signal x(t- ⁇ RFn+1 ) to obtain the n+th
  • M N.
  • N envelope generating units namely ED 0 , ED 1 , ..., ED N-1 , ED 0 , ED 1 , ..., ED N-1 respectively with x(t- ⁇ RF1 ), x(t - ⁇ RF2 ),...,x(t- ⁇ RFN ), as input, convert it to the corresponding envelope signal r(t- ⁇ BB1 ), r(t- ⁇ BB2 ), ..., r(t- ⁇ BBN ) and output to the action matrix module 3.
  • ⁇ RF1 is equal to 0 or very close to 0, so x(t- ⁇ RF1 ) can be considered to be the same signal as the feedforward RF signal x(t).
  • a second embodiment of a second implementation of the envelope module 2 of the present invention is provided.
  • M N + 2.
  • N+1 envelope generating units ED which are ED 0 , ED 1 , . . . , ED N , ED 0 , ED 1 , . . .
  • ED N respectively fed forward RF signals, first RF delay signals, and Two RF delay signals, ..., the Nth RF delay signal, that is, x(t), x(t- ⁇ RF1 ), x(t- ⁇ RF2 ), ..., x(t- ⁇ RFN ), as inputs And converting it into a corresponding first envelope delay signal, a second envelope delay signal, ..., an N+1 envelope delay signal, that is, r(t), r(t- ⁇ BB1 ), r(t- ⁇ BB2 ),...,r(t- ⁇ BBN ), and delay r(t- ⁇ BBN ) to obtain r(t- ⁇ BBN+1 ), and finally r(t), r(t - ⁇ BB1 ), r(t ⁇ BB2 ), .
  • the envelope module 2 includes a plurality of envelope generating units ED and BBD, and the plurality of EDs are ED 0 , ED 1 , ..., ED N , respectively, and N is the number of columns of the predetermined nonlinear model matrix. ;
  • the input end of the ED 0 receives the feedforward radio frequency signal, and the output end is connected to the action matrix module 3;
  • the input end of the BBD is connected to the output end of the ED N , and the output end is connected to the action matrix module 3;
  • ED 0 is used for receiving the feedforward RF signal x(t), and performing envelope detection on the feedforward RF delay signal x(t) to obtain a first envelope signal r(t- ⁇ BB1 ), and the first envelope signal r(t- ⁇ BB1 ) is output to the action matrix module 3;
  • ED N is used for receiving the Nth radio frequency delay signal x(t- ⁇ RFN ), and performing envelope detection on the Nth radio frequency delay signal x(t- ⁇ RFN ) to obtain an N+1th envelope signal r(t- ⁇ BBN+1 ), output the N+1th envelope signal r(t- ⁇ BBN+1 ) to the action matrix module 3 and the BBD;
  • the N+2 envelope signal r(t ⁇ BBN+2 ) is output to the action matrix module 3.
  • BSL n is a number from 1 to N.
  • the BSL includes an in-phase BLUT 325, an orthogonal BLUT 326, and an AVM 327.
  • the RF signal input of the BSL is connected to the AVM input.
  • the envelope signal input of the BSL is connected to the envelope inputs of the in-phase BLUT and the quadrature BLUT.
  • the envelope inputs of the in-phase BLUT and the quadrature BLUT contain one or more envelope signals.
  • the coefficient input of the in-phase BLUT and the coefficient input of the quadrature BLUT are connected to the coefficient input of the BSL module.
  • the coefficients at the coefficient input of the in-phase BLUT are in-phase BLUT coefficients.
  • the coefficients at the coefficient input of the orthogonal BLUT are orthogonal BLUT coefficients.
  • the coefficient at the coefficient input of the BSL module is the BSL coefficient.
  • the BSL coefficient consists of two coefficients, the in-phase BLUT coefficient and the orthogonal BLUT coefficient.
  • the BSL coefficients of each BSL are pre-distortion coefficients from the APD training module C output to the action matrix module. Therefore, it can be considered that the in-phase BLUT and the orthogonal BLUT receive the in-phase BLUT and the orthogonal BLUT coefficients from the APD training module C, respectively. Both the in-phase BLUT coefficients and the orthogonal BLUT coefficients include linear coefficients and nonlinear coefficients.
  • the outputs of the in-phase BLUT and the quadrature BLUT are respectively connected to the in-phase modulation signal input terminal of the AVM and the quadrature modulation signal input terminal.
  • the output of the AVM unit is the output of the BSL module.
  • the in-phase BLUT 325 acquires the in-phase BLUT output signal w n according to the linear predistortion coefficient h n,i , the nonlinear predistortion coefficients c m,n,1,i ⁇ c m,n,K,i and the selected at least one envelope signal , i (t), output the in-phase BLUT output signal w n,i (t) to the in-phase modulation signal input end of the AVM;
  • the orthogonal BLUT 326 acquires the orthogonal BLUT output signal according to the linear predistortion coefficient h n,q , the nonlinear predistortion coefficients c m,n,1,q ⁇ c m,n,K,q and the selected at least one envelope signal.
  • w n,q (t) output the orthogonal BLUT output signal w n,q (t) to the quadrature modulation signal input end of the AVM;
  • the AVM processes the input RF delay signal x(t- ⁇ RFn ) under the action of the in-phase BLUT output signal w n,i (t) and the orthogonal BLUT output signal w n,q (t) to obtain the output RF.
  • Signal v n (t). This process can be formulated To represent.
  • the structure of the two BLUTs is the same, that is, the structure of the in-phase BLUT 325 is exactly the same as the internal structure of the orthogonal BLUT 326, and the input envelope signals are the same, except that the input coefficients are different.
  • the output signals are different, that is, w n,i (t) and w n,q (t) are different.
  • the envelope input of the in-phase BLUT 325 and the envelope input of the quadrature BLUT 326 are coupled to the envelope module 2.
  • the coefficient input of the in-phase BLUT 325 and the coefficient input of the quadrature BLUT 326 are coupled to the coefficient input of the BSL module.
  • the coefficients at the coefficient input of the in-phase BLUT are in-phase BLUT coefficients.
  • the coefficients at the coefficient input of the orthogonal BLUT are orthogonal BLUT coefficients.
  • the coefficient of the coefficient input end of the BSL module is a BSL coefficient.
  • the BSL coefficient is composed of two coefficients of the in-phase BLUT coefficient and the orthogonal BLUT coefficient.
  • An output end of the in-phase BLUT and an output end of the orthogonal BLUT are respectively connected to an in-phase modulation signal input end of the AVM and a quadrature modulation signal input end, and the first input end of the AVM and the radio frequency delay Modules are connected, and an output of the AVM is connected to the predistortion signal adder;
  • the envelope inputs of the in-phase BLUT and the quadrature BLUT input include at least one delayed envelope signal. Which envelope signals are included are determined by the nonlinear model matrix A. Correspondingly, the nonlinear predistortion coefficients included in the in-phase BLUT coefficients and the orthogonal BLUT coefficients are also determined by the nonlinear model matrix A;
  • the in-phase BLUT coefficient and the orthogonal BLUT coefficient include a linear pre-distortion coefficient determined by a linear model vector L; the in-phase BLUT receives a linear pre-distortion coefficient h n,i and a nonlinear pre-distortion coefficient input by the APD training module c m,n,1,i ⁇ c m,n,K,i and selecting at least one envelope signal according to the linear predistortion coefficient h n,i , the nonlinear predistortion coefficient c m,n,1,i ⁇ c m,n,K,i and said selected at least one envelope signal acquire an in-phase BLUT output signal w n,i (t), and output said in-phase BLUT output signal w n,i (t) to said In-phase modulation signal input of AVM;
  • the i in the coefficient subscript indicates that the radio frequency signal to which the coefficient acts is the nth radio frequency delay signal x(t- ⁇ RFn ), and the q in the coefficient subscript indicates that the radio frequency signal to which the coefficient acts is Hilbert transform of the nth radio frequency delay signal
  • the radio frequency signal to which the h n,i acts is the nth radio frequency delay signal x(t- ⁇ RFn )
  • the radio frequency signal affected by h n,q is the Hilbert transform of the nth radio frequency delay signal. Said It is generated in the AVM.
  • m in the coefficient subscript indicates that the envelope signal to which the coefficient acts is the mth envelope delay signal r(t- ⁇ BBm ).
  • the envelope signal to which c m,n,1,i to c m,n,K,i acts is the mth envelope delay signal r(t- ⁇ BBm ).
  • m 1, 2, ..., M.
  • the orthogonal BLUT receives the linear predistortion coefficients h n,q input by the APD training module, the nonlinear predistortion coefficients c m,n,1,q ⁇ c m,n,K,q and select at least one envelope signal, Obtaining an orthogonal BLUT output signal according to the linear predistortion coefficient h n,q , the nonlinear predistortion coefficients c m,n,1,q ⁇ c m,n,K,q and the selected at least one envelope signal w n,q (t), outputting the orthogonal BLUT output signal w n,q (t) to the quadrature modulation signal input end of the AVM;
  • the AVM receives the in-phase BLUT output signal w n,i (t), the orthogonal BLUT output signal w n,q (t), and the radio frequency delay signal x(t- ⁇ output by the radio frequency delay module RFn), according to the in-phase output signal BLUT w n, i (t) and the quadrature output signal BLUT w n, q (t) to do the processing of the radio frequency signal delayed x (t- ⁇ RFn), to give
  • the in-phase BLUT 325 also includes at least one LUT (Look Up Table) and a BLUT adder 3211, the at least one LUT including the LUT m,n .
  • LUT m,n The subscript m of the LUT, m in n, indicates that the input envelope signal is the mth envelope signal r(t- ⁇ BBm ), and m takes a specific one of 1, 2, ..., M value.
  • LUT m,n The subscript m of the LUT, n in n, indicates that the input RF signal is the nth delayed radio frequency signal x(t- ⁇ RFn ), and n takes a certain value of 1, 2, ..., N .
  • the total nonlinear predistortion coefficient of the in-phase BLUT 325 is S*K real numbers, and S does not exceed M.
  • K is the number of basis functions. It is assumed here that all S columns use the same number of basis functions and are all K. In principle, the number of different base functions can be used for S columns, and it is not difficult to calculate the total number of nonlinear predistortion coefficients of the in-phase BLUT 325, but the total nonlinear predistortion coefficient is not necessarily S. *K.
  • the first input of the LUT m,n is connected to the envelope module 2, the second input is connected to the APD training module C, and the output is connected to the BLUT adder 3211.
  • the BLUT adder 3211 receives the LUT signal output by each LUT and the linear predistortion coefficient h n,i output by the APD training module C , and the respective LUT signals ⁇ m,n,i (t) and the linear predistortion coefficient h n, i is added to obtain the BLUT output signal, that is, the in-phase modulation signal w n,i (t), Output w n,i (t) to the in-phase modulation signal input of AVM 327.
  • the structure and working process of the in-phase BLUT 325 are identical to the internal structure and working process of the orthogonal BLUT 326, and the input envelope signals are also the same.
  • the linear predistortion coefficient of the APD training module C output to the in-phase BLUT is h. n, i
  • the nonlinear predistortion coefficient is c m,n,1,i ⁇ c m,n,K,i
  • the linear predistortion coefficient output to the orthogonal BLUT is h n,q
  • the in-phase BLUT output signal is among them
  • the orthogonal BLUT output signal is among them
  • a LUT unit LUT m,n in the in-phase BLUT 325 is taken as an example to illustrate the composition of the LUT unit and its working process. And assume that the basis function uses an even degree polynomial.
  • the LUT m,n LUT includes a LUT adder 331, a plurality of BFGs, and a plurality of multipliers, respectively BFG_1, BFG_2, ..., BFG_K, and the plurality of multipliers are a multiplier M1 and a multiplier M2, respectively.
  • ..., multiplier MK, K is a preset integer value.
  • BFG is the abbreviation of Base Function Generator, which is the basis function generator.
  • the nonlinear predistortion coefficients of LUT m,n LUT are c m,n,1,i ⁇ c m,n,K,i , so the nonlinear predistortion coefficient of LUT m,n in inphase BLUT 325 is K Real number.
  • the input of BFG_k is connected to the output of BBD m-1 included in envelope module 2.
  • a multiplier Mk for receiving the basis function signal s k (r(t- ⁇ BBm )) and the nonlinear predistortion coefficient c m,n,k,i output by the APD training module C , and the basis function signal s k (r (t- ⁇ BBm )) and the nonlinear predistortion coefficient c m,n,k,i are multiplied to obtain the base contribution signal c m,n,k,i s k (r(t- ⁇ BBm )), and the base contribution
  • the LUT adder 331 is configured to receive the base contribution signal c m,n,k,i s k (r(t- ⁇ BBm )) output by the multiplier Mk , and add each received base contribution signal to obtain a LUT output signal.
  • ⁇ m,n,i (t) Since the basis function is assumed to be an even polynomial, the output signal of the LUT m, n in the in-phase LUT 325 is actually
  • FIG. 2-8b an internal block diagram of the LUT m, n LUT unit in the orthogonal BLUT 326 is shown.
  • the working principle is exactly the same as the LUT m, n LUT unit in the in-phase BLUT 325 in the above 2-8a, except that the input coefficients are different.
  • the input coefficients in 2-8a are c m,n,1,i ⁇ c m,n,K,i
  • the output signal of the LUT m,n in the orthogonal LUT 326 is ⁇ m,n,q (t), Since the basis function is assumed to be an even polynomial, the output signal of the LUT m, n in the orthogonal LUT 326 is actually
  • the structure and working process of the LUT in the in-phase BLUT 325 are identical to the internal structure and working process of the LUT of the orthogonal BLUT 326, except that the nonlinear predistortion coefficient of the APD training module C output to the in-phase BLUT is c m , n,1,i ⁇ c m,n,K,i , the nonlinear predistortion coefficients output to the orthogonal BLUT are c m,n,1,q ⁇ c m,n,K,q . m takes a value of 1, 2, ..., M.
  • the orthogonal BLUT 326 is based on a linear predistortion coefficient h n,q , a nonlinear predistortion coefficient c m,n,1,q ⁇ c m,n,K,q and at least one selected envelope signal.
  • the quadrature BLUT output signals w n,q (t) are obtained, and the orthogonal BLUT output signals w n,q (t) are output to the quadrature modulation signal input terminal of the AVM.
  • the AVM includes a QPS (Quadrature Phase Splitter) 3271, an in-phase multiplier 3272, an orthogonal multiplier 3273, and a subtractor 3274.
  • QPS Quadrature Phase Splitter
  • AVM is in BSL n
  • n is a certain number from 1 to N.
  • QPS 3271 is configured to receive the nth radio frequency delay signal x(t- ⁇ RFn ) sent by the radio frequency delay module 1, and divide the nth radio frequency delay signal x(t- ⁇ RFn ) into 0 degrees with a phase difference of 90 degrees.
  • RF delay signal x(t- ⁇ RFn ) and -90 degree RF delay signal Output the 0-channel RF delay signal x(t- ⁇ RFn ) to the in-phase multiplier 3272 and the -90-degree RF delay signal Output to the orthogonal multiplier 3273.
  • the QPS output signal is 0 degrees and -90 degrees, which is for the convenience of the principle description.
  • the key is to have a phase of 90 degrees between the two RF signals output by the QPS.
  • the actual 45 and -45 degrees, or 20 degrees and -70 degrees, or -16 degrees and -106 degrees, or 133 degrees and 43 degrees, etc. are all possible, do not affect the function and performance of QPS.
  • the in-phase multiplier 3272 is configured to receive the in-phase BLUT output signal w n,i (t) and the 0-channel RF delay signal x(t- ⁇ RFn ), and the in-phase BLUT output signal w n,i (t) Multiplying the RF delay signal x(t- ⁇ RFn ) of the 0-degree path to obtain the in-phase modulated RF signal w n,i (t)x(t- ⁇ RFn ), and outputting the in-phase modulated RF signal to the subtractor 3274.
  • Orthogonal multiplier 3273 for receiving quadrature BLUT output signals w n,q (t) and -90 degree channel radio frequency delay signals Output quadrature BLUT output signals w n,q (t) and -90 degree RF delay signals Multiply to obtain an orthogonal modulated RF signal
  • the quadrature modulated RF signal is output to a subtractor 3274.
  • the in-phase modulation signal and the quadrature modulation signal input by the AVM are baseband signals, and the baseband signal and the radio frequency signal of the AVM input are both analog signals, which is why the AVM is called an Analog Vector Modulator, that is, an analog vector modulator.
  • the in-phase multiplier 3272 and the orthogonal multiplier 3273 perform multiplication of the baseband signal and the radio frequency signal.
  • the output of the AVM is a radio frequency signal.
  • Subtractor 3274 for subtracting the quadrature modulated RF signal from the in-phase modulated RF signal w n,i (t)x(t- ⁇ RFn ) Obtain the RF signal v n (t) output by the AVM, that is, the nth tap signal output by the BSL n
  • the AVM outputs a radio frequency signal v n (t), that is, a BSL n output radio frequency signal, that is, an nth tap signal received by the predistortion signal adder 31.
  • the 0 degree path signal of the output of the QPS is x(t- ⁇ RFn ), but for convenience of description, it does not mean that the 0 degree path signal of the QPS output is the same as the QPS input radio frequency signal x(t- ⁇ RFn ).
  • the key technical feature of QPS is that the output of the 0 degree RF delay signal and the -90 degree RF delay signal have a 90 degree phase difference relationship, and do not care whether one of them is the same as the input RF signal.
  • the LUT includes a LUT adder, a reference voltage generating module, a plurality of basis function generating units BFG, and a plurality of multipliers, each of the plurality of BFGs corresponding to one multiplier;
  • each BFG is connected to the envelope module, and the second input end is connected to the reference voltage generating module, and the output end of each BFG is respectively corresponding to the multiplier of each BFG
  • the first input is connected;
  • a second input of each of the plurality of multipliers is coupled to the APD training module, and an output is coupled to the LUT adder;
  • the multiplier is configured to receive the basis function signal and a first pre-distortion coefficient output by the APD training module, and obtain a base contribution signal according to the base signal and the first pre-distortion coefficient, and the base contribution Signal output to the BLUT adder;
  • the LUT adder is configured to receive a base contribution signal output by each of the multipliers, and add a received LUT signal to each of the received base contribution signals.
  • the LUT includes a LUT adder, a plurality of basis function generating units BFG, and a plurality of multipliers, each of the plurality of BFGs corresponding to one multiplier;
  • each BFG is connected to the envelope module, and the output end is respectively connected to the first input end of the multiplier corresponding to each BFG; the first of each of the plurality of multipliers The two input ends are connected to the APD training module, and the output ends are connected to the LUT adder;
  • the multiplier is configured to receive the basis function signal and a first pre-distortion coefficient output by the APD training module, and obtain a base contribution signal according to the base signal and the first pre-distortion coefficient, and the base contribution Signal output to the BLUT adder;
  • the LUT adder is configured to receive a base contribution signal output by each of the multipliers, and add a received LUT signal to each of the received base contribution signals.
  • the first type of APD model of the present invention delays the feedforward RF signal by the RF delay module to obtain multiple delayed RF delay signals, and outputs each RF delay signal to the action matrix.
  • the module causes the action matrix module to generate a pre-failure according to the RF delay signal of each delay True signal.
  • the APD core module of the matrix model generates nonlinear memory predistortion characteristics, so that when the PA has a distortion characteristic opposite to the predistortion characteristic of the APD core module, the distortion generated by the PA can be effectively cancelled,
  • the PA output signal is the same as the input signal of the APD core module.
  • the RF delay module is used to delay the feedforward RF signal to obtain multiple RF delay signals with different delays, and each RF delay signal is input to the action matrix module, so that the action matrix module is Each time-delayed RF delay signal generates a pre-distortion signal, so that when the PA has a distortion characteristic that does not correspond to the APD core module, the influence on the action matrix module can be eliminated, thereby effectively canceling the distortion generated by the PA.
  • the third part of the invention the second type of APD model of the invention, namely a cascade model.
  • the second type of APD model of the APD core module B in the system block diagram of the present invention is a cascaded model.
  • the first embodiment of the cascading model of the APD core module B includes:
  • ZMNL is Zero Memory Nonlinear, an abbreviation for Zero Memory Nonlinearity.
  • the linear filtering module 4 is configured to receive the feedforward RF signal, linearly filter the feedforward RF signal according to the linear filter coefficient, and output the linearly filtered RF signal to the ZMNL module 5.
  • the linearly filtered RF signal is called a linear preconditioned signal.
  • the ZMNL module 5 is configured to receive the linear preconditioning signal output by the linear filtering module 4, and perform nonlinear processing on the linear preconditioning signal according to the ZMNL coefficient to generate a predistortion signal.
  • the linear filter coefficient and the ZMNL coefficient are outputted by the APD training module C to the APD core module B, and the feedforward RF signal is output from the analog predistorter system to the APD core module B.
  • the internal block diagram of the linear filtering module 4 and the ZMNL module 5 is shown in Figure 3-2.
  • the linear filtering module 4 includes: P-1 RF delay units RFD, P DVM (Digital Vector Modulator), and a linear adder, and P-1 RF delay units RFD are RFDs respectively.
  • P digital vector modulator units DVM are DVM in1 , DVM in2 , ..., DVM inP , respectively, P is a preset integer value.
  • RFD in1 , RFD in2 , ..., RFD inP-1 are connected in series. The feedforward RF signal is sent to the input of DVM 1 in addition to the input of RFD in1 .
  • the outputs of RFD in2 , ..., RFD inP-1 are respectively connected to the inputs of DVM in2 , DVM in3 , ..., DVM inP . Connected.
  • the outputs of DVM in1 , DVM in2 , ..., DVM inP are connected to the input of linear adder 41.
  • RFD in1 is used for receiving the feedforward RF signal x(t), delaying the feedforward RF signal x(t) to obtain the first RF delay signal x(t- ⁇ RFx1 ), and the first RF delay signal x (t- ⁇ RFx1 ) is output to RFD in2 and DVM in2 , where ⁇ RFx1 is the delay generated by RFD in1 .
  • RFD inp for receiving the p- 1th radio frequency delay signal x(t- ⁇ RFxp-1 ) of the RFD inp-1 output, and delaying the p-1 radio frequency delay signal x(t- ⁇ RFxp-1 )
  • the pth radio frequency delay signal x(t- ⁇ RFxp ) is obtained, and the pth radio frequency delay signal x(t- ⁇ RFxp ) is output to RFD inp +1 and DVM inp +1 , where ⁇ RFxp is RFD in1 ,
  • the delay generated by RFD in2 , ..., RFD inp , p 2, 3, ..., P-2.
  • RFD inP-1 for receiving the P-2 RF delay signal x(t- ⁇ RFxP-2 ) of the RFD inP-2 output, and for the P-2 RF delay signal x(t- ⁇ RFxP-2 ) Delaying to obtain the P-1 RF delay signal x(t- ⁇ RFxP-1 ), and outputting the P-1 RF delay signal x(t- ⁇ RFxP-1 ) to DVM inP , where ⁇ RFxP- 1 is the delay generated by RFD in1 , RFD in2 , ..., RFD inP-1 .
  • APD training module C is DVM in1, DVM in2, ..., DVM inP generated pre-distortion coefficient corresponding respectively, DVM in1, DVM in2, ... , DVM inP corresponding pre-distortion coefficients are c FIRin, 1, c FIRin, 2, ..., c FIRin, P.
  • DVM in1 is used for receiving the feedforward RF delay signal x(t) and the external input predistortion coefficient c FIRin,1 , according to the predistortion coefficient c FIRin,1 , for the feedforward RF delay signal x(t)
  • the amplitude and phase transform yields an output signal u 1 (t) and sends the output signal u 1 (t) to a linear filter adder 41.
  • DVM inp for receiving the p- 1th radio frequency delay signal x(t- ⁇ RFxp-1 ) and the external input predistortion coefficient c FIRin,p according to the predistortion coefficient c FIRin,p , for the p-1
  • the RF delay signal x(t- ⁇ RFxp-1 ) performs amplitude and phase transformation to obtain an output signal u p (t), and sends the output signal u p (t) to the linear filter adder 41.
  • p 2,3,...,P.
  • DVM in1 ⁇ DVM inP1 specific processing of the input signal can be formulated To represent.
  • p 1, 2,..., P. See the DVM narrative section for a detailed description of the process.
  • the linear adder is configured to receive output signals u 1 (t), u 2 (t), ..., u P (t) of the DVM in1 , DVM in2 , . . . , DVM inP , for each output signal Accumulate to obtain a linear preconditioning signal.
  • the DVM includes a QPS 421, an in-phase multiplier 422, an orthogonal multiplier 423, and a subtractor 424.
  • the internal block diagram and connection relationship of the QPS 421 are the same as those of the QPS 3271 described above. No longer.
  • the first output of QPS 421 is coupled to the input of in-phase multiplier 422, and the second output is coupled to the input of quadrature multiplier 423.
  • the output of the in-phase multiplier 422 is coupled to the first input of the subtractor 424
  • the output of the quadrature multiplier 423 is coupled to the second input of the subtractor 424
  • the DVM includes a QPS 421 for receiving the pth radio frequency delay signal x(t- ⁇ RFxp ), and dividing the pth radio frequency delay signal x(t- ⁇ RFxp ) into a 0 degree channel with a phase difference of 90 degrees.
  • Signal x(t- ⁇ RFxp ) and -90 degree RF signal RF signal x (t- ⁇ RFxp ) and -90 degree RF signal of 0 degree channel respectively
  • the output is output to the in-phase multiplier 422 and the orthogonal multiplier 423.
  • DVM inp is a specific number in 1, 2, ..., P.
  • c FIRin, p, i and c FIRin, p, q are called in-phase coefficients and orthogonal coefficients, respectively. Therefore, the training module may be considered APD actual configuration C to the linear filter coefficients for the DVM inp c FIRin, p, i, and c FIRin, p, q two real numbers.
  • the in-phase coefficient c FIRin,p,i and the orthogonal coefficient c FIRin,p,q of the DVM input are all digital, and the RF signal input by the DVM is analog. This is the DVM is called Digital Vector Modulator, ie digital vector modulation. The reason for the device.
  • the in-phase multiplier 422 and the quadrature multiplier 423 perform multiplication of the digital quantity with the radio frequency signal.
  • the output of the DVM is a radio frequency signal.
  • the in-phase multiplier 422 is configured to receive the 0-channel RF signal x(t- ⁇ RFxp-1 ) and the in-phase coefficient c FIRin,p,i , and the 0-channel RF signal x(t- ⁇ RFxp-1 Multiplying the in- phase coefficients c FIRin,p,i to obtain the in-phase product signal c FIRin,p,i x(t- ⁇ RFxp-1 ), and the in-phase product signal c FIRin,p,i x(t- ⁇ RFxp-1 ) is output to the subtractor 424.
  • Orthogonal multiplier 423 for receiving RF signals of -90 degrees And the orthogonal coefficient c FIRin, p, q , the RF signal of -90 degrees Multiplying by the orthogonal coefficient c FIRin,p,q to obtain an orthogonal product signal Orthogonal product signal Output to subtractor n4.
  • a subtracter 424 for subtracting the orthogonal product signal from the in - phase product signal c FIRin,p,i x(t- ⁇ RFxp-1 ) Obtaining the p-th tap signal u p (t), that is, the DVM radio frequency signal output by the DVM unit
  • the output signals of the P DVM units that is, DVM in1 , DVM in2 , ..., DVM inP , that is, u 1 (t), u 2 (t), ..., u 2 (t) are added in the linear filter adder 41, Obtaining the output linear preconditioning signal v(t) of the linear filtering module,
  • the linear pre-conditioning signal is the RF signal output by the linear filter module, which is the RF signal input by the ZMNL module.
  • the ZMNL module 5 includes:
  • Envelope detection unit ED and signal lookup table unit SL The ZMNL module input and ED input are connected to the RF input x of the SL.
  • the ED output is connected to the RF input y of the SL.
  • the output of the SL is the output of the ZMNL.
  • the internal block diagram and connection relationship of the ED are as described above. No longer.
  • the ED is used for envelope detection of the linear preconditioning signal v(t) output from the linear filter to generate an envelope signal, and outputs the envelope signal to the SL. Assuming that the envelope of v (t) is r v (t), the ED output signal is r v (t).
  • the ED may also output the square of the envelope of the linear preconditioning signal v(t), ie the ED output signal is r v 2 (t).
  • the linear preconditioning signal v(t) is subjected to amplitude and phase transformation according to the predistortion coefficient and the envelope signal to obtain a predistortion signal z(t).
  • the SL module 5 includes:
  • In-phase LUT 521, orthogonal LUT 522, AVM unit The RF signal input x of the SL is connected to the AVM input.
  • the envelope signal input y of the SL is connected to the envelope inputs of the in-phase LUT and the quadrature LUT.
  • the in-phase LUT 521 and the orthogonal LUT 522 also receive ZMNL coefficients from the APD training module C.
  • the outputs of the in-phase LUT 521 and the quadrature LUT 522 are coupled to the in-phase modulation signal input of the AVM and the quadrature modulation signal input, respectively.
  • the output of the AVM unit is the output of the SL module.
  • the internal block diagram and operation of the in-phase LUT 521 and the orthogonal LUT 522 are as described above.
  • the internal block diagram and operation of the AVM 523 is the same as that of the AVM 327. No longer.
  • the AVM 523 receives the linear preconditioning signal v(t) output by the linear filtering module, according to the in-phase modulation signal And quadrature modulated signal Amplitude and phase modulation of v(t) to obtain the output RF signal of the AVM A Hilbert transform representing v(t), that is, a signal obtained by shifting v(t) by -90 degrees.
  • the output RF signal z(t) of the AVM is also the output signal of the APDcore module, that is, the predistortion signal.
  • a second embodiment of the cascading model of the APD core module B includes:
  • Linear filter module 6 ZMNL module 7 and wideband linear filter module 8.
  • the working principle of the linear filtering module 6 and the ZMNL module 7 is the same as that of the linear filtering module 4 and the ZMNL module 5, and will not be described again.
  • the wideband linear filtering module 8 is identical in form to the linear filtering module 4, except that the respective processing units of the wideband linear filtering module 8 have a wider processing bandwidth than the linear filtering module 4.
  • the bandwidth of the RF signal x(t) is 100 MHz
  • the bandwidth of the SL output signal is generally not lower than 500 MHz.
  • the signal bandwidth of the linear filtering module 4 is 100 MHz
  • the wideband linear filtering module 8 The processed signal bandwidth is not less than 500MHz. This requires that the wideband linear filtering module 8 and the linear filtering module 4 have different circuit designs.
  • the radio frequency delay units in the wideband linear filtering module 8 are RFD out1 , RFD out2 , . . . , RFD outL , and a total of L radio frequency delay units RFD out , wherein each RFD out has a larger bandwidth than RFD in .
  • L digital vector modulator means DVM out wherein each of the bandwidth than the DVM in DVM out large.
  • the circuit connection relationship and working principle in the broadband linear filtering module 8 are similar to those of the linear filtering module 4, and will not be described again.
  • the linear filtering module 6 processes the feedforward RF signal under the action of the linear filter coefficient input by the APD training module C, and outputs a linear preconditioning signal.
  • the ZMNL module 7 processes the linear preconditioning signal and outputs the intermediate predistortion signal under the action of the ZMNL coefficient input by the APD training module C.
  • the wideband linear filtering module 8 processes the intermediate predistortion signal input from the ZMNL module 7 under the action of the wideband linear filter coefficient input by the APD training module C, and outputs a predistortion signal.
  • a third embodiment of the cascading model of APD core module B includes:
  • Linear filtering module 9 SBSL (Single Block Signal LUT) module 10 and wideband linear filtering module 11.
  • the working principle of the linear filtering module 9 and the wideband linear filtering module 11 is the same as that of the linear filtering module 4 and the wideband linear filtering module 8, and will not be described again.
  • the SBSL of the SBSL module 10 is a single block signal LUT, an abbreviation for a single BSL.
  • the internal block diagram of the SBSL module 10 is shown in Figures 3-8. It can be seen that the SBSL module 10 is actually a special case of an action matrix module containing only a single BSL. The working principle can be referred to the function matrix module, and will not be described again.
  • the linear filtering module 9 processes the feedforward RF signal under the action of the linear filter coefficient input by the APD training module C, and outputs a linear preconditioning signal.
  • the SBSL module 10 processes the linear preconditioning signal and outputs an intermediate predistortion signal under the action of the SBSL coefficient input by the APD training module C.
  • the wideband linear filtering module 11 processes the intermediate predistortion signal input from the SBSL module 10 under the action of the wideband linear filter coefficients input by the APD training module C, and outputs a predistortion signal.
  • the second type of APD model of the present invention is through a linear filtering module, a cascade of ZMNL modules, or a linear filtering module, a ZMNL module, a cascade of broadband linear filtering modules, or a linear filtering module, an SBSL module, and a broadband.
  • the cascading of the linear filtering module enables the non-linear memory pre-distortion characteristic of the APD core module of the cascaded model by configuring appropriate coefficients, so that when the PA has a distortion characteristic opposite to the pre-distortion characteristic of the APD core module, it can be effective.
  • the distortion generated by the PA is cancelled to make the PA output signal the same as the input signal of the APD core module.
  • the fourth part of the invention the basis function of the invention, i.e. the ramp basis function.
  • the basis function of the present invention is independent of the foregoing invention.
  • APD model The first type of APD model, that is, the matrix model, and the aforementioned second APD model, that is, the cascade model, are included. That is to say, the ramp basis function can be used not only in the first APD model and the second APD model of the present invention, but also in the prior art APD model, or other APD models to be invented in the future.
  • the difference between the ramp basis function and the polynomial basis function is the internal implementation of a LUT in the BLUT. It is also assumed that this LUT is in phase BLUT 325, and BLUT 325 is in BSL n , that is, one LUT unit LUT m,n in in-phase BLUT 325 is taken as an example to illustrate the composition of the ramp basis function and its working process.
  • the LUT m,n LUT includes a LUT adder 331, a reference voltage generating module 332, a plurality of BFGs, and a plurality of multipliers, the plurality of BFGs being BFG_1, BFG_2, ..., BFG_K, respectively, and the plurality of multipliers are multipliers respectively M1, multiplier M2, ..., multiplier MK, K are preset integer values.
  • BFG is an abbreviation for Base Function Generator, the base function generator.
  • the first input end of the BFG_k is connected to the envelope module 2, the second input end is connected to the reference voltage generating module 332, the output end of the BFG_k is connected to the input end of the multiplier Mk, and the output end of the multiplier Mk is connected to the LUT adder 331.
  • k 1, 2, ..., K.
  • the first input of BFG_k is connected to the output of BBD m-1 included in envelope module 2.
  • the reference voltage generating module 332 is configured to generate a corresponding reference voltage Vrefk for the BFG_k and output the reference voltage Vrefk to the BFG_k.
  • BFG_k for receiving the mth envelope signal r(t- ⁇ BBm ) output by the envelope module 2 and the reference voltage Vrefk input by the reference voltage generating module 332, according to the mth envelope signal r(t- ⁇ BBm ) and the reference
  • the voltage Vrefk generates a basis function signal s k (r(t - ⁇ BBm )) and outputs it to its corresponding multiplier Mk.
  • a multiplier Mk for receiving the basis function signal s k (r(t- ⁇ BBm )) and the linear predistortion coefficient c m,n,k,i output by the APD training module C , and the basis function signal s k (r( T- ⁇ BBm )) and the linear predistortion coefficient c m,n,k,i are multiplied to obtain a base contribution signal c m,n,k,i s k (r(t- ⁇ BBm )), and the base contribution signal c m, n, k, i s k (r(t - ⁇ BBm )) are output to the LUT adder 331.
  • the LUT adder 331 is configured to receive the base contribution signal c m,n,k,i s k (r(t- ⁇ BBm )) output by the multiplier Mk , and add each of the received base contribution signals to obtain a LUT signal.
  • the reference voltage generating module 332 includes a first amplifier Amp1, a third resistor R3, a fourth resistor R4, and a plurality of fifth resistors R5, and the plurality of fifth resistors R5 are sequentially connected in series to form a series circuit.
  • the positive input of the first amplifier Amp1 is used to receive the bandgap voltage of the external input, and the output terminal is One end of the third resistor R3, one end of the series circuit is connected to the input end of the BFG_1, and the other end of the third resistor R3 is connected to the negative input terminal of the first amplifier Amp1 and one end of the fourth resistor R4, and the other end of the fourth resistor R4 Ground.
  • connection point of any two adjacent fifth resistors R5 in the series circuit is connected to a BFG, and the other end of the series circuit is grounded.
  • the + input terminal of the first amplifier Amp1 receives the bandgap voltage, the bandgap voltage is amplified to obtain the reference voltage Vref1, and the reference voltage Vref1 is output to the series circuit, and the connection of any two adjacent fifth resistors R5 in the series circuit is connected.
  • the point generates a reference voltage and outputs it to the BFG connected to the connection point, and the reference voltages generated in the connection points included in the series circuit are Vref2, Vref3, ..., VrefK, respectively.
  • LS includes two circuit structures as shown in Figure 4-3 and Figure 4-4.
  • LS is Level Shifter, which is an abbreviation for Level Shifter.
  • the LS may include a fourth MOS (Metal Oxid Semiconductor) transistor MOS4 and a constant current source I.
  • MOS Metal Oxid Semiconductor
  • the drain of the fourth MOS transistor MOS4 is connected to the power source, and the source and the constant current source I are An input terminal is connected, a gate Vin is connected to the envelope module 2, a second input terminal of the constant current source I is connected to an output end of the reference voltage generating module 332, and an output terminal is grounded.
  • MOS Metal Oxid Semiconductor
  • the LS may include a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, and a second amplifier Amp2.
  • One end of the sixth resistor R6 is connected to the envelope module 2, and the other end is connected to one end of the seventh resistor R7, one end of the eighth resistor R8, and the positive input terminal of the second amplifier Amp2.
  • the other end of the seventh resistor R7 is connected to the reference voltage generating module 332, and the other end of the eighth resistor R8 is grounded.
  • the negative input terminal of the second amplifier Amp2 is connected to one end of the ninth resistor R9 and one end of the tenth resistor R10, the output end is connected to the other end of the tenth resistor R10, and the other end of the ninth resistor R9 is grounded.
  • the present invention provides a basis function generating unit BFG comprising:
  • One end of the first resistor R1 and one end of the second resistor R2 are connected to the power source Vcc, and the other end of the first resistor R1 and the other end of the second resistor R2 are respectively connected to the drain of the first MOS transistor MOS1 and the second MOS transistor MOS2. The drains are connected.
  • the gate of the first MOS transistor MOS1 is connected to the envelope module 2, and the source is connected to the drain of the third MOS transistor MOS3.
  • the gate of the second MOS transistor MOS2 is connected to the reference voltage generating module 332, the source It is connected to the drain of the third MOS transistor MOS1.
  • the gate of the third MOS transistor MOS3 is connected to the fixed voltage Vy, and the source is grounded.
  • the gate of the first MOS transistor MOS1 is connected to the output of the BBD m-1 included in the envelope module 2.
  • the basis function signal generated by BFG is as follows:
  • f is a basis function signal
  • V x1 is an envelope signal r(t- ⁇ BBm ) output by the envelope module 2
  • Vrefk is a reference voltage generated by the reference voltage generating module 11 as BFG_k.
  • V T kT/q.
  • k is the Boltzmann constant
  • k 1.3806488*10 -23 JK -1
  • J is an abbreviation for the energy unit Joule.
  • K represents the absolute temperature.
  • T 300K
  • V T 26mV.
  • ⁇ is a constant related to the characteristics of the circuit.
  • f(V y ) is a fixed function determined by the characteristics of the semiconductor.
  • V y is determined
  • f(V y ) is determined
  • V 2 -V 1 and V x1 -V x2 are determined by the hyperbolic tangent function.
  • Th is a hyperbolic tangent function
  • the characteristic of the hyperbolic tangent function is the slope basis function curve.
  • the translation of the slope basis function curve is achieved by applying a bias on V x1 , V x2 .
  • the slope of the ramp basis function curve is achieved by changing V y .
  • the parameter V y is a design value related to the supply voltage V y and the number of basis functions K. At a certain V y and K, it can be designed to find the most suitable V y .
  • BFG_k can generate single-ended up-slope basis function signal, single-ended down-slope basis function signal, differential up-slope basis function signal and differential down-slope basis function signal.
  • the V1 output of BFG_k outputs a single-ended down-slope basis function signal
  • the V2 output outputs a single-ended up-slope basis function signal
  • the V1 output signal-V2 outputs a signal as a differential upper-base function signal
  • V2 outputs a signal-V1 output.
  • the signal is a differential downslope function signal.
  • one LUT may include K BFGs, the gate of the first MOS transistor MOS1 of each BFG is connected to the single-ended envelope module, the gate of the second MOS transistor MOS2 and the reference voltage generating module of the LUT.
  • the V1 output of each BFG outputs a single-ended down-slope basis function signal.
  • the single-ended down-slope basis function signal generated by BFG_15.
  • the single-ended envelope module outputs an envelope signal in a single-ended form, the envelope signal being a delayed envelope signal output by the envelope module 2, and outputted as a single-ended signal.
  • one LUT includes K BFGs, and the gate of the first MOS transistor MOS1 of each BFG is connected to the differential envelope module, and the gate of the second MOS transistor MOS2 is connected to the reference voltage generating module 332 included in the LUT.
  • the V2 output of each BFG outputs a single-ended up-slope basis function signal.
  • the differential envelope module outputs an envelope signal of a differential form, the envelope signal being a delayed envelope signal output by the envelope module 2, and outputted as a differential signal.
  • the LUT further includes a plurality of LSs, LS0, LS1, LS2, ..., LSK, and K BFGs.
  • the LS0 is called the first LS.
  • the first input of the first LS, LS0 is connected to the external constant voltage signal Vref0
  • the second input of LS0 is connected to the differential positive output of the differential envelope module
  • the output of LS0 is respectively coupled to the differential positive input of BFG_k.
  • the gate of the first MOS transistor is connected for translating the envelope differential positive end signal input from the differential envelope module according to the constant voltage signal Vref0, and outputting the translated envelope differential positive end signal to the BFG_k
  • the gate of the first MOS transistor, k 1, 2, ..., K.
  • the first input of the kth LS in the second LS that is, the LSk, is connected to the Vrefk outputted by the reference voltage generating module 332, and the second input of the LSk is connected to the differential negative output of the differential envelope module, and the output of the LSk is
  • the signal output from the V1 output of each BFG is subtracted from the signal output from the V2 output to form a differential downslope function signal.
  • the signal output from the V2 output of each BFG is subtracted from the signal output from the V1 output to form a differential up-slope function signal. See the differential up-slope basis function signals generated by BFG_1, BFG_2, ..., BFG_15 shown in Figure 4-13.
  • the prior art such as the APD chip of Scintera Corporation (now acquired by Maxiam), its APD core module is equivalent to an SBSL module, and its memory distortion correction capability is very limited.
  • the PD core module of the present invention uses a matrix model, it may include multiple BSLs, and the RF delay module may delay the feedforward RF signal to obtain multiple delayed RF delay signals, and output each RF delay signal.
  • the action matrix module is configured to cause the action matrix module to generate a predistortion signal according to each of the different delayed RF delay signals, so that the correction capability of the memory distortion of the APD system is greatly improved.
  • the correction capability of the memory distortion of the APD system is greatly improved due to the linear filtering module and the wideband linear filtering module that may be included.
  • the PA can effectively correct these distortions when the PA has strong memory linear distortion and memory nonlinear distortion.
  • prior art such as the APD chip of Scintera Corporation (now acquired by Maxiam), uses an even polynomial for its APD basis function.
  • the problem with the even polynomial is that the PAR (Peak to Average Ratio) dynamic expansion of the envelope signal is too large.
  • the PAR of the envelope signal r(t) of the radio frequency signal x(t) is 7 dB
  • the PAR of the output signal r 2 (t) of the second-order polynomial basis function unit is 14 dB
  • the fourth-order polynomial basis function unit output signal r The PAR of 4 (t) is 28 dB
  • the PAR of the 6th polynomial basis function unit output signal r 6 (t) is 42 dB
  • the PAR of the 8th order polynomial basis function unit output signal r 8 (t) is 56 dB
  • the PAR of the unit output signal r 10 (t) is 70 dB.
  • the peak value of the output signal of the base function unit allowed to pass under a certain power supply voltage is 0 dBm, and the noise level of the circuit is -70 dBm.
  • the ramp-based function of the present invention can be seen from the implementation circuit. Since the characteristics of the respective basis functions are only translational, the PAR between the output signals of the respective base function units is substantially equal, at a certain power supply voltage and constant. At the circuit noise level, there is no decrease in the SNR of some basis functions due to the difference in the output signal PAR of the basis function unit, and it does not cause a drop in the APD correction performance.

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Abstract

本发明公开了一种APD核心模块及APD系统，属于通信领域。所述APD核心模块包括：射频延时模块、包络模块和作用矩阵模块；所述射频延时模块，用于接收前馈射频信号，根据所述前馈射频信号产生多路不同延时的射频延时信号，将每路射频延时信号输出给所述作用矩阵模块；所述包络模块，用于接收前馈射频信号，对所述前馈射频信号进行包络检测得到多路不同延时的包络信号，将每路包络信号输出给所述作用矩阵模块；所述作用矩阵模块，用于接收所述每路射频延时信号、所述每路包络信号和来自外部的预失真系数，根据所述预失真系数，所述每路射频延时信号和所述每路包络信号产生预失真信号。本发明能够有效地抵消PA产生的失真。

Description

一种模拟预失真器核心模块及模拟预失真器系统 技术领域
本发明涉及通信领域，特别涉及一种模拟预失真器核心模块及模拟预失真器系统。
背景技术
PA(Power Amplifier，功率放大器)是一种对信号功率进行放大的放大器，常常应用在通信领域中。例如，在通信领域的基站中，常常使用PA对待发射信号的功率进行放大。但是，在基站中，由于PA存在发射失真的问题，使得经过PA放大后得到的发射信号中存在失真，影响了通信质量。
为了保证通信质量，目前采用模拟预失真器系统对PA产生的失真进行校正，以消除经过PA放大后的信号中存在的失真。模拟预失真器系统包括主延时模块、APD(Analog Predistorter，模拟预失真器)核心模块和APD训练模块。主延时模块的输入端、APD核心模块的第一输入端和APD训练模块的第一输入端都与模拟预失真器系统的输入端相连，主延时模块的输出端和APD核心模块的输出端分别与PA的输入端相连，PA的输出端与APD训练模块的第二输入端相连，APD训练模块的输出端与APD核心模块的第二输入端相连。
模拟预失真器系统的输入端接收外部的射频信号，将该射信号分别传输给主延时模块、APD核心模块和APD训练模块，主延时模块对该射频信号进行延时得到主延时信号，将该主延时信号输出给PA。PA将自身产生的发射信号耦合出一部分发送给APD训练模块，APD训练模块根据该射频信号和PA产生的发射信号计算预失真系数，将该预失真系数发送给APD核心模块，APD核心模块根据该射频信号和该数字信号产生预失真信号，将该预失真信号传输给PA。PA对该预失真信号与该主延时信号相混合的混合信号进行放大，得到发射信号。
其中，APD训练模块根据该射频信号和PA输出的发射信号，计算并调整预失真系数。当APD训练模块产生的预失真系数足够准确时，APD核心模块产生预失真信号就能正好抵消PA产生的失真，使得PA输出的发射信号几乎 和该射频信号完全一致了。
在实现本发明的过程中，发明人发现现有技术至少存在以下问题：
在上述模拟预失真器系统中，当PA具有与APD核心模块不对应的失真特性时，就无法有效地抵消PA产生的失真。
发明内容
为了解决上述问题，本发明实施例提供了一种模拟预失真器核心模块及模拟预失真器系统。所述技术方案如下：
第一方面、一种模拟预失真器APD核心模块，所述APD核心模块包括:
射频延时模块、包络模块和作用矩阵模块，所述作用矩阵模块分别与所述射频延时模块和所述包络模块相连；
所述射频延时模块，用于接收前馈射频信号，根据所述前馈射频信号产生多路不同延时的射频延时信号，将每路射频延时信号输出给所述作用矩阵模块；
所述包络模块，用于接收前馈射频信号，对所述前馈射频信号进行包络检测得到多路不同延时的包络信号，将每路包络信号输出给所述作用矩阵模块；
所述作用矩阵模块，用于接收所述每路射频延时信号、所述每路包络信号和来自外部的预失真系数，根据所述预失真系数，所述每路射频延时信号和所述每路包络信号产生预失真信号。
结合第一方面，在第一方面的第一种可能的实现方式中，所述射频延时模块包括多个射频延时单元RFD，分别为RFD0、RFD1、…、RFDN-1，N为预设非线性模型矩阵的列数；
所述RFD0、RFD1、…、RFDN-1依次串联，且所述RFD0、RFD1、…、RFDN-1中的每个RFD的输出端都与所述作用矩阵模块相连；
所述RFD0，用于接收前馈射频信号x(t)，对所述前馈射频信号x(t)进行延时得到第1射频延时信号x(t-τRF1)，将所述第1射频延时信号x(t-τRF1)输出给所述作用矩阵模块；
所述RFDn，用于接收RFDn-1输出的第n射频延时信号x(t-τRFn)，对所述第n射频延时信号x(t-τRFn)进行延时得到第n+1射频延时信号x(t-τRFn+1)，将所述第n+1射频延时信号x(t-τRFn+1)输出给所述所述作用矩阵模块，n＝1、2、…、N-1。
结合第一方面或第一种可能的实现方式，在第一方面的第二种可能的实现方式中，所述包络模块包括一个包络产生单元ED和多个包络延时单元BBD，所述多个BBD分别为BBD1、BBD2、…、BBDM-1，M为预设非线性模型矩阵的行数；
所述ED的输出端与所述BBD1的输入端相连，所述BBD1、BBD2、…、BBDM依次串联，且所述BBD1、BBD2、…、BBDM-1中的每个BBD的输出端与所述作用矩阵模块相连；
所述ED，用于接收前馈射频信号x(t)，对所述前馈射频信号x(t)进行包络检测得到第1包络信号r(t-τBB1)，将所述第1包络信号r(t-τBB1)输出给所述BBD1和所述作用矩阵模块；
所述BBD1，用于对所述第1包络信号r(t-τBB1)进行延时得到第2包络信号r(t-τBB2)，将所述第2包络信号r(t-τBB2)输出给所述BBD2和所述作用矩阵模块；
所述BBDm，用于接收BBDm-1输出的第m包络信号r(t-τBBm)，对所述第m包络信号r(t-τBBm)进行延时得到第m+1包络信号r(t-τBBm+1)，将所述第m+1包络信号r(t-τBBm+1)输出给所述BBDm+1和所述作用矩阵模块，m＝2、3、…、M-2；
所述BBDM-1，用于接收BBDM-2输出的第M-1包络信号r(t-τBBM-1)，对所述第M-1包络信号r(t-τBBM-1)进行延时处理得到第M包络信号r(t-τBBM)，将所述第M包络信号r(t-τBBM)输出给所述作用矩阵模块。
结合第一方面，在第一方面的第三种可能的实现方式中，所述包络模块包括多个包络产生单元ED，分别为ED0、ED1、…、EDN-1，N为预设非线性模型矩阵的列数；
所述ED0的输入端用于接收所述前馈射频信号，输出端与所述作用矩阵模块相连；
所述EDn的输入端与所述射频延时模块的输出端相连，输出端与所述作用矩阵模块相连，n＝1、2、…、N-1；
所述EDn，用于接收第n+1射频延时信号x(t-τRFn+1)，对所述第n+1射频延时信号x(t-τRFn+1)进行包络检测得到第n+1包络信号r(t-τBBn+1)，将所述第n+1包络信号r(t-τBBn+1)输出给所述作用矩阵模块，n＝0、1、…、N-1。
结合第一方面，在第一方面的第四种可能的实现方式中，所述包络模块包括多个包络产生单元ED和BBD，所述多个ED分别为ED0、ED1、…、EDN， N为预设非线性模型矩阵的列数；
所述ED0的输入端用于接收所述前馈射频信号，输出端与所述作用矩阵模块相连；
所述EDn的输入端与所述射频延时模块的输出端相连，输出端与所述作用矩阵模块相连，n＝1、2、…、N；
所述BBD的输入端与所述EDN的输出端相连，输出端与所述作用矩阵模块相连；
所述ED0，用于接收前馈射频信号x(t)，对所述前馈射频延时信号x(t)进行包络检测得到第1包络信号r(t-τBB1)，将所述第1包络信号r(t-τBB1)输出给所述作用矩阵模块；
所述EDn，用于接收第n射频延时信号x(t-τRFn)，对所述第n射频延时信号x(t-τRFn)进行包络检测得到第n+1包络信号r(t-τBBn+1)，将所述第n+1包络信号r(t-τBBn+1)输出给所述作用矩阵模块，n＝1、2、…、N-1；
所述EDN，用于接收第N射频延时信号x(t-τRFN)，对所述第N射频延时信号x(t-τRFN)进行包络检测得到第N+1包络信号r(t-τBBN+1)，将所述第N+1包络信号r(t-τBBN+1)输出给所述作用矩阵模块和所述BBD；
所述BBD，用于接收所述第N+1包络信号r(t-τBBN+1)，对所述第N+1包络信号r(t-τBBN+1)进行延时得到第N+2包络信号r(t-τBBN+2)，将所述第N+2包络信号r(t-τBBN+2)输出给所述作用矩阵模块。
结合第一方面，在第一方面的第五种可能的实现方式中，所述作用矩阵模块包括：
多个BSL和预失真信号加法器，所述多个BSL分别为BSL1、BSL2、…、BSLN，N为预设整数值；
BSLn分别与所述射频延时模块、所述包络模块、所述预失真信号加法器和APD训练模块相连，n＝1、2、…、N；
所述BSLn接收所述射频延时模块输出的第n射频延时信号x(t-τRFn)、所述包络模块输出的M路包络信号和所述APD训练模块输出的预失真系数，从所述M路包络信号中选择至少一路包络信号，根据所述选择的至少一路包络信号和所述接收的预失真系数，对所述第n射频延时信号x(t-τRFn)进行幅度和相位变换得到第n抽头信号，将第n抽头信号输出给所述预失真信号加法器；
所述预失真信号加法器，用于接收每个BSL输出的抽头信号，分别为第1 抽头信号、第2抽头信号、…、第N抽头信号，对所述第1抽头信号、第2抽头信号、…、第N抽头信号相加得到预失真信号。
结合第一方面的第五种可能的实现方式，在第一方面的第六种可能的实现方式中，所述BSLn包括同相BLUT，正交BLUT和AVM；所述同相BLUT的包络输入端和所述正交BLUT的包络输入端与所述包络模块相连，所述同相BLUT的系数输入端和所述正交BLUT的系数输入端与所述BSL模块的系数输入端相连，所述同相BLUT的系数输入端的系数为同相BLUT系数，所述正交BLUT的系数输入端的系数为正交BLUT系数，所述BSL模块的系数输入端的系数为BSL系数，所述BSL系数由所述同相BLUT系数和所述正交BLUT系数这两部分系数所组成，所述同相BLUT的输出端和所述正交BLUT的输出端分别与所述AVM的同相调制信号输入端和正交调制信号输入端相连，所述AVM的第一输入端与所述射频延时模块相连，所述AVM的输出端与所述预失真信号加法器相连；
所述同相BLUT和所述正交BLUT输入的包络输入端包含至少一个延时的包络信号，包含哪些包络信号由非线性模型矩阵A所确定，相应地，所述同相BLUT系数和所述正交BLUT系数所包含的非线性预失真系数也由非线性模型矩阵A所确定；
所述同相BLUT系数和所述正交BLUT系数是否包含线性预失真系数由线性模型向量L所确定；所述同相BLUT接收APD训练模块输入的线性预失真系数hn,i、非线性预失真系数cm,n,1,i～cm,n,K,i以及选择至少一路包络信号，根据所述线性预失真系数hn,i、非线性预失真系数cm,n,1,i～cm,n,K,i和所述选择的至少一路包络信号获取同相BLUT输出信号wn,i(t)，将所述同相BLUT输出信号wn,i(t)输出给所述AVM的同相调制信号输入端；
所述BSLn中，系数下标中的i表示该系数所作用的射频信号为第n射频延时信号x(t-τRFn)，系数下标中的q表示该系数所作用的射频信号为第n射频延时信号的Hilbert变换
Figure PCTCN2014091111-appb-000001
所述BSLn中，系数下标中的m表示该系数所作用的包络信号为第m包络延时信号r(t-τBBm)；
所述正交BLUT接收APD训练模块输入的线性预失真系数hn,q、非线性预失真系数cm,n,1,q～cm,n,K,q以及选择至少一路包络信号，根据所述线性预失真系数hn,q、非线性预失真系数cm,n,1,q～cm,n,K,q和所述选择的至少一路包络信号获取正交 BLUT输出信号wn,q(t)，将所述正交BLUT输出信号wn,q(t)输出给所述AVM的正交调制信号输入端；
所述AVM接收所述同相BLUT输出信号wn,i(t)、所述正交BLUT输出信号wn,q(t)和所述射频延时模块输出的射频延时信号x(t-τRFn)，根据所述同相BLUT输出信号wn,i(t)和所述正交BLUT输出信号wn,q(t)对所述射频延时信号x(t-τRFn)做处理，得到输出射频信号vn(t)，也就是第n抽头信号，n＝1、2、…、N。
结合第一方面的第六种可能的实现方式，在第一方面的第七种可能的实现方式中，所述BSLn所包括的AVM包括QPS、同相乘法器、正交乘法器和减法器；
所述QPS的输入端与所述射频延时模块的输出端相连，第一输出端与所述同相乘法器的第一输入端相连，第二输出端与所述正交乘法器的第一输入端相连；
所述QPS，用于接收所述射频延时模块发送的第n射频延时信号x(t-τRFn)，将所述第n射频延时信号x(t-τRFn)分为相位差为90度的0度路的射频延时信号x(t-τRFn)和-90度路的射频延时信号
Figure PCTCN2014091111-appb-000002
将所述0度路的射频延时信号x(t-τRFn)输出给所述同相乘法器以及将所述-90度路的射频延时信号
Figure PCTCN2014091111-appb-000003
输出给所述正交乘法器；
所述QPS的输出的0度路信号为x(t-τRFn)，只是为了表述方便，并不表示所述QPS输出的0度路信号与QPS输入射频信号x(t-τRFn)相同，QPS的关键技术特征是输出的0度路的射频延时信号和-90度路的射频延时信号之间成90度的相差关系，并不关心二者之一是否与输入射频信号相同；
所述同相乘法器，用于接收所述同相BLUT输出信号和所述0度路的射频延时信号x(t-τRFn)，将所述同相BLUT输出信号和所述0度路的射频延时信号x(t-τRFn)相乘，得到同相已调射频信号，将所述同相已调射频信号输出给所述减法器；
所述第二乘法器，用于接收所述正交BLUT输出信号和所述-90度路的射频延时信号
Figure PCTCN2014091111-appb-000004
将所述正交BLUT输出信号和所述-90度路的射频延时信号
Figure PCTCN2014091111-appb-000005
相乘，得到正交已调射频信号，将所述正交已调射频信号输出给所述减法器；
所述减法器，用于将所述同相已调射频信号减去所述正交已调射频信号， 得到第n抽头信号。
结合第一方面的第六种可能的实现方式，在第一方面的第八种可能的实现方式中，所述BSLn所包括的所述BLUT包括：至少一个LUT和BLUT加法器，所述至少一个LUT包括LUTm,n，m＝1、2、…、M，M为预设整数值；
其中，预设非线性模型矩阵A，A有M行N列，A的第m行第n列上的元为Am,n，Am,n的取值为0或1，当Am,n＝1时，表示所述BLUT包括LUTm,n，而且其输入的BLUT系数中包括非线性预失真系数cm,n,1,i～cm,n,K,i；当Am,n＝0时，表示所述BLUT不包括LUTm,n，而且其输入的BLUT系数中不包括非线性预失真系数cm,n,1,i～cm,n,K,i，m＝1、2、…、M，M为预设整数值；
其中，预设线性模型向量L，L有N个元，L的第n个元为Ln，Ln的取值为0或1，当Ln＝1时，则所述BLUT系数包含线性预失真系数hn,i和hn,q，当Ln＝0时，则所述BLUT系数不包含线性预失真系数hn,i和hn,q，n＝1、2、…、N；LUTm,n的第一输入端与所述包络模块相连，第二输入端与APD训练模块相连，输出端与所述BLUT加法器相连，所述BLUT加法器还与所述APD训练模块相连；
所述LUTm,n接收所述包络模块输出的第m包络信号r(t-τBBm)以及所述APD训练模块输出的非线性预失真系数，根据所述预失真系数获取所述第m包络信号r(t-τBBm)对应的LUT信号，将所述LUT信号输出给所述BLUT加法器，m＝1,2,...,M；
所述BLUT加法器接收每个LUT输出的LUT信号和所述APD训练模块输出的线性预失真系数，对所述每路LUT信号和所述线性预失真系数相加得到同相调制信号或正交调制信号。
结合第一方面的第八种可能的实现方式，在第一方面的第九种可能的实现方式中，所述LUT包括LUT加法器、参考电压产生模块、多个基函数产生单元BFG和多个乘法器，所述多个BFG中的每个BFG对应一个乘法器；
所述每个BFG的第一输入端与所述包络模块相连、第二输入端与所述参考电压产生模块相连，所述每个BFG的输出端分别与所述每个BFG对应的乘法器的第一输入端相连；
所述多个乘法器中的每个乘法器的第二输入端与所述APD训练模块相连，输出端都与所述LUT加法器相连；
所述BFG，用于接收所述包络模块输出的包络信号r(t-τBBm)和所述参考电 压产生模块输入的参考电压，根据所述包络信号r(t-τBBm)和所述参考电压产生基函数信号并输出给其对应的乘法器，m＝1,2,...,M；
所述乘法器，用于接收所述基函数信号和所述APD训练模块输出的第一预失真系数，根据所述基信号和所述第一预失真系数获取基贡献信号，将所述基贡献信号输出给所述BLUT加法器；
所述LUT加法器，用于接收所述每个乘法器输出的基贡献信号，对接收的每路基贡献信号相加得到LUT信号。
结合第一方面的第八种可能的实现方式，在第一方面的第十种可能的实现方式中，所述LUT包括LUT加法器、多个基函数产生单元BFG和多个乘法器，所述多个BFG中的每个BFG对应一个乘法器；
所述每个BFG的输入端与所述包络模块相连，输出端分别与所述每个BFG对应的乘法器的第一输入端相连；所述多个乘法器中的每个乘法器的第二输入端与所述APD训练模块相连，输出端都与所述LUT加法器相连；
所述BFG，用于接收所述包络模块输出的包络信号r(t-τBBm)，根据所述包络信号r(t-τBBm)产生基函数信号并输出给其对应的乘法器，m＝1,2,...,M；
所述乘法器，用于接收所述基函数信号和所述APD训练模块输出的第一预失真系数，根据所述基信号和所述第一预失真系数获取基贡献信号，将所述基贡献信号输出给所述BLUT加法器；
所述LUT加法器，用于接收所述每个乘法器输出的基贡献信号，对接收的每路基贡献信号相加得到LUT信号。
结合第一方面的第八种可能的实现方式，在第一方面的第十一种可能的实现方式中，所述LUT所包括的所述参考电压产生模块包括放大器、第三电阻、第四电阻和多个第五电阻，所述多个第五电阻依次串联形成串联电路；
所述放大器的输出端与所述第三电阻的一端、所述串联电路的一端和一个BFG相连，所述第三电阻的另一端与所述放大器的负极输入端和所述第四电阻的一端相连，所述第四电阻的另一端接地；
所述串联电路内任意相邻的两第五电阻的连接点与一BFG相连，所述串联电路的另一端接地。
结合第一方面的第八种可能的实现方式，在第一方面的第十二种可能的实现方式中，所述LUT所包括包括K个BFG，分别为BFG_1、BFG_2、…、BFG_K，K为预设整数值；
BFG_k的第一MOS管的栅极与APD核心模块中包括的包络模块相连，第二MOS管的栅极与所述APD核心模块包括的参考电压产生模块相连，由所述BFG_k的V1输出端输出单端下坡基函数信号，或者，由所述BFG_k的V2输出端输出单端上坡基函数信号，k＝1、2、…、K。
结合第一方面的第八种可能的实现方式，在第一方面的第十三种可能的实现方式中，所述LUT包括K个BFG和K+1个LS，K为预设整数值，所述K个BFG分别为BFG_1、BFG_2、…、BFG_K，所述K+1个LS分别为LS0、LS1、…、LSK；
LS0的第一输入端与所述差分包络模块输出端的差分正端相连，第二输入端接收外部输入的恒压信号Vref0，输出端分别与BFG_k的差分正输入端相连，用于根据所述恒压信号对所述差分包络模块输出的包络差分正端信号进行平移，将平移后的包络差分正端信号输出给BFG_k的输入端的差分正输入端，k＝1、2、…、K；
LSk的第一输入端与所述包络模块输出端的差分负端相连，第二输入端与所述参考电压产生模块输出的Vrefk相连，输出端与所述BFG_k的输入端的差分负输入端相连，用于接收所述参考电压产生模块输出的参考电压和包络差分负端信号，根据所述所述参考电压对包络差分负端信号进行平移，将平移后的包络差分负端信号输出给所述BFG_k的输入端的差分负输入端，k＝1、2、…、K；
所述BFG_k的V1输出端输出的信号减V2输出端输出的信号形成差分下坡函数信号，或者所述BFG_k的V2输出端输出的信号减V1输出端输出的信号形成差分上坡函数信号。
结合第一方面的第十二种可能的实现方式或第十三种可能的实现方式，在第一方面的第十四种可能的实现方式中，还包括一个第一LS和多个第二LS，所述多个BFG中的每个BFG对应一个第二LS；
所述第一LS的第一输入端与所述差分包络模块的差分正输出端相连，输出端分别与多个BFG中的每个BFG的差分正输入端相连；
所述多个第二LS中的每一个第二LS的第一输入端与所述包络模块的差分负输出端相连，第二输入端与所述参考电压产生模块相连，输出端与其对应的BFG的差分负输入端相连。
结合第一方面的第十二种可能的实现方式或第十三种可能的实现方式，在 第一方面的第十五种可能的实现方式中，所述K个BFG的每一个BFG包括第一MOS管、第二MOS管、第三MOS管、第一电阻和第二电阻；
所述第一电阻的一端和所述第二电阻的一端都与电源相连，所述第一电阻的另一端与所述第一MOS管的漏极相连，所述第二电阻的另一端与所述第二MOS管的漏极相连；
所述第一MOS管的基集与外部的包络模块相连，源极与所述第三MOS管的漏极相连。所述第二MOS管的基集与外部的参考电压产生模块相连，源极与所述第三MOS管的漏极相连。所述第三MOS管的源极接地。
第二方面、一种模拟预失真器APD核心模块，所述APD核心模块包括：
线性滤波模块和ZMNL模块，所述线性滤波模块的输出端与所述ZMNL模块的输入端相连；
所述线性滤波模块，用于接收前馈射频信号、根据线性滤波系数对所述前馈射频信号进行线性滤波，将线性滤波后的射频信号输出给所述ZMNL模块，所述线性滤波后的射频信号称为线性预调理信号；
所述ZMNL模块，用于接收所述线性滤波模块输出的线性预调理信号，根据ZMNL系数对所述线性预调理信号进行非线性处理以产生预失真信号。
结合第二方面，在第二方面的第一种可能的实现方式中，所述线性滤波模块包括：
P-1个射频延时单元、P个数字矢量调制器单元和线性加法器，其中P-1个射频延时单元分别为RFDin1、RFDin2、…、RFDinP-1，P个数字矢量调制器单元分别为DVMin1、DVMin2、…、DVMinP，P为预设整数值；
所述RFDin1、RFDin2、…、RFDinP-1依次串联，所述RFDin1、RFDin2、…、RFDinP-1的输出端分别与所述DVMin2、DVMin3、…、DVMinP的输入端相连，所述DVMin1、DVMin2、…、DVMinP的输出出端与所述线性加法器相连；
所述RFDin1，用于接收前馈射频信号x(t)，对所述前馈射频信号x(t)进行延时得到第1射频延时信号x(t-τRF1)，将所述第1射频延时信号x(t-τRF1)输出给所述RFDin2和所述DVMin2；
所述RFDinp，用于接收所述RFDinp-1输出的第p-1射频延时信号x(t-τRFp-1)，对所述第p-1射频延时信号x(t-τRFp-1)进行延时得到第p射频延时信号x(t-τRFp)，将所述第p射频延时信号x(t-τRFp)输出给所述RFDinp+1和DVMinp+1，p＝2、3、…、 P-2；
所述RFDinP-1，用于接收RFDinP-2输出的第P-2射频延时信号x(t-τRFP-2)，对所述第P-2射频延时信号x(t-τRFP-2)进行延时得到第P-1射频延时信号x(t-τRFP-1)，将所述第P-1射频延时信号x(t-τRFP-1)输出给DVMinP；
所述DVMin1，用于接收所述前馈射频信号x(t)和外部输入的预失真系数，根据所述预失真系数，对所述前馈射频信号x(t)进行幅度和相位变换得到输出信号u1(t)，将所述输出信号u1(t)输出给所述线性加法器；
所述DVMinp，用于接收第p-1射频延时信号x(t-τRFi-1)，对所述第p-1射频延时信号x(t-τRFp-1)进行幅度和相位变换得到输出信号up(t)，将所述输出信号up(t)输出给所述线性加法器；
所述线性加法器，用于接收所述DVMin1、DVMin2、…、DVMinP输出输出的输出信号，将u1(t)、u2(t)、…、uP(t)相加得到线性预调理信号。
结合第二方面，在第二方面的第二种可能的实现方式中，所述ZMNL模块包括：
包络检测单元ED和信号查找表单元SL，所述ZMNL模块输入端和所述ED输入端与所述SL的射频输入端x相连，所述ED输出端与所述SL的包络输入端y相连，所述SL的输出端就是所述ZMNL的输出端；
所述ED，用于对线性滤波器输出的线性预调理信号进行包络检测产生包络信号，将所述包络信号输出给SL；
所述SL，用于接收所述线性滤波器输出的线性预调理信号、所述ED输出的包络信号和外部输入的预失真系数，根据所述预失真系数和所述包络信号，对所述线性预调理信号进行幅度和相位变换得到预失真信号。
结合第二方面、第二方面的第一种可能的实现方式或第二种可能的实现方式，在第二方面的第三种可能的实现方式中，还包括：
宽带线性滤波模块，所述宽带线性滤波模块与所述ZMNL模块相连；
所述宽带线性滤波模块，用于在APD训练模块输入的预失真系数的作用下，对所述ZMNL模块输入的线性预调理信号进行处理，输出预失真信号。
第三方面、一种APD核心模块，包括：
线性滤波模块、SBSL模块和宽带线性滤波模块；
所述线性滤波模块在APD训练模块输入的线性滤波系数的作用下，对前 馈射频信号进行处理，输出线性预调理信号；
所述SBSL模块在APD训练模块C输入的SBSL系数的作用下，对线性预调理信号进行处理，输出中间预失真信号；
所述宽带线性滤波模块在所述APD训练模块C输入的宽带线性滤波系数的作用下，对从所述SBSL模块输入的中间预失真信号进行处理，输出预失真信号。
第四方面、一种模拟预失真器APD系统，包括：
主延时模块、如第一方面或第一方面的第一至第十五可能的实现方式中的任一种可能的实现方式所述的APD核心模块和APD训练模块，模拟预失真器系统的输入端与所述主延时模块的输入端相连，所述模拟预失真器系统的输入端通过前馈耦合器与所述APD核心模块的第一输入端和所述APD训练模块的第一输入端都与相连，所述主延时模块的输出端和APD核心模块的输出端分别与合路耦合器的第一输入端和第二输入端相连，所述合路耦合器的输出端与所述PA的输入端相连，所述APD训练模块的第二输入端通过反馈耦合器与所述PA的输出端相连，APD训练模块的输出端与所述APD核心模块的第二输入端相连；
所述主延时模块，用于接收所述模拟预失真器系统的输入端输入的前馈射频信号，对所述前馈射频信号进行延时得到主延时信号，将所述主延时信号输出给所述合路耦合器；
所述APD训练模块，用于接收所述前馈耦合器从所述模拟预失真器系统的输入端耦合出的前馈射频信号和所述反馈耦合器从所述PA产生的发射信号耦合的发射信号，根据接收的前馈射频信号和发射信号计算预失真系数，将所述预失真系数发送给所述APD核心模块；
所述APD核心模块，用于接收所述前馈耦合器从所述模拟预失真器系统的输入端耦合出的前馈射频信号和所述APD训练模块发送的预失真系数，根据接收的前馈射频信号和预失真系数产生预失真信号，将所述预失真信号输出给合路耦合器，由所述合路耦合器对所述预失真信号和主延时信号进行混合得到混合信号，将所述混合信号输出给PA，由PA对所述混合信号进行放大后输出发射信号。
第五方面、一种模拟预失真器APD系统，包括：
主延时模块、如第二方面或第二方面的第一至第三可能的实现方式中的任一种可能的实现方式所述的APD核心模块和APD训练模块，模拟预失真器系统的输入端与所述主延时模块的输入端相连，所述模拟预失真器系统的输入端通过前馈耦合器与所述APD核心模块的第一输入端和所述APD训练模块的第一输入端都与相连，所述主延时模块的输出端和APD核心模块的输出端分别与合路耦合器的第一输入端和第二输入端相连，所述合路耦合器的输出端与所述PA的输入端相连，所述APD训练模块的第二输入端通过反馈耦合器与所述PA的输出端相连，APD训练模块的输出端与所述APD核心模块的第二输入端相连；
所述主延时模块，用于接收所述模拟预失真器系统的输入端输入的前馈射频信号，对所述前馈射频信号进行延时得到主延时信号，将所述主延时信号输出给所述合路耦合器；
所述APD训练模块，用于接收所述前馈耦合器从所述模拟预失真器系统的输入端耦合出的前馈射频信号和所述反馈耦合器从所述PA产生的发射信号耦合的发射信号，根据接收的前馈射频信号和发射信号计算预失真系数，将所述预失真系数发送给所述APD核心模块；
所述APD核心模块，用于接收所述前馈耦合器从所述模拟预失真器系统的输入端耦合出的前馈射频信号和所述APD训练模块发送的预失真系数，根据接收的前馈射频信号和预失真系数产生预失真信号，将所述预失真信号输出给合路耦合器，由所述合路耦合器对所述预失真信号和主延时信号进行混合得到混合信号，将所述混合信号输出给PA，由PA对所述混合信号进行放大后输出发射信号。
在本发明实例中，通过射频延时模块对前馈射频信号进行延时得到多路不同延时的射频延时信号，并将每路射频延时信号输入给作用矩阵模块，使作用矩阵模块根据每路不同延时的射频延时信号产生预失真信号，如此当PA具有与APD核心模块不对应的失真特性时，可以消除对作用矩阵模块的影响，从而有效抵消PA产生的失真。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所 需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种模拟预失真器系统结构框图；
图2-1是本发明实施例提供的矩阵模型的APD核心模块粗框图；
图2-2是本发明实施例提供的矩阵模型的APD核心模块包络模块第一实施例细框图；
图2-3是本发明实施例提供的矩阵模型的APD核心模块包络模块第二实施例细框图；
图2-4是本发明实施例提供的矩阵模型的APD核心模块包络模块第三实施例细框图；
图2-5是本发明实施例提供的BSL模块内部框图；
图2-6是本发明实施例提供的AVM模块内部框图；
图2-7a是本发明实施例提供的同相BLUT框图；
图2-7b是本发明实施例提供的正交BLUT框图；
图2-8a是本发明实施例提供的使用多项式基函数的同相LUT框图；
图2-8b是本发明实施例提供的使用多项式基函数的正交LUT框图；
图3-1是本发明实施例提供的级联模型的APD核心模块第一种实施例粗框图；
图3-2是本发明实施例提供的级联模型的APD核心模块第一种实施例细框图；
图3-3是本发明实施例提供的DVM模块内部框图；
图3-4是本发明实施例提供的SL(Signal LUT(Look Up Table，查找表)，块信号查找表)模块内部框图；
图3-5是本发明实施例提供的级联模型的APD核心模块第二种实施例粗框图；
图3-6是本发明实施例提供的级联模型的APD核心模块第二种实施例细框图；
图3-7是本发明实施例提供的级联模型的APD核心模块第三实施例粗框图；
图3-8是本发明实施例提供的SBSL模块内部框图；
图4-1a是本发明实施例提供的使用发明斜坡基函数的同相LUT框图；
图4-1b是本发明实施例提供的使用本发明斜坡基函数的正交LUT框图；
图4-2是本发明实施例提供的斜坡基函数的参考电压模块；
图4-3是本发明实施例提供的斜坡基函数的电平平移器第一种结构框图；
图4-4是本发明实施例提供的斜坡基函数的电平平移器第二种结构框图；
图4-5是本发明实施例提供的斜坡基函数基本单元；
图4-6是本发明实施例提供的斜坡基函数单端下坡基函数产生电路；
图4-7是本发明实施例提供的斜坡基函数单端下坡基函数；
图4-8是本发明实施例提供的斜坡基函数单端上坡基函数产生电路；
图4-9是本发明实施例提供的斜坡基函数单端上坡基函数；
图4-10是本发明实施例提供的斜坡基函数差分下坡基函数产生电路；
图4-11是本发明实施例提供的斜坡基函数差分下坡基函数；
图4-12是本发明实施例提供的斜坡基函数差分上坡基函数产生电路；
图4-13是本发明实施例提供的斜坡基函数差分上坡基函数。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
本发明技术说明分四个部分叙述：
第一部分：本发明系统框图。
第二部分：本发明第一类APD模型，即矩阵模型。
第三部分：本发明第二类APD模型，即级联模型。
第四部分：本发明APD基函数，即斜坡基函数。
现有技术至少存在以下问题：
第一方面，当PA具有较强的记忆性失真时，由于现有技术APD核心模块对记忆性失真的校正能力非常有限，就无法有效地校正PA产生的失真。
第二方面，现有技术使用偶次多项式作为APD基函数。偶次多项式的问题是不同的基函数之间，主要是高次项与低次项间的动态差异非常大，造成电路实现和算法稳健性的一系列问题。
为解决第一方面的问题，本发明提出了两类APD模型，即矩阵模型和级联模型。两类模型都有较强的记忆性失真的校正能力，当PA具有较强的记忆 性失真时，可以有效地校正PA产生的失真。
为解决第二方面的问题，本发明提出斜坡基函数，不同的基函数之间的动态差异很小，有利于电路实现和算法稳健性。
本发明第一部分：本发明系统框图。
参见图1，本发明提供了一种模拟预失真器系统，包括：
主延时模块A、APD核心模块B、APD训练模块C、前馈耦合器、合路耦合器和反馈耦合器。模拟预失真器系统的输入端与主延时模块A的输入端相连。模拟预失真器系统的输入端通过前馈耦合器与APD核心模块B的第一输入端和APD训练模块C的第一输入端相连。主延时模块A的输出端和APD核心模块B的输出端分别与合路耦合器的第一输入端和第二输入端相连，合路耦合器的输出端与PA的输入端相连。APD训练模块C的第二输入端通过反馈耦合器与PA的输出端相连，APD训练模块C的输出端与APD核心模块B的第二输入端相连。
模拟预失真器系统的输入端接收射频信号，将该射频信号输出给主延时模块A和前馈耦合器。
前馈耦合器，用于从该射频信号中耦合中出部分射频信号作为前馈射频信号，将该前馈射频信号输出给APD核心模块B和APD训练模块C。
主延时模块A，用于接收该射频信号，对该射频信号进行延时得到主延时信号，将该主延时信号输出给合路耦合器。
反馈耦合器，用于从PA产生的发射信号中耦合出部分发射信号，将耦合出的部分发射信号发送给APD训练模块C。
APD训练模块C，用于接收前馈射频信号和反馈耦合器发送的部分发射信号，根据该前馈射频信号和部分发射信号计算预失真系数，将该预失真系数发送给APD核心模块B。
APD核心模块B，用于接收前馈射频信号和APD训练模块C发送的预失真系数，根据接收的前馈射频信号和预失真系数产生预失真信号，将该预失真信号输出给合路耦合器。
合路耦合器，用于对该预失真信号和主延时信号进行混合得到混合信号，将该混合信号输出给PA，由PA对该混合信号进行放大后输出发射信号。
其中，APD训练模块C根据前馈射频信号和PA输出的发射信号，计算并 调整预失真系数。当APD训练模块C产生的预失真系数足够准确时，APD核心模块B产生的预失真信号就能正好抵消PA产生的失真，使得PA输出的发射信号几乎和前馈射频信号完全一致了。
第二部分：本发明第一类APD模型，即矩阵模型。
本发明系统框图中的APD核心模块B的第一类模型，即矩阵模型，参见图2-1，APD核心模块B的矩阵模型包括:
射频延时模块1、包络模块2和作用矩阵模块3，作用矩阵模块3分别与射频延时模块1和包络模块2相连。
射频延时模块1，用于接收前馈射频信号，根据该前馈射频信号产生多路不同延时的射频延时信号，将每路射频延时信号输出给作用矩阵模块3。
包络模块2，用于接收该前馈射频信号，对该前馈射频信号进行包络检测得到多路不同延时的包络信号，将每路包络信号输出给作用矩阵模块3。
作用矩阵模块3，用于接收每路射频延时信号、每路包络信号以及来自外部的预失真系数、根据预失真系数，每路射频延时信号和每路包络信号产生预失真信号。
其中，预失真系数是APD训练模块C输出给作用矩阵模块3的，前馈射频信号是模拟预失真器系统的输入端输出给射频延时模块1、包络模块2和作用矩阵模块3的。
其中，在本发明中，外部是指APD核心模块B以外部分，即射频延时模块1、包络模块2和作用矩阵模块3接收的外部信号是从APD核心模块B以外的其他部分输入到APD核心模块B的信号。
参见图2-2，射频延时模块1包括多个射频延时单元RFD(RF(RadioFrequency，电磁频率)Delay，射频延时)，分别为RFD0、RFD1、…、RFDN-1，N为预设整数。
RFD0、RFD1、…、RFDN-1依次串联，且RFD0、RFD1、…、RFDN-1中的每个RFD的输出端都与作用矩阵模块3相连。
RFD0，用于接收前馈射频信号x(t)，对前馈射频信号x(t)进行延时得到第1射频延时信号x(t-τRF1)，将第1射频延时信号x(t-τRF1)输出给作用矩阵模块3，τRF1为RFD0产生的延时。
RFDn，用于接收RFDn-1输出的第n射频延时信号x(t-τRFn)，对第n射频延 时信号x(t-τRFn)进行延时得到第n+1射频延时信号x(t-τRFn+1)，将第n+1射频延时信号x(t-τRFn+1)输出给作用矩阵模块3，n＝1、3、…、N-1，τRFn+1为RFD0、RFD1、…、RFDn共同产生的延时。
优选的，参见图2-2，包络模块2包括一个ED(Envelope Detector，包络检测)和多个BBD(Baseband Delay，基带延时)，多个BBD分别为BBD1、BBD2、…、BBDM-1，M为预设整数值。
ED的输出端与BBD1的输入端相连，BBD1、BBD2、…、BBDM-1依次串联，且BBD1、BBD2、…、BBDM-1中的每个BBD的输出端与作用矩阵模块3相连。
ED，用于接收前馈射频信号x(t)，对前馈射频信号x(t)进行包络检测得到第1包络信号r(t-τBB1)。假设x(t)的包络信号为r(t)，ED模块的延时为τBB1，则ED输出包络信号r(t-τBB1)。由于ED模块的延时通常很小，可以近似认为τBB1＝0。即ED输出的包络信号，也就是第1包络信号，近似为前馈射频信号x(t)的包络信号r(t)。将第1包络信号r(t-τBB1)输出给BBD1。
根据设计，ED也可能输出射频信号的包络的平方，即ED输出信号也可能为r2(t-τBB1)。“根据设计”的意思是，如果设计为ED输出r(t-τBB1)，并制作为相应的电路，则ED就只能输出r(t-τBB1)，而不能输出r2(t-τBB1)。同样，设计为ED输出r2(t-τBB1)，并制作为相应的电路，则ED就只能输出r2(t-τBB1)，而不能输出r(t-τBB1)。
下面都是基于ED输出信号为r(t-τBB1)来叙述的。实际上，ED输出信号为r2(t-τBB1)也是可以的，只是叙述方式要做相应的修改，就不再赘述了。
相对于x(t)，r(t)和r2(t)的频率要低的多。实际上r(t)和r2(t)为基带信号。
r(t-τBBm)表示x(t-τBBm)的包络，m＝1、2、...、M-1。x(t-τBBm)并不是电路中出现的信号，是为了使技术说明更加明晰引入的一个假想信号。就是说x(t-τBBm)是假想将前馈射频信号做延时量等于τBBm的射频延时得到的射频信号。
BBD1，用于对第1包络信号r(t-τBB1)进行延时得到第2包络信号r(t-τBB2)，将第2包络信号r(t-τBB2)输出给BBD2和作用矩阵模块3，τBB2为BBD1产生的延时。
BBDm，用于接收BBDm-1输出的第m包络信号r(t-τBBm)，对第m包络信号r(t-τBBm)进行延时得到第m+1包络信号r(t-τBBm+1)，将第m+1包络信号 r(t-τBBm+1)输出给BBDm+1和作用矩阵模块3，m＝2、3、…、M-2，τBBm+1为BBD1、BBD2、…、BBDm共同产生的延时。
BBDM-1，用于接收BBDM-2输出的第M-1包络信号r(t-τBBM-1)，对第M-1包络信号r(t-τBBM-1)进行延时处理得到第M包络信号r(t-τBBM)，将第M包络信号r(t-τBBM)输出给作用矩阵模块3，τBBM为BBD1、BBD2、…、BBDM-1共同产生的延时。
参见图2-2，作用矩阵模块3包括：
多个BSL(Block Signal LUT(Look Up Table，查找表)，块信号查找表)和预失真信号加法器31，该多个BSL分别为BSL1、BSL2、…、BSLN。
BSLn分别与射频延时模块1、包络模块2、预失真信号加法器31和APD训练模块C相连。优选的，BSLn分别与射频延时模块1包括的RFDn-1的输出端和包络模块2包括的ED的输出端、BBD1的输出端、BBD2的输出端、…、BBDM-1的输出端相连，n＝1、2、…、N。
BSLn接收射频延时模块1输出的第n射频延时信号x(t-τRFn)、包络模块2输出的M路包络信号和APD训练模块C输出的预失真系数。BSLn接收BSLn系数，即APD训练模块C输出给作用矩阵模块3的预失真系数中与BSLn有关的预失真系数。BSLn从M路包络信号中选择至少一路包络信号，根据选择的至少一路包络信号和接收的BSLn系数，对第n射频延时信号x(t-τRFn)进行幅度和相位变换得到第n抽头信号vn(t)，将第n抽头信号vn(t)输出给预失真信号加法器31。
预失真信号加法器31，用于接收每个BSL输出的抽头信号，分别为第1抽头信号、第2抽头信号、…、第N抽头信号，对第1抽头信号、第2抽头信号、…、第N抽头信号相加得到预失真信号。
其中，APD训练模块C输出给BSLn的预失真系数，即BSLn系数，BSLn系数包含同相BLUT(Block LUT(Look Up Table，查找表)，块查找表)系数和正交BLUT系数，而同相BLUT系数和正交BLUT系数都包含线性预失真系数和非线性预失真系数。
由此可以看到，本发明第一类APD模型，即矩阵模型中，APD训练模块C输出给APD核心模块B的预失真系数包括N个BSL系数，即BSL1～BSLN系数。BSL1～BSLN中的每个BSL系数又包含同相BLUT系数和正交BLUT系数。而同相BLUT系数和正交BLUT系数又都包含线性预失真系数和非线性预 失真系数。其中，事先预设线性模型向量L，L有N个元，L的第n个元为Ln，Ln的取值为0或1。当Ln＝1时，则BSLn系数包含线性预失真系数hn,i和hn,q。当Ln＝0时，则BSLn系数不包含线性预失真系数hn,i和hn,q。n＝1、2、…、N。
其中，线性模型向量L的设置与图1中的主延时模块的延时量τRFmain有关。一般，需要将与τRFmain相等或者与τRFmain最相近的那个射频延时对应的那个Ln置为0。n＝1、2、…、N。
其中，事先预设非线性模型矩阵A，A有M行N列，A的第m行第n列上的元为Am,n，Am,n的取值为0或1。BSLn根据非线性模型矩阵A，从M路包络信号中选择至少一路包络信号，并设置相应的非线性预失真系数。当Am,n＝1时，则BSLn从M路包络信号中选择第m包络信号r(t-τBBm)，并设置相应的非线性预失真系数cm,n,k,i和cm,n,k,q。当Am,n＝0时，则BSLn从M路包络信号中不选择包络模块2输出的第m包络信号r(t-τBBm)，当然也就不设置相应的非线性预失真系数cm,n,k,i和cm,n,k,q。m＝1、2、…、M，n＝1、2、…、N，k＝1、2、…、K。此处K为基函数的个数，k为基号。
BSLn中，非线性预失真系数cm,n,k,i下标中的i表示该系数所作用的射频信号为第n射频延时信号x(t-τRFn)，非线性预失真系数cm,n,k,q下标中的q表示该系数所作用的射频信号为第n射频延时信号的Hilbert变换
Figure PCTCN2014091111-appb-000006
例如，hn，i所作用的射频信号为第n射频延时信号x(t-τRFn)，hn,q所作用的射频信号为第n射频延时信号的Hilbert变换
Figure PCTCN2014091111-appb-000007
所述
Figure PCTCN2014091111-appb-000008
是在所述AVM(Analogue Vector Modulator模拟矢量调制器)中生成的。
BSLn中，系数下标中的m表示该系数所作用的包络信号为第m包络延时信号r(t-τBBm)。例如，cm,n,1,i～cm,n,K,i所作用的包络信号为第m包络延时信号
r(t-τBBm)。m＝1,2,...,M。例如，模拟预失真设计参数如下
τRFmain＝2ns
N＝3，M＝3
τRF1＝0ns，τRF2＝2ns，τRF3＝4ns
τBB1＝0ns，τBB2＝2ns，τBB3＝4ns
L＝[101]
Figure PCTCN2014091111-appb-000009
其中，τRFmain为图1中的主延时模块的延时量，L为预设的线性模型向量，A为预设的非线性模型矩阵。
由于τRF2与τRFmain相等，都是2ns，所以L中的第2个元，即L2，被设置为0。
对应于上述设计参数，射频延时模块1输出3路射频信号，分别为第1射频延时信号x(t-τRF1)、第2射频延时信号x(t-τRF2)和第3射频延时信号x(t-τRF3)。包络模块2输出3路包络信号，分别为第1包络信号r(t-τBB1)、第2包络信号r(t-τBB2)和第3包络信号r(t-τBB3)。
对于BSL1，射频延时模块1输出x(t-τRF1)到BSL1，包络模块2输出r(t-τBB1)到BSL1。相应地，BSL1将输入的预失真系数中的h1,i、h1,q分拆出来作为的BSL1线性预失真系数，BSL1将输入的预失真系数中的c1,1,k,i和c1,1,k,q分拆出来作为的BSL1非线性预失真系数，k＝1、2、…、K。
对于BSL2，射频延时模块1输出x(t-τRF2)到BSL2，包络模块2输出r(t-τBB1)、r(t-τBB2)、r(t-τBB3)到BSL2。相应地，BSL2将输入的预失真系数中的c1,2,k,i、c1,2,k,q c2,2,k,i、c2,2,k,q、c3,2,k,i和c3,2,k,q分拆出来作为的BSL2非线性预失真系数，k＝1、2、…、K。
对于BSL3，射频延时模块1输出x(t-τRF3)到BSL3，包络模块2输出r(t-τBB3)到BSL3。相应地，BSL3将输入的预失真系数中的h3,i、h3,q分拆出来作为的BSL1线性预失真系数，BSL3将输入的预失真系数中的c3,3,k,i和c3,3,k,q分拆出来作为BSL3非线性预失真系数，k＝1、2、…、K。
图2-2给出的是包络模块2的第一种实现方式。这种实现方式的特点是，只有一个包络产生单元ED，所有的包络延时信号为ED的输出信号，或者将ED输出信号做不同延时来得到。
包络模块2还有第二种实现方式，其特点是有多个包络产生单元ED。
不管是包络模块2的第一种实现方式，还是包络模块2的第二种实现方式，总共都是要产生M路的包络信号。各路包络信号的延时不同。一般M不小于N，N为射频延时信号的路数。
对于包络模块2的第二种实现方式，一般有R个ED，R不大于N。R个ED中的每个ED输入一个射频延时信号。其余M-R路包络信号，通过将某些 ED的输出信号做延时产生。
参见图2-3，提供了本发明包络模块2的第二种实现方式的第一个实施例。
图2-3所示的包络模块2包括多个包络产生单元ED，分别为ED0、ED1、…、EDN-1，N为预设非线性模型矩阵的列数；
ED0的输入端接收前馈射频信号相连，输出端与作用矩阵模块3相连；
EDn的输入端与射频延时模块1的输出端相连，输出端与作用矩阵模块3相连，n＝1、2、…、N-1；
EDn，用于接收第n+1射频延时信号x(t-τRFn+1)，对第n+1射频延时信号x(t-τRFn+1)进行包络检测得到第n+1包络信号r(t-τBBn+1)，将第n+1包络信号r(t-τBBn+1)输出给作用矩阵模块3，n＝0、1、…、N-1。
在该实施例中，M＝N。此时有N个包络产生单元，分别为ED0、ED1、…、EDN-1，ED0、ED1、…、EDN-1分别以x(t-τRF1)、x(t-τRF2)、…、x(t-τRFN)，作为输入，将之转换为相应的包络信号r(t-τBB1)、r(t-τBB2)、…、r(t-τBBN)，并输出给作用矩阵模块3。在此实施例中，τRF1等于0或者非常接近0，所以可以认为x(t-τRF1)与前馈射频信号x(t)是同一个信号。
参见图2-4，提供了本发明包络模块2的第二种实现方式的第二个实施例。在该实施例中，M＝N+2。此时有N+1个包络产生单元ED，分别为ED0、ED1、…、EDN，ED0、ED1、…、EDN分别以前馈射频信号、第一射频延时信号、第二射频延时信号、…、第N射频延时信号，也就是x(t)、x(t-τRF1)、x(t-τRF2)、…、x(t-τRFN)，作为输入，将之转换为相应的第一包络延时信号、第二包络延时信号、…、第N+1包络延时信号，也就是r(t)、r(t-τBB1)、r(t-τBB2)、…、r(t-τBBN)，并将r(t-τBBN)延时得到r(t-τBBN+1)，最后将r(t)、r(t-τBB1)、r(t-τBB2)、…、r(t-τBBN+1)，这N+2个包络信号输出给作用矩阵模块3。此处τBBn表示包络延时，但是数值上与射频延时τRFn相同，n＝1,2,...,N+1。
在第二个实施例中，包络模块2包括多个包络产生单元ED和BBD，多个ED分别为ED0、ED1、…、EDN，N为预设非线性模型矩阵的列数；
ED0的输入端接收所述前馈射频信号，输出端与作用矩阵模块3相连；
EDn的输入端与射频延时模块1的输出端相连，输出端与作用矩阵模块3相连，n＝1、2、…、N；
BBD的输入端与EDN的输出端相连，输出端与作用矩阵模块3相连；
ED0，用于接收前馈射频信号x(t)，对前馈射频延时信号x(t)进行包络检测 得到第1包络信号r(t-τBB1)，将第1包络信号r(t-τBB1)输出给作用矩阵模块3；
EDn，用于接收第n射频延时信号x(t-τRFn)，对第n射频延时信号x(t-τRFn)进行包络检测得到第n+1包络信号r(t-τBBn+1)，将第n+1包络信号r(t-τBBn+1)输出给作用矩阵模块3，n＝1、2、…、N-1；
EDN，用于接收第N射频延时信号x(t-τRFN)，对第N射频延时信号x(t-τRFN)进行包络检测得到第N+1包络信号r(t-τBBN+1)，将第N+1包络信号r(t-τBBN+1)输出给作用矩阵模块3和BBD；
BBD，用于接收第N+1包络信号r(t-τBBN+1)，对第N+1包络信号r(t-τBBN+1)进行延时得到第N+2包络信号r(t-τBBN+2)，将第N+2包络信号r(t-τBBN+2)输出给作用矩阵模块3。
以下叙述的BSL的结构和工作过程以BSLn为例，n为1～N中的某个数。
参见图2-5，BSL包括同相BLUT 325，正交BLUT 326和AVM327。
BSL的射频信号输入端与AVM输入端相连。BSL的包络信号输入端与同相BLUT和正交BLUT的包络输入端相连。同相BLUT和正交BLUT的包络输入端包含一个或多个包络信号。
同相BLUT的系数输入端和正交BLUT的系数输入端与BSL模块的系数输入端相连。同相BLUT的系数输入端的系数为同相BLUT系数。正交BLUT的系数输入端的系数为正交BLUT系数。BSL模块的系数输入端的系数为BSL系数。BSL系数由同相BLUT系数和正交BLUT系数这两部分系数所组成。
每个BSL的BSL系数都是来自APD训练模块C输出给作用矩阵模块的预失真系数。所以可以认为，同相BLUT和正交BLUT分别从APD训练模块C接收同相BLUT和正交BLUT系数。同相BLUT系数和正交BLUT系数都包括线性系数和非线性系数。同相BLUT和正交BLUT的输出端分别与AVM的同相调制信号输入端和正交调制信号输入端相连。AVM单元的输出端就是BSL模块的输出端。
同相BLUT 325根据线性预失真系数hn,i、非线性预失真系数cm,n,1,i～cm,n,K,i和选择的至少一路包络信号获取同相BLUT输出信号wn,i(t)，将同相BLUT输出信号wn,i(t)输出给AVM的同相调制信号输入端；
正交BLUT 326根据线性预失真系数hn,q、非线性预失真系数cm,n,1,q～cm,n,K,q和选择的至少一路包络信号获取正交BLUT输出信号wn,q(t)，将正交BLUT输出信号wn,q(t)输出给AVM的正交调制信号输入端；
AVM在同相BLUT输出信号wn,i(t)和正交BLUT输出信号wn,q(t)的作用下，对输入的射频延时信号x(t-τRFn)做处理，得到输出射频信号vn(t)。这个处理可以用公式
Figure PCTCN2014091111-appb-000010
来表示。
Figure PCTCN2014091111-appb-000011
表示x(t-τRFn)的Hilbert变换，即-90度移相后的信号。详细过程描述请见AVM叙述部分。
其中，两个BLUT的结构相同，即同相BLUT 325的结构与正交BLUT 326的内部结构完和工作过程完全相同，输入的包络信号也相同，只是输入系数不同。当然，由于输入系数不同，会导致输出信号不同，即wn,i(t)和wn,q(t)不同。
同相BLUT325的包络输入端和正交BLUT326的包络输入端与包络模块2相连。同相BLUT325的系数输入端和正交BLUT326的系数输入端与BSL模块的系数输入端相连。所述同相BLUT的系数输入端的系数为同相BLUT系数。所述正交BLUT的系数输入端的系数为正交BLUT系数。所述BSL模块的系数输入端的系数为BSL系数。所述BSL系数由所述同相BLUT系数和所述正交BLUT系数这两部分系数所组成。所述同相BLUT的输出端和所述正交BLUT的输出端分别与所述AVM的同相调制信号输入端和正交调制信号输入端相连，所述AVM的第一输入端与所述射频延时模块相连，所述AVM的输出端与所述预失真信号加法器相连；
所述同相BLUT和所述正交BLUT输入的包络输入端包含至少一个延时的包络信号。包含哪些包络信号由非线性模型矩阵A所确定。相应地，所述同相BLUT系数和所述正交BLUT系数所包含的非线性预失真系数也由非线性模型矩阵A所确定；
所述同相BLUT系数和所述正交BLUT系数是否包含线性预失真系数由线性模型向量L所确定；所述同相BLUT接收APD训练模块输入的线性预失真系数hn,i、非线性预失真系数cm,n,1,i～cm,n,K,i以及选择至少一路包络信号，根据所述线性预失真系数hn,i、非线性预失真系数cm,n,1,i～cm,n,K,i和所述选择的至少一路包络信号获取同相BLUT输出信号wn,i(t)，将所述同相BLUT输出信号wn,i(t)输出给所述AVM的同相调制信号输入端；
所述BSLn中，系数下标中的i表示该系数所作用的射频信号为第n射频延时信号x(t-τRFn)，系数下标中的q表示该系数所作用的射频信号为第n射频延时信号的Hilbert变换
Figure PCTCN2014091111-appb-000012
例如，所述hn,i所作用的射频信号为第n射频延时信号x(t-τRFn)，hn,q所作用的射频信号为第n射频延时信号的Hilbert变换x
Figure PCTCN2014091111-appb-000013
所述
Figure PCTCN2014091111-appb-000014
是在所述AVM中生成的。
所述BSLn中，系数下标中的m表示该系数所作用的包络信号为第m包络延时信号r(t-τBBm)。例如，所述cm,n,1,i～cm,n,K,i所作用的包络信号为第m包络延时信号r(t-τBBm)。m＝1,2,...,M。
所述正交BLUT接收APD训练模块输入的线性预失真系数hn,q、非线性预失真系数cm,n,1,q～cm,n,K,q以及选择至少一路包络信号，根据所述线性预失真系数hn,q、非线性预失真系数cm,n,1,q～cm,n,K,q和所述选择的至少一路包络信号获取正交BLUT输出信号wn,q(t)，将所述正交BLUT输出信号wn,q(t)输出给所述AVM的正交调制信号输入端；
所述AVM接收所述同相BLUT输出信号wn,i(t)、所述正交BLUT输出信号wn,q(t)和所述射频延时模块输出的射频延时信号x(t-τRFn)，根据所述同相BLUT输出信号wn,i(t)和所述正交BLUT输出信号wn,q(t)对所述射频延时信号x(t-τRFn)做处理，得到输出射频信号vn(t)，也就是第n抽头信号，n＝1、2、…、N。
以下以同相BLUT为例，对其内部框图做进一步说明。假设下述同相BLUT325在BSLn中。参见图2-7a。
由于BLUT位于BSLn中，如果线性模型向量L的第n元Ln＝1，同相BLUT325输入的BLUT系数中就包括线性预失真系数hn,i，如果线性模型向量L的第n元Ln＝0，同相BLUT 325输入的BLUT系数中就不包括线性预失真系数hn,i。
同相BLUT 325还包括：至少一个LUT(Look Up Table，查找表)和BLUT加法器3211，该至少一个LUT包括LUTm,n。LUTm,n这个LUT的下标m,n中的m，表示其输入的包络信号为第m包络信号r(t-τBBm)，m取1、2、…、M中某个特定值。LUTm,n这个LUT的下标m,n中的n，表示其输入的射频信号为第n延时射频信号x(t-τRFn)，n取1、2、…、N某个特定值。
其中，当Am,n＝1时，表示BLUT包括LUTm,n，而且其输入的BLUT系数中包括非线性预失真系数cm,n,1,i～cm,n,K,i。当Am,n＝0时，表示同相BLUT不包括LUTm,n，而且其输入的BLUT系数中不包括非线性预失真系数cm,n,1,i～cm,n,K,i。m＝1、2、…、M，M为预设整数值。
如果A的同一列(对应某个特定的n的不同的m)中有S个元Am,n＝1，则同相BLUT 325总的非线性预失真系数为S*K个实数，S不超过M。K为基函数个数。这里假设所有S个列元所使用的基函数个数相同，都是K。原则上，S个列元可以使用不同的基函数个数，也不难计算出同相BLUT 325总的非线 性预失真系数的个数，但此时总的非线性预失真系数就不一定为S*K。
LUTm,n的第一输入端与包络模块2相连，第二输入端与APD训练模块C相连，输出端与BLUT加法器3211相连。BLUT加法器3211还与APD训练模块C相连。m＝1,2,...,M。
LUTm,n接收包络模块2输出的第m包络信号r(t-τBBm)以及APD训练模块C输出的非线性预失真系数cm,n,1,i～cm,n,K,i，根据非线性预失真系数cm,n,1,i～cm,n,K,i获取第m包络信号r(t-τBBm)对应的LUT信号ρm,n,i(t)，将该LUT信号ρm,n,i(t)输出给BLUT加法器3211。m＝1,2,...,M。
BLUT加法器3211接收每个LUT输出的LUT信号和APD训练模块C输出的线性预失真系数hn,i，将各路LUT信号ρm,n,i(t)和线性预失真系数hn,i相加得到BLUT输出信号，即同相调制信号wn,i(t)，
Figure PCTCN2014091111-appb-000015
将wn,i(t)输出到AVM 327的同相调制信号输入端。
同相BLUT 325的结构及工作过程与正交BLUT 326的内部结构及工作过程完全相同，输入的包络信号也相同，所不同的是，APD训练模块C输出给同相BLUT的线性预失真系数为hn,i，非线性预失真系数为cm,n,1,i～cm,n,K,i，输出给正交BLUT的线性预失真系数为hn,q，非线性预失真系数为cm,n,1,q～cm,n,K,q。m＝1,2,...,M。同相BLUT输出信号为
Figure PCTCN2014091111-appb-000016
其中
Figure PCTCN2014091111-appb-000017
正交BLUT输出信号为
Figure PCTCN2014091111-appb-000018
其中
Figure PCTCN2014091111-appb-000019
参见图2-8a，以同相BLUT 325中的一个LUT单元LUTm,n为例说明LUT单元的构成与其工作过程。并假设基函数使用偶次多项式。
LUTm,n这个LUT包括LUT加法器331、多个BFG和多个乘法器，该多个BFG分别为BFG_1、BFG_2、…、BFG_K，该多个乘法器分别为乘法器M1、乘法器M2、…、乘法器MK，K为预设整数值。BFG为Base Function Generator，即基函数产生器的缩写。
LUTm,n这个LUT的非线性预失真系数为cm,n,1,i～cm,n,K,i，所以同相BLUT 325中的LUTm,n的非线性预失真系数为K个实数。
BFG_k的输入端与包络模块2相连，BFG_k的输出端与乘法器Mk的输入端相连，乘法器Mk的输出端与LUT加法器331相连，k＝1、2、…、K。
优选的，BFG_k的输入端与包络模块2包括的BBDm-1的输出端相连。
BFG_k，用于接收包络模块2输出的第m包络信号r(t-τBBm)，根据第m包络信号r(t-τBBm)，产生基函数信号sk(r(t-τBBm))并输出给其对应的乘法器Mk。由于假设基函数为偶次多项式，所以BFG_k产生的基函数sk(r(t-τBBm))实际是r2k(t-τBBm))，k＝1,2,...,K。
乘法器Mk，用于接收基函数信号sk(r(t-τBBm))和APD训练模块C输出的非线性预失真系数cm,n,k,i，对基函数信号sk(r(t-τBBm))和非线性预失真系数cm,n,k,i相乘得到基贡献信号cm,n,k,isk(r(t-τBBm))，将基贡献信号cm,n,k,isk(r(t-τBBm))输出给LUT加法器331。由于假设基函数为偶次多项式，所以输出给LUT加法器331的基贡献信号实际为cm,n,k,ir2k(t-τBBm)，k＝1,2,...,K。
LUT加法器331，用于接收乘法器Mk输出的基贡献信号cm,n,k,isk(r(t-τBBm))，对接收的每个基贡献信号相加得到LUT输出信号ρm,n,i(t)，
Figure PCTCN2014091111-appb-000020
由于假设基函数为偶次多项式，所以同相LUT325中的LUTm,n这个LUT的输出信号实际为
Figure PCTCN2014091111-appb-000021
参见图2-8b，给出了正交BLUT 326中的LUTm,n这个LUT单元内部框图。其工作原理与前述2-8a中的同相BLUT 325中的LUTm,n这个LUT单元完全相同，只是输入系数不同。2-8a中的输入系数为cm,n,1,i～cm,n,K,i，2-8b中的输入系数为cm,n,1,q～cm,n,K,q，k＝1,2,...,K。正交LUT326中的LUTm,n这个LUT的输出信号为ρm,n,q(t)，
Figure PCTCN2014091111-appb-000022
由于假设基函数为偶次多项式，所以正交LUT326中的LUTm,n这个LUT的输出信号实际为
Figure PCTCN2014091111-appb-000023
同相BLUT 325中的LUT的结构及工作过程与正交BLUT 326的LUT的内部结构及工作过程完全相同，所不同的是，APD训练模块C输出给同相BLUT的非线性预失真系数为cm,n,1,i～cm,n,K,i，输出给正交BLUT的非线性预失真系数为cm,n,1,q～cm,n,K,q。m取1、2、…、M中某个值。
参见图2-7b，正交BLUT 326根据线性预失真系数hn,q、非线性预失真系数cm,n,1,q～cm,n,K,q和选择的至少一路包络信号获取正交BLUT输出信号wn,q(t)，将正交BLUT输出信号wn,q(t)输出给AVM的正交调制信号输入端。
参见图2-6，AVM包括QPS(Quadrature Phase Splitter，正交分路器)3271，同相乘法器3272，正交乘法器3273，减法器3274。以下叙述假设AVM在BSLn中，n为1～N中的某个数。
QPS 3271，用于接收射频延时模块1发送的第n射频延时信号x(t-τRFn)，将第n射频延时信号x(t-τRFn)分为相位差为90度的0度路的射频延时信号x(t-τRFn)和-90度路的射频延时信号
Figure PCTCN2014091111-appb-000024
将0度路的射频延时信号x(t-τRFn)输出给同相乘法器3272以及将-90度路的射频延时信号
Figure PCTCN2014091111-appb-000025
输出给正交乘法器3273。
这里说QPS输出信号为0度和-90度，是为了方便做原理说明。关键是要QPS输出的两路射频信号间的相位为90度。至于实际是45和-45度，或者20度和-70度，或者-16度和-106度，或者133度和43度，等，都是可以的，都不影响QPS的功能和性能。
同相乘法器3272，用于接收同相BLUT输出信号wn,i(t)和0度路的射频延时信号x(t-τRFn)，将同相BLUT输出信号wn,i(t)和0度路的射频延时信号x(t-τRFn)相乘，得到同相已调射频信号wn,i(t)x(t-τRFn)，将同相已调射频信号输出给减法器3274。
正交乘法器3273，用于接收正交BLUT输出信号wn,q(t)和-90度路的射频延时信号
Figure PCTCN2014091111-appb-000026
将正交BLUT输出信号wn,q(t)和-90度路的射频延时信号
Figure PCTCN2014091111-appb-000027
相乘，得到正交已调射频信号
Figure PCTCN2014091111-appb-000028
将正交已调射频信号输出给减法器3274。
AVM输入的同相调制信号和正交调制信号都是基带信号，而且AVM输入的基带信号和射频信号都是模拟信号，这就是AVM被称为Analog Vector Modulator，即模拟矢量调制器的原因。同相乘法器3272和正交乘法器3273完成基带信号与射频信号的相乘。AVM的输出为射频信号。
减法器3274，用于将同相已调射频信号wn，i(t)x(t-τRFn)减去正交已调射频信号
Figure PCTCN2014091111-appb-000029
得到AVM输出的射频信号vn(t)，就是说，BSLn输出的第n抽头信号
Figure PCTCN2014091111-appb-000030
AVM输出射频信号vn(t)也就是BSLn输出射频信号，也就是预失真信号加法器31接收的第n抽头信号。
所述QPS的输出的0度路信号为x(t-τRFn)，只是为了表述方便，并不表示所述QPS输出的0度路信号与QPS输入射频信号x(t-τRFn)相同。QPS的关键技术特征是输出的0度路的射频延时信号和-90度路的射频延时信号之间成90 度的相差关系，并不关心二者之一是否与输入射频信号相同。
所述LUT包括LUT加法器、参考电压产生模块、多个基函数产生单元BFG和多个乘法器，所述多个BFG中的每个BFG对应一个乘法器；
所述每个BFG的第一输入端与所述包络模块相连、第二输入端与所述参考电压产生模块相连，所述每个BFG的输出端分别与所述每个BFG对应的乘法器的第一输入端相连；
所述多个乘法器中的每个乘法器的第二输入端与所述APD训练模块相连，输出端都与所述LUT加法器相连；
所述BFG，用于接收所述包络模块输出的包络信号r(t-τBBm)和所述参考电压产生模块输入的参考电压，根据所述包络信号r(t-τBBm)和所述参考电压产生基函数信号并输出给其对应的乘法器，m＝1,2,...,M；
所述乘法器，用于接收所述基函数信号和所述APD训练模块输出的第一预失真系数，根据所述基信号和所述第一预失真系数获取基贡献信号，将所述基贡献信号输出给所述BLUT加法器；
所述LUT加法器，用于接收所述每个乘法器输出的基贡献信号，对接收的每路基贡献信号相加得到LUT信号。
所述LUT包括LUT加法器、多个基函数产生单元BFG和多个乘法器，所述多个BFG中的每个BFG对应一个乘法器；
所述每个BFG的输入端与所述包络模块相连，输出端分别与所述每个BFG对应的乘法器的第一输入端相连；所述多个乘法器中的每个乘法器的第二输入端与所述APD训练模块相连，输出端都与所述LUT加法器相连；
所述BFG，用于接收所述包络模块输出的包络信号r(t-τBBm)，根据所述包络信号r(t-τBBm)产生基函数信号并输出给其对应的乘法器，m＝1,2,...,M；
所述乘法器，用于接收所述基函数信号和所述APD训练模块输出的第一预失真系数，根据所述基信号和所述第一预失真系数获取基贡献信号，将所述基贡献信号输出给所述BLUT加法器；
所述LUT加法器，用于接收所述每个乘法器输出的基贡献信号，对接收的每路基贡献信号相加得到LUT信号。
本发明的第一类APD模型，即矩阵模型，通过射频延时模块对前馈射频信号进行延时得到多路不同延时的射频延时信号，并将每路射频延时信号输出给作用矩阵模块，使作用矩阵模块根据每路不同延时的射频延时信号产生预失 真信号。通过配置合适的系数，使矩阵模型的的APD核心模块产生非线性记忆预失真特性，如此当PA具有与APD核心模块的预失真特性相反的失真特性时，就可以有效抵消PA产生的失真，让PA输出信号与APD核心模块的输入信号相同。
在本发明实例中，通过射频延时模块对前馈射频信号进行延时得到多路不同延时的射频延时信号，并将每路射频延时信号输入给作用矩阵模块，使作用矩阵模块根据每路不同延时的射频延时信号产生预失真信号，如此当PA具有与APD核心模块不对应的失真特性时，可以消除对作用矩阵模块的影响，从而有效抵消PA产生的失真。
本发明第三部分：本发明第二类APD模型，即级联模型。
本发明系统框图中的APD核心模块B的第二类APD模型为级联模型，参见图3-1，APD核心模块B的级联模型的第一个实施例包括:
线性滤波模块4和ZMNL模块5，线性滤波模块4的输出端与ZMNL模块的输入端相连。ZMNL为Zero Memory Nonlinear，即零记忆非线性的缩写。
线性滤波模块4，用于接收前馈射频信号、根据线性滤波系数对该前馈射频信号进行线性滤波，将线性滤波后的射频信号输出给ZMNL模块5。线性滤波后的射频信号称为线性预调理信号。
ZMNL模块5，用于接收线性滤波模块4输出的线性预调理信号，根据ZMNL系数对该线性预调理信号进行非线性处理以产生预失真信号。
其中，线性滤波系数和ZMNL系数是APD训练模块C输出给APD核心模块B的，前馈射频信号是模拟预失真器系统的输入端输出给APD核心模块B的。
优选的，线性滤波模块4与ZMNL模块5的内部框图参见图3-2。
其中，线性滤波模块4包括：P-1个射频延时单元RFD、P个DVM(Digital Vector Modulator，数字矢量调制器单元)，以及线性加法器，P-1个射频延时单元RFD分别为RFDin1、RFDin2、…、RFDinP-1，P个数字矢量调制器单元DVM分别为DVMin1、DVMin2、…、DVMinP，P为预设整数值。RFDin1、RFDin2、…、RFDinP-1依次串联。前馈射频信号除了送到RFDin1的输入端外，也送到DVM1的输入端，RFDin2、…、RFDinP-1的输出端分别与DVMin2、DVMin3、…、DVMinP的输入端相连。DVMin1、DVMin2、…、DVMinP的输出端都与线性加法器41 的输入端相连。
RFDin1，用于接收前馈射频信号x(t)，对前馈射频信号x(t)进行延时得到第1射频延时信号x(t-τRFx1)，将第1射频延时信号x(t-τRFx1)输出给RFDin2和DVMin2，其中，τRFx1为RFDin1产生的延时。
RFDinp，用于接收RFDinp-1输出的第p-1射频延时信号x(t-τRFxp-1)，对第p-1射频延时信号x(t-τRFxp-1)进行延时得到第p射频延时信号x(t-τRFxp)，将第p射频延时信号x(t-τRFxp)输出给RFDinp+1和DVMinp+1，其中，τRFxp为RFDin1、RFDin2、…、RFDinp共同产生的延时，p＝2,3,...,P-2。
RFDinP-1，用于接收RFDinP-2输出的第P-2射频延时信号x(t-τRFxP-2)，对第P-2射频延时信号x(t-τRFxP-2)进行延时得到第P-1射频延时信号x(t-τRFxP-1)，将第P-1射频延时信号x(t-τRFxP-1)输出给DVMinP，其中，τRFxP-1为RFDin1、RFDin2、…、RFDinP-1共同产生的延时。
APD训练模块C为DVMin1、DVMin2、…、DVMinP分别产生对应的预失真系数，DVMin1、DVMin2、…、DVMinP对应的预失真系数分别为cFIRin,1、cFIRin,2、…、cFIRin,P。cFIRin,p为复数，cFIRin,p＝cFIRin,p,i+jcFIRin,p,q，cFIR,p,i和cFIR,p,q为实数。
DVMin1，用于接收前馈射频延时信号x(t)和外部输入的预失真系数cFIRin,1，根据该预失真系数cFIRin,1，对前馈射频延时信号x(t)进行幅度和相位变换得到输出信号u1(t)，并将输出信号u1(t)送至线性滤波加法器41。
DVMinp，用于接收第p-1射频延时信号x(t-τRFxp-1)和外部输入的预失真系数cFIRin,p，根据该预失真系数cFIRin,p，对第p-1射频延时信号x(t-τRFxp-1)进行幅度和相位变换得到输出信号up(t)，并将输出信号up(t)送至线性滤波加法器41。p＝2,3,...,P。
DVMin1～DVMinP1对输入信号的具体的处理可以用公式
Figure PCTCN2014091111-appb-000031
来表示。
Figure PCTCN2014091111-appb-000032
表示x(t-τRFxp-1)的Hilbert变换，即-90度移相后的信号。p＝1,2,...,P。详细过程描述请见DVM叙述部分。
所述线性加法器，用于接收所述DVMin1、DVMin2、…、DVMinP的输出信号u1(t)、u2(t)、…、uP(t)，对每种输出信号进行累加得到线性预调理信号。
Figure PCTCN2014091111-appb-000033
Figure PCTCN2014091111-appb-000034
参见图3-3，所示的DVM结构，以下DVM的框图与工作过程的叙述p＝1适用于所有DVMin1、DVMin2、…、DVMinP。DVM包括QPS 421，同相乘法器422、正交乘法器423和减法器424。
QPS 421的内部框图与连接关系与前述QPS 3271相同。不再赘述。
QPS 421的第一输出端与同相乘法器422的输入端相连，第二输出端与正交乘法器423的输入端相连。同相乘法器422的输出端与减法器424的第一输入端相连，正交乘法器423的输出端与减法器424的第二输入端相连，减法器424的输出端与线性滤波加法器41相连。
DVM包括的QPS 421，用于接收第p射频延时信号x(t-τRFxp)，将第p射频延时信号x(t-τRFxp)分为相位差为90度的0度路的射频信号x(t-τRFxp)和-90度路的射频信号
Figure PCTCN2014091111-appb-000035
分别将0度路的射频信号x(t-τRFxp)和-90度路的射频信号
Figure PCTCN2014091111-appb-000036
输出给同相乘法器422和正交乘法器423。
以下以DVMinp为例说明DVM的工作原理，p为1、2、…、P中某个特定数。
APD训练模块C产生并配置给DVMinp的线性滤波系数为cFIRin,p＝cFIRin,p,i+jcFIRin,p,q，cFIRin,p,i和cFIRin,p,q为实数。cFIRin,p,i和cFIRin,p,q分别被称为同相系数与正交系数。所以，也可以认为APD训练模块C实际配置给DVMinp的线性滤波系数为cFIRin,p,i和cFIRin,p,q两个实数。
DVM输入的同相系数cFIRin,p,i和正交系数cFIRin,p,q都是数字量，而DVM输入的射频信号为模拟量，这就是DVM被称为Digital Vector Modulator，即数字矢量调制器的原因。同相乘法器422和正交乘法器423完成数字量与射频信号的相乘。DVM的输出为射频信号。
同相乘法器422，用于接收0度路的射频信号x(t-τRFxp-1)和同相系数cFIRin,p,i，对0度路的射频信号x(t-τRFxp-1)和同相系数cFIRin,p,i相乘得到同相乘积信号cFIRin,p,ix(t-τRFxp-1)，将同相乘积信号cFIRin,p,ix(t-τRFxp-1)输出至减法器424。
正交乘法器423，用于接收-90度路的射频信号
Figure PCTCN2014091111-appb-000037
和正交系数cFIRin,p,q，对-90度路的射频信号
Figure PCTCN2014091111-appb-000038
和正交系数cFIRin,p,q相乘得到正交乘积信号
Figure PCTCN2014091111-appb-000039
将正交乘积信号
Figure PCTCN2014091111-appb-000040
输出至减法器n4。
减法器424，用于将同相乘积信号cFIRin,p,ix(t-τRFxp-1)减去正交乘积信号
Figure PCTCN2014091111-appb-000041
得到第p抽头信号up(t)，就是说，DVM单元输出的DVM射频信号
Figure PCTCN2014091111-appb-000042
P个DVM单元，即DVMin1、DVMin2、…、DVMinP的输出信号，即u1(t)、u2(t)、…、u2(t)在线性滤波加法器41中相加，得到线性滤波模块的输出线性预调理信号v(t)，
Figure PCTCN2014091111-appb-000043
线性预调 理信号就是线性滤波模块输出的射频信号，也就是ZMNL模块输入的射频信号。
参见图3-2，ZMNL模块5包括：
包络检测单元ED和信号查找表单元SL。ZMNL模块输入端和ED输入端与SL的射频输入端x相连。ED输出端与SL的射频输入端y相连。SL的输出端就是ZMNL的输出端。
ED的内部框图与连接关系的叙述如前。不再赘述。ED用于对线性滤波器输出的线性预调理信号v(t)进行包络检测产生包络信号，将包络信号输出给SL。假设v(t)的包络为rv(t)，则ED输出信号为rv(t)。
根据设计，ED也可能输出线性预调理信号v(t)的包络的平方，即ED输出信号为rv 2(t)。
下面的都是基于ED输出信号为rv(t)来叙述的。实际上，ED输出信号为rv 2(t)也是可以的，只是叙述方式要做相应的修改，就不再赘述了。
SL，用于接收线性滤波器输出的线性预调理信号v(t)、ED输出的包络信号和外部输入的预失真系数cSL,1～cSL,K，cSL,1～cSL,K为K个复数，cSL,k＝cSL,k,i+jcSL,k,q，cSL,k,i和cSL,k,q都是实数。根据该预失真系数和该包络信号，对该线性预调理信号v(t)进行幅度和相位变换得到预失真信号z(t)。此处，K表示SL所用的基函数的个数，k＝1,2,...,K。
参见图3-4，SL模块5包括：
同相LUT 521，正交LUT 522，AVM单元。SL的射频信号输入端x与AVM输入端相连。SL的包络信号输入端y与同相LUT和正交LUT的包络输入端相连。同相LUT 521和正交LUT 522还从APD训练模块C接收ZMNL系数。同相LUT 521和正交LUT 522的输出端分别与AVM的同相调制信号输入端和正交调制信号输入端相连。AVM单元的输出端就是SL模块的输出端。
APD训练模块C产生并配置给SL的ZMNL系数为cSL,k＝cSL,k,i+jcSL,k,q，cSL,k,i和cSL,k,q为实数。k＝1,2,...,K，所以，也可以认为APD训练模块C实际配置给SL的ZMNL系数为2K个实数。
同相LUT 521和正交LUT 522的内部框图和工作原理如前所述。AVM 523的内部框图和工作原理与所述AVM 327相同。不再赘述。
同相LUT521接收包络信号rv(t)和同相LUT系数cSL,1,i～cSL,K,i，在同相LUT521内部有K个基函数产生单元，以产生K个基函数sk(rv(t))，k＝1,2,...,K， 由此产生同相调制信号
Figure PCTCN2014091111-appb-000044
将同相调制信号
Figure PCTCN2014091111-appb-000045
输出至AVM523的同相调制信号输入端。
正交LUT522接收包络信号rv(t)和正交LUT系数cSL,1,q～cSL,K,q，在正交LUT521内部有K个基函数产生单元，以产生K个基函数sk(rv(t))，k＝1,2,...,K，由此产生正交调制信号
Figure PCTCN2014091111-appb-000046
将正交调制信号
Figure PCTCN2014091111-appb-000047
输出至AVM523的正交调制信号输入端。
AVM523接收线性滤波模块输出的线性预调理信号v(t)，根据同相调制信号
Figure PCTCN2014091111-appb-000048
和正交调制信号
Figure PCTCN2014091111-appb-000049
对v(t)进行幅度和相位调制得到AVM的输出射频信号
Figure PCTCN2014091111-appb-000050
Figure PCTCN2014091111-appb-000051
表示v(t)的Hilbert变换，即将v(t)移相-90度得到的信号。AVM的输出射频信号z(t)也就是APDcore模块的输出信号，即预失真信号。
进一步地，参见图3-5，APD核心模块B的级联模型的第二个实施例包括:
线性滤波模块6、ZMNL模块7和宽带线性滤波模块8。
线性滤波模块6、ZMNL模块7和宽带线性滤波模块8的内部框图参见图4-6。
线性滤波模块6、ZMNL模块7的工作原理与线性滤波模块4、ZMNL模块5相同，不再赘述。
宽带线性滤波模块8与线性滤波模块4形式上是相同的，所不同的是宽带线性滤波模块8中的各个相应的单元的处理带宽比线性滤波模块4更宽。以前馈射频信号x(t)的带宽为100MHz为例，SL输出信号的带宽一般不低于500MHz，相应地，此时线性滤波模块4所述处理的信号带宽为100MHz，宽带线性滤波模块8所述处理的信号带宽不低于500MHz。这要求宽带线性滤波模块8与线性滤波模块4的电路设计有所不同。
具体地，宽带线性滤波模块8中的射频延时单元为RFDout1、RFDout2、…、RFDoutL，共L个射频延时单元RFDout，其中的每个RFDout的带宽都比RFDin大。相应地，有L个数字矢量调制器单元DVMout，其中的每个DVMout的带宽都比DVMin大。宽带线性滤波模块8中的电路连接关系和工作原理与线性滤波模块4类似，不再赘述。
线性滤波模块6在APD训练模块C输入的线性滤波系数的作用下，对前馈射频信号进行处理，输出线性预调理信号。
ZMNL模块7在APD训练模块C输入的ZMNL系数的作用下，对线性预调理信号进行处理，输出中间预失真信号。
宽带线性滤波模块8在APD训练模块C输入的宽带线性滤波系数的作用下，对从ZMNL模块7输入的中间预失真信号进行处理，输出预失真信号。
进一步地，参见图3-7，APD核心模块B的级联模型的第三个实施例包括:
线性滤波模块9、SBSL(Single Block Signal LUT，单块信号查找表)模块10和宽带线性滤波模块11。
线性滤波模块9、SBSL模块10和宽带线性滤波模块11的内部框图参见图4-6。
线性滤波模块9、宽带线性滤波模块11的工作原理与线性滤波模块4、宽带线性滤波模块8相同，不再赘述。
SBSL模块10的SBSL是Single Block Signal LUT，即单BSL的缩写。SBSL模块10内部框图见图3-8，可以看到SBSL模块10实际上是只包含单个BSL的作用矩阵模块的特例。其工作原理可以参见作用矩阵模块，不再赘述。
线性滤波模块9在APD训练模块C输入的线性滤波系数的作用下，对前馈射频信号进行处理，输出线性预调理信号。
SBSL模块10在APD训练模块C输入的SBSL系数的作用下，对线性预调理信号进行处理，输出中间预失真信号。
宽带线性滤波模块11在APD训练模块C输入的宽带线性滤波系数的作用下，对从SBSL模块10输入的中间预失真信号进行处理，输出预失真信号。
本发明的第二类APD模型，即级联模型，通过线性滤波模块、ZMNL模块的级联，或者线性滤波模块、ZMNL模块、宽带线性滤波模块的级联，或者线性滤波模块、SBSL模块、宽带线性滤波模块的级联，通过配置合适的系数，使级联模型的APD核心模块产生非线性记忆预失真特性，如此当PA具有与APD核心模块的预失真特性相反的失真特性时，就可以有效抵消PA产生的失真，让PA输出信号与APD核心模块的输入信号相同。
本发明第四部分：本发明基函数，即斜坡基函数。
首先要说明的是，本发明基函数，即斜坡基函数，是独立于前述本发明的 APD模型的。包括前述的第一种APD模型，即矩阵模型，以及前述的第二种APD模型，即级联模型。就是说，斜坡基函数，不但可以用在本发明的第一种APD模型以及第二种APD模型中，也可以用在现有技术的APD模型中，或者将来被发明的其它APD模型中。
参见图4-1a，斜坡基函数与多项式基函数的差异，在于BLUT中的某个LUT的内部实现。还是假设这个LUT同相BLUT 325中，而且BLUT 325在BSLn中，即，以同相BLUT 325中的一个LUT单元LUTm,n为例说明斜坡基函数的构成与其工作过程。
LUTm,n这个LUT包括LUT加法器331、参考电压产生模块332、多个BFG和多个乘法器，该多个BFG分别为BFG_1、BFG_2、…、BFG_K，该多个乘法器分别为乘法器M1、乘法器M2、…、乘法器MK，K为预设整数值。BFG为Base Function Generator，即基函数产生器，的缩写。
BFG_k的第一输入端与包络模块2相连、第二输入端与参考电压产生模块332相连，BFG_k的输出端与乘法器Mk的输入端相连，乘法器Mk的输出端与LUT加法器331相连，k＝1、2、…、K。
优选的，BFG_k的第一输入端与包络模块2包括的BBDm-1的输出端相连。参考电压产生模块332，用于为BFG_k产生对应的参考电压Vrefk，将参考电压Vrefk输出给BFG_k。
BFG_k，用于接收包络模块2输出的第m包络信号r(t-τBBm)和参考电压产生模块332输入的参考电压Vrefk，根据第m包络信号r(t-τBBm)和参考电压Vrefk，产生基函数信号sk(r(t-τBBm))并输出给其对应的乘法器Mk。
乘法器Mk，用于接收基函数信号sk(r(t-τBBm))和APD训练模块C输出的线性预失真系数cm,n,k,i，对基函数信号sk(r(t-τBBm))和线性预失真系数cm，n，k，i相乘得到基贡献信号cm,n,k,isk(r(t-τBBm))，将基贡献信号cm,n,k,isk(r(t-τBBm))输出给LUT加法器331。
LUT加法器331，用于接收乘法器Mk输出的基贡献信号cm,n,k,isk(r(t-τBBm))，对接收的每个基贡献信号相加得到LUT信号
Figure PCTCN2014091111-appb-000052
参见图4-2，参考电压产生模块332包括第一放大器Amp1、第三电阻R3、第四电阻R4和多个第五电阻R5，多个第五电阻R5依次串联形成串联电路。
第一放大器Amp1的正极输入端用于接收外部输入的带隙电压，输出端与 第三电阻R3的一端、串联电路的一端和BFG_1的输入端相连，第三电阻R3的另一端与第一放大器Amp1的负极输入端和第四电阻R4的一端相连，第四电阻R4的另一端接地。
串联电路内任意相邻的两第五电阻R5的连接点与一BFG相连，串联电路的另一端接地。
其中，第一放大器Amp1的+输入端接收带隙电压，对该带隙电压进行放大得到参考电压Vref1，将参考电压Vref1输出给串联电路，串联电路内任意相邻的两第五电阻R5的连接点产生参考电压并输出给与该连接点相连的BFG，串联电路内包括的连接点产生的参考电压分别为Vref2、Vref3、…、VrefK。
LS包括如图4-3和如图4-4两种电路结构，LS为Level Shifter，即电平平移器的缩写，具体为：
参见图4-3，LS可以包括第四MOS(Metal Oxid Semiconductor，场效应晶体管)管MOS4和恒流源I，第四MOS管MOS4的漏极与电源相连，源极与恒流源I的第一输入端相连，栅极Vin与包络模块2相连，恒流源I的第二输入端与参考电压产生模块332的输出端相连，输出端接地。
参见图4-4，LS可以包括第六电阻R6、第七电阻R7、第八电阻R8、第九电阻R9、第十电阻R10和第二放大器Amp2。
第六电阻R6的一端与包络模块2相连，另一端与第七电阻R7的一端、第八电阻R8的一端和第二放大器Amp2的正极输入端相连。第七电阻R7的另一端与参考电压产生模块332相连，第八电阻R8的另一端接地。第二放大器Amp2的负极输入端与第九电阻R9的一端和第十电阻R10的一端相连，输出端与第十电阻R10的另一端相连，第九电阻R9的另一端接地。
参见图4-5，本发明提供了一种基函数产生单元BFG包括：
第一MOS管MOS1、第二MOS管MOS2、第三MOS管MOS3、第一电阻R1和第二电阻R2。
第一电阻R1的一端和第二电阻R2的一端都与电源Vcc相连，第一电阻R1的另一端和第二电阻R2的另一端分别与第一MOS管MOS1的漏极和第二MOS管MOS2的漏极相连。
第一MOS管MOS1的栅极与包络模块2相连，源极与第三MOS管MOS3的漏极相连。第二MOS管MOS2的栅极与参考电压产生模块332相连，源极 与第三MOS管MOS1的漏极相连。
第三MOS管MOS3的栅极接固定电压Vy，源极接地。
优选的，第一MOS管MOS1的栅极与包络模块2包括的BBDm-1的输出端相连。其中，BFG产生的基函数信号如下公式所示：
Figure PCTCN2014091111-appb-000053
其中，在上述公式中，f为基函数信号，Vx1为包络模块2输出的包络信号r(t-τBBm)，Vrefk为参考电压产生模块11为BFG_k产生的参考电压。VT＝kT/q。k为Boltzmann常数，k＝1.3806488*10-23JK-1，J为能量单位Joule的缩写。K表示绝对温度。q为电子电量，q＝1.6021892*10-19C，C为电量单位Coulomb的缩写。当T＝300K时，VT＝26mV。α为与电路特性有关的一个常数。f(Vy)是由半导体特性确定的一个固定的函数。当Vy确定之后，f(Vy)就是确定的，V2-V1与Vx1-Vx2就由双曲正切函数所确定。th为双曲正切函数，
Figure PCTCN2014091111-appb-000054
而双曲正切函数的特性正是斜坡基函数曲线。其中，斜坡基函数曲线的平移系通过在Vx1、Vx2上加偏置来实现。斜坡基函数曲线的斜率系通过改变Vy来实现。参数Vy是一个设计值，与电源电压Vy和基函数个数K有关。在一定的Vy和K下，可以通过设计以寻找最合适的Vy。
其中，BFG_k可以产生单端上坡基函数信号、单端下坡基函数信号、差分上坡基函数信号和差分下坡基函数信号。BFG_k的V1输出端输出单端下坡基函数信号，V2输出端输出单端上坡基函数信号，V1输出的信号-V2输出的信号为差分上城基函数信号，V2输出的信号-V1输出的信号为差分下坡函数信号。
参见图4-6，一个LUT可以包括K个BFG，每个BFG的第一MOS管MOS1的栅极与单端包络模块相连，第二MOS管MOS2的栅极与该LUT的参考电压产生模块332相连，每个BFG的V1输出端输出单端下坡基函数信号。例如，K＝15，即存在BFG_1、BFG_2、…、BFG_15，参见图4-7所示的BFG_1、BFG_2、…、 BFG_15分别产生的单端下坡基函数信号。单端包络模块输出单端形式的包络信号，该包络信号为包络模块2输出的某个延时的包络信号，而且是以单端信号的形式输出的。
参见图4-8，一个LUT包括K个BFG，每个BFG的第一MOS管MOS1栅极与差分包络模块相连，第二MOS管MOS2的栅极与该LUT包括的参考电压产生模块332相连，每个BFG的V2输出端输出单端上坡基函数信号。例如，K＝15，即存在BFG_1、BFG_2、…、BFG_15，参见图4-9所示的BFG_1、BFG_2、…、BFG_15分别产生的单端上坡基函数信号。差分包络模块输出差分形式的包络信号，该包络信号为包络模块2输出的某个延时的包络信号，而且是以差分信号的形式输出的。
参见图4-10，该LUT还包括多个LS，分别为LS0、LS1、LS2、…、LSK，以及包括K个BFG。差分包络模块输出差分的包络信号，第m包络信号r(t-τBBm)＝(差分正端信号)-(差分负端信号)。差分包络模块的差分正输出端与LS0的第二输入端相连，差分包络模块的差分负输出端与LSk的第二输入端相连，k＝1、2、…、K。
LS0称为第一LS。第一LS，即LS0，的第一输入端与外部恒压信号Vref0相连，LS0的第二输入端与差分包络模块的差分正输出端相连，LS0的输出端分别与BFG_k的差分正输入端，即第一MOS管的栅极，相连，用于根据该恒压信号Vref0对从差分包络模块输入的包络差分正端信号进行平移，将平移后的包络差分正端信号输出至BFG_k的第一MOS管的栅极，k＝1、2、…、K。
K个LSk(k＝1、2、…、K)称为第二LS。第二LS中的第k个LS即LSk的第一输入端与参考电压产生模块332输出的Vrefk相连，LSk的第二输入端与差分包络模块的差分负输出端相连，LSk的输出端与BFG_k的差分正输入端，即第二MOS管的栅极，相连，用于根据第m包络差分负端信号对参考电压Vrefk进行平移，将平移后的Vrefk输出至BFG_k的第二MOS管的栅极，k＝1、2、…、K。
每个BFG的V1输出端输出的信号减V2输出端输出的信号形成差分下坡函数信号。例如，K＝15，即存在BFG_1、BFG_2、…、BFG_15，参见图4-11所示的BFG_1、BFG_2、…、BFG_15分别产生的差分下坡基函数信号。
参见图4-12，将每个BFG的V2输出端输出的信号减V1输出端输出的信号形成差分上坡函数信号。参见图4-13所示的BFG_1、BFG_2、…、BFG_15分别产生的差分上坡基函数信号。
现有技术，如美国Scintera公司(现已被Maxiam公司兼并)的APD芯片，其APD核心模块就相当于一个SBSL模块，其记忆性失真的校正能力非常有限。
本发明PD核心模块如果用矩阵模型，可以含多个BSL，通过射频延时模块对前馈射频信号进行延时得到多路不同延时的射频延时信号，并将每路射频延时信号输出给作用矩阵模块，使作用矩阵模块根据每路不同延时的射频延时信号产生预失真信号，使APD系统的记忆性失真的校正能力大大提升。
发明PD核心模块如果用级联模型，由于线性滤波模块，以及可能含有的宽带线性滤波模块，使APD系统的记忆性失真的校正能力大大提升。
可见，不管是用本发明PD核心模块用矩阵模型还是级联模型，都会在PA具有较强的记忆性线性失真和记忆性非线性失真时，都会对PA产生的这些失真做有效的校正。
而且现有技术，如美国Scintera公司(现已被Maxiam公司兼并)的APD芯片，其APD基函数使用偶次多项式。偶次多项式的问题是包络信号的PAR(Peak to Average Ratio，峰均比)动态扩展太大。比如，射频信号x(t)的包络信号r(t)的PAR为7dB，则其2次多项式基函数单元输出信号r2(t)的PAR为14dB，4次多项式基函数单元输出信号r4(t)的PAR为28dB，6次多项式基函数单元输出信号r6(t)的PAR为42dB，8次多项式基函数单元输出信号r8(t)的PAR为56dB，10次多项式基函数单元输出信号r10(t)的PAR为70dB。
假设在一定的电源电压下所允许通过的基函数单元输出信号峰值为0dBm，而电路的噪声水平为-70dBm。对于射频信号x(t)的包络信号r(t)，其峰值功率为0dBm，其均值功率＝峰值功率-PAR＝-7dBm，其SNR＝均值功率-电路噪声＝-7-(-70)＝63dB；对于2次多项式基函数单元输出信号r2(t)，其峰值功率为0dBm，其均值功率＝峰值功率-PAR＝-14dBm，其SNR＝均值功率-电路噪声＝-14-(-70)＝56dB；对于4次多项式基函数单元输出信号r4(t)，其峰值功率为0dBm，其均值功率＝峰值功率-PAR＝-28dBm，其SNR＝均值功率-电路噪声＝-28-(-70)＝42dB；对于6次多项式基函数单元输出信号r6(t)，其峰值功率为0dBm，其均值功率＝峰值功率-PAR＝-42dBm，其SNR＝均值功率-电路噪声＝-42-(-70)＝28dB；对于8次多项式基函数单元输出信号r8(t)，其峰值功率为 0dBm，其均值功率＝峰值功率-PAR＝-56dBm，其SNR＝均值功率-电路噪声＝-56-(-70)＝14dB；对于10次多项式基函数单元输出信号r10(t)，其峰值功率为0dBm，其均值功率＝峰值功率-PAR＝-70dBm，其SNR＝均值功率-电路噪声＝-70-(-70)＝0dB。
可见，在一定的电源电压和一定的电路噪声水平下，由于SNR中的S指的是信号的平均功率，所以高次基函数单元输出信号PAR造成了高次基函数SNR的下降，进而导致APD校正性能的下降。
本发明的斜坡基函数，从实现电路可以看出，由于各个基函数的特性之间只是平移的关系，所以各个基函数单元输出信号之间的PAR是基本相等的，在一定的电源电压和一定的电路噪声水平下，不会因为基函数单元输出信号PAR的差异而造成某些基函数SNR的下降，也不会因此导致APD校正性能的下降。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (23)

  1. 一种模拟预失真器APD核心模块，其特征在于，所述APD核心模块包括:
    射频延时模块、包络模块和作用矩阵模块，所述作用矩阵模块分别与所述射频延时模块和所述包络模块相连；
    所述射频延时模块，用于接收前馈射频信号，根据所述前馈射频信号产生多路不同延时的射频延时信号，将每路射频延时信号输出给所述作用矩阵模块；
    所述包络模块，用于接收前馈射频信号，对所述前馈射频信号进行包络检测得到多路不同延时的包络信号，将每路包络信号输出给所述作用矩阵模块；
    所述作用矩阵模块，用于接收所述每路射频延时信号、所述每路包络信号和来自外部的预失真系数，根据所述预失真系数，所述每路射频延时信号和所述每路包络信号产生预失真信号。
  2. 如权利要求1所述的APD核心模块，其特征在于，所述射频延时模块包括多个射频延时单元RFD，分别为RFD0、RFD1、…、RFDN-1，N为预设非线性模型矩阵的列数；
    所述RFD0、RFD1、…、RFDN-1依次串联，且所述RFD0、RFD1、…、RFDN-1中的每个RFD的输出端都与所述作用矩阵模块相连；
    所述RFD0，用于接收前馈射频信号x(t)，对所述前馈射频信号x(t)进行延时得到第1射频延时信号x(t-τRF1)，将所述第1射频延时信号x(t-τRF1)输出给所述作用矩阵模块；
    所述RFDn，用于接收RFDn-1输出的第n射频延时信号x(t-τRFn)，对所述第n射频延时信号x(t-τRFn)进行延时得到第n+1射频延时信号x(t-τRFn+1)，将所述第n+1射频延时信号x(t-τRFn+1)输出给所述所述作用矩阵模块，n＝1、2、…、N-1。
  3. 如权利要求1或2所述的APD核心模块，其特征在于，所述包络模块包括一个包络产生单元ED和多个包络延时单元BBD，所述多个BBD分别为BBD1、BBD2、…、BBDM-1，M为预设非线性模型矩阵的行数；
    所述ED的输出端与所述BBD1的输入端相连，所述BBD1、BBD2、…、BBDM依次串联，且所述BBD1、BBD2、…、BBDM-1中的每个BBD的输出端与所述作 用矩阵模块相连；
    所述ED，用于接收前馈射频信号x(t)，对所述前馈射频信号x(t)进行包络检测得到第1包络信号r(t-τBB1)，将所述第1包络信号r(t-τBB1)输出给所述BBD1和所述作用矩阵模块；
    所述BBD1，用于对所述第1包络信号r(t-τBB1)进行延时得到第2包络信号r(t-τBB2)，将所述第2包络信号r(t-τBB2)输出给所述BBD2和所述作用矩阵模块；
    所述BBDm，用于接收BBDm-1输出的第m包络信号r(t-τBBm)，对所述第m包络信号r(t-τBBm)进行延时得到第m+1包络信号r(t-τBBm+1)，将所述第m+1包络信号r(t-τBBm+1)输出给所述BBDm+1和所述作用矩阵模块，m＝2、3、…、M-2；
    所述BBDM-1，用于接收BBDM-2输出的第M-1包络信号r(t-τBBM-1)，对所述第M-1包络信号r(t-τBBM-1)进行延时处理得到第M包络信号r(t-τBBM)，将所述第M包络信号r(t-τBBM)输出给所述作用矩阵模块。
  4. 如权利要求1所述的APD核心模块，其特征在于，所述包络模块包括多个包络产生单元ED，分别为ED0、ED1、…、EDN-1，N为预设非线性模型矩阵的列数；
    所述ED0的输入端用于接收所述前馈射频信号，输出端与所述作用矩阵模块相连；
    所述EDn的输入端与所述射频延时模块的输出端相连，输出端与所述作用矩阵模块相连，n＝1、2、…、N-1；
    所述EDn，用于接收第n+1射频延时信号x(t-τRFn+1)，对所述第n+1射频延时信号x(t-τRFn+1)进行包络检测得到第n+1包络信号r(t-τBBn+1)，将所述第n+1包络信号r(t-τBBn+1)输出给所述作用矩阵模块，n＝0、1、…、N-1。
  5. 如权利要求1所述的APD核心模块，其特征在于，所述包络模块包括多个包络产生单元ED和BBD，所述多个ED分别为ED0、ED1、…、EDN，N为预设非线性模型矩阵的列数；
    所述ED0的输入端用于接收所述前馈射频信号，输出端与所述作用矩阵模块相连；
    所述EDn的输入端与所述射频延时模块的输出端相连，输出端与所述作用矩阵模块相连，n＝1、2、…、N；
    所述BBD的输入端与所述EDN的输出端相连，输出端与所述作用矩阵模块相连；
    所述ED0，用于接收前馈射频信号x(t)，对所述前馈射频延时信号x(t)进行包络检测得到第1包络信号r(t-τBB1)，将所述第1包络信号r(t-τBB1)输出给所述作用矩阵模块；
    所述EDn，用于接收第n射频延时信号x(t-τRFn)，对所述第n射频延时信号x(t-τRFn)进行包络检测得到第n+1包络信号r(t-τBBn+1)，将所述第n+1包络信号r(t-τBBn+1)输出给所述作用矩阵模块，n＝1、2、…、N-1；
    所述EDN，用于接收第N射频延时信号x(t-τRFN)，对所述第N射频延时信号x(t-τRFN)进行包络检测得到第N+1包络信号r(t-τBBN+1)，将所述第N+1包络信号r(t-τBBN+1)输出给所述作用矩阵模块和所述BBD；
    所述BBD，用于接收所述第N+1包络信号r(t-τBBN+1)，对所述第N+1包络信号r(t-τBBN+1)进行延时得到第N+2包络信号r(t-τBBN+2)，将所述第N+2包络信号r(t-τBBN+2)输出给所述作用矩阵模块。
  6. 如权利要求1所述的APD核心模块，其特征在于，所述作用矩阵模块包括：
    多个块信号查找表BSL和预失真信号加法器，所述多个BSL分别为BSL1、BSL2、…、BSLN，N为预设整数值；
    BSLn分别与所述射频延时模块、所述包络模块、所述预失真信号加法器和APD训练模块相连，n＝1、2、…、N；
    所述BSLn接收所述射频延时模块输出的第n射频延时信号x(t-τRFn)、所述包络模块输出的M路包络信号和所述APD训练模块输出的预失真系数，从所述M路包络信号中选择至少一路包络信号，根据所述选择的至少一路包络信号和所述接收的预失真系数，对所述第n射频延时信号x(t-τRFn)进行幅度和相位变换得到第n抽头信号，将第n抽头信号输出给所述预失真信号加法器；
    所述预失真信号加法器，用于接收每个BSL输出的抽头信号，分别为第1抽头信号、第2抽头信号、…、第N抽头信号，对所述第1抽头信号、第2抽头信号、…、第N抽头信号相加得到预失真信号。
  7. 如权利要求6所述的APD核心模块，其特征在于，所述BSLn包括同相 块查找表BLUT，正交BLUT和模拟矢量调制器AVM；所述同相BLUT的包络输入端和所述正交BLUT的包络输入端与所述包络模块相连，所述同相BLUT的系数输入端和所述正交BLUT的系数输入端与所述BSL模块的系数输入端相连，所述同相BLUT的系数输入端的系数为同相BLUT系数，所述正交BLUT的系数输入端的系数为正交BLUT系数，所述BSL模块的系数输入端的系数为BSL系数，所述BSL系数由所述同相BLUT系数和所述正交BLUT系数这两部分系数所组成，所述同相BLUT的输出端和所述正交BLUT的输出端分别与所述AVM的同相调制信号输入端和正交调制信号输入端相连，所述AVM的第一输入端与所述射频延时模块相连，所述AVM的输出端与所述预失真信号加法器相连；
    所述同相BLUT和所述正交BLUT输入的包络输入端包含至少一个延时的包络信号，包含哪些包络信号由非线性模型矩阵A所确定，相应地，所述同相BLUT系数和所述正交BLUT系数所包含的非线性预失真系数也由非线性模型矩阵A所确定；
    所述同相BLUT系数和所述正交BLUT系数是否包含线性预失真系数由线性模型向量L所确定；所述同相BLUT接收APD训练模块输入的线性预失真系数hn,i、非线性预失真系数cm,n,1,i～cm,n,K,i以及选择至少一路包络信号，根据所述线性预失真系数hn,i、非线性预失真系数cm,n,1,i～cm,n,K,i和所述选择的至少一路包络信号获取同相BLUT输出信号wn,i(t)，将所述同相BLUT输出信号wn,i(t)输出给所述AVM的同相调制信号输入端；
    所述BSLn中，系数下标中的i表示该系数所作用的射频信号为第n射频延时信号x(t-τRFn)，系数下标中的q表示该系数所作用的射频信号为第n射频延时信号的Hilbert变换
    Figure PCTCN2014091111-appb-100001
    所述BSLn中，系数下标中的m表示该系数所作用的包络信号为第m包络延时信号r(t-τBBm)；
    所述正交BLUT接收APD训练模块输入的线性预失真系数hn,q、非线性预失真系数cm,n,1,q～cm,n,K,q以及选择至少一路包络信号，根据所述线性预失真系数hn,q、非线性预失真系数cm,n,1,q～cm,n,K,q和所述选择的至少一路包络信号获取正交BLUT输出信号wn,q(t)，将所述正交BLUT输出信号wn,q(t)输出给所述AVM的正交调制信号输入端；
    所述AVM接收所述同相BLUT输出信号wn,i(t)、所述正交BLUT输出信号 wn,q(t)和所述射频延时模块输出的射频延时信号x(t-τRFn)，根据所述同相BLUT输出信号wn,i(t)和所述正交BLUT输出信号wn,q(t)对所述射频延时信号x(t-τRFn)做处理，得到输出射频信号vn(t)，也就是第n抽头信号，n＝1、2、…、N。
  8. 如权利要求7所述的APD核心模块，其特征在于，所述BSLn所包括的AVM包括正交分路器QPS、同相乘法器、正交乘法器和减法器；
    所述QPS的输入端与所述射频延时模块的输出端相连，第一输出端与所述同相乘法器的第一输入端相连，第二输出端与所述正交乘法器的第一输入端相连；
    所述QPS，用于接收所述射频延时模块发送的第n射频延时信号x(t-τRFn)，将所述第n射频延时信号x(t-τRFn)分为相位差为90度的0度路的射频延时信号x(t-τRFn)和-90度路的射频延时信号
    Figure PCTCN2014091111-appb-100002
    将所述0度路的射频延时信号x(t-τRFn)输出给所述同相乘法器以及将所述-90度路的射频延时信号
    Figure PCTCN2014091111-appb-100003
    输出给所述正交乘法器；
    所述QPS的输出的0度路信号为x(t-τRFn)，只是为了表述方便，并不表示所述QPS输出的0度路信号与QPS输入射频信号x(t-τRFn)相同，QPS的关键技术特征是输出的0度路的射频延时信号和-90度路的射频延时信号之间成90度的相差关系，并不关心二者之一是否与输入射频信号相同；
    所述同相乘法器，用于接收所述同相BLUT输出信号和所述0度路的射频延时信号x(t-τRFn)，将所述同相BLUT输出信号和所述0度路的射频延时信号x(t-τRFn)相乘，得到同相已调射频信号，将所述同相已调射频信号输出给所述减法器；
    所述第二乘法器，用于接收所述正交BLUT输出信号和所述-90度路的射频延时信号
    Figure PCTCN2014091111-appb-100004
    将所述正交BLUT输出信号和所述-90度路的射频延时信号
    Figure PCTCN2014091111-appb-100005
    相乘，得到正交已调射频信号，将所述正交已调射频信号输出给所述减法器；
    所述减法器，用于将所述同相已调射频信号减去所述正交已调射频信号，得到第n抽头信号。
  9. 如权利要求7所述的APD核心模块，其特征在于，所述BSLn所包括的所述BLUT包括：至少一个查找表LUT和BLUT加法器，所述至少一个LUT 包括LUTm,n，m＝1、2、…、M，M为预设整数值；
    其中，预设非线性模型矩阵A，A有M行N列，A的第m行第n列上的元为Am,n，Am,n的取值为0或1，当Am,n＝1时，表示所述BLUT包括LUTm,n，而且其输入的BLUT系数中包括非线性预失真系数cm,n,1,i～cm,n,K,i；当Am,n＝0时，表示所述BLUT不包括LUTm,n，而且其输入的BLUT系数中不包括非线性预失真系数cm,n,1,i～cm,n,K,i，m＝1、2、…、M，M为预设整数值；
    其中，预设线性模型向量L，L有N个元，L的第n个元为Ln，Ln的取值为0或1，当Ln＝1时，则所述BLUT系数包含线性预失真系数hn,i和hn,q，当Ln＝0时，则所述BLUT系数不包含线性预失真系数hn,i和hn,q，n＝1、2、…、N；LUTm,n的第一输入端与所述包络模块相连，第二输入端与APD训练模块相连，输出端与所述BLUT加法器相连，所述BLUT加法器还与所述APD训练模块相连；
    所述LUTm,n接收所述包络模块输出的第m包络信号r(t-τBBm)以及所述APD训练模块输出的非线性预失真系数，根据所述预失真系数获取所述第m包络信号r(t-τBBm)对应的LUT信号，将所述LUT信号输出给所述BLUT加法器，m＝1,2,...,M；
    所述BLUT加法器接收每个LUT输出的LUT信号和所述APD训练模块输出的线性预失真系数，对所述每路LUT信号和所述线性预失真系数相加得到同相调制信号或正交调制信号。
  10. 如权利要求9所述的APD核心模块，其特征在于，所述LUT包括LUT加法器、参考电压产生模块、多个基函数产生单元BFG和多个乘法器，所述多个BFG中的每个BFG对应一个乘法器；
    所述每个BFG的第一输入端与所述包络模块相连、第二输入端与所述参考电压产生模块相连，所述每个BFG的输出端分别与所述每个BFG对应的乘法器的第一输入端相连；
    所述多个乘法器中的每个乘法器的第二输入端与所述APD训练模块相连，输出端都与所述LUT加法器相连；
    所述BFG，用于接收所述包络模块输出的包络信号r(t-τBBm)和所述参考电压产生模块输入的参考电压，根据所述包络信号r(t-τBBm)和所述参考电压产生基函数信号并输出给其对应的乘法器，m＝1,2,...,M；
    所述乘法器，用于接收所述基函数信号和所述APD训练模块输出的第一预 失真系数，根据所述基信号和所述第一预失真系数获取基贡献信号，将所述基贡献信号输出给所述BLUT加法器；
    所述LUT加法器，用于接收所述每个乘法器输出的基贡献信号，对接收的每路基贡献信号相加得到LUT信号。
  11. 如权利要求9所述的APD核心模块，其特征在于，所述LUT包括LUT加法器、多个基函数产生单元BFG和多个乘法器，所述多个BFG中的每个BFG对应一个乘法器；
    所述每个BFG的输入端与所述包络模块相连，输出端分别与所述每个BFG对应的乘法器的第一输入端相连；所述多个乘法器中的每个乘法器的第二输入端与所述APD训练模块相连，输出端都与所述LUT加法器相连；
    所述BFG，用于接收所述包络模块输出的包络信号r(t-τBBm)，根据所述包络信号r(t-τBBm)产生基函数信号并输出给其对应的乘法器，m＝1,2,...,M；
    所述乘法器，用于接收所述基函数信号和所述APD训练模块输出的第一预失真系数，根据所述基信号和所述第一预失真系数获取基贡献信号，将所述基贡献信号输出给所述BLUT加法器；
    所述LUT加法器，用于接收所述每个乘法器输出的基贡献信号，对接收的每路基贡献信号相加得到LUT信号。
  12. 如权利要求9所述的APD核心模块，其特征在于，所述LUT所包括的所述参考电压产生模块包括放大器、第三电阻、第四电阻和多个第五电阻，所述多个第五电阻依次串联形成串联电路；
    所述放大器的输出端与所述第三电阻的一端、所述串联电路的一端和一个BFG相连，所述第三电阻的另一端与所述放大器的负极输入端和所述第四电阻的一端相连，所述第四电阻的另一端接地；
    所述串联电路内任意相邻的两第五电阻的连接点与一BFG相连，所述串联电路的另一端接地。
  13. 如权利要求9所述的APD核心模块，其特征在于，所述LUT所包括包括K个BFG，分别为BFG_1、BFG_2、…、BFG_K，K为预设整数值；
    BFG_k的第一MOS管的栅极与APD核心模块中包括的包络模块相连，第 二MOS管的栅极与所述APD核心模块包括的参考电压产生模块相连，由所述BFG_k的V1输出端输出单端下坡基函数信号，或者，由所述BFG_k的V2输出端输出单端上坡基函数信号，k＝1、2、…、K。
  14. 如权利要求9所述的APD核心模块，其特征在于，所述LUT包括K个BFG和K+1个电平平移器LS，K为预设整数值，所述K个BFG分别为BFG_1、BFG_2、…、BFG_K，所述K+1个LS分别为LS0、LS1、…、LSK；
    LS0的第一输入端与所述差分包络模块输出端的差分正端相连，第二输入端接收外部输入的恒压信号Vref0，输出端分别与BFG_k的差分正输入端相连，用于根据所述恒压信号对所述差分包络模块输出的包络差分正端信号进行平移，将平移后的包络差分正端信号输出给BFG_k的输入端的差分正输入端，k＝1、2、…、K；
    LSk的第一输入端与所述包络模块输出端的差分负端相连，第二输入端与所述参考电压产生模块输出的Vrefk相连，输出端与所述BFG_k的输入端的差分负输入端相连，用于接收所述参考电压产生模块输出的参考电压和包络差分负端信号，根据所述所述参考电压对包络差分负端信号进行平移，将平移后的包络差分负端信号输出给所述BFG_k的输入端的差分负输入端，k＝1、2、…、K；
    所述BFG_k的V1输出端输出的信号减V2输出端输出的信号形成差分下坡函数信号，或者所述BFG_k的V2输出端输出的信号减V1输出端输出的信号形成差分上坡函数信号。
  15. 如权利要求13或14所述的APD核心模块，其特征在于，还包括一个第一LS和多个第二LS，所述多个BFG中的每个BFG对应一个第二LS；
    所述第一LS的第一输入端与所述差分包络模块的差分正输出端相连，输出端分别与多个BFG中的每个BFG的差分正输入端相连；
    所述多个第二LS中的每一个第二LS的第一输入端与所述包络模块的差分负输出端相连，第二输入端与所述参考电压产生模块相连，输出端与其对应的BFG的差分负输入端相连。
  16. 如权利要求13或14所述的APD核心模块，其特征在于，所述K个BFG的每一个BFG包括第一场效应晶体管MOS管、第二MOS管、第三MOS 管、第一电阻和第二电阻；
    所述第一电阻的一端和所述第二电阻的一端都与电源相连，所述第一电阻的另一端与所述第一MOS管的漏极相连，所述第二电阻的另一端与所述第二MOS管的漏极相连；
    所述第一MOS管的基集与外部的包络模块相连，源极与所述第三MOS管的漏极相连。所述第二MOS管的基集与外部的参考电压产生模块相连，源极与所述第三MOS管的漏极相连。所述第三MOS管的源极接地。
  17. 一种模拟预失真器APD核心模块，其特征在于，所述APD核心模块包括：
    线性滤波模块和零记忆非线性ZMNL模块，所述线性滤波模块的输出端与所述ZMNL模块的输入端相连；
    所述线性滤波模块，用于接收前馈射频信号、根据线性滤波系数对所述前馈射频信号进行线性滤波，将线性滤波后的射频信号输出给所述ZMNL模块，所述线性滤波后的射频信号称为线性预调理信号；
    所述ZMNL模块，用于接收所述线性滤波模块输出的线性预调理信号，根据ZMNL系数对所述线性预调理信号进行非线性处理以产生预失真信号。
  18. 如权利要求17所述的APD核心模块，其特征在于，所述线性滤波模块包括：
    P-1个射频延时单元、P个数字矢量调制器单元和线性加法器，其中P-1个射频延时单元分别为RFDin1、RFDin2、…、RFDinP-1，P个数字矢量调制器单元分别为DVMin1、DVMin2、…、DVMinP，P为预设整数值；
    所述RFDin1、RFDin2、…、RFDinP-1依次串联，所述RFDin1、RFDin2、…、RFDinP-1的输出端分别与所述DVMin2、DVMin3、…、DVMinP的输入端相连，所述DVMin1、DVMin2、…、DVMinP的输出出端与所述线性加法器相连；
    所述RFDin1，用于接收前馈射频信号x(t)，对所述前馈射频信号x(t)进行延时得到第1射频延时信号x(t-τRF1)，将所述第1射频延时信号x(t-τRF1)输出给所述RFDin2和所述DVMin2；
    所述RFDinp，用于接收所述RFDinp-1输出的第p-1射频延时信号x(t-τRFp-1)，对所述第p-1射频延时信号x(t-τRFp-1)进行延时得到第p射频延时信号x(t-τRFp)， 将所述第p射频延时信号x(t-τRFp)输出给所述RFDinp+1和DVMinp+1，p＝2、3、…、P-2；
    所述RFDinP-1，用于接收RFDinP-2输出的第P-2射频延时信号x(t-τRFP-2)，对所述第P-2射频延时信号x(t-τRFP-2)进行延时得到第P-1射频延时信号x(t-τRFP-1)，将所述第P-1射频延时信号x(t-τRFP-1)输出给DVMinP；
    所述DVMin1，用于接收所述前馈射频信号x(t)和外部输入的预失真系数，根据所述预失真系数，对所述前馈射频信号x(t)进行幅度和相位变换得到输出信号u1(t)，将所述输出信号u1(t)输出给所述线性加法器；
    所述DVMinp，用于接收第p-1射频延时信号x(t-τRFi-1)，对所述第p-1射频延时信号x(t-τRFp-1)进行幅度和相位变换得到输出信号up(t)，将所述输出信号up(t)输出给所述线性加法器；
    所述线性加法器，用于接收所述DVMin1、DVMin2、…、DVMinP输出输出的输出信号，将u1(t)、u2(t)、…、uP(t)相加得到线性预调理信号。
  19. 如权利要求17所述的APD核心模块，其特征在于，所述ZMNL模块包括：
    包络检测单元ED和信号查找表单元SL，所述ZMNL模块输入端和所述ED输入端与所述SL的射频输入端x相连，所述ED输出端与所述SL的包络输入端y相连，所述SL的输出端就是所述ZMNL的输出端；
    所述ED，用于对线性滤波器输出的线性预调理信号进行包络检测产生包络信号，将所述包络信号输出给SL；
    所述SL，用于接收所述线性滤波器输出的线性预调理信号、所述ED输出的包络信号和外部输入的预失真系数，根据所述预失真系数和所述包络信号，对所述线性预调理信号进行幅度和相位变换得到预失真信号。
  20. 如权利要求17至19任一项权利要求所述的所述的APD核心模块，其特征在于，还包括：
    宽带线性滤波模块，所述宽带线性滤波模块与所述ZMNL模块相连；
    所述宽带线性滤波模块，用于在APD训练模块输入的预失真系数的作用下，对所述ZMNL模块输入的线性预调理信号进行处理，输出预失真信号。
  21. 一种APD核心模块，其特征在于，包括：
    线性滤波模块、单块信号查找表SBSL模块和宽带线性滤波模块；
    所述线性滤波模块在APD训练模块输入的线性滤波系数的作用下，对前馈射频信号进行处理，输出线性预调理信号；
    所述SBSL模块在APD训练模块输入的SBSL系数的作用下，对线性预调理信号进行处理，输出中间预失真信号；
    所述宽带线性滤波模块在所述APD训练模块输入的宽带线性滤波系数的作用下，对从所述SBSL模块输入的中间预失真信号进行处理，输出预失真信号。
  22. 一种模拟预失真器APD系统，其特征在于，包括：
    主延时模块、如权利要求1至16任一项权利要求所述的APD核心模块和APD训练模块，模拟预失真器系统的输入端与所述主延时模块的输入端相连，所述模拟预失真器系统的输入端通过前馈耦合器与所述APD核心模块的第一输入端和所述APD训练模块的第一输入端都与相连，所述主延时模块的输出端和APD核心模块的输出端分别与合路耦合器的第一输入端和第二输入端相连，所述合路耦合器的输出端与所述PA的输入端相连，所述APD训练模块的第二输入端通过反馈耦合器与所述PA的输出端相连，APD训练模块的输出端与所述APD核心模块的第二输入端相连；
    所述主延时模块，用于接收所述模拟预失真器系统的输入端输入的前馈射频信号，对所述前馈射频信号进行延时得到主延时信号，将所述主延时信号输出给所述合路耦合器；
    所述APD训练模块，用于接收所述前馈耦合器从所述模拟预失真器系统的输入端耦合出的前馈射频信号和所述反馈耦合器从所述PA产生的发射信号耦合的发射信号，根据接收的前馈射频信号和发射信号计算预失真系数，将所述预失真系数发送给所述APD核心模块；
    所述APD核心模块，用于接收所述前馈耦合器从所述模拟预失真器系统的输入端耦合出的前馈射频信号和所述APD训练模块发送的预失真系数，根据接收的前馈射频信号和预失真系数产生预失真信号，将所述预失真信号输出给合路耦合器，由所述合路耦合器对所述预失真信号和主延时信号进行混合得到混合信号，将所述混合信号输出给PA，由PA对所述混合信号进行放大后输出发射信号。
  23. 一种模拟预失真器APD系统，其特征在于，包括：
    主延时模块、如权利要求17至20任一项权利要求所述的APD核心模块和APD训练模块，模拟预失真器系统的输入端与所述主延时模块的输入端相连，所述模拟预失真器系统的输入端通过前馈耦合器与所述APD核心模块的第一输入端和所述APD训练模块的第一输入端都与相连，所述主延时模块的输出端和APD核心模块的输出端分别与合路耦合器的第一输入端和第二输入端相连，所述合路耦合器的输出端与所述PA的输入端相连，所述APD训练模块的第二输入端通过反馈耦合器与所述PA的输出端相连，APD训练模块的输出端与所述APD核心模块的第二输入端相连；
    所述主延时模块，用于接收所述模拟预失真器系统的输入端输入的前馈射频信号，对所述前馈射频信号进行延时得到主延时信号，将所述主延时信号输出给所述合路耦合器；
    所述APD训练模块，用于接收所述前馈耦合器从所述模拟预失真器系统的输入端耦合出的前馈射频信号和所述反馈耦合器从所述PA产生的发射信号耦合的发射信号，根据接收的前馈射频信号和发射信号计算预失真系数，将所述预失真系数发送给所述APD核心模块；
    所述APD核心模块，用于接收所述前馈耦合器从所述模拟预失真器系统的输入端耦合出的前馈射频信号和所述APD训练模块发送的预失真系数，根据接收的前馈射频信号和预失真系数产生预失真信号，将所述预失真信号输出给合路耦合器，由所述合路耦合器对所述预失真信号和主延时信号进行混合得到混合信号，将所述混合信号输出给PA，由PA对所述混合信号进行放大后输出发射信号。
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