WO2016067908A1 - Module de communication sans fil - Google Patents

Module de communication sans fil Download PDF

Info

Publication number
WO2016067908A1
WO2016067908A1 PCT/JP2015/078917 JP2015078917W WO2016067908A1 WO 2016067908 A1 WO2016067908 A1 WO 2016067908A1 JP 2015078917 W JP2015078917 W JP 2015078917W WO 2016067908 A1 WO2016067908 A1 WO 2016067908A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductor
signal
layer
pillar
ground
Prior art date
Application number
PCT/JP2015/078917
Other languages
English (en)
Japanese (ja)
Inventor
薫 須藤
通春 横山
宏毅 加藤
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Publication of WO2016067908A1 publication Critical patent/WO2016067908A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00—Coupling devices of the waveguide type
    • H01P5/08—Coupling devices of the waveguide type for linking dissimilar lines or devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a wireless communication module in which a semiconductor element for wireless communication is mounted.
  • Patent Document 1 discloses a wireless device that inputs and outputs a signal in a radio frequency band.
  • This radio apparatus is composed of a radio frequency module (RF module) and an intermediate frequency module (IF module). Between them, an intermediate frequency signal (IF signal), a local oscillation signal (LO signal), and a control signal are transmitted and received.
  • RF module radio frequency module
  • IF module intermediate frequency module
  • LO signal local oscillation signal
  • control signal a control signal
  • the RF module and the IF module include a dielectric substrate and a semiconductor element for wireless communication mounted on the dielectric substrate.
  • the input / output terminals of the RF module and IF module and the semiconductor element are connected by a transmission line arranged in the dielectric substrate.
  • This transmission line is composed of a strip line, a micro strip line, a coplanar line, etc. extending in the in-plane direction of the dielectric substrate.
  • the transmission line is connected to the input / output terminal by an interlayer connection conductor extending in the thickness direction of the dielectric substrate.
  • the characteristic impedance of the transmission line in the dielectric substrate can be stably managed to a target value.
  • the characteristic impedance is likely to be disturbed at the connection point between the transmission line and the input / output terminal.
  • the voltage standing wave ratio (VSWR) becomes large, and it is difficult to efficiently transmit and receive the IF signal and the LO signal.
  • An object of the present invention is to provide a wireless communication module capable of reducing disturbance of characteristic impedance in the vicinity of an input / output terminal.
  • a wireless communication module provides: A dielectric substrate; A semiconductor element for wireless communication mounted on the dielectric substrate; A plurality of signal conductor pillars and a plurality of ground conductor pillars protruding from the bottom surface of the dielectric substrate and connected to the mounting substrate at the tip; A transmission line disposed on the dielectric substrate and connecting the signal conductor column and the semiconductor element, and is paired with a linear conductor extending in an in-plane direction of the dielectric substrate, and the linear conductor
  • the transmission line including a ground conductor layer; Including a first interlayer connection conductor for connecting the linear conductor and the signal conductor pillar in the thickness direction;
  • the signal conductor pillar is thicker than the first interlayer connection conductor, A clearance hole is provided in the ground conductor layer at a position corresponding to the first interlayer connection conductor, and the clearance hole includes the signal conductor pillar in a plan view.
  • the clearance hole that encloses the signal conductor pillar is provided in the ground conductor layer, the parasitic capacitance between the signal conductor pillar and the ground conductor layer is small. Thereby, disturbance of the characteristic impedance in the coupling
  • the ground conductor layer in which the clearance hole is provided has a thickness direction of the dielectric substrate. Is arranged between the linear conductor and the signal conductor column.
  • ground conductor layer is arranged in a layer close to the signal conductor pillar, a great effect of providing a clearance hole can be obtained.
  • the ground conductor layer in which the clearance hole is provided is the same layer as the linear conductor. Is arranged.
  • the clearance hole is connected to the outer periphery of the ground conductor layer.
  • the clearance hole is not necessarily arranged in the inner part of the ground conductor layer.
  • the clearance hole is connected to the outer periphery of the ground conductor layer.
  • a wireless communication module includes, in addition to the configurations of the wireless communication modules according to the first to fourth aspects, a second interlayer connection conductor that connects the grounding conductor column and the grounding conductor layer.
  • the ground conductor layer of the wireless communication module is connected to the ground conductor layer of the mounting board via the ground conductor pillar.
  • the signal conductor pillar and the ground conductor pillar are provided on an edge of the dielectric substrate. Are arranged along the edge, and the grounding conductor pillars are arranged on both sides of the signal conductor pillars.
  • the grounding conductor pillar is also placed adjacent to the signal conductor pillar. Is arranged.
  • the effect of suppressing electrostatic breakdown of the semiconductor element can be enhanced.
  • the shortest distance in the in-plane direction from the signal conductor pillar to the ground conductor layer is The distance from the signal conductor post to the adjacent ground conductor post is 1 ⁇ 4 or more.
  • Alignment margin is secured in consideration of manufacturing variations.
  • the clearance hole that encloses the signal conductor pillar is provided in the ground conductor layer, the parasitic capacitance between the signal conductor pillar and the ground conductor layer is small. Thereby, disturbance of the characteristic impedance in the coupling
  • FIG. 1 is a block diagram of a wireless device equipped with a wireless communication module according to an embodiment.
  • FIG. 2A is a plan sectional view of the uppermost conductor layer in the dielectric substrate used in the RF module
  • FIG. 2B is a bottom view of the RF module.
  • 3A is a cross-sectional view taken along one-dot chain line 3A-3A in FIG. 2A
  • FIG. 3B is a cross-sectional view taken along one-dot chain line 3B-3B in FIG. 2A
  • 4 is a cross-sectional view taken along one-dot chain line 4-4 of FIGS. 2A and 2B.
  • 5A is a plan sectional view of the second lowermost conductor layer shown in FIG. 4, and FIG.
  • FIG. 5B is a plan sectional view of the third lowermost conductor layer shown in FIG. 4.
  • FIG. 6 is a cross-sectional view of an RF module according to a comparative example.
  • FIG. 7A is a cross-sectional view of an RF module according to a comparative example, and FIG. 7B is a cross-sectional view of the RF module according to the embodiment.
  • 8A and 8B are cross-sectional views of the IF module according to the embodiment.
  • 9A to 9C are plan sectional views of the first to third conductor layers shown in FIGS. 8A and 8B, respectively.
  • FIG. 1 shows a block diagram of a wireless device equipped with a wireless communication module according to the embodiment.
  • a radio frequency module (RF module) 20 and an intermediate frequency module (IF module) 70 are mounted on the mounting substrate 10.
  • RF module 20 and the IF module 70 are each referred to as a wireless communication module.
  • a semiconductor element 80 for wireless communication and a local oscillator 81 are mounted on the IF module 70.
  • a semiconductor element 30 for wireless communication is mounted on the RF module 20.
  • An intermediate frequency signal (IF signal), a local oscillation signal (LO signal), a control signal, and the like are transmitted and received between the RF module 20 and the IF module 70.
  • the IF signal and the LO signal are transmitted through a transmission line arranged on the mounting substrate 10.
  • FIG. 2A shows a plan sectional view of a conductor layer on which an antenna in a dielectric substrate 22 used in the RF module 20 is arranged.
  • the dielectric substrate 22 has a rectangular or square planar shape.
  • the conductor layer includes a plurality of printed dipole antennas 23, a feeder line 24, a balun (balance-unbalance converter) 25, and a plurality of patch antennas 27.
  • ceramic, epoxy resin or the like is used for the dielectric substrate 22 .
  • the feeder 24, the balun 25, and the patch antenna 27 for example, a conductive material such as copper is used.
  • conductive materials such as copper are used for the other conductor layers.
  • the plurality of dipole antennas 23 are arranged slightly inside the outer peripheral line along the outer peripheral line of the dielectric substrate 22. Each of the dipole antennas 23 is disposed in parallel to the outer peripheral line of the dielectric substrate 22. As an example, three dipole antennas 23 are arranged on one side of the dielectric substrate 22.
  • a balanced feed line 24 extends from each of the dipole antennas 23 toward the inside of the dielectric substrate 22.
  • a balun (balance-unbalance converter) 25 is provided at the inner end of the feeder line 24.
  • the balun 25 shifts one phase of the balanced power supply line 24 by 180 degrees with respect to the other phase.
  • the balun 25 is connected to the transmission line below the dielectric substrate 22 at the connection point 26.
  • a reflector pattern 28 is disposed slightly inside the dipole antenna 23 and outside the balun 25.
  • the reflector pattern 28 is composed of a linear conductor pattern disposed along a rectangular outer peripheral line that is slightly smaller than the dielectric substrate 22.
  • the reflector pattern 28 is cut at a location where it intersects the power supply line 24 and is insulated from the power supply line 24.
  • the distance between the dipole antenna 23 and the reflector pattern 28 is equal to 1 ⁇ 4 of the effective wavelength of the radio wave at the operating frequency of the dipole antenna 23.
  • connection points 29 arranged along the reflector pattern 28, the reflector pattern 28 is connected to the inner ground conductor layer.
  • the plurality of patch antennas 27 are arranged in a matrix inside the dipole antenna 23.
  • the patch antennas 27 are arranged in a matrix of 2 rows and 3 columns.
  • the row direction and the column direction are parallel to the outer peripheral line of the dielectric substrate 22.
  • the dipole antenna 23 operates as an endfire antenna having directivity in a direction parallel to the surface of the dielectric substrate 22.
  • the patch antenna 27 has directivity in the normal direction (bore sight direction) of the surface of the dielectric substrate 22.
  • FIG. 2B shows a bottom view of the RF module 20.
  • the sealing resin layer 35 is in close contact with the bottom surface of the dielectric substrate 22 (FIG. 2A).
  • the semiconductor element 30, the high-frequency circuit component 31, and the conductive pillar 40 are embedded.
  • the semiconductor element 30 supplies a high frequency signal to the dipole antenna 23 and the patch antenna 27 (FIG. 2A).
  • the high frequency circuit component 31 includes an inductor, a capacitor, and the like.
  • the semiconductor element 30 and the high-frequency circuit component 31 are mounted on the bottom surface of the dielectric substrate 22 (FIG. 2A).
  • the conductor column 40 protrudes from the bottom surface of the dielectric substrate 22, and its tip is exposed on the surface of the sealing resin layer 35.
  • a conductive material such as copper is used.
  • a thermosetting resin such as an epoxy resin or a cyanate resin is used.
  • the sealing resin layer 35 defines a mounting surface that faces the mounting substrate 10 when the RF module 20 is mounted on the mounting substrate 10 (FIG. 1).
  • the plurality of conductive pillars 40 are arranged at equal intervals along the reflector pattern 28 (FIG. 2A) in plan view. That is, the conductor pillar 40 is disposed on the inner side than the dipole antenna 23.
  • the conductor pillar 40 includes a plurality of signal conductor pillars 400 and a plurality of ground conductor pillars 401.
  • the signal conductor pillar 400 is connected to the semiconductor element 30 by a conductor pattern formed on the dielectric substrate 22 (FIG. 2A).
  • the grounding conductor column 401 is connected to the grounding conductor layer and the reflector pattern 28 in the dielectric substrate 22 (FIG. 2A).
  • the grounding conductor pillar 401 operates as a reflector of the dipole antenna 23 together with the reflector pattern 28.
  • FIG. 3A is a cross-sectional view taken along one-dot chain line 3A-3A in FIG. 2A.
  • a plurality of conductive pillars 40 protrude from the bottom surface of the dielectric substrate 22.
  • the conductive pillar 40 is embedded in a sealing resin layer 35 that covers the bottom surface of the dielectric substrate 22, and the tip thereof is exposed on the surface (mounting surface) of the sealing resin layer 35.
  • a plurality of conductor layers are arranged in the dielectric substrate 22. In the example shown in FIG. 3A, six conductor layers including the conductor layers arranged on the bottom surface are arranged.
  • the first conductor layer disposed on the bottom surface of the dielectric substrate 22 includes a plurality of lands 41.
  • the land 41 is arranged corresponding to the conductor pillar 40 and is connected to the conductor pillar 40.
  • the ground conductor layer 44 is included in the second to fifth conductor layers.
  • the ground conductor layer 44 is connected to the ground conductor column 401 via a via conductor 420 connecting the layers.
  • the first conductor layer includes a linear conductor 43 in addition to the ground conductor layer 44.
  • the linear conductor 43 is connected to the signal conductor pillar 400 via the via conductor 420 and the inner layer land 421.
  • the inner land 421 is not necessarily provided. Different conductor layers may be connected by only via conductors 420 filled in through holes extending over a plurality of layers. In this specification, the via conductor 420 and the inner layer land 421 connected in the thickness direction are referred to as an interlayer connection conductor 42.
  • the linear conductor 43 forms a transmission line together with the upper and lower sides and the ground conductor layer 44 in the same conductor layer.
  • the fifth conductor layer includes the feeder line 24 in addition to the ground conductor layer 44.
  • the sixth conductor layer includes the parasitic element 270 of the patch antenna 27 (FIG. 1A).
  • FIG. 3B shows a cross-sectional view taken along one-dot chain line 3B-3B in FIG. 2A.
  • a semiconductor element 30 and a high-frequency circuit component 31 are mounted on the bottom surface of the dielectric substrate 22.
  • the semiconductor element 30 is surface-mounted using solder, for example, on a land 46 disposed on the bottom surface of the dielectric substrate 22.
  • a part of the land 46 is connected to the ground conductor layer 44, and another part of the land 46 is connected to the linear conductor 43.
  • the semiconductor element 30 and the high-frequency circuit component 31 are embedded in the sealing resin layer 35.
  • the fifth conductor layer includes the feed element 271 of the patch antenna 27 (FIG. 1A), the dipole antenna 23, and the reflector pattern 28.
  • the feed element 271 is electromagnetically coupled to the parasitic element 270 disposed thereon.
  • the power feeding element 271 is connected to the linear conductor 47 in the fourth layer.
  • the linear conductor 47 and the surrounding ground conductor layer 44 constitute a transmission line.
  • FIG. 4 shows a cross-sectional view taken along one-dot chain line 4-4 of FIGS. 2A and 2B and a cross-sectional view of the mounting substrate 60 on which the RF module 20 is mounted.
  • the signal conductor column 400 is connected to the land 62 of the mounting substrate 60 via the solder 61.
  • the land 62 is connected to a transmission line 63 disposed on the mounting substrate 60.
  • the signal conductor column 400 is connected to the third-layer linear conductor 43 via the first-layer land 41 and the interlayer connection conductor 42 disposed between the first and third layers. .
  • the linear conductor 43 is connected to the signal terminal 300 of the semiconductor element 30.
  • a ground conductor layer 44 is disposed below and above the linear conductor 43.
  • the linear conductor 43 and the upper and lower ground conductor layers 44 constitute a transmission line.
  • the ground terminal 301 of the semiconductor element 30 is connected to the ground conductor layer 44.
  • the fifth conductor layer includes the feeding element 271 of the patch antenna 27 (FIG. 2A), the reflector pattern 28, and the dipole antenna 23.
  • a parasitic element 270 of the patch antenna 27 (FIG. 2A) is included in the sixth conductor layer.
  • FIG. 5A shows a plan sectional view of the second conductor layer from the bottom shown in FIG.
  • the ground conductor layer 44 and the inner land 421 are included in the second conductor layer from the bottom.
  • An interlayer connection conductor 42 including a via conductor 420 and an inner layer land 421 is connected to the signal conductor pillar 400.
  • Clearance holes 48 and 49 are provided in the ground conductor layer 44.
  • the clearance hole 48 is disposed at a position where the signal conductor column 400 is disposed.
  • the interlayer connection conductor 42 is insulated from the ground conductor layer 44 by the clearance hole 48.
  • the signal conductor pillar 400 is thicker than the interlayer connection conductor 42 and includes the interlayer connection conductor 42 in a plan view.
  • the diameter of the signal conductor post 400 is in the range of 2 to 4 times the maximum diameter of the interlayer connection conductor 42.
  • the clearance hole 48 includes not only the interlayer connection conductor 42 but also a signal conductor column 400 larger than the interlayer connection conductor 42.
  • the shortest distance between the outer periphery of the clearance hole 48 and the outer periphery of the signal conductor column 400 is represented by W. In the cross-sectional view shown in FIG. 4, the distance between the left end of the second ground conductor layer 44 from the bottom and the right side surface of the signal conductor post 400 corresponds to the shortest distance W.
  • the clearance hole 48 may be connected to the outer periphery of the ground conductor layer 44 depending on the relationship between the distance from the signal conductor pillar 400 to the outer periphery of the ground conductor layer 44 and the size of the clearance hole 48.
  • FIG. 5A shows an example in which the clearance hole 48 is connected to the outer periphery of the ground conductor layer 44.
  • the planar shape of the clearance hole 48 is not necessarily circular.
  • a U-shaped notch entering from the outer periphery of the ground conductor layer 44 toward the inside may be used as the clearance hole 48.
  • the grounding conductor column 401 is arranged on both sides of the signal conductor column 400. Further, one grounding conductor pillar 401 is arranged adjacent to the signal conductor pillar 400. The grounding conductor column 401 is connected to the grounding conductor layer 44 via the via conductor 420. The thickness of the grounding conductor column 401 is the same as that of the signal conductor column 400.
  • a plurality of conductor pillars 40 (FIG. 2B) including the signal conductor pillars 400 and the ground conductor pillars 401 are arranged at equal intervals. Via conductors 420 connected to the respective conductor pillars 40 are also arranged at equal intervals.
  • the distance from the signal conductor column 400 to the via conductor 420 connected to the adjacent ground conductor column 401 is represented by WB.
  • WB The distance from the signal conductor column 400 to the via conductor 420 connected to the adjacent ground conductor column 401.
  • the shortest distance W is preferably set to be equal to or less than the interval WB.
  • the clearance hole 49 is disposed at a position corresponding to the signal terminal 300 of the semiconductor element 30 (FIG. 4).
  • the clearance hole 49 is smaller than the clearance hole 48 provided at the position of the signal conductor post 400.
  • the ground terminal 301 of the semiconductor element 30 is connected to the ground conductor layer 44.
  • FIG. 5B shows a plan sectional view of the third conductor layer from the bottom shown in FIG.
  • the ground conductor layer 44 and the linear conductor 43 are included in the third conductor layer from the bottom.
  • One end of the linear conductor 43 is connected to the signal conductor pillar 400 via the interlayer connection conductor 42, and the other end is connected to the signal terminal 300 of the semiconductor element 30 (FIG. 4).
  • a ground conductor layer 44 is disposed via a slit.
  • the linear conductor 43 and the ground conductor layer 44 constitute a coplanar line.
  • a grounded coplanar line is configured including the upper and lower ground conductor layers 44 (FIG. 4) of the linear conductor 43.
  • the transmission line including the linear conductor 43 and the ground conductor layer 44 connects the signal conductor column 400 and the semiconductor element 30.
  • the transmission line 63 (FIG. 4) of the mounting substrate 60 is electromagnetically coupled to the grand coplanar line including the linear conductor 43 via the signal conductor post 400.
  • FIG. 6 shows a cross-sectional view of the RF module 20 according to the comparative example.
  • the cross-sectional view shown in FIG. 6 corresponds to the cross-sectional view shown in FIG. 4 of the RF module 20 according to the embodiment.
  • the clearance hole 48 provided at the position of the signal conductor column 400 and the clearance hole 49 provided at the position of the signal terminal 300 of the semiconductor element 30 have substantially the same size. is there.
  • the clearance holes 48 and 49 in the same conductor layer have substantially the same size as in this comparative example.
  • the plane dimension of the signal conductor post 400 is larger than the plane dimension of the interlayer connection conductor 42. Therefore, the second ground conductor layer 44 from the bottom overlaps the signal conductor pillar 400 in plan view. When they overlap, the parasitic capacitance C between them increases. When the parasitic capacitance C between the signal conductor column 400 and the ground conductor layer 44 is increased, at the coupling point between the transmission line 63 of the mounting substrate 60 and the grounded coplanar line including the linear conductor 43 of the RF module 20, The characteristic impedance of the transmission line is disturbed.
  • the clearance hole 48 (FIG. 5A) encloses the signal conductor post 400 in plan view. Therefore, the second ground conductor layer 44 from the bottom does not overlap the signal conductor pillar 400.
  • the parasitic capacitance C between the two is smaller than that in the comparative example shown in FIG. In the embodiment, since the parasitic capacitance C can be reduced, the disturbance of the characteristic impedance of the transmission line can be suppressed.
  • the shortest distance W (FIGS. 4 and 5A) in the in-plane direction from the signal conductor column 400 to the ground conductor layer 44 is determined from the signal conductor column 400 and the adjacent ground conductor. It is preferable to set it to 1/4 or more of the distance to the column 401.
  • FIG. 7A shows a cross-sectional view of the RF module 20 according to the comparative example.
  • the signal conductor columns 400 are continuously arranged.
  • the grounding conductor column 401 is not disposed between the signal conductor columns 400.
  • FIG. 7B shows a cross-sectional view of the RF module 20 according to the embodiment.
  • grounding conductor columns 401 are arranged on both sides of the signal conductor column 400. Further, one grounding conductor pillar 401 is disposed from one of the signal conductor pillars 400. That is, at least two grounding conductor columns 401 are arranged on both sides of the signal conductor column 400, respectively.
  • the grounding conductor column 401 is connected to a larger grounding conductor layer 44 than the linear conductor 43 to which the signal conductor column 400 is connected. For this reason, when the charged object 50 approaches the signal conductor pillar 400 and the ground conductor pillar 401, a discharge is likely to occur between the charged object 50 and the ground conductor pillar 401. As a result, discharge to the signal conductor column 400 is avoided.
  • FIG. 8A and 8B are cross-sectional views of the IF module 70 (FIG. 1). Similarly to the RF module 20, the IF module 70 also includes a dielectric substrate 82, a conductor post 90 protruding from the bottom surface of the dielectric substrate 82, and a semiconductor element 80 mounted on the bottom surface. 8A shows a cross-sectional view of a portion where the conductor pillars 90 are arranged in a straight line, and FIG. 8B shows a cross-sectional view of a portion where the semiconductor element 80 is disposed.
  • the conductor pillar 90 includes a plurality of signal conductor pillars 900 and a plurality of ground conductor pillars 901.
  • the order of arrangement of the plurality of signal conductor columns 900 and the plurality of ground conductor columns 901 is the same as the order of arrangement of the signal conductor columns 400 and the ground conductor columns 401 of the RF module 20.
  • a power supply system component 83 is mainly mounted on the upper surface of the dielectric substrate 82.
  • the bottom surface of the dielectric substrate 82 is covered with the sealing resin layer 85, and the top surface is covered with the sealing resin layer 86.
  • the semiconductor element 80 and the conductor pillar 90 are embedded in the sealing resin layer 85.
  • the tips of the conductor columns 90 are exposed on the surface of the sealing resin layer 85.
  • the power supply system component 83 is embedded in the sealing resin layer 86.
  • the ground conductor layer 92 is included in the bottom conductor layer (first conductor layer) and the second to fourth conductor layers.
  • the first conductor layer further includes a plurality of lands 91 and 95.
  • the plurality of lands 91 are each connected to the conductor pillar 90.
  • the plurality of lands 95 are each connected to the semiconductor element 80.
  • the second conductor layer includes a linear conductor 93 in addition to the ground conductor layer 92.
  • the fourth conductor layer includes a wiring 94 in addition to the ground conductor layer 92.
  • the wiring 94 is connected to the power supply system component 83.
  • One end of the linear conductor 93 is connected to the signal conductor post 900 via the interlayer connection conductor 99.
  • the linear conductor 93 constitutes a transmission line together with the upper and lower ground conductor layers 92. This transmission line connects the signal conductor pillar 900 and the semiconductor element 80.
  • FIG. 9A is a plan sectional view of the first conductor layer shown in FIGS. 8A and 8B.
  • Lands 91 and 95 and a ground conductor layer 92 are included in the first conductor layer.
  • the land 91 for the conductor pillar 90 (FIGS. 8A and 8B) is disposed outside the ground conductor layer 92.
  • the land 95 for the semiconductor element 80 is disposed inside the ground conductor layer 92.
  • a clearance hole 96 for insulating the land 95 is provided in the ground conductor layer 92.
  • FIG. 9B is a plan sectional view of the second conductor layer shown in FIGS. 8A and 8B.
  • a ground conductor layer 92 and a linear conductor 93 are included in the second conductor layer.
  • a clearance hole 98 is provided at the position of the land 95 (FIG. 9A) for the semiconductor element 80.
  • a clearance hole 97 is provided at the position of the signal conductor post 900.
  • the clearance hole 97 includes the signal conductor column 900.
  • the positional relationship between the clearance hole 97 and the signal conductor column 900 is the same as the positional relationship between the clearance hole 48 of the RF module 20 and the signal conductor column 400. That is, the second ground conductor layer 92 does not overlap the signal conductor pillar 900. For this reason, the parasitic capacitance between the signal conductor pillar 900 and the ground conductor layer 92 can be reduced.
  • FIG. 9C shows a plan sectional view of the third conductor layer shown in FIGS. 8A and 8B.
  • the ground conductor layer 92 is included in the third conductor layer.
  • the linear conductor 93 constitutes a grounded coplanar line together with the ground conductor layer 92 (FIG. 9B) and the upper and lower ground conductor layers 92 (FIGS. 9A and 9C) included in the same conductor layer. Since the parasitic capacitance between the signal conductor pillar 900 and the ground conductor layer 92 is small, the coupling point between the transmission line of the mounting substrate 60 (FIG. 4) and the grounded coplanar line having the linear conductor 93 as the central conductor. Disturbances in characteristic impedance can be suppressed.
  • the disturbance of the characteristic impedance of the transmission line connecting the IF module 70 and the RF module 20 shown in FIG. 1 can be suppressed. For this reason, the IF signal and the LO signal can be efficiently transmitted between the IF module 70 and the RF module 20.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Transceivers (AREA)

Abstract

Selon la présente invention, un dispositif à semi-conducteur pour communication sans fil est monté sur une carte diélectrique. Un pôle de conducteur de signal et un pôle de conducteur de masse font saillie sur la surface inférieure de la carte diélectrique. Les extrémités avant de ces pôles de conducteur sont destinées à être connectées à une carte de montage. Une ligne de transfert agencée sur la carte diélectrique connecte le pôle de conducteur de signal au dispositif à semi-conducteur. La ligne de transfert comprend un conducteur linéaire s'étendant dans une direction dans le plan de la carte diélectrique et comprend également une couche de conducteur de masse formant une paire avec le conducteur linéaire. Un premier conducteur de connexion inter-couche connecte le conducteur linéaire au pôle de conducteur de signal dans la direction de l'épaisseur. Le pôle de conducteur de signal est plus épais que le premier conducteur de connexion inter-couche. Un trou de dégagement est formé, dans la couche de conducteur de masse, à l'emplacement correspondant au premier conducteur de connexion inter-couche. Le trou de dégagement, en vue plane, contient le pôle de conducteur de signal. L'invention porte sur un module de communication sans fil dans lequel la perturbation de l'impédance caractéristique à proximité des bornes d'entrée/sortie peut être réduite.
PCT/JP2015/078917 2014-10-29 2015-10-13 Module de communication sans fil WO2016067908A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014-220355 2014-10-29
JP2014220355 2014-10-29

Publications (1)

Publication Number Publication Date
WO2016067908A1 true WO2016067908A1 (fr) 2016-05-06

Family

ID=55857249

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2015/078917 WO2016067908A1 (fr) 2014-10-29 2015-10-13 Module de communication sans fil

Country Status (1)

Country Link
WO (1) WO2016067908A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021193092A1 (fr) 2020-03-25 2021-09-30 京セラ株式会社 Carte de câblage

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001160598A (ja) * 1999-11-30 2001-06-12 Kyocera Corp 半導体素子搭載用基板および光半導体素子収納用パッケージ
JP2003218482A (ja) * 2002-01-25 2003-07-31 Mitsubishi Electric Corp 高周波信号接続構造
JP2004095614A (ja) * 2002-08-29 2004-03-25 Fujitsu Ltd 多層基板及び半導体装置
WO2013035655A1 (fr) * 2011-09-09 2013-03-14 株式会社村田製作所 Substrat de module
JP2013069730A (ja) * 2011-09-21 2013-04-18 Kyocer Slc Technologies Corp 配線基板
JP2013126029A (ja) * 2011-12-13 2013-06-24 Mitsubishi Electric Corp 高周波伝送線路
WO2014017228A1 (fr) * 2012-07-26 2014-01-30 株式会社村田製作所 Module

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001160598A (ja) * 1999-11-30 2001-06-12 Kyocera Corp 半導体素子搭載用基板および光半導体素子収納用パッケージ
JP2003218482A (ja) * 2002-01-25 2003-07-31 Mitsubishi Electric Corp 高周波信号接続構造
JP2004095614A (ja) * 2002-08-29 2004-03-25 Fujitsu Ltd 多層基板及び半導体装置
WO2013035655A1 (fr) * 2011-09-09 2013-03-14 株式会社村田製作所 Substrat de module
JP2013069730A (ja) * 2011-09-21 2013-04-18 Kyocer Slc Technologies Corp 配線基板
JP2013126029A (ja) * 2011-12-13 2013-06-24 Mitsubishi Electric Corp 高周波伝送線路
WO2014017228A1 (fr) * 2012-07-26 2014-01-30 株式会社村田製作所 Module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021193092A1 (fr) 2020-03-25 2021-09-30 京セラ株式会社 Carte de câblage
KR20220143068A (ko) 2020-03-25 2022-10-24 교세라 가부시키가이샤 배선 기판

Similar Documents

Publication Publication Date Title
US10498025B2 (en) Wireless communication module
CN108352599B (zh) 适用于基站天线的天线元件
US10790576B2 (en) Multi-band base station antennas having multi-layer feed boards
US9660340B2 (en) Multiband antenna
US7026999B2 (en) Pattern antenna
JP6500859B2 (ja) 無線モジュール
US9172131B2 (en) Semiconductor structure having aperture antenna
US20160172761A1 (en) Antenna-in-package structures with broadside and end-fire radiations
WO2014073355A1 (fr) Antenne réseau
US20160372839A1 (en) Antenna Element for Signals with Three Polarizations
US8390529B1 (en) PCB spiral antenna and feed network for ELINT applications
KR20150041054A (ko) 편파 공용 안테나
US8842046B2 (en) Loop antenna
US12015204B2 (en) Semiconductor device, communication system, and method of manufacturing semiconductor device
TWI686011B (zh) 高頻模組
US9496623B2 (en) Dual band multi-layer dipole antennas for wireless electronic devices
US20170133767A1 (en) Flexible polymer antenna with multiple ground resonators
JP6202281B2 (ja) アンテナ装置
WO2019111025A1 (fr) Antenne
WO2016067908A1 (fr) Module de communication sans fil
JP6807946B2 (ja) アンテナ、モジュール基板およびモジュール
JP2020174285A (ja) アンテナ装置
US20190103666A1 (en) Mountable Antenna Fabrication and Integration Methods
WO2018100912A1 (fr) Module haute fréquence et dispositif de communication
JP6761480B2 (ja) アンテナ、モジュール基板およびモジュール

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15854940

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

NENP Non-entry into the national phase

Ref country code: JP

122 Ep: pct application non-entry in european phase

Ref document number: 15854940

Country of ref document: EP

Kind code of ref document: A1