WO2016067908A1 - Wireless communication module - Google Patents

Wireless communication module Download PDF

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Publication number
WO2016067908A1
WO2016067908A1 PCT/JP2015/078917 JP2015078917W WO2016067908A1 WO 2016067908 A1 WO2016067908 A1 WO 2016067908A1 JP 2015078917 W JP2015078917 W JP 2015078917W WO 2016067908 A1 WO2016067908 A1 WO 2016067908A1
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WO
WIPO (PCT)
Prior art keywords
conductor
signal
layer
pillar
ground
Prior art date
Application number
PCT/JP2015/078917
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French (fr)
Japanese (ja)
Inventor
薫 須藤
通春 横山
宏毅 加藤
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株式会社村田製作所
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Publication of WO2016067908A1 publication Critical patent/WO2016067908A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00—Coupling devices of the waveguide type
    • H01P5/08—Coupling devices of the waveguide type for linking dissimilar lines or devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a wireless communication module in which a semiconductor element for wireless communication is mounted.
  • Patent Document 1 discloses a wireless device that inputs and outputs a signal in a radio frequency band.
  • This radio apparatus is composed of a radio frequency module (RF module) and an intermediate frequency module (IF module). Between them, an intermediate frequency signal (IF signal), a local oscillation signal (LO signal), and a control signal are transmitted and received.
  • RF module radio frequency module
  • IF module intermediate frequency module
  • LO signal local oscillation signal
  • control signal a control signal
  • the RF module and the IF module include a dielectric substrate and a semiconductor element for wireless communication mounted on the dielectric substrate.
  • the input / output terminals of the RF module and IF module and the semiconductor element are connected by a transmission line arranged in the dielectric substrate.
  • This transmission line is composed of a strip line, a micro strip line, a coplanar line, etc. extending in the in-plane direction of the dielectric substrate.
  • the transmission line is connected to the input / output terminal by an interlayer connection conductor extending in the thickness direction of the dielectric substrate.
  • the characteristic impedance of the transmission line in the dielectric substrate can be stably managed to a target value.
  • the characteristic impedance is likely to be disturbed at the connection point between the transmission line and the input / output terminal.
  • the voltage standing wave ratio (VSWR) becomes large, and it is difficult to efficiently transmit and receive the IF signal and the LO signal.
  • An object of the present invention is to provide a wireless communication module capable of reducing disturbance of characteristic impedance in the vicinity of an input / output terminal.
  • a wireless communication module provides: A dielectric substrate; A semiconductor element for wireless communication mounted on the dielectric substrate; A plurality of signal conductor pillars and a plurality of ground conductor pillars protruding from the bottom surface of the dielectric substrate and connected to the mounting substrate at the tip; A transmission line disposed on the dielectric substrate and connecting the signal conductor column and the semiconductor element, and is paired with a linear conductor extending in an in-plane direction of the dielectric substrate, and the linear conductor
  • the transmission line including a ground conductor layer; Including a first interlayer connection conductor for connecting the linear conductor and the signal conductor pillar in the thickness direction;
  • the signal conductor pillar is thicker than the first interlayer connection conductor, A clearance hole is provided in the ground conductor layer at a position corresponding to the first interlayer connection conductor, and the clearance hole includes the signal conductor pillar in a plan view.
  • the clearance hole that encloses the signal conductor pillar is provided in the ground conductor layer, the parasitic capacitance between the signal conductor pillar and the ground conductor layer is small. Thereby, disturbance of the characteristic impedance in the coupling
  • the ground conductor layer in which the clearance hole is provided has a thickness direction of the dielectric substrate. Is arranged between the linear conductor and the signal conductor column.
  • ground conductor layer is arranged in a layer close to the signal conductor pillar, a great effect of providing a clearance hole can be obtained.
  • the ground conductor layer in which the clearance hole is provided is the same layer as the linear conductor. Is arranged.
  • the clearance hole is connected to the outer periphery of the ground conductor layer.
  • the clearance hole is not necessarily arranged in the inner part of the ground conductor layer.
  • the clearance hole is connected to the outer periphery of the ground conductor layer.
  • a wireless communication module includes, in addition to the configurations of the wireless communication modules according to the first to fourth aspects, a second interlayer connection conductor that connects the grounding conductor column and the grounding conductor layer.
  • the ground conductor layer of the wireless communication module is connected to the ground conductor layer of the mounting board via the ground conductor pillar.
  • the signal conductor pillar and the ground conductor pillar are provided on an edge of the dielectric substrate. Are arranged along the edge, and the grounding conductor pillars are arranged on both sides of the signal conductor pillars.
  • the grounding conductor pillar is also placed adjacent to the signal conductor pillar. Is arranged.
  • the effect of suppressing electrostatic breakdown of the semiconductor element can be enhanced.
  • the shortest distance in the in-plane direction from the signal conductor pillar to the ground conductor layer is The distance from the signal conductor post to the adjacent ground conductor post is 1 ⁇ 4 or more.
  • Alignment margin is secured in consideration of manufacturing variations.
  • the clearance hole that encloses the signal conductor pillar is provided in the ground conductor layer, the parasitic capacitance between the signal conductor pillar and the ground conductor layer is small. Thereby, disturbance of the characteristic impedance in the coupling
  • FIG. 1 is a block diagram of a wireless device equipped with a wireless communication module according to an embodiment.
  • FIG. 2A is a plan sectional view of the uppermost conductor layer in the dielectric substrate used in the RF module
  • FIG. 2B is a bottom view of the RF module.
  • 3A is a cross-sectional view taken along one-dot chain line 3A-3A in FIG. 2A
  • FIG. 3B is a cross-sectional view taken along one-dot chain line 3B-3B in FIG. 2A
  • 4 is a cross-sectional view taken along one-dot chain line 4-4 of FIGS. 2A and 2B.
  • 5A is a plan sectional view of the second lowermost conductor layer shown in FIG. 4, and FIG.
  • FIG. 5B is a plan sectional view of the third lowermost conductor layer shown in FIG. 4.
  • FIG. 6 is a cross-sectional view of an RF module according to a comparative example.
  • FIG. 7A is a cross-sectional view of an RF module according to a comparative example, and FIG. 7B is a cross-sectional view of the RF module according to the embodiment.
  • 8A and 8B are cross-sectional views of the IF module according to the embodiment.
  • 9A to 9C are plan sectional views of the first to third conductor layers shown in FIGS. 8A and 8B, respectively.
  • FIG. 1 shows a block diagram of a wireless device equipped with a wireless communication module according to the embodiment.
  • a radio frequency module (RF module) 20 and an intermediate frequency module (IF module) 70 are mounted on the mounting substrate 10.
  • RF module 20 and the IF module 70 are each referred to as a wireless communication module.
  • a semiconductor element 80 for wireless communication and a local oscillator 81 are mounted on the IF module 70.
  • a semiconductor element 30 for wireless communication is mounted on the RF module 20.
  • An intermediate frequency signal (IF signal), a local oscillation signal (LO signal), a control signal, and the like are transmitted and received between the RF module 20 and the IF module 70.
  • the IF signal and the LO signal are transmitted through a transmission line arranged on the mounting substrate 10.
  • FIG. 2A shows a plan sectional view of a conductor layer on which an antenna in a dielectric substrate 22 used in the RF module 20 is arranged.
  • the dielectric substrate 22 has a rectangular or square planar shape.
  • the conductor layer includes a plurality of printed dipole antennas 23, a feeder line 24, a balun (balance-unbalance converter) 25, and a plurality of patch antennas 27.
  • ceramic, epoxy resin or the like is used for the dielectric substrate 22 .
  • the feeder 24, the balun 25, and the patch antenna 27 for example, a conductive material such as copper is used.
  • conductive materials such as copper are used for the other conductor layers.
  • the plurality of dipole antennas 23 are arranged slightly inside the outer peripheral line along the outer peripheral line of the dielectric substrate 22. Each of the dipole antennas 23 is disposed in parallel to the outer peripheral line of the dielectric substrate 22. As an example, three dipole antennas 23 are arranged on one side of the dielectric substrate 22.
  • a balanced feed line 24 extends from each of the dipole antennas 23 toward the inside of the dielectric substrate 22.
  • a balun (balance-unbalance converter) 25 is provided at the inner end of the feeder line 24.
  • the balun 25 shifts one phase of the balanced power supply line 24 by 180 degrees with respect to the other phase.
  • the balun 25 is connected to the transmission line below the dielectric substrate 22 at the connection point 26.
  • a reflector pattern 28 is disposed slightly inside the dipole antenna 23 and outside the balun 25.
  • the reflector pattern 28 is composed of a linear conductor pattern disposed along a rectangular outer peripheral line that is slightly smaller than the dielectric substrate 22.
  • the reflector pattern 28 is cut at a location where it intersects the power supply line 24 and is insulated from the power supply line 24.
  • the distance between the dipole antenna 23 and the reflector pattern 28 is equal to 1 ⁇ 4 of the effective wavelength of the radio wave at the operating frequency of the dipole antenna 23.
  • connection points 29 arranged along the reflector pattern 28, the reflector pattern 28 is connected to the inner ground conductor layer.
  • the plurality of patch antennas 27 are arranged in a matrix inside the dipole antenna 23.
  • the patch antennas 27 are arranged in a matrix of 2 rows and 3 columns.
  • the row direction and the column direction are parallel to the outer peripheral line of the dielectric substrate 22.
  • the dipole antenna 23 operates as an endfire antenna having directivity in a direction parallel to the surface of the dielectric substrate 22.
  • the patch antenna 27 has directivity in the normal direction (bore sight direction) of the surface of the dielectric substrate 22.
  • FIG. 2B shows a bottom view of the RF module 20.
  • the sealing resin layer 35 is in close contact with the bottom surface of the dielectric substrate 22 (FIG. 2A).
  • the semiconductor element 30, the high-frequency circuit component 31, and the conductive pillar 40 are embedded.
  • the semiconductor element 30 supplies a high frequency signal to the dipole antenna 23 and the patch antenna 27 (FIG. 2A).
  • the high frequency circuit component 31 includes an inductor, a capacitor, and the like.
  • the semiconductor element 30 and the high-frequency circuit component 31 are mounted on the bottom surface of the dielectric substrate 22 (FIG. 2A).
  • the conductor column 40 protrudes from the bottom surface of the dielectric substrate 22, and its tip is exposed on the surface of the sealing resin layer 35.
  • a conductive material such as copper is used.
  • a thermosetting resin such as an epoxy resin or a cyanate resin is used.
  • the sealing resin layer 35 defines a mounting surface that faces the mounting substrate 10 when the RF module 20 is mounted on the mounting substrate 10 (FIG. 1).
  • the plurality of conductive pillars 40 are arranged at equal intervals along the reflector pattern 28 (FIG. 2A) in plan view. That is, the conductor pillar 40 is disposed on the inner side than the dipole antenna 23.
  • the conductor pillar 40 includes a plurality of signal conductor pillars 400 and a plurality of ground conductor pillars 401.
  • the signal conductor pillar 400 is connected to the semiconductor element 30 by a conductor pattern formed on the dielectric substrate 22 (FIG. 2A).
  • the grounding conductor column 401 is connected to the grounding conductor layer and the reflector pattern 28 in the dielectric substrate 22 (FIG. 2A).
  • the grounding conductor pillar 401 operates as a reflector of the dipole antenna 23 together with the reflector pattern 28.
  • FIG. 3A is a cross-sectional view taken along one-dot chain line 3A-3A in FIG. 2A.
  • a plurality of conductive pillars 40 protrude from the bottom surface of the dielectric substrate 22.
  • the conductive pillar 40 is embedded in a sealing resin layer 35 that covers the bottom surface of the dielectric substrate 22, and the tip thereof is exposed on the surface (mounting surface) of the sealing resin layer 35.
  • a plurality of conductor layers are arranged in the dielectric substrate 22. In the example shown in FIG. 3A, six conductor layers including the conductor layers arranged on the bottom surface are arranged.
  • the first conductor layer disposed on the bottom surface of the dielectric substrate 22 includes a plurality of lands 41.
  • the land 41 is arranged corresponding to the conductor pillar 40 and is connected to the conductor pillar 40.
  • the ground conductor layer 44 is included in the second to fifth conductor layers.
  • the ground conductor layer 44 is connected to the ground conductor column 401 via a via conductor 420 connecting the layers.
  • the first conductor layer includes a linear conductor 43 in addition to the ground conductor layer 44.
  • the linear conductor 43 is connected to the signal conductor pillar 400 via the via conductor 420 and the inner layer land 421.
  • the inner land 421 is not necessarily provided. Different conductor layers may be connected by only via conductors 420 filled in through holes extending over a plurality of layers. In this specification, the via conductor 420 and the inner layer land 421 connected in the thickness direction are referred to as an interlayer connection conductor 42.
  • the linear conductor 43 forms a transmission line together with the upper and lower sides and the ground conductor layer 44 in the same conductor layer.
  • the fifth conductor layer includes the feeder line 24 in addition to the ground conductor layer 44.
  • the sixth conductor layer includes the parasitic element 270 of the patch antenna 27 (FIG. 1A).
  • FIG. 3B shows a cross-sectional view taken along one-dot chain line 3B-3B in FIG. 2A.
  • a semiconductor element 30 and a high-frequency circuit component 31 are mounted on the bottom surface of the dielectric substrate 22.
  • the semiconductor element 30 is surface-mounted using solder, for example, on a land 46 disposed on the bottom surface of the dielectric substrate 22.
  • a part of the land 46 is connected to the ground conductor layer 44, and another part of the land 46 is connected to the linear conductor 43.
  • the semiconductor element 30 and the high-frequency circuit component 31 are embedded in the sealing resin layer 35.
  • the fifth conductor layer includes the feed element 271 of the patch antenna 27 (FIG. 1A), the dipole antenna 23, and the reflector pattern 28.
  • the feed element 271 is electromagnetically coupled to the parasitic element 270 disposed thereon.
  • the power feeding element 271 is connected to the linear conductor 47 in the fourth layer.
  • the linear conductor 47 and the surrounding ground conductor layer 44 constitute a transmission line.
  • FIG. 4 shows a cross-sectional view taken along one-dot chain line 4-4 of FIGS. 2A and 2B and a cross-sectional view of the mounting substrate 60 on which the RF module 20 is mounted.
  • the signal conductor column 400 is connected to the land 62 of the mounting substrate 60 via the solder 61.
  • the land 62 is connected to a transmission line 63 disposed on the mounting substrate 60.
  • the signal conductor column 400 is connected to the third-layer linear conductor 43 via the first-layer land 41 and the interlayer connection conductor 42 disposed between the first and third layers. .
  • the linear conductor 43 is connected to the signal terminal 300 of the semiconductor element 30.
  • a ground conductor layer 44 is disposed below and above the linear conductor 43.
  • the linear conductor 43 and the upper and lower ground conductor layers 44 constitute a transmission line.
  • the ground terminal 301 of the semiconductor element 30 is connected to the ground conductor layer 44.
  • the fifth conductor layer includes the feeding element 271 of the patch antenna 27 (FIG. 2A), the reflector pattern 28, and the dipole antenna 23.
  • a parasitic element 270 of the patch antenna 27 (FIG. 2A) is included in the sixth conductor layer.
  • FIG. 5A shows a plan sectional view of the second conductor layer from the bottom shown in FIG.
  • the ground conductor layer 44 and the inner land 421 are included in the second conductor layer from the bottom.
  • An interlayer connection conductor 42 including a via conductor 420 and an inner layer land 421 is connected to the signal conductor pillar 400.
  • Clearance holes 48 and 49 are provided in the ground conductor layer 44.
  • the clearance hole 48 is disposed at a position where the signal conductor column 400 is disposed.
  • the interlayer connection conductor 42 is insulated from the ground conductor layer 44 by the clearance hole 48.
  • the signal conductor pillar 400 is thicker than the interlayer connection conductor 42 and includes the interlayer connection conductor 42 in a plan view.
  • the diameter of the signal conductor post 400 is in the range of 2 to 4 times the maximum diameter of the interlayer connection conductor 42.
  • the clearance hole 48 includes not only the interlayer connection conductor 42 but also a signal conductor column 400 larger than the interlayer connection conductor 42.
  • the shortest distance between the outer periphery of the clearance hole 48 and the outer periphery of the signal conductor column 400 is represented by W. In the cross-sectional view shown in FIG. 4, the distance between the left end of the second ground conductor layer 44 from the bottom and the right side surface of the signal conductor post 400 corresponds to the shortest distance W.
  • the clearance hole 48 may be connected to the outer periphery of the ground conductor layer 44 depending on the relationship between the distance from the signal conductor pillar 400 to the outer periphery of the ground conductor layer 44 and the size of the clearance hole 48.
  • FIG. 5A shows an example in which the clearance hole 48 is connected to the outer periphery of the ground conductor layer 44.
  • the planar shape of the clearance hole 48 is not necessarily circular.
  • a U-shaped notch entering from the outer periphery of the ground conductor layer 44 toward the inside may be used as the clearance hole 48.
  • the grounding conductor column 401 is arranged on both sides of the signal conductor column 400. Further, one grounding conductor pillar 401 is arranged adjacent to the signal conductor pillar 400. The grounding conductor column 401 is connected to the grounding conductor layer 44 via the via conductor 420. The thickness of the grounding conductor column 401 is the same as that of the signal conductor column 400.
  • a plurality of conductor pillars 40 (FIG. 2B) including the signal conductor pillars 400 and the ground conductor pillars 401 are arranged at equal intervals. Via conductors 420 connected to the respective conductor pillars 40 are also arranged at equal intervals.
  • the distance from the signal conductor column 400 to the via conductor 420 connected to the adjacent ground conductor column 401 is represented by WB.
  • WB The distance from the signal conductor column 400 to the via conductor 420 connected to the adjacent ground conductor column 401.
  • the shortest distance W is preferably set to be equal to or less than the interval WB.
  • the clearance hole 49 is disposed at a position corresponding to the signal terminal 300 of the semiconductor element 30 (FIG. 4).
  • the clearance hole 49 is smaller than the clearance hole 48 provided at the position of the signal conductor post 400.
  • the ground terminal 301 of the semiconductor element 30 is connected to the ground conductor layer 44.
  • FIG. 5B shows a plan sectional view of the third conductor layer from the bottom shown in FIG.
  • the ground conductor layer 44 and the linear conductor 43 are included in the third conductor layer from the bottom.
  • One end of the linear conductor 43 is connected to the signal conductor pillar 400 via the interlayer connection conductor 42, and the other end is connected to the signal terminal 300 of the semiconductor element 30 (FIG. 4).
  • a ground conductor layer 44 is disposed via a slit.
  • the linear conductor 43 and the ground conductor layer 44 constitute a coplanar line.
  • a grounded coplanar line is configured including the upper and lower ground conductor layers 44 (FIG. 4) of the linear conductor 43.
  • the transmission line including the linear conductor 43 and the ground conductor layer 44 connects the signal conductor column 400 and the semiconductor element 30.
  • the transmission line 63 (FIG. 4) of the mounting substrate 60 is electromagnetically coupled to the grand coplanar line including the linear conductor 43 via the signal conductor post 400.
  • FIG. 6 shows a cross-sectional view of the RF module 20 according to the comparative example.
  • the cross-sectional view shown in FIG. 6 corresponds to the cross-sectional view shown in FIG. 4 of the RF module 20 according to the embodiment.
  • the clearance hole 48 provided at the position of the signal conductor column 400 and the clearance hole 49 provided at the position of the signal terminal 300 of the semiconductor element 30 have substantially the same size. is there.
  • the clearance holes 48 and 49 in the same conductor layer have substantially the same size as in this comparative example.
  • the plane dimension of the signal conductor post 400 is larger than the plane dimension of the interlayer connection conductor 42. Therefore, the second ground conductor layer 44 from the bottom overlaps the signal conductor pillar 400 in plan view. When they overlap, the parasitic capacitance C between them increases. When the parasitic capacitance C between the signal conductor column 400 and the ground conductor layer 44 is increased, at the coupling point between the transmission line 63 of the mounting substrate 60 and the grounded coplanar line including the linear conductor 43 of the RF module 20, The characteristic impedance of the transmission line is disturbed.
  • the clearance hole 48 (FIG. 5A) encloses the signal conductor post 400 in plan view. Therefore, the second ground conductor layer 44 from the bottom does not overlap the signal conductor pillar 400.
  • the parasitic capacitance C between the two is smaller than that in the comparative example shown in FIG. In the embodiment, since the parasitic capacitance C can be reduced, the disturbance of the characteristic impedance of the transmission line can be suppressed.
  • the shortest distance W (FIGS. 4 and 5A) in the in-plane direction from the signal conductor column 400 to the ground conductor layer 44 is determined from the signal conductor column 400 and the adjacent ground conductor. It is preferable to set it to 1/4 or more of the distance to the column 401.
  • FIG. 7A shows a cross-sectional view of the RF module 20 according to the comparative example.
  • the signal conductor columns 400 are continuously arranged.
  • the grounding conductor column 401 is not disposed between the signal conductor columns 400.
  • FIG. 7B shows a cross-sectional view of the RF module 20 according to the embodiment.
  • grounding conductor columns 401 are arranged on both sides of the signal conductor column 400. Further, one grounding conductor pillar 401 is disposed from one of the signal conductor pillars 400. That is, at least two grounding conductor columns 401 are arranged on both sides of the signal conductor column 400, respectively.
  • the grounding conductor column 401 is connected to a larger grounding conductor layer 44 than the linear conductor 43 to which the signal conductor column 400 is connected. For this reason, when the charged object 50 approaches the signal conductor pillar 400 and the ground conductor pillar 401, a discharge is likely to occur between the charged object 50 and the ground conductor pillar 401. As a result, discharge to the signal conductor column 400 is avoided.
  • FIG. 8A and 8B are cross-sectional views of the IF module 70 (FIG. 1). Similarly to the RF module 20, the IF module 70 also includes a dielectric substrate 82, a conductor post 90 protruding from the bottom surface of the dielectric substrate 82, and a semiconductor element 80 mounted on the bottom surface. 8A shows a cross-sectional view of a portion where the conductor pillars 90 are arranged in a straight line, and FIG. 8B shows a cross-sectional view of a portion where the semiconductor element 80 is disposed.
  • the conductor pillar 90 includes a plurality of signal conductor pillars 900 and a plurality of ground conductor pillars 901.
  • the order of arrangement of the plurality of signal conductor columns 900 and the plurality of ground conductor columns 901 is the same as the order of arrangement of the signal conductor columns 400 and the ground conductor columns 401 of the RF module 20.
  • a power supply system component 83 is mainly mounted on the upper surface of the dielectric substrate 82.
  • the bottom surface of the dielectric substrate 82 is covered with the sealing resin layer 85, and the top surface is covered with the sealing resin layer 86.
  • the semiconductor element 80 and the conductor pillar 90 are embedded in the sealing resin layer 85.
  • the tips of the conductor columns 90 are exposed on the surface of the sealing resin layer 85.
  • the power supply system component 83 is embedded in the sealing resin layer 86.
  • the ground conductor layer 92 is included in the bottom conductor layer (first conductor layer) and the second to fourth conductor layers.
  • the first conductor layer further includes a plurality of lands 91 and 95.
  • the plurality of lands 91 are each connected to the conductor pillar 90.
  • the plurality of lands 95 are each connected to the semiconductor element 80.
  • the second conductor layer includes a linear conductor 93 in addition to the ground conductor layer 92.
  • the fourth conductor layer includes a wiring 94 in addition to the ground conductor layer 92.
  • the wiring 94 is connected to the power supply system component 83.
  • One end of the linear conductor 93 is connected to the signal conductor post 900 via the interlayer connection conductor 99.
  • the linear conductor 93 constitutes a transmission line together with the upper and lower ground conductor layers 92. This transmission line connects the signal conductor pillar 900 and the semiconductor element 80.
  • FIG. 9A is a plan sectional view of the first conductor layer shown in FIGS. 8A and 8B.
  • Lands 91 and 95 and a ground conductor layer 92 are included in the first conductor layer.
  • the land 91 for the conductor pillar 90 (FIGS. 8A and 8B) is disposed outside the ground conductor layer 92.
  • the land 95 for the semiconductor element 80 is disposed inside the ground conductor layer 92.
  • a clearance hole 96 for insulating the land 95 is provided in the ground conductor layer 92.
  • FIG. 9B is a plan sectional view of the second conductor layer shown in FIGS. 8A and 8B.
  • a ground conductor layer 92 and a linear conductor 93 are included in the second conductor layer.
  • a clearance hole 98 is provided at the position of the land 95 (FIG. 9A) for the semiconductor element 80.
  • a clearance hole 97 is provided at the position of the signal conductor post 900.
  • the clearance hole 97 includes the signal conductor column 900.
  • the positional relationship between the clearance hole 97 and the signal conductor column 900 is the same as the positional relationship between the clearance hole 48 of the RF module 20 and the signal conductor column 400. That is, the second ground conductor layer 92 does not overlap the signal conductor pillar 900. For this reason, the parasitic capacitance between the signal conductor pillar 900 and the ground conductor layer 92 can be reduced.
  • FIG. 9C shows a plan sectional view of the third conductor layer shown in FIGS. 8A and 8B.
  • the ground conductor layer 92 is included in the third conductor layer.
  • the linear conductor 93 constitutes a grounded coplanar line together with the ground conductor layer 92 (FIG. 9B) and the upper and lower ground conductor layers 92 (FIGS. 9A and 9C) included in the same conductor layer. Since the parasitic capacitance between the signal conductor pillar 900 and the ground conductor layer 92 is small, the coupling point between the transmission line of the mounting substrate 60 (FIG. 4) and the grounded coplanar line having the linear conductor 93 as the central conductor. Disturbances in characteristic impedance can be suppressed.
  • the disturbance of the characteristic impedance of the transmission line connecting the IF module 70 and the RF module 20 shown in FIG. 1 can be suppressed. For this reason, the IF signal and the LO signal can be efficiently transmitted between the IF module 70 and the RF module 20.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Transceivers (AREA)

Abstract

A semiconductor device for wireless communications is mounted on a dielectric board. A signal conductor pole and a ground conductor pole protrude from the bottom surface of the dielectric board. The front ends of these conductor poles are to be connected to a mounting board. A transfer line arranged on the dielectric board connects the signal conductor pole to the semiconductor device. The transfer line includes a linear conductor extending in an intra-plane direction of the dielectric board and also includes a ground conductor layer forming a pair together with the linear conductor. A first inter-layer connection conductor connects the linear conductor to the signal conductor pole in the thickness direction. The signal conductor pole is thicker than the first inter-layer connection conductor. A clearance hole is formed, in the ground conductor layer, at the position corresponding to the first inter-layer connection conductor. The clearance hole, when seen in a plan view, contains the signal conductor pole. Provided is a wireless communication module wherein the disturbance of the characteristic impedance in the vicinity of the input/output terminals can be reduced.

Description

無線通信モジュールWireless communication module
　本発明は、無線通信用の半導体素子を実装した無線通信モジュールに関する。 The present invention relates to a wireless communication module in which a semiconductor element for wireless communication is mounted.
　下記の特許文献１に、無線周波数帯の信号の入出力を行う無線装置が開示されている。この無線装置は、無線周波数モジュール（ＲＦモジュール）と中間周波数モジュール（ＩＦモジュール）とで構成される。両者の間で、中間周波数信号（ＩＦ信号）、局部発振信号（ＬＯ信号）、及び制御信号の送受が行われる。 The following Patent Document 1 discloses a wireless device that inputs and outputs a signal in a radio frequency band. This radio apparatus is composed of a radio frequency module (RF module) and an intermediate frequency module (IF module). Between them, an intermediate frequency signal (IF signal), a local oscillation signal (LO signal), and a control signal are transmitted and received.
米国特許出願公開第２０１２／０３０７６９５号明細書US Patent Application Publication No. 2012/0307695
　一般的に、ＲＦモジュール及びＩＦモジュールは、誘電体基板、及び誘電体基板に実装された無線通信用の半導体素子を含む。ＲＦモジュール及びＩＦモジュールの入出力端子と半導体素子とは、誘電体基板内に配置された伝送線路で接続される。この伝送線路は、誘電体基板の面内方向に延びるストリップライン、マイクロストリップライン、コプレーナライン等で構成される。伝送線路を入出力端子とは、誘電体基板の厚さ方向に延びる層間接続導体で接続される。 Generally, the RF module and the IF module include a dielectric substrate and a semiconductor element for wireless communication mounted on the dielectric substrate. The input / output terminals of the RF module and IF module and the semiconductor element are connected by a transmission line arranged in the dielectric substrate. This transmission line is composed of a strip line, a micro strip line, a coplanar line, etc. extending in the in-plane direction of the dielectric substrate. The transmission line is connected to the input / output terminal by an interlayer connection conductor extending in the thickness direction of the dielectric substrate.
　誘電体基板内の伝送線路の特性インピーダンスは、目標とする値に安定して管理することが可能である。ところが、伝送線路と入出力端子との接続箇所において、特性インピーダンスの乱れが生じやすい。特性インピーダンスが乱れると、電圧定在波比（ＶＳＷＲ）が大きくなってしまうため、ＩＦ信号及びＬＯ信号を効率的に送受することが困難である。 The characteristic impedance of the transmission line in the dielectric substrate can be stably managed to a target value. However, the characteristic impedance is likely to be disturbed at the connection point between the transmission line and the input / output terminal. When the characteristic impedance is disturbed, the voltage standing wave ratio (VSWR) becomes large, and it is difficult to efficiently transmit and receive the IF signal and the LO signal.
　本発明の目的は、入出力端子近傍における特性インピーダンスの乱れを低減することが可能な無線通信モジュールを提供することである。 An object of the present invention is to provide a wireless communication module capable of reducing disturbance of characteristic impedance in the vicinity of an input / output terminal.
　本発明の第１の観点による無線通信モジュールは、
　誘電体基板と、
　前記誘電体基板に実装された無線通信用の半導体素子と、
　前記誘電体基板の底面から突出し、先端において実装基板に接続される複数の信号用導体柱及び複数の接地用導体柱と、
　前記誘電体基板に配置され、前記信号用導体柱と前記半導体素子とを接続する伝送線路であって、前記誘電体基板の面内方向に延びる線状導体、及び前記線状導体と対を成す接地導体層を含む前記伝送線路と、
　前記線状導体と前記信号用導体柱とを厚さ方向に接続する第１の層間接続導体と
を含み、
　前記信号用導体柱は、前記第１の層間接続導体より太く、
　前記接地導体層の、前記第１の層間接続導体に対応する位置にクリアランスホールが設けられており、前記クリアランスホールは、平面視において前記信号用導体柱を内包する。 A wireless communication module according to a first aspect of the present invention provides:
A dielectric substrate;
A semiconductor element for wireless communication mounted on the dielectric substrate;
A plurality of signal conductor pillars and a plurality of ground conductor pillars protruding from the bottom surface of the dielectric substrate and connected to the mounting substrate at the tip;
A transmission line disposed on the dielectric substrate and connecting the signal conductor column and the semiconductor element, and is paired with a linear conductor extending in an in-plane direction of the dielectric substrate, and the linear conductor The transmission line including a ground conductor layer;
Including a first interlayer connection conductor for connecting the linear conductor and the signal conductor pillar in the thickness direction;
The signal conductor pillar is thicker than the first interlayer connection conductor,
A clearance hole is provided in the ground conductor layer at a position corresponding to the first interlayer connection conductor, and the clearance hole includes the signal conductor pillar in a plan view.
　接地導体層に信号用導体柱を内包するクリアランスホールが設けられているため、信号用導体柱と接地導体層との間の寄生容量が小さい。これにより、実装基板の伝送線路と、無線通信モジュールの伝送線路との結合箇所における特性インピーダンスの乱れが抑制される。 Since the clearance hole that encloses the signal conductor pillar is provided in the ground conductor layer, the parasitic capacitance between the signal conductor pillar and the ground conductor layer is small. Thereby, disturbance of the characteristic impedance in the coupling | bond location of the transmission line of a mounting board | substrate and the transmission line of a radio | wireless communication module is suppressed.
　本発明の第２の観点による無線通信モジュールにおいては、第１の観点による無線通信モジュールの構成に加えて、前記クリアランスホールが設けられている前記接地導体層が、前記誘電体基板の厚さ方向に関して、前記線状導体と前記信号用導体柱との間に配置されている。 In the wireless communication module according to the second aspect of the present invention, in addition to the configuration of the wireless communication module according to the first aspect, the ground conductor layer in which the clearance hole is provided has a thickness direction of the dielectric substrate. Is arranged between the linear conductor and the signal conductor column.
　接地導体層が信号用導体柱に近い層に配置されているため、クリアランスホールを設ける大きな効果が得られる。 Since the ground conductor layer is arranged in a layer close to the signal conductor pillar, a great effect of providing a clearance hole can be obtained.
　本発明の第３の観点による無線通信モジュールにおいては、第１の観点による無線通信モジュールの構成に加えて、前記クリアランスホールが設けられている前記接地導体層が、前記線状導体と同一の層に配置されている。 In the wireless communication module according to the third aspect of the present invention, in addition to the configuration of the wireless communication module according to the first aspect, the ground conductor layer in which the clearance hole is provided is the same layer as the linear conductor. Is arranged.
　接地導体層が線状導体と同一の層に配置されている場合にも、クリアランスホールを設けることにより、特性インピーダンスの乱れが軽減される。 Even when the ground conductor layer is disposed on the same layer as the linear conductor, the disturbance of the characteristic impedance is reduced by providing the clearance hole.
　本発明の第４の観点による無線通信モジュールにおいては、第１乃至第３の観点による無線通信モジュールの構成に加えて、前記クリアランスホールが、前記接地導体層の外周に繋がっている。 In the wireless communication module according to the fourth aspect of the present invention, in addition to the configuration of the wireless communication module according to the first to third aspects, the clearance hole is connected to the outer periphery of the ground conductor layer.
　クリアランスホールは、必ずしも接地導体層の内奥部に配置されている必要はない。信号用導体柱が接地導体層の外周の近傍に配置されている場合には、クリアランスホールが接地導体層の外周に繋がる。 The clearance hole is not necessarily arranged in the inner part of the ground conductor layer. When the signal conductor pillar is disposed in the vicinity of the outer periphery of the ground conductor layer, the clearance hole is connected to the outer periphery of the ground conductor layer.
　本発明の第５の観点による無線通信モジュールは、第１乃至第４の観点による無線通信モジュールの構成に加えて、前記接地用導体柱と前記接地導体層とを接続する第２の層間接続導体を有する。 A wireless communication module according to a fifth aspect of the present invention includes, in addition to the configurations of the wireless communication modules according to the first to fourth aspects, a second interlayer connection conductor that connects the grounding conductor column and the grounding conductor layer. Have
　接地用導体柱を介して、無線通信モジュールの接地導体層が、実装基板の接地導体層に接続される。 The ground conductor layer of the wireless communication module is connected to the ground conductor layer of the mounting board via the ground conductor pillar.
　本発明の第６の観点による無線通信モジュールにおいては、第１乃至第５の観点による無線通信モジュールの構成に加えて、前記信号用導体柱及び前記接地用導体柱が、前記誘電体基板の縁の内側に、前記縁に沿って並んでおり、前記信号用導体柱の両隣に、前記接地用導体柱が配置されている。 In the radio communication module according to the sixth aspect of the present invention, in addition to the configurations of the radio communication modules according to the first to fifth aspects, the signal conductor pillar and the ground conductor pillar are provided on an edge of the dielectric substrate. Are arranged along the edge, and the grounding conductor pillars are arranged on both sides of the signal conductor pillars.
　無線通信モジュールに帯電物が近接した場合、帯電物と接地用導体柱との間で放電が生じる。このため、帯電物と信号用導体柱との間で放電が生じにくい。その結果、半導体素子の静電破壊を抑制することができる。 When a charged object comes close to the wireless communication module, discharge occurs between the charged object and the grounding conductor pillar. For this reason, it is difficult for discharge to occur between the charged object and the signal conductor pillar. As a result, electrostatic breakdown of the semiconductor element can be suppressed.
　本発明の第７の観点による無線通信モジュールにおいては、第１乃至第５の観点による無線通信モジュールの構成に加えて、前記信号用導体柱から１つ置いて隣にも、前記接地用導体柱が配置されている。 In the wireless communication module according to the seventh aspect of the present invention, in addition to the configurations of the wireless communication modules according to the first to fifth aspects, the grounding conductor pillar is also placed adjacent to the signal conductor pillar. Is arranged.
　半導体素子の静電破壊を抑制する効果を高めることができる。 The effect of suppressing electrostatic breakdown of the semiconductor element can be enhanced.
　本発明の第８の観点による無線通信モジュールにおいては、第１乃至第５の観点による無線通信モジュールの構成に加えて、前記信号用導体柱から前記接地導体層までの面内方向の最短距離が、前記信号用導体柱から隣の前記接地用導体柱までの間隔の１／４以上である。 In the radio communication module according to the eighth aspect of the present invention, in addition to the configurations of the radio communication modules according to the first to fifth aspects, the shortest distance in the in-plane direction from the signal conductor pillar to the ground conductor layer is The distance from the signal conductor post to the adjacent ground conductor post is ¼ or more.
　製造時のばらつきを考慮して、位置合わせマージンが確保されている。 Alignment margin is secured in consideration of manufacturing variations.
　接地導体層に信号用導体柱を内包するクリアランスホールが設けられているため、信号用導体柱と接地導体層との間の寄生容量が小さい。これにより、実装基板の伝送線路と、無線通信モジュールの伝送線路との結合箇所における特性インピーダンスの乱れが抑制される。 Since the clearance hole that encloses the signal conductor pillar is provided in the ground conductor layer, the parasitic capacitance between the signal conductor pillar and the ground conductor layer is small. Thereby, disturbance of the characteristic impedance in the coupling | bond location of the transmission line of a mounting board | substrate and the transmission line of a radio | wireless communication module is suppressed.
図１は、実施例による無線通信モジュールを搭載した無線装置のブロック図である。FIG. 1 is a block diagram of a wireless device equipped with a wireless communication module according to an embodiment. 図２Ａは、ＲＦモジュールに用いられている誘電体基板内の最も上の導体層の平断面図であり、図２Ｂは、ＲＦモジュールの底面図である。FIG. 2A is a plan sectional view of the uppermost conductor layer in the dielectric substrate used in the RF module, and FIG. 2B is a bottom view of the RF module. 図３Ａは、図２Ａの一点鎖線３Ａ－３Ａにおける断面図であり、図３Ｂは、図２Ａの一点鎖線３Ｂ－３Ｂにおける断面図である。3A is a cross-sectional view taken along one-dot chain line 3A-3A in FIG. 2A, and FIG. 3B is a cross-sectional view taken along one-dot chain line 3B-3B in FIG. 2A. 図４は、図２Ａ及び図２Ｂの一点鎖線４－４における断面図である。4 is a cross-sectional view taken along one-dot chain line 4-4 of FIGS. 2A and 2B. 図５Ａは、図４に示された下から２層目の導体層の平断面図であり、図５Ｂは、図４に示された下から３層目の導体層の平断面図である。5A is a plan sectional view of the second lowermost conductor layer shown in FIG. 4, and FIG. 5B is a plan sectional view of the third lowermost conductor layer shown in FIG. 4. 図６は、比較例によるＲＦモジュールの断面図である。FIG. 6 is a cross-sectional view of an RF module according to a comparative example. 図７Ａは、比較例によるＲＦモジュールの断面図であり、図７Ｂは、実施例によるＲＦモジュールの断面図である。FIG. 7A is a cross-sectional view of an RF module according to a comparative example, and FIG. 7B is a cross-sectional view of the RF module according to the embodiment. 図８Ａ及び図８Ｂは、実施例によるＩＦモジュールの断面図である。8A and 8B are cross-sectional views of the IF module according to the embodiment. 図９Ａ乃至図９Ｃは、それぞれ図８Ａ及び図８Ｂに示した１層目乃至３層目の導体層の平断面図である。9A to 9C are plan sectional views of the first to third conductor layers shown in FIGS. 8A and 8B, respectively.
　図１に、実施例による無線通信モジュールを搭載した無線装置のブロック図を示す。実装基板１０に、無線周波数モジュール（ＲＦモジュール）２０及び中間周波数モジュール（ＩＦモジュール）７０が実装されている。本明細書において、ＲＦモジュール２０及びＩＦモジュール７０を、それぞれ無線通信モジュールという。 FIG. 1 shows a block diagram of a wireless device equipped with a wireless communication module according to the embodiment. A radio frequency module (RF module) 20 and an intermediate frequency module (IF module) 70 are mounted on the mounting substrate 10. In this specification, the RF module 20 and the IF module 70 are each referred to as a wireless communication module.
　ＩＦモジュール７０に、無線通信用の半導体素子８０、及び局部発振器８１が実装されている。ＲＦモジュール２０に、無線通信用の半導体素子３０が実装されている。ＲＦモジュール２０とＩＦモジュール７０との間で、中間周波数信号（ＩＦ信号）、局部発振信号（ＬＯ信号）、制御信号等の送受が行われる。ＩＦ信号及びＬＯ信号は、実装基板１０に配置された伝送線路を通して伝送される。 A semiconductor element 80 for wireless communication and a local oscillator 81 are mounted on the IF module 70. A semiconductor element 30 for wireless communication is mounted on the RF module 20. An intermediate frequency signal (IF signal), a local oscillation signal (LO signal), a control signal, and the like are transmitted and received between the RF module 20 and the IF module 70. The IF signal and the LO signal are transmitted through a transmission line arranged on the mounting substrate 10.
　図２Ａに、ＲＦモジュール２０に用いられている誘電体基板２２内のアンテナが配置された導体層の平断面図を示す。誘電体基板２２は、長方形または正方形の平面形状を有する。導体層は、複数のプリンテッドダイポールアンテナ２３、給電線２４、バラン（平衡不平衡変換器）２５、及び複数のパッチアンテナ２７を含む。誘電体基板２２には、例えばセラミック、エポキシ樹脂等が用いられる。ダイポールアンテナ２３、給電線２４、バラン２５、及びパッチアンテナ２７には、例えば銅等の導電材料が用いられる。同様に、他の導体層にも、銅等の導電材料が用いられる。 FIG. 2A shows a plan sectional view of a conductor layer on which an antenna in a dielectric substrate 22 used in the RF module 20 is arranged. The dielectric substrate 22 has a rectangular or square planar shape. The conductor layer includes a plurality of printed dipole antennas 23, a feeder line 24, a balun (balance-unbalance converter) 25, and a plurality of patch antennas 27. For the dielectric substrate 22, for example, ceramic, epoxy resin or the like is used. For the dipole antenna 23, the feeder 24, the balun 25, and the patch antenna 27, for example, a conductive material such as copper is used. Similarly, conductive materials such as copper are used for the other conductor layers.
　複数のダイポールアンテナ２３は、誘電体基板２２の外周線に沿って、外周線よりもやや内側に配置されている。ダイポールアンテナ２３の各々は、誘電体基板２２の外周線に対して平行に配置されている。一例として、誘電体基板２２の１つの辺に３個のダイポールアンテナ２３が配置される。 The plurality of dipole antennas 23 are arranged slightly inside the outer peripheral line along the outer peripheral line of the dielectric substrate 22. Each of the dipole antennas 23 is disposed in parallel to the outer peripheral line of the dielectric substrate 22. As an example, three dipole antennas 23 are arranged on one side of the dielectric substrate 22.
　ダイポールアンテナ２３の各々から、誘電体基板２２の内側に向かって平衡型の給電線２４が延びる。給電線２４の内側の端部にバラン（平衡不平衡変換器）２５が設けられている。バラン２５は、平衡型の給電線２４の一方の位相を他方の位相に対して１８０度ずらす。バラン２５は、接続点２６において、誘電体基板２２の下層の伝送線路に接続されている。 A balanced feed line 24 extends from each of the dipole antennas 23 toward the inside of the dielectric substrate 22. A balun (balance-unbalance converter) 25 is provided at the inner end of the feeder line 24. The balun 25 shifts one phase of the balanced power supply line 24 by 180 degrees with respect to the other phase. The balun 25 is connected to the transmission line below the dielectric substrate 22 at the connection point 26.
　ダイポールアンテナ２３よりもやや内側に、かつバラン２５より外側に、反射器パターン２８が配置されている。反射器パターン２８は、誘電体基板２２よりもやや小さい長方形の外周線に沿って配置された線状の導体パターンで構成される。反射器パターン２８は、給電線２４と交差する箇所において切断されており、給電線２４から絶縁されている。ダイポールアンテナ２３と反射器パターン２８との間隔は、ダイポールアンテナ２３の動作周波数の電波の実効波長の１／４に等しい。反射器パターン２８に沿って並ぶ複数の接続点２９において、反射器パターン２８が内層の接地導体層に接続されている。 A reflector pattern 28 is disposed slightly inside the dipole antenna 23 and outside the balun 25. The reflector pattern 28 is composed of a linear conductor pattern disposed along a rectangular outer peripheral line that is slightly smaller than the dielectric substrate 22. The reflector pattern 28 is cut at a location where it intersects the power supply line 24 and is insulated from the power supply line 24. The distance between the dipole antenna 23 and the reflector pattern 28 is equal to ¼ of the effective wavelength of the radio wave at the operating frequency of the dipole antenna 23. At a plurality of connection points 29 arranged along the reflector pattern 28, the reflector pattern 28 is connected to the inner ground conductor layer.
　複数のパッチアンテナ２７は、ダイポールアンテナ２３よりも内側に、行列状に配置されている。図２Ａに示した例では、パッチアンテナ２７が２行３列の行列状に配置されている。行方向及び列方向は、誘電体基板２２の外周線に対して平行である。 The plurality of patch antennas 27 are arranged in a matrix inside the dipole antenna 23. In the example shown in FIG. 2A, the patch antennas 27 are arranged in a matrix of 2 rows and 3 columns. The row direction and the column direction are parallel to the outer peripheral line of the dielectric substrate 22.
　ダイポールアンテナ２３は、誘電体基板２２の表面に対して平行な方向に指向性を持つエンドファイアアンテナとして動作する。パッチアンテナ２７は、誘電体基板２２の表面の法線方向（ボアサイト方向）に指向性を持つ。複数のダイポールアンテナ２３及び複数のパッチアンテナ２７が、二次元フェーズドアレイアンテナとして動作することにより、放射パターンのメインローブの方向を、方位角方向及び仰角方向に変化させることができる。 The dipole antenna 23 operates as an endfire antenna having directivity in a direction parallel to the surface of the dielectric substrate 22. The patch antenna 27 has directivity in the normal direction (bore sight direction) of the surface of the dielectric substrate 22. By operating the plurality of dipole antennas 23 and the plurality of patch antennas 27 as a two-dimensional phased array antenna, the direction of the main lobe of the radiation pattern can be changed to the azimuth and elevation directions.
　図２Ｂに、ＲＦモジュール２０の底面図を示す。誘電体基板２２（図２Ａ）の底面に封止樹脂層３５が密着している。封止樹脂層３５内に、半導体素子３０、高周波回路部品３１、及び導体柱４０が埋め込まれている。半導体素子３０は、ダイポールアンテナ２３及びパッチアンテナ２７（図２Ａ）に高周波信号を供給する。高周波回路部品３１には、インダクタ、キャパシタ等が含まれる。半導体素子３０及び高周波回路部品３１は、誘電体基板２２（図２Ａ）の底面に実装されている。 FIG. 2B shows a bottom view of the RF module 20. The sealing resin layer 35 is in close contact with the bottom surface of the dielectric substrate 22 (FIG. 2A). In the sealing resin layer 35, the semiconductor element 30, the high-frequency circuit component 31, and the conductive pillar 40 are embedded. The semiconductor element 30 supplies a high frequency signal to the dipole antenna 23 and the patch antenna 27 (FIG. 2A). The high frequency circuit component 31 includes an inductor, a capacitor, and the like. The semiconductor element 30 and the high-frequency circuit component 31 are mounted on the bottom surface of the dielectric substrate 22 (FIG. 2A).
　導体柱４０は、誘電体基板２２の底面から突出しており、その先端は、封止樹脂層３５の表面に露出している。導体柱４０には、例えば銅等の導電材料が用いられる。封止樹脂層３５には、例えばエポキシ樹脂、シアネート樹脂等の熱硬化性樹脂が用いられる。封止樹脂層３５は、ＲＦモジュール２０を実装基板１０（図１）に実装するときに、実装基板１０に対向する実装面を画定する。 The conductor column 40 protrudes from the bottom surface of the dielectric substrate 22, and its tip is exposed on the surface of the sealing resin layer 35. For the conductive pillar 40, for example, a conductive material such as copper is used. For the sealing resin layer 35, for example, a thermosetting resin such as an epoxy resin or a cyanate resin is used. The sealing resin layer 35 defines a mounting surface that faces the mounting substrate 10 when the RF module 20 is mounted on the mounting substrate 10 (FIG. 1).
　複数の導体柱４０は、平面視において反射器パターン２８（図２Ａ）に沿って、等間隔に配列している。すなわち、導体柱４０は、ダイポールアンテナ２３よりも内側に配置されている。導体柱４０には、複数の信号用導体柱４００と複数の接地用導体柱４０１とが含まれる。信号用導体柱４００は、誘電体基板２２（図２Ａ）に形成された導体パターンにより半導体素子３０に接続されている。接地用導体柱４０１は、誘電体基板２２（図２Ａ）内の接地導体層及び反射器パターン２８に接続されている。接地用導体柱４０１は、反射器パターン２８とともに、ダイポールアンテナ２３の反射器として動作する。 The plurality of conductive pillars 40 are arranged at equal intervals along the reflector pattern 28 (FIG. 2A) in plan view. That is, the conductor pillar 40 is disposed on the inner side than the dipole antenna 23. The conductor pillar 40 includes a plurality of signal conductor pillars 400 and a plurality of ground conductor pillars 401. The signal conductor pillar 400 is connected to the semiconductor element 30 by a conductor pattern formed on the dielectric substrate 22 (FIG. 2A). The grounding conductor column 401 is connected to the grounding conductor layer and the reflector pattern 28 in the dielectric substrate 22 (FIG. 2A). The grounding conductor pillar 401 operates as a reflector of the dipole antenna 23 together with the reflector pattern 28.
　図３Ａに、図２Ａの一点鎖線３Ａ－３Ａにおける断面図を示す。誘電体基板２２の底面から複数の導体柱４０が突出している。導体柱４０は、誘電体基板２２の底面を覆う封止樹脂層３５に埋め込まれており、その先端は、封止樹脂層３５の表面（実装面）に露出している。誘電体基板２２内に、複数の導体層が配置されている。図３Ａに示した例では、底面に配置された導体層を含めて６層の導体層が配置されている。 FIG. 3A is a cross-sectional view taken along one-dot chain line 3A-3A in FIG. 2A. A plurality of conductive pillars 40 protrude from the bottom surface of the dielectric substrate 22. The conductive pillar 40 is embedded in a sealing resin layer 35 that covers the bottom surface of the dielectric substrate 22, and the tip thereof is exposed on the surface (mounting surface) of the sealing resin layer 35. A plurality of conductor layers are arranged in the dielectric substrate 22. In the example shown in FIG. 3A, six conductor layers including the conductor layers arranged on the bottom surface are arranged.
　誘電体基板２２の底面に配置された１層目の導体層は、複数のランド４１を含む。ランド４１は、導体柱４０に対応して配置されており、導体柱４０に接続されている。２層目から５層目までの導体層に、接地導体層４４が含まれる。接地導体層４４は、層間を接続するビア導体４２０を介して接地用導体柱４０１に接続されている。 The first conductor layer disposed on the bottom surface of the dielectric substrate 22 includes a plurality of lands 41. The land 41 is arranged corresponding to the conductor pillar 40 and is connected to the conductor pillar 40. The ground conductor layer 44 is included in the second to fifth conductor layers. The ground conductor layer 44 is connected to the ground conductor column 401 via a via conductor 420 connecting the layers.
　層目の導体層が、接地導体層４４の他に、線状導体４３を含む。線状導体４３は、ビア導体４２０及び内層ランド４２１を介して信号用導体柱４００に接続されている。異なる層の導体層を相互に接続する場合、必ずしも内層ランド４２１を設ける必要はない。複数層にまたがるスルーホール内に充填されたビア導体４２０のみで、異なる層の導体層を接続してもよい。本明細書において、厚さ方向に繋がるビア導体４２０及び内層ランド４２１を、層間接続導体４２ということとする。線状導体４３は、上下、及び同一導体層内の接地導体層４４とともに伝送線路を構成する。５層目の導体層が、接地導体層４４の他に、給電線２４を含む。６層目の導体層が、パッチアンテナ２７（図１Ａ）の無給電素子２７０を含む。 The first conductor layer includes a linear conductor 43 in addition to the ground conductor layer 44. The linear conductor 43 is connected to the signal conductor pillar 400 via the via conductor 420 and the inner layer land 421. When different conductor layers are connected to each other, the inner land 421 is not necessarily provided. Different conductor layers may be connected by only via conductors 420 filled in through holes extending over a plurality of layers. In this specification, the via conductor 420 and the inner layer land 421 connected in the thickness direction are referred to as an interlayer connection conductor 42. The linear conductor 43 forms a transmission line together with the upper and lower sides and the ground conductor layer 44 in the same conductor layer. The fifth conductor layer includes the feeder line 24 in addition to the ground conductor layer 44. The sixth conductor layer includes the parasitic element 270 of the patch antenna 27 (FIG. 1A).
　図３Ｂに、図２Ａの一点鎖線３Ｂ－３Ｂにおける断面図を示す。誘電体基板２２の底面に半導体素子３０及び高周波回路部品３１が実装されている。半導体素子３０は、例えば誘電体基板２２の底面に配置されたランド４６に、はんだを用いて表面実装される。ランド４６の一部は接地導体層４４に接続され、他の一部のランド４６は、線状導体４３に接続される。半導体素子３０及び高周波回路部品３１は、封止樹脂層３５に埋め込まれている。 FIG. 3B shows a cross-sectional view taken along one-dot chain line 3B-3B in FIG. 2A. A semiconductor element 30 and a high-frequency circuit component 31 are mounted on the bottom surface of the dielectric substrate 22. The semiconductor element 30 is surface-mounted using solder, for example, on a land 46 disposed on the bottom surface of the dielectric substrate 22. A part of the land 46 is connected to the ground conductor layer 44, and another part of the land 46 is connected to the linear conductor 43. The semiconductor element 30 and the high-frequency circuit component 31 are embedded in the sealing resin layer 35.
　５層目の導体層に、パッチアンテナ２７（図１Ａ）の給電素子２７１、ダイポールアンテナ２３、及び反射器パターン２８が含まれる。給電素子２７１は、その上に配置された無給電素子２７０と電磁結合する。給電素子２７１は、４層目の線状導体４７に接続される。線状導体４７は、周囲の接地導体層４４とともに伝送線路を構成する。 The fifth conductor layer includes the feed element 271 of the patch antenna 27 (FIG. 1A), the dipole antenna 23, and the reflector pattern 28. The feed element 271 is electromagnetically coupled to the parasitic element 270 disposed thereon. The power feeding element 271 is connected to the linear conductor 47 in the fourth layer. The linear conductor 47 and the surrounding ground conductor layer 44 constitute a transmission line.
　図４に、図２Ａ及び図２Ｂの一点鎖線４－４における断面図、及びＲＦモジュール２０が実装された実装基板６０の断面図を示す。信号用導体柱４００が、はんだ６１を介して実装基板６０のランド６２に接続されている。ランド６２は、実装基板６０に配置された伝送線路６３に接続されている。信号用導体柱４００は、１層目のランド４１、及び１層目と３層目との間に配置された層間接続導体４２を介して、３層目の線状導体４３に接続されている。この線状導体４３は、半導体素子３０の信号用端子３００に接続されている。 4 shows a cross-sectional view taken along one-dot chain line 4-4 of FIGS. 2A and 2B and a cross-sectional view of the mounting substrate 60 on which the RF module 20 is mounted. The signal conductor column 400 is connected to the land 62 of the mounting substrate 60 via the solder 61. The land 62 is connected to a transmission line 63 disposed on the mounting substrate 60. The signal conductor column 400 is connected to the third-layer linear conductor 43 via the first-layer land 41 and the interlayer connection conductor 42 disposed between the first and third layers. . The linear conductor 43 is connected to the signal terminal 300 of the semiconductor element 30.
　線状導体４３の下層及び上層には、接地導体層４４が配置されている。線状導体４３、及び上下の接地導体層４４により、伝送線路が構成される。半導体素子３０の接地用端子３０１は接地導体層４４に接続されている。 A ground conductor layer 44 is disposed below and above the linear conductor 43. The linear conductor 43 and the upper and lower ground conductor layers 44 constitute a transmission line. The ground terminal 301 of the semiconductor element 30 is connected to the ground conductor layer 44.
　５層目の導体層に、パッチアンテナ２７（図２Ａ）の給電素子２７１、反射器パターン２８、及びダイポールアンテナ２３が含まれる。６層目の導体層に、パッチアンテナ２７（図２Ａ）の無給電素子２７０が含まれる。 The fifth conductor layer includes the feeding element 271 of the patch antenna 27 (FIG. 2A), the reflector pattern 28, and the dipole antenna 23. A parasitic element 270 of the patch antenna 27 (FIG. 2A) is included in the sixth conductor layer.
　図５Ａに、図４に示された下から２層目の導体層の平断面図を示す。下から２層目の導体層に、接地導体層４４及び内層ランド４２１が含まれる。ビア導体４２０及び内層ランド４２１からなる層間接続導体４２が、信号用導体柱４００に接続されている。接地導体層４４に、クリアランスホール４８、４９が設けられている。クリアランスホール４８は、信号用導体柱４００が配置された位置に配置されている。クリアランスホール４８により、層間接続導体４２が接地導体層４４から絶縁される。 FIG. 5A shows a plan sectional view of the second conductor layer from the bottom shown in FIG. The ground conductor layer 44 and the inner land 421 are included in the second conductor layer from the bottom. An interlayer connection conductor 42 including a via conductor 420 and an inner layer land 421 is connected to the signal conductor pillar 400. Clearance holes 48 and 49 are provided in the ground conductor layer 44. The clearance hole 48 is disposed at a position where the signal conductor column 400 is disposed. The interlayer connection conductor 42 is insulated from the ground conductor layer 44 by the clearance hole 48.
　信号用導体柱４００は、層間接続導体４２より太く、平面視において層間接続導体４２を内包する。一例として、信号用導体柱４００の直径は、層間接続導体４２の最大直径の２倍から４倍の範囲である。クリアランスホール４８は、層間接続導体４２のみならず、層間接続導体４２より大きな信号用導体柱４００をも内包する。クリアランスホール４８の外周と、信号用導体柱４００の外周との最短距離をＷで表す。図４に示した断面図においては、下から２層目の接地導体層４４の左端と、信号用導体柱４００の右側の側面との間隔が最短距離Ｗに相当する。 The signal conductor pillar 400 is thicker than the interlayer connection conductor 42 and includes the interlayer connection conductor 42 in a plan view. As an example, the diameter of the signal conductor post 400 is in the range of 2 to 4 times the maximum diameter of the interlayer connection conductor 42. The clearance hole 48 includes not only the interlayer connection conductor 42 but also a signal conductor column 400 larger than the interlayer connection conductor 42. The shortest distance between the outer periphery of the clearance hole 48 and the outer periphery of the signal conductor column 400 is represented by W. In the cross-sectional view shown in FIG. 4, the distance between the left end of the second ground conductor layer 44 from the bottom and the right side surface of the signal conductor post 400 corresponds to the shortest distance W.
　信号用導体柱４００から接地導体層４４の外周までの距離と、クリアランスホール４８の大きさとの関係で、クリアランスホール４８が接地導体層４４の外周に繋がる場合がある。図５Ａでは、クリアランスホール４８が接地導体層４４の外周に繋がっている例が示されている。クリアランスホール４８の平面形状は、必ずしも円形である必要はない。接地導体層４４の外周から内部に向って侵入するＵ字状の切り込みを、クリアランスホール４８としてもよい。信号用導体柱４００が、接地導体層４４の外周から離れて配置される場合には、クリアランスホール４８は接地導体層４４の外周から離れ、接地導体層４４の内部に配置される。 The clearance hole 48 may be connected to the outer periphery of the ground conductor layer 44 depending on the relationship between the distance from the signal conductor pillar 400 to the outer periphery of the ground conductor layer 44 and the size of the clearance hole 48. FIG. 5A shows an example in which the clearance hole 48 is connected to the outer periphery of the ground conductor layer 44. The planar shape of the clearance hole 48 is not necessarily circular. A U-shaped notch entering from the outer periphery of the ground conductor layer 44 toward the inside may be used as the clearance hole 48. When the signal conductor column 400 is disposed away from the outer periphery of the ground conductor layer 44, the clearance hole 48 is disposed away from the outer periphery of the ground conductor layer 44 and disposed inside the ground conductor layer 44.
　信号用導体柱４００の両隣に、接地用導体柱４０１が配置されている。さらに、信号用導体柱４００から１つ置いて隣にも接地用導体柱４０１が配置されている。接地用導体柱４０１は、ビア導体４２０を介して接地導体層４４に接続されている。接地用導体柱４０１の太さは、信号用導体柱４００の太さを同一である。信号用導体柱４００及び接地用導体柱４０１を含む複数の導体柱４０（図２Ｂ）は、等間隔で配列されている。各導体柱４０に接続されるビア導体４２０も、等間隔に配列されている。信号用導体柱４００から、隣の接地用導体柱４０１に接続されているビア導体４２０までの距離をＷＢで表す。最短距離Ｗを間隔ＷＢより大きくすると、接地用導体柱４０１に接続されたビア導体４２０を、接地導体層４４に接続することが困難になる。接地用導体柱４０１を接地導体層４４に接続するために、最短距離Ｗは間隔ＷＢ以下にすることが好ましい。 The grounding conductor column 401 is arranged on both sides of the signal conductor column 400. Further, one grounding conductor pillar 401 is arranged adjacent to the signal conductor pillar 400. The grounding conductor column 401 is connected to the grounding conductor layer 44 via the via conductor 420. The thickness of the grounding conductor column 401 is the same as that of the signal conductor column 400. A plurality of conductor pillars 40 (FIG. 2B) including the signal conductor pillars 400 and the ground conductor pillars 401 are arranged at equal intervals. Via conductors 420 connected to the respective conductor pillars 40 are also arranged at equal intervals. The distance from the signal conductor column 400 to the via conductor 420 connected to the adjacent ground conductor column 401 is represented by WB. When the shortest distance W is larger than the interval WB, it becomes difficult to connect the via conductor 420 connected to the grounding conductor column 401 to the grounding conductor layer 44. In order to connect the grounding conductor column 401 to the grounding conductor layer 44, the shortest distance W is preferably set to be equal to or less than the interval WB.
　クリアランスホール４９は、半導体素子３０（図４）の信号用端子３００に対応する位置に配置されている。クリアランスホール４９は、信号用導体柱４００の位置に設けられたクリアランスホール４８よりも小さい。半導体素子３０の接地用端子３０１は接地導体層４４に接続される。 The clearance hole 49 is disposed at a position corresponding to the signal terminal 300 of the semiconductor element 30 (FIG. 4). The clearance hole 49 is smaller than the clearance hole 48 provided at the position of the signal conductor post 400. The ground terminal 301 of the semiconductor element 30 is connected to the ground conductor layer 44.
　図５Ｂに、図４に示された下から３層目の導体層の平断面図を示す。下から３層目の導体層に接地導体層４４及び線状導体４３が含まれる。線状導体４３の一端は、層間接続導体４２を介して信号用導体柱４００に接続されており、他端は半導体素子３０（図４）の信号用端子３００に接続されている。線状導体４３の両側には、スリットを介して接地導体層４４が配置されている。線状導体４３と接地導体層４４とにより、コプレーナ線路が構成される。さらに、線状導体４３の上層及び下層の接地導体層４４（図４）を含めて、グランデッドコプレーナ線路が構成される。 FIG. 5B shows a plan sectional view of the third conductor layer from the bottom shown in FIG. The ground conductor layer 44 and the linear conductor 43 are included in the third conductor layer from the bottom. One end of the linear conductor 43 is connected to the signal conductor pillar 400 via the interlayer connection conductor 42, and the other end is connected to the signal terminal 300 of the semiconductor element 30 (FIG. 4). On both sides of the linear conductor 43, a ground conductor layer 44 is disposed via a slit. The linear conductor 43 and the ground conductor layer 44 constitute a coplanar line. Further, a grounded coplanar line is configured including the upper and lower ground conductor layers 44 (FIG. 4) of the linear conductor 43.
　図４、図５Ａ及び図５Ｂに示したように、線状導体４３及び接地導体層４４を含む伝送線路が、信号用導体柱４００と半導体素子３０とを接続する。実装基板６０の伝送線路６３（図４）が、信号用導体柱４００を介して、線状導体４３を含むグランデットコプレーナ線路に電磁結合する。 As shown in FIG. 4, FIG. 5A and FIG. 5B, the transmission line including the linear conductor 43 and the ground conductor layer 44 connects the signal conductor column 400 and the semiconductor element 30. The transmission line 63 (FIG. 4) of the mounting substrate 60 is electromagnetically coupled to the grand coplanar line including the linear conductor 43 via the signal conductor post 400.
　次に、図４及び図６を参照しながら、上記実施例によるＲＦモジュール２０の優れた効果について説明する。 Next, the excellent effects of the RF module 20 according to the above embodiment will be described with reference to FIGS.
　図６に、比較例によるＲＦモジュール２０の断面図を示す。図６に示した断面図は、実施例によるＲＦモジュール２０の図４に示した断面図に対応する。図６に示した比較例では、信号用導体柱４００の位置に設けられたクリアランスホール４８と、半導体素子３０の信号用端子３００の位置に設けられたクリアランスホール４９とが、ほぼ同じ大きさである。一般的には、同一の導体層内のクリアランスホール４８、４９は、この比較例のように、ほぼ同一の大きさを有する。 FIG. 6 shows a cross-sectional view of the RF module 20 according to the comparative example. The cross-sectional view shown in FIG. 6 corresponds to the cross-sectional view shown in FIG. 4 of the RF module 20 according to the embodiment. In the comparative example shown in FIG. 6, the clearance hole 48 provided at the position of the signal conductor column 400 and the clearance hole 49 provided at the position of the signal terminal 300 of the semiconductor element 30 have substantially the same size. is there. In general, the clearance holes 48 and 49 in the same conductor layer have substantially the same size as in this comparative example.
　信号用導体柱４００の平面寸法が、層間接続導体４２の平面寸法よりも大きい。このため、下から２層目の接地導体層４４が、平面視において信号用導体柱４００と重なる。両者が重なることにより、両者の間の寄生容量Ｃが大きくなる。信号用導体柱４００と接地導体層４４との間の寄生容量Ｃが大きくなると、実装基板６０の伝送線路６３と、ＲＦモジュール２０の線状導体４３を含むグランデッドコプレーナ線路との結合箇所において、伝送線路の特性インピーダンスが乱れる。 The plane dimension of the signal conductor post 400 is larger than the plane dimension of the interlayer connection conductor 42. Therefore, the second ground conductor layer 44 from the bottom overlaps the signal conductor pillar 400 in plan view. When they overlap, the parasitic capacitance C between them increases. When the parasitic capacitance C between the signal conductor column 400 and the ground conductor layer 44 is increased, at the coupling point between the transmission line 63 of the mounting substrate 60 and the grounded coplanar line including the linear conductor 43 of the RF module 20, The characteristic impedance of the transmission line is disturbed.
　これに対し、図４に示した実施例においては、平面視においてクリアランスホール４８（図５Ａ）が信号用導体柱４００を内包する。このため、下から２層目の接地導体層４４が、信号用導体柱４００と重ならない。両者の間の寄生容量Ｃは、図６に示した比較例の場合に比べて小さい。実施例においては、寄生容量Ｃを小さくできるため、伝送線路の特性インピーダンスの乱れを抑制することができる。 On the other hand, in the embodiment shown in FIG. 4, the clearance hole 48 (FIG. 5A) encloses the signal conductor post 400 in plan view. Therefore, the second ground conductor layer 44 from the bottom does not overlap the signal conductor pillar 400. The parasitic capacitance C between the two is smaller than that in the comparative example shown in FIG. In the embodiment, since the parasitic capacitance C can be reduced, the disturbance of the characteristic impedance of the transmission line can be suppressed.
　製造工程における位置合わせマージンを考慮して、信号用導体柱４００から接地導体層４４までの面内方向の最短距離Ｗ（図４、図５Ａ）を、信号用導体柱４００から隣の接地用導体柱４０１までの間隔の１／４以上とすることが好ましい。 In consideration of the alignment margin in the manufacturing process, the shortest distance W (FIGS. 4 and 5A) in the in-plane direction from the signal conductor column 400 to the ground conductor layer 44 is determined from the signal conductor column 400 and the adjacent ground conductor. It is preferable to set it to 1/4 or more of the distance to the column 401.
　次に、図７Ａ及び図７Ｂを参照しながら、上記実施例によるＲＦモジュール２０の他の優れた効果について説明する。 Next, other excellent effects of the RF module 20 according to the above embodiment will be described with reference to FIGS. 7A and 7B.
　図７Ａに、比較例によるＲＦモジュール２０の断面図を示す。比較例においては、信号用導体柱４００が連続して配列している。信号用導体柱４００の間に、接地用導体柱４０１が配置されていない。信号用導体柱４００に静電気を帯びた帯電物５０が近づくと、帯電物５０と信号用導体柱４００との間で静電気による放電が発生する。信号用導体柱４００は、半導体素子３０（図３Ｂ）に接続されているため、半導体素子３０が静電気によって破壊される場合がある。 FIG. 7A shows a cross-sectional view of the RF module 20 according to the comparative example. In the comparative example, the signal conductor columns 400 are continuously arranged. The grounding conductor column 401 is not disposed between the signal conductor columns 400. When the charged object 50 charged with static electricity approaches the signal conductor column 400, a discharge due to static electricity occurs between the charged object 50 and the signal conductor column 400. Since the signal conductor pillar 400 is connected to the semiconductor element 30 (FIG. 3B), the semiconductor element 30 may be destroyed by static electricity.
　図７Ｂに、実施例によるＲＦモジュール２０の断面図を示す。実施例においては、信号用導体柱４００の両隣に接地用導体柱４０１が配置されている。さらに、信号用導体柱４００から１つ置いて、さらに接地用導体柱４０１が配置されている。すなわち、信号用導体柱４００の両側に、それぞれ少なくとも２つの接地用導体柱４０１が配置されている。 FIG. 7B shows a cross-sectional view of the RF module 20 according to the embodiment. In the embodiment, grounding conductor columns 401 are arranged on both sides of the signal conductor column 400. Further, one grounding conductor pillar 401 is disposed from one of the signal conductor pillars 400. That is, at least two grounding conductor columns 401 are arranged on both sides of the signal conductor column 400, respectively.
　接地用導体柱４０１は、信号用導体柱４００が接続されている線状導体４３に比べて大きな接地導体層４４に接続されている。このため、帯電物５０が信号用導体柱４００及び接地用導体柱４０１に近づくと、帯電物５０と、接地用導体柱４０１との間で放電が生じやすい。その結果、信号用導体柱４００への放電が回避される。 The grounding conductor column 401 is connected to a larger grounding conductor layer 44 than the linear conductor 43 to which the signal conductor column 400 is connected. For this reason, when the charged object 50 approaches the signal conductor pillar 400 and the ground conductor pillar 401, a discharge is likely to occur between the charged object 50 and the ground conductor pillar 401. As a result, discharge to the signal conductor column 400 is avoided.
　上述のように、実施例によるＲＦモジュール２０においては、信号用導体柱４００への放電が生じにくいため、図７Ａに示した比較例によるＲＦモジュール２０に比べて、静電破壊が生じにくい。 As described above, in the RF module 20 according to the embodiment, since the discharge to the signal conductor column 400 is less likely to occur, electrostatic breakdown is less likely to occur compared to the RF module 20 according to the comparative example illustrated in FIG. 7A.
　図８Ａ及び図８Ｂに、ＩＦモジュール７０（図１）の断面図を示す。ＩＦモジュール７０も、ＲＦモジュール２０と同様に、誘電体基板８２、及び誘電体基板８２の底面から突出する導体柱９０、及び底面に実装された半導体素子８０を含む。図８Ａは、導体柱９０が直線上に並んでいる部分の断面図を示し、図８Ｂは、半導体素子８０が配置された部分の断面図を示す。導体柱９０には、複数の信号用導体柱９００及び複数の接地用導体柱９０１が含まれる。複数の信号用導体柱９００及び複数の接地用導体柱９０１の配列の順番は、ＲＦモジュール２０の信号用導体柱４００及び接地用導体柱４０１の配列の順番と同様である。誘電体基板８２の上面に、主に電源系の部品８３が実装されている。 8A and 8B are cross-sectional views of the IF module 70 (FIG. 1). Similarly to the RF module 20, the IF module 70 also includes a dielectric substrate 82, a conductor post 90 protruding from the bottom surface of the dielectric substrate 82, and a semiconductor element 80 mounted on the bottom surface. 8A shows a cross-sectional view of a portion where the conductor pillars 90 are arranged in a straight line, and FIG. 8B shows a cross-sectional view of a portion where the semiconductor element 80 is disposed. The conductor pillar 90 includes a plurality of signal conductor pillars 900 and a plurality of ground conductor pillars 901. The order of arrangement of the plurality of signal conductor columns 900 and the plurality of ground conductor columns 901 is the same as the order of arrangement of the signal conductor columns 400 and the ground conductor columns 401 of the RF module 20. On the upper surface of the dielectric substrate 82, a power supply system component 83 is mainly mounted.
　誘電体基板８２の底面を封止樹脂層８５が被覆し、上面を封止樹脂層８６が被覆する。半導体素子８０及び導体柱９０が、封止樹脂層８５に埋め込まれている。導体柱９０の先端は、封止樹脂層８５の表面に露出している。電源系の部品８３は、封止樹脂層８６に埋め込まれている。 The bottom surface of the dielectric substrate 82 is covered with the sealing resin layer 85, and the top surface is covered with the sealing resin layer 86. The semiconductor element 80 and the conductor pillar 90 are embedded in the sealing resin layer 85. The tips of the conductor columns 90 are exposed on the surface of the sealing resin layer 85. The power supply system component 83 is embedded in the sealing resin layer 86.
　誘電体基板８２に、底面の導体層を含めて４層の導体層が配置されている。底面の導体層（１層目の導体層）、２層目から４層目の導体層に、接地導体層９２が含まれる。１層目の導体層に、さらに、複数のランド９１、９５が含まれる。複数のランド９１は、それぞれ導体柱９０に接続される。複数のランド９５は、それぞれ半導体素子８０に接続される。 On the dielectric substrate 82, four conductor layers including the bottom conductor layer are arranged. The ground conductor layer 92 is included in the bottom conductor layer (first conductor layer) and the second to fourth conductor layers. The first conductor layer further includes a plurality of lands 91 and 95. The plurality of lands 91 are each connected to the conductor pillar 90. The plurality of lands 95 are each connected to the semiconductor element 80.
　２層目の導体層に、接地導体層９２の他に線状導体９３が含まれる。４層目の導体層に、接地導体層９２の他に配線９４が含まれる。配線９４は、電源系の部品８３に接続される。線状導体９３の一端は、層間接続導体９９を介して信号用導体柱９００に接続される。線状導体９３は、上下の接地導体層９２とともに、伝送線路を構成する。この伝送線路は、信号用導体柱９００と半導体素子８０とを接続する。 The second conductor layer includes a linear conductor 93 in addition to the ground conductor layer 92. The fourth conductor layer includes a wiring 94 in addition to the ground conductor layer 92. The wiring 94 is connected to the power supply system component 83. One end of the linear conductor 93 is connected to the signal conductor post 900 via the interlayer connection conductor 99. The linear conductor 93 constitutes a transmission line together with the upper and lower ground conductor layers 92. This transmission line connects the signal conductor pillar 900 and the semiconductor element 80.
　図９Ａに、図８Ａ及び図８Ｂに示した１層目の導体層の平断面図を示す。１層目の導体層に、ランド９１、９５、及び接地導体層９２が含まれる。導体柱９０（図８Ａ、図８Ｂ）用のランド９１は、接地導体層９２の外側に配置されている。半導体素子８０用のランド９５は、接地導体層９２の内部に配置されている。接地導体層９２に、ランド９５と絶縁するためのクリアランスホール９６が設けられている。 FIG. 9A is a plan sectional view of the first conductor layer shown in FIGS. 8A and 8B. Lands 91 and 95 and a ground conductor layer 92 are included in the first conductor layer. The land 91 for the conductor pillar 90 (FIGS. 8A and 8B) is disposed outside the ground conductor layer 92. The land 95 for the semiconductor element 80 is disposed inside the ground conductor layer 92. A clearance hole 96 for insulating the land 95 is provided in the ground conductor layer 92.
　図９Ｂに、図８Ａ及び図８Ｂに示した２層目の導体層の平断面図を示す。２層目の導体層に、接地導体層９２及び線状導体９３が含まれる。半導体素子８０用のランド９５（図９Ａ）の位置に、クリアランスホール９８が設けられている。信号用導体柱９００の位置に、クリアランスホール９７が設けられている。平面視において、クリアランスホール９７は信号用導体柱９００を内包する。クリアランスホール９７と信号用導体柱９００との位置関係は、ＲＦモジュール２０のクリアランスホール４８と信号用導体柱４００との位置関係と同様である。すなわち、２層目の接地導体層９２は、信号用導体柱９００と重ならない。このため、信号用導体柱９００と接地導体層９２との間の寄生容量を小さくすることができる。 FIG. 9B is a plan sectional view of the second conductor layer shown in FIGS. 8A and 8B. A ground conductor layer 92 and a linear conductor 93 are included in the second conductor layer. A clearance hole 98 is provided at the position of the land 95 (FIG. 9A) for the semiconductor element 80. A clearance hole 97 is provided at the position of the signal conductor post 900. In plan view, the clearance hole 97 includes the signal conductor column 900. The positional relationship between the clearance hole 97 and the signal conductor column 900 is the same as the positional relationship between the clearance hole 48 of the RF module 20 and the signal conductor column 400. That is, the second ground conductor layer 92 does not overlap the signal conductor pillar 900. For this reason, the parasitic capacitance between the signal conductor pillar 900 and the ground conductor layer 92 can be reduced.
　図９Ｃに、図８Ａ及び図８Ｂに示した３層目の導体層の平断面図を示す。３層目の導体層に接地導体層９２が含まれる。 FIG. 9C shows a plan sectional view of the third conductor layer shown in FIGS. 8A and 8B. The ground conductor layer 92 is included in the third conductor layer.
　線状導体９３は、同一導体層に含まれる接地導体層９２（図９Ｂ）、及び上下の接地導体層９２（図９Ａ、図９Ｃ）とともに、グランデッドコプレーナ線路を構成する。信号用導体柱９００と、接地導体層９２との間の寄生容量が小さいため、実装基板６０（図４）の伝送線路と、線状導体９３を中心導体とするグランデッドコプレーナ線路との結合箇所における特性インピーダンスの乱れを抑制することができる。 The linear conductor 93 constitutes a grounded coplanar line together with the ground conductor layer 92 (FIG. 9B) and the upper and lower ground conductor layers 92 (FIGS. 9A and 9C) included in the same conductor layer. Since the parasitic capacitance between the signal conductor pillar 900 and the ground conductor layer 92 is small, the coupling point between the transmission line of the mounting substrate 60 (FIG. 4) and the grounded coplanar line having the linear conductor 93 as the central conductor. Disturbances in characteristic impedance can be suppressed.
　上述のように、実施例においては、図１に示したＩＦモジュール７０とＲＦモジュール２０とを接続する伝送線路の特性インピーダンスの乱れを抑制することができる。このため、ＩＦモジュール７０とＲＦモジュール２０との間で、効率的にＩＦ信号及びＬＯ信号の伝送を行うことができる。 As described above, in the embodiment, the disturbance of the characteristic impedance of the transmission line connecting the IF module 70 and the RF module 20 shown in FIG. 1 can be suppressed. For this reason, the IF signal and the LO signal can be efficiently transmitted between the IF module 70 and the RF module 20.
　本発明は上述の実施例に制限されるものではない。例えば、種々の変更、改良、組み合わせ等が可能なことは当業者に自明であろう。 The present invention is not limited to the above-described embodiments. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
１０　実装基板
２０　無線周波数モジュール（ＲＦモジュール）
２２　誘電体基板
２３　ダイポールアンテナ
２４　給電線
２５　バラン（平衡不平衡変換器）
２６　接続点
２７　パッチアンテナ
２８　反射器パターン
２９　接続点
３０　無線通信用の半導体素子
３１　高周波回路部品
３５　封止樹脂層
４０　導体柱
４１　ランド
４２　層間接続導体
４３　線状導体
４４　接地導体層
４６　ランド
４７　線状導体
４８、４９　クリアランスホール
５０　静電気を帯びた物体
６０　実装基板
６１　はんだ
６２　ランド
６３　伝送線路
７０　中間周波数モジュール（ＩＦモジュール）
８０　無線通信用の半導体素子
８１　局部発振器
８２　誘電体基板
８３　電源系の部品
８５、８６　封止樹脂層
９０　導体柱
９１　ランド
９２　接地導体層
９３　線状導体
９４　配線
９５　ランド
９６、９７、９８　クリアランスホール
９９　ビア導体
２７０　パッチアンテナの無給電素子
２７１　パッチアンテナの給電素子
３００　信号用端子
３０１　接地用端子
４００　信号用導体柱
４０１　接地用導体柱
４２０　ビア導体
４２１　内層ランド
９００　信号用導体柱
９０１　接地用導体柱 10 Mounting Board 20 Radio Frequency Module (RF Module)
22 Dielectric substrate 23 Dipole antenna 24 Feed line 25 Balun (balance-unbalance converter)
26 Connection point 27 Patch antenna 28 Reflector pattern 29 Connection point 30 Semiconductor element 31 for wireless communication High frequency circuit component 35 Sealing resin layer 40 Conductor column 41 Land 42 Interlayer connection conductor 43 Linear conductor 44 Grounding conductor layer 46 Land 47 Line Conductor 48, 49 Clearance hole 50 Static object 60 Mounting substrate 61 Solder 62 Land 63 Transmission line 70 Intermediate frequency module (IF module)
80 Semiconductor Device 81 for Wireless Communication Local Oscillator 82 Dielectric Substrate 83 Power Supply Components 85 and 86 Sealing Resin Layer 90 Conductor Pillar 91 Land 92 Grounding Conductor Layer 93 Linear Conductor 94 Wiring 95 Land 96, 97, 98 Clearance Hole 99 Via conductor 270 Patch antenna parasitic element 271 Patch antenna power supply element 300 Signal terminal 301 Ground terminal 400 Signal conductor pillar 401 Ground conductor pillar 420 Via conductor 421 Inner layer land 900 Signal conductor pillar 901 Ground conductor pillar

Claims (8)

  1. 　誘電体基板と、
    　前記誘電体基板に実装された無線通信用の半導体素子と、
    　前記誘電体基板の底面から突出し、先端において実装基板に接続される複数の信号用導体柱及び複数の接地用導体柱と、
    　前記誘電体基板に配置され、前記信号用導体柱と前記半導体素子とを接続する伝送線路であって、前記誘電体基板の面内方向に延びる線状導体、及び前記線状導体と対を成す接地導体層を含む前記伝送線路と、
    　前記線状導体と前記信号用導体柱とを厚さ方向に接続する第１の層間接続導体と
    を含み、
    　前記信号用導体柱は、前記第１の層間接続導体より太く、
    　前記接地導体層の、前記第１の層間接続導体に対応する位置にクリアランスホールが設けられており、前記クリアランスホールは、平面視において前記信号用導体柱を内包する無線通信モジュール。     A dielectric substrate;
    A semiconductor element for wireless communication mounted on the dielectric substrate;
    A plurality of signal conductor pillars and a plurality of ground conductor pillars protruding from the bottom surface of the dielectric substrate and connected to the mounting substrate at the tip;
    A transmission line disposed on the dielectric substrate and connecting the signal conductor column and the semiconductor element, and is paired with a linear conductor extending in an in-plane direction of the dielectric substrate, and the linear conductor The transmission line including a ground conductor layer;
    Including a first interlayer connection conductor for connecting the linear conductor and the signal conductor pillar in the thickness direction;
    The signal conductor pillar is thicker than the first interlayer connection conductor,
    A clearance hole is provided in the ground conductor layer at a position corresponding to the first interlayer connection conductor, and the clearance hole includes the signal conductor pillar in a plan view.
  2. 　前記クリアランスホールが設けられている前記接地導体層は、前記誘電体基板の厚さ方向に関して、前記線状導体と前記信号用導体柱との間に配置されている請求項１に記載の無線通信モジュール。 2. The wireless communication according to claim 1, wherein the ground conductor layer in which the clearance hole is provided is disposed between the linear conductor and the signal conductor column in a thickness direction of the dielectric substrate. module.
  3. 　前記クリアランスホールが設けられている前記接地導体層は、前記線状導体と同一の層に配置されている請求項１に記載の無線通信モジュール。 The radio communication module according to claim 1, wherein the ground conductor layer in which the clearance hole is provided is disposed in the same layer as the linear conductor.
  4. 　前記クリアランスホールは、前記接地導体層の外周に繋がっている請求項１乃至３のいずれか１項に記載の無線通信モジュール。 4. The wireless communication module according to claim 1, wherein the clearance hole is connected to an outer periphery of the ground conductor layer.
  5. 　さらに、前記接地用導体柱と前記接地導体層とを接続する第２の層間接続導体を有する請求項１乃至４のいずれか１項に記載の無線通信モジュール。 The wireless communication module according to any one of claims 1 to 4, further comprising a second interlayer connection conductor that connects the grounding conductor post and the grounding conductor layer.
  6. 　前記信号用導体柱及び前記接地用導体柱は、前記誘電体基板の縁の内側に、前記縁に沿って並んでおり、前記信号用導体柱の両隣に、前記接地用導体柱が配置されている請求項１乃至５のいずれか１項に記載の無線通信モジュール。 The signal conductor pillar and the ground conductor pillar are arranged along the edge inside the edge of the dielectric substrate, and the ground conductor pillar is arranged on both sides of the signal conductor pillar. The wireless communication module according to any one of claims 1 to 5.
  7. 　前記信号用導体柱から１つ置いて隣にも、前記接地用導体柱が配置されている請求項６に記載の無線通信モジュール。 The wireless communication module according to claim 6, wherein the grounding conductor pillar is disposed adjacent to one of the signal conductor pillars.
  8. 　前記信号用導体柱から前記接地導体層までの面内方向の最短距離が、前記信号用導体柱から隣の前記接地用導体柱までの間隔の１／４以上である請求項６または７に記載の無線通信モジュール。 8. The shortest distance in the in-plane direction from the signal conductor column to the ground conductor layer is ¼ or more of an interval from the signal conductor column to the adjacent ground conductor column. 9. Wireless communication module.
PCT/JP2015/078917 2014-10-29 2015-10-13 Wireless communication module WO2016067908A1 (en)

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