WO2016065633A1 - 一种曲线拟合电路、模拟预失真器和射频信号发射机 - Google Patents

一种曲线拟合电路、模拟预失真器和射频信号发射机 Download PDF

Info

Publication number
WO2016065633A1
WO2016065633A1 PCT/CN2014/090095 CN2014090095W WO2016065633A1 WO 2016065633 A1 WO2016065633 A1 WO 2016065633A1 CN 2014090095 W CN2014090095 W CN 2014090095W WO 2016065633 A1 WO2016065633 A1 WO 2016065633A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
signal
output
amplitude
resistor
Prior art date
Application number
PCT/CN2014/090095
Other languages
English (en)
French (fr)
Inventor
黄伟
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201480024986.4A priority Critical patent/CN105745641B/zh
Priority to JP2017523242A priority patent/JP6442053B2/ja
Priority to KR1020177012917A priority patent/KR101926665B1/ko
Priority to EP14904793.8A priority patent/EP3197045B1/en
Priority to PCT/CN2014/090095 priority patent/WO2016065633A1/zh
Publication of WO2016065633A1 publication Critical patent/WO2016065633A1/zh
Priority to US15/581,823 priority patent/US10141896B2/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
    • H03F1/3247—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits using feedback acting on predistortion circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/17—Function evaluation by approximation methods, e.g. inter- or extrapolation, smoothing, least mean square method
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
    • H03F1/3258—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits based on polynomial terms
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/102—A non-specified detector of a signal envelope being used in an amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a curve fitting circuit, an analog predistorter, and a radio frequency signal transmitter.
  • a multi-input RF power amplifier is a power amplifier with two or more RF signal inputs and a single output.
  • Multi-input RF power amplifiers offer better performance than traditional single-input, single-output RF power amplifiers, and multi-input RF power amplifiers allow multi-input RF power by adjusting the amplitude and phase relationships between inputs. The performance of the amplifier is even better, so multi-input RF power amplifiers are gaining more and more attention.
  • the current transmitter often uses a radio frequency decomposition scheme to simplify the structure of the transmitter.
  • the structure of the transmitter using the radio frequency decomposition scheme can be as shown in FIG. 1: the signal component separation module 15 receives the orthogonal modulator. 14 output signal, and the received signal is decomposed into two paths, and output to two driving amplifiers 16.
  • the transmitter shown in FIG. 1 further includes a digital predistortion module 11, a quadrature modulation compensation module 12, and digital to analog conversion. Module 13, RF power amplifier 17, down converter 18 and analog to digital conversion module 19.
  • the signal component separation module includes an envelope detector 21, a quadrature signal separator 22, a multiplier 23, and a curve fitting circuit 24, as shown in FIG.
  • the design of the curve fitting circuit 24 is the key in the signal component separation module.
  • the function of the curve fitting circuit is to convert the input signal represented by the real number into the output signal represented by the complex number. Therefore, since the curve fitting circuit uses the circuit to realize the mathematical calculation This will inevitably have errors, so this requires the circuit structure to have certain tolerance characteristics.
  • the usual method for realizing the function of the curve fitting circuit is a polynomial fitting.
  • the curve fitting circuit outputs the signal y after receiving the signal x.
  • Embodiments of the present invention provide a curve fitting circuit, an analog predistorter, and a radio frequency signal transmitter, which are used to solve the problem of using a polynomial fitting in the decomposition of a radio frequency signal, often using a high order polynomial.
  • the result is very sensitive to high-order coefficients and quantization noise.
  • a curve fitting circuit comprising: n segment processing circuits and q first adding circuits; n is greater than or equal to 2; q is a natural number;
  • Each segment processing circuit receives an input signal, and intercepts a portion of the input signal according to a preset rule, and generates a to-be-processed signal according to the intercepted portion, and generates a q according to the to-be-processed signal by a polynomial fitting method. Output signals; wherein the portions intercepted by different segment processing circuits are not identical;
  • Each first adding circuit receives one of the q output signals of each segment processing circuit, and obtains an output signal of the curve fitting circuit according to the sum of the received n signals; wherein, the first difference
  • the summing circuit receives different ones of the q output signals of the same segmentation processing circuit.
  • each of the first adding circuits is specifically configured to:
  • each segment processing circuit is specifically configured to:
  • the signal to be processed generates q output signals.
  • each segment processing circuit is specifically configured to:
  • each segment processing circuit includes a limiting circuit, a polynomial operation circuit, and a weighting circuit
  • the limiting circuit receives an input signal and generates a magnitude along with the input signal when an amplitude of the input signal is within a preset range of amplitude of a segment processing circuit in which the limiting circuit is located a signal whose amplitude is monotonously changed and outputted; and when the amplitude of the input signal is less than a minimum value of the preset range of the amplitude, outputting a first preset value; and the amplitude of the input signal is greater than And outputting, by the maximum value of the preset range, the second preset value; wherein the first preset value is equal to the amplitude of the input signal is generated when the amplitude is the minimum value of the preset range of the amplitude The amplitude of the signal to be processed, the second preset value being equal to the amplitude of the signal to be processed generated when the amplitude of the input signal is the maximum value of the preset range of the amplitude;
  • the polynomial operation circuit generates a value of each order calculation item whose order is not higher than a preset order according to the amplitude of the signal to be processed outputted by the limiter circuit;
  • the weighting circuit receives the values of the calculation items of the respective orders, and generates an output signal of the segmentation processing circuit according to the coefficients of the calculation terms of the respective orders in the weighting coefficients and the values of the calculation items of the respective orders.
  • the limiting circuit includes a pre-adjusting circuit and a limiting amplifier circuit
  • the pre-adjustment circuit receives an input signal, and amplifies the input signal and/or performs offset adjustment on the input signal to output;
  • the limiting amplifier circuit receives a signal output by the preconditioning circuit, and generates a magnitude along with a magnitude of a signal output by the preconditioning circuit within a limiting range of the limiting amplifier circuit a signal to be processed whose amplitude of the signal outputted by the pre-adjustment circuit monotonously changes is output; and when the amplitude of the signal output by the pre-conditioning circuit is smaller than a minimum value of the limiting range of the limiting amplifier circuit, the output Determining a first preset value; and outputting the second preset value when a magnitude of a signal output by the preconditioning circuit is greater than a maximum value of a limiting range of the limiting amplifier circuit;
  • the limiting amplifier circuit includes a first triode, a second triode, a third triode, and a fourth a triode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor;
  • One end of the first resistor receives a clipping signal, and the other end of the first resistor is respectively connected to a collector of the first triode, a base of the first triode, and a base of the second triode.
  • the emitter of the first transistor is grounded through a second resistor, the emitter of the second transistor is grounded through a third resistor, and the collector output of the second transistor and the amplitude of the limiting signal Value related signal;
  • a base of the third transistor receives a first input signal
  • a base of the fourth transistor receives a second input signal
  • a collector of the third transistor passes through a fourth resistor and a fifth Resistingly connecting the collector of the fourth transistor, the emitter of the third transistor sequentially connecting the emitter of the fourth transistor through a sixth resistor and a seventh resistor, the sixth resistor and The seventh resistor is connected
  • One end receives a signal related to the amplitude of the limiter signal, and the signal of the end of the fourth resistor connected to the collector of the third transistor is the two signals output by the limiting amplifier circuit a signal, the signal of one end of the fifth resistor connected to the collector of the fourth transistor is the other of the two signals output by the limiting amplifier circuit;
  • the difference between the first input signal and the second input signal is equal to the signal output by the pre-conditioning circuit; the difference between the two signals output by the limiting amplifier circuit is a limiting circuit in which the limiting amplifier circuit is located The pending signal to be output.
  • the preset order is m
  • the polynomial operation circuit includes m-1 multipliers, each of the multipliers An input terminal receives a signal output by a limiter circuit in a segment processing circuit in which the polynomial operation circuit is located; and another input end of the first multiplier receives a limit in a segmentation processing circuit in which the polynomial operation circuit is located
  • the p+1 power of the signal output by the limiter circuit in the segment processing circuit, p 1,...,m-1.
  • the preset order is m
  • the weighting circuit includes n*m multipliers and n second adding circuits Where n*m multipliers are divided into n groups, each group being m multipliers; n is a natural number;
  • each multiplier of the kth group receives one of the values of the respective order calculation items output by the polynomial operation circuit; and receives an output of the polynomial operation circuit at an input end of a multiplier of the kth group
  • Each second adding circuit adds and outputs a signal outputted by each of the plurality of multipliers as an output signal of the segment processing circuit in which the weighting circuit is located.
  • an analog predistorter including the curve fitting circuit provided by the embodiment of the present invention.
  • a radio frequency signal transmitter including the curve provided by the embodiment of the present invention. Combined circuit.
  • each segment processing circuit in the curve fitting circuit respectively intercepts a part of the input signal, and each segment processing circuit only fits The intercepted part, so that even if the input signal is more complicated, after the input signal is divided into n parts, the complexity of each part of the signal is greatly reduced. Therefore, each segment processing circuit is only based on a part of the signals in the input signal.
  • the highest order of the basis functions in the polynomial used also decreases, which reduces the sensitivity of the output signals of the segment processing circuits to the high order coefficient and the quantization noise, thereby It also reduces the sensitivity of the output signal of the curve fitting circuit to the high order term coefficients and quantization noise.
  • FIG. 1 is a schematic structural diagram of a transmitter using a radio frequency decomposition scheme in the prior art
  • FIG. 2 is a schematic structural diagram of a signal component separation module in the prior art
  • FIG. 3 is a schematic structural diagram of a curve fitting circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a segment processing circuit according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a limiter circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a limiting amplifier circuit according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a polynomial operation circuit according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a weighting circuit according to an embodiment of the present invention.
  • Embodiments of the present invention provide a curve fitting circuit, an analog predistorter, and a radio frequency signal transmitter.
  • Each segment processing circuit in the curve fitting circuit generates q by using a polynomial fitting method only according to a part of the input signal.
  • the sensitivity of the output signal of the path to the high order term coefficients and the quantization noise also reduces the sensitivity of the output signal of the curve fitting circuit to the high order term coefficients and quantization noise.
  • the curve fitting circuit provided by the embodiment of the present invention includes n segment processing circuits 31 and q first adding circuits 32; n is greater than or equal to 2; q is a natural number;
  • Each segment processing circuit 31 receives an input signal, and intercepts a part of the input signal according to a preset rule, and generates a to-be-processed signal according to the intercepted portion, and generates a signal according to the to-be-processed signal by using a polynomial fitting method. q output signals; wherein the portions intercepted by different segment processing circuits are not identical;
  • Each of the first adding circuits 32 is configured to receive one of the q output signals of each of the segment processing circuits 31, and obtain an output signal of the curve fitting circuit according to the sum of the received n signals;
  • the different first adder circuits 32 receive different ones of the q output signals of the same segmentation processing circuit 31.
  • the intercepting a part of the input signal according to a preset rule may be a part of intercepting the amplitude of the input signal within a preset range of the amplitude of the segment processing circuit, or between two points intercepting the input signal.
  • the part can also intercept the input signal according to other characteristics of the input signal.
  • the signal B is fitted to the signal B.
  • the highest order of the basis function in the polynomial to be used is 5 steps to achieve the target precision. That is to say, the basis functions in the polynomial to be used are x 5 , x 4 , x 3 , x 2 , x 1 and x 0 , respectively, and the signal A is divided into several parts according to a certain rule, since each part of the signal The complexity is less than the complexity of the signal A. Therefore, the highest order of the basis function in the polynomial used in the fitting according to a part of the signal A is less than 5 steps, so that the target accuracy can be achieved. After the signal A is divided into several parts, the sensitivity of the fitted results to the higher order coefficients and the quantization noise is reduced according to the fitting of each part by the polynomial fitting method.
  • each segment processing circuit If there is only one curve to be fitted, for example, a signal of a real number is fitted by a signal of a real number, then each segment processing circuit generates only one output signal, and the first addition circuit is After the output signals of the respective segment processing circuits are added, the output signal of the curve fitting circuit provided by the embodiment of the present invention is obtained, and the curve and the circuit also have only one output signal.
  • each segment processing circuit needs to generate two output signals, and a first addition circuit receives each segment processing. After an output signal of the circuit, the received n output signals are added to obtain an output signal of the curve fitting circuit, and the other first adding circuit receives the output signal of each segment processing circuit and receives the received signal. The n output signals are summed to obtain another output signal of the curve fitting circuit, the two first adding circuits receiving different ones of the two output signals of the same segment processing circuit.
  • One output signal of the curve fitting circuit is the real part of the complex signal, and the other output signal of the curve fitting circuit is the imaginary part of the complex signal.
  • each segmentation processing circuit If there are q curves to be fitted, each segmentation processing circuit generates q output signals, and each first addition circuit receives one of the q signals output by each segment processing circuit, and will receive The n signals are added as an output signal of the curve fitting circuit, and the different first adding circuits receive different output signals of the two output signals of the same segment processing circuit, thereby obtaining q outputs of the curve fitting circuit. signal.
  • each first adding circuit is specifically configured to: receive one of the q output signals output by each segment processing circuit; and do not include a constant in each of the q output signals of each segment processing circuit a term, the sum of the received n signals plus a constant term as an output signal of the curve fitting circuit; and when the q output signals of the at least one segmentation processing circuit include a constant term, the received The sum of the n signals is used as an output signal of the curve fitting circuit.
  • each segment processing circuit when each segment processing circuit generates an output signal according to a signal to be processed by a polynomial fitting method, when the polynomial used does not include a constant term (that is, a constant), each first adding circuit After adding the received n signals, a constant is added, and the signal after the constant is added as an output signal of the curve fitting circuit.
  • a constant term that is, a constant
  • each of the An addition circuit can add only the received n signals as a song An output signal of the line fitting circuit.
  • each segment processing circuit is specifically configured to: receive an input signal, and intercept a portion between two points of the input signal, and generate a to-be-processed signal according to the intercepted portion, and adopt a polynomial fitting method. And generating q output signals according to the to-be-processed signal.
  • it may be segmented at the turning point of the input signal, or may be segmented at any other point of the input signal, wherein the turning point of the input signal is a point at which the rate of change of the slope of the input signal is greater than a preset value.
  • the curve fitting circuit includes three segment processing circuits, and the inflection points of the input signals are x1, x2, x3, x4, and x5, where x1 ⁇ x2 ⁇ x3 ⁇ x4 ⁇ x5; in the three segment processing circuits
  • the first segmentation processing circuit only processes the portion between x1 and x3 in the input signal
  • the second segmentation processing circuit of the three segmentation processing circuits processes only the portion between x2 and x4 in the input signal
  • the second segmentation processing circuit in the segmentation processing circuit processes only the portion between x3 and x5 in the input signal.
  • each segment processing circuit is specifically configured to: receive an input signal, determine a truncated portion according to a magnitude of the input signal and a preset range of amplitudes of the segment processing circuit, and generate a segment according to the intercepted portion The signal to be processed, and a polynomial fitting method is used to generate q output signals according to the signal to be processed.
  • the curve fitting circuit includes three segment processing circuits, and the amplitude of the input signal ranges from [y1, y5], and the first segment processing circuit of the three segment processing circuits processes only the amplitude of the input signal.
  • the second segment processing circuit of the three segment processing circuits processes only the portion of the input signal whose amplitude is within [y2, y4], in the three segment processing circuits.
  • the third segmentation processing circuit only processes the portion of the input signal whose amplitude is within [y4, y5], where y1 ⁇ y2 ⁇ y3 ⁇ y4 ⁇ y5, that is, the amplitude of any two segmentation processing circuits Value preset ranges can overlap, but not exactly the same.
  • each segment processing circuit includes a limiter circuit 41, a polynomial operation circuit 42 and a weighting circuit 43;
  • the limiter circuit 41 receives an input signal, and when the amplitude of the input signal is within a preset range of the amplitude of the segment processing circuit in which the limiter circuit is located, generates a magnitude corresponding to the amplitude of the input signal a monotonically varying signal to be processed and output; and the amplitude of the input signal is less than the amplitude When the minimum value of the range is set, the first preset value is output; and when the amplitude of the input signal is greater than the maximum value of the preset range of the amplitude, the second preset value is output; wherein the first pre- And a value equal to a magnitude of the signal to be processed generated when the amplitude of the input signal is a minimum value of the preset range of the amplitude, the second preset value being equal to the amplitude of the input signal being the amplitude The amplitude of the signal to be processed generated when the value is the maximum value of the preset range;
  • the polynomial operation circuit 42 generates a value of each order calculation item whose order is not higher than a preset order according to the amplitude of the signal to be processed outputted by the limiter circuit;
  • the weighting circuit 43 receives the values of the calculation items of the respective orders, and generates an output signal of the segmentation processing circuit according to the coefficients of the calculation terms of the respective orders in the weighting coefficients and the values of the calculation items of the respective orders.
  • the segmentation processing circuit only generates the amplitude value
  • the amplitude of the portion of the input signal y located in [y3, y4] monotonously changes, that is, the monotonically increasing or monotonically decreasing signal to be processed and output; and for the portion of the input signal y located in [y1, y3] And outputting the amplitude of the signal to be processed generated when the amplitude of the input signal is y3; for the portion of the input signal y located in [y4, y2], when the amplitude of the linearly adjusted signal is y4 The amplitude of the signal to be processed.
  • the preset order is 3
  • the amplitude of the signal to be processed received by the polynomial operation circuit is z
  • the values of the calculation terms generated by the polynomial operation circuit 42 are: z 3 , z 2 , z.
  • an output signal of the segmentation processing circuit in which the weighting circuit is generated is A3*z 3 + a2*z 2 + a1*z
  • the weighting circuit may also add a constant term when generating an output signal of the segment processing circuit in which the weighting circuit is located, that is, the generated weighting circuit is located
  • An output signal of the segmentation processing circuit is a3*z 3 + a2*z 2 + a1*z+a0, where a0, a1, a2, and a3 are all constants.
  • the limiter circuit includes a pre-adjustment circuit 51 and a limiting amplifier circuit 52;
  • the pre-adjustment circuit 51 receives an input signal, and amplifies the input signal and/or performs offset adjustment on the input signal to output;
  • the pre-adjustment circuit implements offset adjustment or/and amplitude amplification of the signal.
  • an adder can be used to achieve offset adjustment, and an amplifier is used to achieve amplitude amplification.
  • the limiting amplifier circuit 52 receives the signal output from the preconditioning circuit 51, and when the amplitude of the signal outputted by the preconditioning circuit 51 is within the clipping range of the limiting amplifier circuit 52, the amplitude is generated along with the output of the preconditioning circuit 51.
  • the amplitude of the signal monotonously changes the signal to be processed and outputs; and when the amplitude of the signal output by the preconditioning circuit 51 is less than the minimum value of the limiting range of the limiting amplifier circuit 52, the first preset value is output; And outputting the second preset value when the amplitude of the signal output by the pre-conditioning circuit 51 is greater than the maximum value of the limiting range of the limiting amplifier circuit 52;
  • the correspondence between the output signals is the same.
  • the value within the preset range, y' is the value within the clipping range of the limiting amplifier circuit 52.
  • the amplitude of the signal to be processed output by the limiting amplifier circuit is between the first preset value and the second preset value.
  • the limiting amplifier circuit When the amplitude of the signal output by the pre-conditioning circuit is less than the minimum value of the limiting range of the limiting amplifier circuit, the limiting amplifier circuit outputs a first preset value; when the amplitude of the signal output by the pre-conditioning circuit is in the segment processing circuit When the amplitude is within the preset range, the output amplitude of the limiting amplifier circuit increases (or decreases) with the amplitude of the signal output by the pre-conditioning circuit; when the amplitude of the signal output by the pre-conditioning circuit The limiting amplifier circuit outputs a second preset value when the value of the limiting range of the limiting amplifier circuit is greater than the minimum value.
  • the limiting amplifier circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a first resistor R1.
  • One end of the first resistor R1 receives the limiter signal Limit, and the other end of the first resistor R1 is respectively connected
  • the collector of the first transistor T1, the base of the first transistor T1, and the base of the second transistor T2 the emitter of the first transistor T1 is grounded through the second resistor R2, and the second three poles
  • the emitter of the tube T2 is grounded through the third resistor R3, and the collector of the second transistor T2 outputs a signal related to the amplitude of the limiter signal Limit;
  • the base of the third transistor T3 receives the first input signal
  • the base of the fourth transistor T4 receives the second input signal
  • the collector of the third transistor T3 sequentially passes through the fourth resistor R4 and the fifth resistor R5.
  • the emitter of the third transistor T3 is sequentially connected to the emitter of the fourth transistor T4 through the sixth resistor R6 and the seventh resistor R7
  • One end connected to R7 receives a signal related to the amplitude of the limiter signal Limit
  • the signal of the end connected to the collector of the third resistor R4 and the third transistor T3 is one of the two signals outputted by the limiting amplifier circuit.
  • a signal of one end of the fifth resistor R5 connected to the collector of the fourth transistor T4 is the other one of the two signals output by the limiting amplifier circuit;
  • the difference between the first input signal and the second input signal is equal to the signal output by the pre-conditioning circuit; the difference between the two signals output by the limiting amplifier circuit is the output of the limiting circuit in which the limiting amplifier circuit is located Process the signal.
  • one end of the fourth resistor R4 and the fifth resistor R5 is connected to receive a power supply signal VCC.
  • the first resistor R1, the second resistor R2, the third resistor R3, the first transistor T1, and the second transistor T2 form a proportional current mirror circuit, which can be controlled by controlling the limiter signal Limit.
  • the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the third transistor T3, and the fourth transistor T4 constitute one differential amplifier.
  • the bias current of the differential amplifier is provided by the current mirror, that is, the bias current of the differential amplifier is the current of the collector of the second transistor T2, and the magnitude of the current of the collector of the second transistor T2 determines the differential amplifier.
  • the range A of the clipping that is, the magnitude of the current of the collector of the second transistor T2 determines that the differential amplifier outputs a signal monotonously with the input signal when the input signal is in the range A; Externally, the output of the differential amplifier no longer changes with the input signal. Therefore, the limiting range A of the limiting amplifier circuit can be controlled by controlling the limiting signal limit.
  • the preset order is m
  • the polynomial operation circuit includes m-1 multiplications.
  • the preset order is m
  • the weighting circuit includes n*m multipliers 81 and n second adding circuits 82; wherein, n*m multipliers 81 For n groups, each group is m multipliers 81; n is a natural number;
  • each multiplier 81 of the kth group receives one of the values of the respective order calculation items output by the polynomial operation circuit; and receives the polynomial operation circuit output at an input terminal of a multiplier 81 of the kth group
  • Each of the second adding circuits 82 adds and outputs a signal output from each of the plurality of multipliers 81 as an output signal of the segment processing circuit in which the weighting circuit is located.
  • two second adding circuits 82 are taken as an example for description, that is, each segment processing circuit has two output signals as an example for description.
  • the second adding circuit 82 does not add a constant term when weighting the respective order calculation items, so that one output signal of the curve fitting circuit is equal to n received by the first adding circuit 32.
  • the sum of the signals is further added with a constant term; and if the second adding circuit 82 adds a constant term when weighting the respective order terms, a output signal of the curve fitting circuit is equal to the first adding circuit.
  • 32 The sum of the n received signals.
  • the different first adding circuits 32 receive different output signals of the same segment processing circuit
  • Each of the multipliers in Fig. 8 is a 4-quadrant multiplier, that is, the signals received by each of the multipliers in Fig. 8 are both positive and negative. Since the coefficients of each order calculation are slow and generally come from the digital configuration, the two input ports of the multiplier can be asymmetrically designed, and only the multiplication function needs to be implemented.
  • An analog predistorter includes a curve fitting circuit provided by an embodiment of the present invention.
  • the embodiment of the invention provides a radio frequency signal transmitter, which comprises a curve fitting circuit provided by an embodiment of the invention.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. Instructions are provided for implementation in the flowchart The steps of a process or a plurality of processes and/or block diagrams of a function specified in a block or blocks.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Data Mining & Analysis (AREA)
  • Mathematical Physics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Algebra (AREA)
  • Computational Mathematics (AREA)
  • Databases & Information Systems (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Amplifiers (AREA)
  • Transmitters (AREA)

Abstract

一种曲线拟合电路、模拟预失真器和射频信号发射机，用以解决在射频信号分解时采用现有的多项式拟合经常会用到高阶多项式所导致的拟合结果对高次项系数和量化噪声都非常敏感的问题。该曲线拟合电路中的每个分段处理电路，按照预设规则截取接收到的输入信号中的一部分，以及根据截取的部分生成待处理信号，并采用多项式拟合的方法根据所述待处理信号生成q个输出信号；不同分段处理电路截取的部分不完全相同；每个第一加法电路，接收各个分段处理电路的q个输出信号中的一个信号，并根据接收到的n个信号之和得到所述曲线拟合电路的一个输出信号；不同第一加法电路接收同一个分段处理电路的q个输出信号中的不同输出信号。

Description

一种曲线拟合电路、模拟预失真器和射频信号发射机 技术领域
本发明涉及通信技术领域，特别涉及一种曲线拟合电路、模拟预失真器和射频信号发射机。
背景技术
多输入射频功率放大器是具有两个或两个以上射频信号输入端和单个输出端的功率放大器。多输入射频功率放大器相比于传统的单输入、单输出的射频功率放大器具有更好的性能，并且由于多输入射频功率放大器可以通过调整各个输入之间的幅度和相位的关系使得多输入射频功率放大器的性能更加优异，因此，多输入射频功率放大器越来越受到重视。
传统的使用多输入功率放大器的发射机中需要至少两个完整的射频小信号链路，这样，在发射机中小信号通道增加，使得发射机的结构复杂。为了简化发射机的结构，目前的发射机中常采用射频分解的方案来简化发射机的结构，采用射频分解方案的发射机的结构可以如图1所示：信号分量分离模块15接收正交调制器14输出的信号，并将接收到的信号分解为两路，输出到两个驱动放大器16中，图1所示的发射机还包括数字预失真模块11、正交调制补偿模块12、数模转换模块13、射频功率放大器17、下变频器18和模数转换模块19。
其中，信号分量分离模块如图2所示，包括包络检波器21、正交信号分离器22、乘法器23和曲线拟合电路24。曲线拟合电路24的设计是信号分量分离模块中的关键，曲线拟合电路的功能是将由实数表示的输入信号转变为复数表示的输出信号，因此，由于曲线拟合电路是用电路实现数学计算，这会不可避免的存在误差，因此，这要求电路结构要具有一定的容差特性。
实现曲线拟合电路的功能通常的方法是多项式拟合，例如，信号x与信号y之间的关系为y＝f(x)，曲线拟合电路在接收到信号x后，要输出信号y，曲 线拟合电路采用xn作为基函数拟合信号x与信号y之间的关系，得到y＝a*x5+b*x4+c*x3+d*x2+e*x1+f，其中，基函数分别为x5、x4、x3、x2、x1和x0，而a、b、c、d、e、f分别为各基函数的系数。
这种直接采用多项式-拟合时，由于实现射频分解功能的信号分量分离模块需要拟合的曲线比较复杂，通常需要用到高阶多项式，这样，拟合结果对高次项的系数，即高阶系数非常敏感，并且，由于要用到高阶多项式，这导致拟合结果对量化噪声非常敏感。
综上所述，由于射频分解需要拟合的曲线比较复杂，采用目前的多项式拟合时，通常会用到高阶多项式，这样，拟合结果不但对高次项系数非常敏感，并且对量化噪声也很敏感。
发明内容
本发明实施例提供了一种曲线拟合电路、模拟预失真器和射频信号发射机，用以解决在射频信号分解时采用现有的多项式拟合经常会用到高阶多项式，所导致的拟合结果对高次项系数和量化噪声都非常敏感的问题。
第一方面，提供了一种曲线拟合电路，其特征在于，包括n个分段处理电路和q个第一加法电路；n大于或等于2；q为自然数；
每个分段处理电路，接收输入信号，并按照预设规则截取所述输入信号中的一部分，以及根据截取的部分生成待处理信号，并采用多项式拟合的方法根据所述待处理信号生成q个输出信号；其中，不同分段处理电路截取的部分不完全相同；
每个第一加法电路，接收各个分段处理电路的q个输出信号中的一个信号，并根据接收到的n个信号之和得到所述曲线拟合电路的一个输出信号；其中，不同第一加法电路接收同一个分段处理电路的q个输出信号中的不同输出信号。
结合第一方面，在第一种可能的实现方式中，所述每个第一加法电路，具体用于：
接收各个分段处理电路输出的q个输出信号中的一个信号；并在每个分段处理电路的q个输出信号中均不包括常数项时，将接收到的n个信号之和加上常数项作为所述曲线拟合电路的一个输出信号；以及至少一个分段处理电路的q个输出信号中包括常数项时，将接收到的n个信号之和作为所述曲线拟合电路的一个输出信号。
结合第一方面，在第二种可能的实现方式中，每个分段处理电路具体用于：
接收输入信号，并根据所述输入信号的幅值和该分段处理电路的幅值预设范围确定截取的部分，以及根据截取的部分生成待处理信号，并采用多项式拟合的方法根据所述待处理信号生成q个输出信号。
结合第一方面，在第三种可能的实现方式中，每个分段处理电路具体用于：
接收输入信号，并截取所述输入信号的两点之间的部分，以及根据截取的部分生成待处理信号，并采用多项式拟合的方法根据所述待处理信号生成q个输出信号。
结合第一方面的第三种可能的实现方式，在第四种可能的实现方式中，每个分段处理电路包括限幅电路、多项式运算电路和加权电路；
所述限幅电路，接收输入信号，并在所述输入信号的幅值在所述限幅电路所在的分段处理电路的幅值预设范围内时，生成幅值随着所述输入信号的幅值单调变化的待处理信号并输出；并在所述输入信号的幅值小于所述幅值预设范围的最小值时，输出第一预设值；以及在所述输入信号的幅值大于所述幅值预设范围的最大值时，输出第二预设值；其中，所述第一预设值等于所述输入信号的幅值为所述幅值预设范围的最小值时生成的待处理信号的幅值，所述第二预设值等于所述输入信号的幅值为所述幅值预设范围的最大值时生成的待处理信号的幅值；
所述多项式运算电路，根据所述限幅电路输出的待处理信号的幅值生成阶数不高于预设阶数的各阶计算项的值；
所述加权电路，接收各阶计算项的值，并根据加权系数中的各阶计算项的系数与所述各阶计算项的值生成所述分段处理电路的输出信号。
结合第一方面的第四种可能的实现方式，在第五种可能的实现方式中，所述限幅电路包括预调整电路和限幅放大器电路；
所述预调整电路，接收输入信号，并将所述输入信号放大和/或对所述输入信号进行偏移调整后输出；
所述限幅放大器电路，接收所述预调整电路输出的信号，并在所述预调整电路输出的信号的幅值在所述限幅放大器电路的限幅范围内时，生成幅值随着所述预调整电路输出的信号的幅值单调变化的待处理信号并输出；并在所述预调整电路输出的信号的幅值小于所述限幅放大器电路的限幅范围的最小值时，输出所述第一预设值；以及在所述预调整电路输出的信号的幅值大于所述限幅放大器电路的限幅范围的最大值时，输出所述第二预设值；
其中，所述限幅放大器电路的限幅范围与所述限幅放大器电路所在的分段处理电路的幅值预设范围之间的对应关系，与所述预调整电路接收到的输入信号与所述预调整电路输出的信号之间的对应关系相同。
结合第一方面的第五种可能的实现方式，在第六种可能的实现方式中，所述限幅放大器电路包括第一三极管、第二三极管、第三三极管、第四三极管、第一电阻、第二电阻、第三电阻、第四电阻、第五电阻、第六电阻和第七电阻；
所述第一电阻的一端接收限幅信号，所述第一电阻的另一端分别连接第一三极管的集电极、第一三极管的基极和第二三极管的基极，所述第一三极管的发射极通过第二电阻接地，所述第二三极管的发射极通过第三电阻接地，所述第二三极管的集电极输出与所述限幅信号的幅值相关的信号；
所述第三三极管的基极接收第一输入信号，所述第四三极管的基极接收第二输入信号，所述第三三极管的集电极依次通过第四电阻和第五电阻连接所述第四三极管的集电极，所述第三三极管的发射极依次通过第六电阻和第七电阻连接所述第四三极管的发射极，所述第六电阻与所述第七电阻相连的 一端接收与所述限幅信号的幅值相关的信号，所述第四电阻与所述第三三极管的集电极相连的一端的信号为所述限幅放大器电路输出的两路信号中的一路信号，所述第五电阻与所述第四三极管的集电极相连的一端的信号为所述限幅放大器电路输出的两路信号中的另一路信号；
所述第一输入信号与所述第二输入信号之差等于所述预调整电路输出的信号；所述限幅放大器电路输出的两路信号之差为所述限幅放大器电路所在的限幅电路输出的待处理信号。
结合第一方面的第四种可能的实现方式，在第七种可能的实现方式中，所述预设阶数为m，所述多项式运算电路包括m-1个乘法器，每个乘法器的一个输入端均接收所述多项式运算电路所在的分段处理电路中的限幅电路输出的信号；第一个乘法器的另一个输入端接收所述多项式运算电路所在的分段处理电路中的限幅电路输出的信号，第l个乘法器的另一个输入端接收第l-1个乘法器输出的信号，l＝2,…,m；第p个乘法器输出的信号为所述多项式生成电路所在的分段处理电路中的限幅电路输出的信号的p+1次方，p＝1,…,m-1。
结合第一方面的第四种可能的实现方式，在第八种可能的实现方式中，所述预设阶数为m，所述加权电路包括n*m个乘法器和n个第二加法电路；其中，n*m个乘法器分为n组，每组为m个乘法器；n为自然数；
第k组的各个乘法器的一个输入端接收所述多项式运算电路输出的各阶计算项的值中的一个；在第k组的一个乘法器的一个输入端接收所述多项式运算电路输出的l阶计算项的值时，该乘法器的另一个输入端接收所述加权系数中的第k组系数中的l阶计算项的系数；k＝1，…，n；l为不大于m的自然数；
每个第二加法电路将一组的各个乘法器输出的信号相加后输出，作为所述加权电路所在的分段处理电路的一个输出信号。
第二方面，提供一种模拟预失真器，包括本发明实施例提供的曲线拟合电路。
第三方面，提供一种射频信号发射机，包括本发明实施例提供的曲线拟 合电路。
本发明实施例的有益效果包括：
本发明实施例提供的曲线拟合电路、模拟预失真器和射频信号发射机，由于曲线拟合电路中的各个分段处理电路分别截取输入信号中的一部分，每个分段处理电路仅拟合其截取的部分，这样即使输入信号比较复杂，但是，将输入信号分成n部分后，每一部分信号的复杂度也会大大降低，因此，每个分段处理电路仅根据输入信号中的一部分信号采用多项式拟合的方法生成输出信号时，用到的多项式中的基函数的最高阶数也会下降，这降低了各分段处理电路的输出信号对高次项系数和量化噪声的敏感程度，从而也降低了曲线拟合电路的输出信号对高次项系数和量化噪声的敏感程度。
附图说明
图1为现有技术中采用射频分解方案的发射机的结构示意图；
图2为现有技术中的信号分量分离模块的结构示意图；
图3为本发明实施例提供的曲线拟合电路的结构示意图；
图4为本发明实施例提供的分段处理电路的结构示意图；
图5为本发明实施例提供的限幅电路的结构示意图；
图6为本发明实施例提供的限幅放大器电路的结构示意图；
图7为本发明实施例提供的多项式运算电路的结构示意图；
图8为本发明实施例提供的加权电路的结构示意图。
具体实施方式
本发明实施例提供了一种曲线拟合电路、模拟预失真器和射频信号发射器，曲线拟合电路中的每个分段处理电路仅根据输入信号中的一部分采用多项式拟合的方法生成q个输出信号，而由于将输入信号分成n部分后，每一部分信号的复杂度都会大大降低，因此，每个分段处理电路采用多项式拟合时，用到的多项式中的基函数的最高阶数也会下降，这降低了各分段处理电 路的输出信号对高次项系数和量化噪声的敏感程度，从而也降低了曲线拟合电路的输出信号对高次项系数和量化噪声的敏感程度。
下面结合说明书附图，对本发明实施例提供的曲线拟合电路、模拟预失真器和射频信号发射机的具体实施方式进行说明。
本发明实施例提供的曲线拟合电路，如图3所示，包括n个分段处理电路31和q个第一加法电路32；n大于或等于2；q为自然数；
每个分段处理电路31，接收输入信号，并按照预设规则截取所述输入信号中的一部分，以及根据截取的部分生成待处理信号，并采用多项式拟合的方法根据所述待处理信号生成q个输出信号；其中，不同分段处理电路截取的部分不完全相同；
每个第一加法电路32，用于接收各个分段处理电路31的q个输出信号中的一个信号，并根据接收到的n个信号之和得到所述曲线拟合电路的一个输出信号；其中，不同第一加法电路32接收同一个分段处理电路31的q个输出信号中的不同输出信号。
其中，按照预设规则截取所述输入信号中的一部分，可以是截取输入信号的幅值在分段处理电路的幅值预设范围内的部分，也可以是截取输入信号的两个点之间的部分，还可以根据输入信号的其它特征来截取输入信号。
例如，由信号A拟合出信号B，在不将信号A分为多部分直接进行拟合的过程中，要用到的多项式中的基函数的最高阶数为5阶才能达到目标精度，也就是说，要用到的多项式中的基函数分别为x5、x4、x3、x2、x1和x0，而按照一定规则将信号A分为若干部分后，由于每一部分信号的复杂程度都小于信号A的复杂程度，因此，在根据信号A的某一部分进行拟合的过程中要用到的多项式中的基函数的最高阶数小于5阶便能达到目标精度，这样，在将信号A分为若干部分后，根据每一部分分别采用多项式拟合的方法拟合时，拟合后的结果对高阶系数和量化噪声的敏感程度都会降低。
如果需要拟合的曲线只有一条，例如，由实数的信号拟合出一个实数的信号，那么，各个分段处理电路仅生成一个输出信号，而第一加法电路在将 各个分段处理电路的输出信号相加后，也就得到了本发明实施例提供的曲线拟合电路的输出信号，曲线你和电路也只有一个输出信号。
如果需要拟合的曲线有两条，例如，由实数的信号拟合出一个复数的信号，那么，各个分段处理电路需要生成两个输出信号，而一个第一加法电路在接收各个分段处理电路的一个输出信号后，将接收到的n个输出信号相加得到曲线拟合电路的一个输出信号，另一个第一加法电路在接收各个分段处理电路的一个输出信号后，将接收到的n个输出信号相加得到曲线拟合电路的另一个输出信号，这两个第一加法电路接收同一个分段处理电路的两个输出信号中的不同的输出信号。曲线拟合电路的一个输出信号为复数的信号的实部，曲线拟合电路的另一个输出信号为复数的信号的虚部。
如果需要拟合的曲线有q条，那么每个分段处理电路要生成q个输出信号，每个第一加法电路接收各个分段处理电路输出的q个信号中的一个信号，并将接收到的n个信号相加作为曲线拟合电路的一个输出信号，不同第一加法电路接收同一个分段处理电路的两个输出信号中的不同的输出信号，从而得到曲线拟合电路的q个输出信号。
可选地，每个第一加法电路，具体用于：接收各个分段处理电路输出的q个输出信号中的一个信号；并在每个分段处理电路的q个输出信号中均不包括常数项时，将接收到的n个信号之和加上常数项作为所述曲线拟合电路的一个输出信号；以及至少一个分段处理电路的q个输出信号中包括常数项时，将接收到的n个信号之和作为所述曲线拟合电路的一个输出信号。
也就是说，当各个分段处理电路在采用多项式拟合的方法根据待处理信号生成输出信号时，所用到的多项式中均不包括常数项(也就是一个常数)时，每个第一加法电路在将接收到的n个信号相加后，还要加上一个常数，并将加上常数后的信号作为曲线拟合电路的一个输出信号。
当n个分段处理电路中的至少一个分段处理电路在采用多项式拟合的方法根据待处理信号生成输出信号时，所用到的多项式中包括常数项(也就是一个常数)时，每个第一加法电路可以只将接收到的n个信号相加，作为曲 线拟合电路的一个输出信号。
可选地，每个分段处理电路具体用于：接收输入信号，并截取所述输入信号的两个点之间的部分，以及根据截取的部分生成待处理信号，并采用多项式拟合的方法根据所述待处理信号生成q个输出信号。
在实际应用中，可以在输入信号的转折点处分段，也可以在输入信号的其他任意点处分段，其中，输入信号的转折点是所述输入信号的斜率的变化率大于预设值的点。
例如，曲线拟合电路中包括3个分段处理电路，输入信号的转折点为x1、x2、x3、x4和x5，其中，x1<x2<x3<x4<x5；3个分段处理电路中的第一个分段处理电路仅处理输入信号中x1到x3之间的部分，3个分段处理电路中的第二个分段处理电路仅处理输入信号中x2到x4之间的部分，3个分段处理电路中的第二个分段处理电路仅处理输入信号中x3到x5之间的部分。
可选地，每个分段处理电路具体用于：接收输入信号，并根据所述输入信号的幅值和该分段处理电路的幅值预设范围确定截取的部分，以及根据截取的部分生成待处理信号，并采用多项式拟合的方法根据所述待处理信号生成q个输出信号。
例如，曲线拟合电路中包括3个分段处理电路，输入信号的幅值的范围为[y1,y5]，3个分段处理电路中的第一个分段处理电路仅处理输入信号的幅值在[y1,y3]内的部分，3个分段处理电路中的第二个分段处理电路仅处理输入信号的幅值在[y2,y4]内的部分，3个分段处理电路中的第三个分段处理电路仅处理输入信号的幅值在[y4,y5]内的部分，其中，y1<y2≤y3≤y4<y5，也就是说，任意两个分段处理电路的幅值预设范围可以有重叠，但是不能完全相同。
可选地，如图4所示，每个分段处理电路包括限幅电路41、多项式运算电路42和加权电路43；
限幅电路41，接收输入信号，并在所述输入信号的幅值在所述限幅电路所在的分段处理电路的幅值预设范围内时，生成幅值随着所述输入信号的幅值单调变化的待处理信号并输出；并在所述输入信号的幅值小于所述幅值预 设范围的最小值时，输出第一预设值；以及在所述输入信号的幅值大于所述幅值预设范围的最大值时，输出第二预设值；其中，所述第一预设值等于所述输入信号的幅值为所述幅值预设范围的最小值时生成的待处理信号的幅值，所述第二预设值等于所述输入信号的幅值为所述幅值预设范围的最大值时生成的待处理信号的幅值；
多项式运算电路42，根据所述限幅电路输出的待处理信号的幅值生成阶数不高于预设阶数的各阶计算项的值；
加权电路43，接收各阶计算项的值，并根据加权系数中的各阶计算项的系数与所述各阶计算项的值生成所述分段处理电路的输出信号。
若输入信号y的值大于y1小于y2，而一个分段处理电路的幅值预设范围为[y3，y4]，其中y1<y3，y2>y4，则该分段处理电路仅生成幅值随着输入信号y中位于[y3，y4]内的部分的幅值单调变化，即单调增大或者单调减小的待处理信号并输出；而对于输入信号y中位于[y1，y3]内的部分，则输出输入信号的幅值为y3时生成的待处理信号的幅值；对于输入信号y中位于[y4，y2]内的部分，则输出线性调整后的信号的幅值为y4时生成的待处理信号的幅值。
例如，预设阶数为3，多项式运算电路接收到的待处理信号的幅值为z，多项式运算电路42生成的各阶计算项的值为：z3、z2、z。若1阶计算项的一个系数为a1，2阶计算项的一个系数为a2，3阶计算项的一个系数为a3，则加权电路生成的该加权电路所在的分段处理电路的一个输出信号为a3*z3+a2*z2+a1*z，当然，加权电路还可以在生成该加权电路所在的分段处理电路的一个输出信号时加上一个常数项，即生成的该加权电路所在的分段处理电路的一个输出信号为a3*z3+a2*z2+a1*z+a0，其中，a0、a1、a2和a3均为常数。
可选地，如图5所示，限幅电路包括预调整电路51和限幅放大器电路52；
预调整电路51，接收输入信号，并将所述输入信号放大和/或对所述输入信号进行偏移调整后输出；
预调整电路实现信号的偏移调整或/和幅度放大。输入信号x与输出信号 y的关系可以表示为y＝a*x+c。其中，a为放大倍数，c为直流偏移。在实际中，可以采用加法器来实现偏移调整，采用放大器来实现幅度放大。
限幅放大器电路52，接收预调整电路51输出的信号，并在预调整电路51输出的信号的幅值在限幅放大器电路52的限幅范围内时，生成幅值随着预调整电路51输出的信号的幅值单调变化的待处理信号并输出；并在预调整电路51输出的信号的幅值小于限幅放大器电路52的限幅范围的最小值时，输出所述第一预设值；以及在预调整电路51输出的信号的幅值大于限幅放大器电路52的限幅范围的最大值时，输出所述第二预设值；
其中，限幅放大器电路52的限幅范围与限幅放大器电路52所在的分段处理电路的幅值预设范围之间的对应关系，与预调整电路51接收到的输入信号与预调整电路51输出的信号之间的对应关系相同。
也就是说，如果预调整电路51接收到的输入信号x与预调整电路51输出的信号y之间的对应关系为y＝f(x)，那么，限幅放大器电路52的限幅范围与限幅放大器电路52所在的分段处理电路的幅值预设范围之间的对应关系为y’＝f(x’)，其中，x’为限幅放大器电路52所在的分段处理电路的幅值预设范围内的值，y’为限幅放大器电路52的限幅范围内的值。
限幅放大器电路输出的待处理信号的幅值在第一预设值和第二预设值之间。当预调整电路输出的信号的幅值小于限幅放大器电路的限幅范围的最小值时，限幅放大器电路输出第一预设值；当预调整电路输出的信号的幅值在分段处理电路的幅值预设范围内时，限幅放大器电路输出幅值随着预调整电路输出的信号的幅值增大而增大(或减小)的信号；当预调整电路输出的信号的幅值大于限幅放大器电路的限幅范围的最小值时，限幅放大器电路输出第二预设值。
可选地，如图6所示，所述限幅放大器电路包括第一三极管T1、第二三极管T2、第三三极管T3、第四三极管T4、第一电阻R1、第二电阻R2、第三电阻R3、第四电阻R4、第五电阻R5、第六电阻R6和第七电阻R7；
第一电阻R1的一端接收限幅信号Limit，第一电阻R1的另一端分别连接 第一三极管T1的集电极、第一三极管T1的基极和第二三极管T2的基极，第一三极管T1的发射极通过第二电阻R2接地，第二三极管T2的发射极通过第三电阻R3接地，第二三极管T2的集电极输出与限幅信号Limit的幅值相关的信号；
第三三极管T3的基极接收第一输入信号，第四三极管T4的基极接收第二输入信号，第三三极管T3的集电极依次通过第四电阻R4和第五电阻R5连接第四三极管T4的集电极，第三三极管T3的发射极依次通过第六电阻R6和第七电阻R7连接第四三极管T4的发射极，第六电阻R6与第七电阻R7相连的一端接收与限幅信号Limit的幅值相关的信号，第四电阻R4与第三三极管T3的集电极相连的一端的信号为限幅放大器电路输出的两路信号中的一路信号，第五电阻R5与第四三极管T4的集电极相连的一端的信号为所述限幅放大器电路输出的两路信号中的另一路信号；
所述第一输入信号与所述第二输入信号之差等于所述预调整电路输出的信号；限幅放大器电路输出的两路信号之差为该限幅放大器电路所在的限幅电路输出的待处理信号。
在图6中，第四电阻R4和第五电阻R5相连的一端接收电源信号VCC。
在图6中，第一电阻R1、第二电阻R2、第三电阻R3、第一三极管T1、第二三极管T2构成一个的比例电流镜电路，通过控制限幅信号Limit可以控制第二三极管T2的集电极的电流。第四电阻R4、第五电阻R5、第六电阻R6、第七电阻R7、第三三极管T3、第四三极管T4构成一个的差分放大器。差分放大器的偏置电流由上述电流镜提供，即差分放大器的偏置电流为第二三极管T2的集电极的电流，第二三极管T2的集电极的电流的大小决定了该差分放大器限幅的范围A，即第二三极管T2的集电极的电流的大小决定了该差分放大器在输入信号在范围A内时，该差分放大器输出的信号随着输入信号单调变化；在范围A外时，该差分放大器的输出不再随着输入信号变化。因此，通过控制限幅信号limit可以控制限幅放大器电路的限幅范围A。
可选地，如图7所示，预设阶数为m，多项式运算电路包括m-1个乘法 器71，每个乘法器71的一个输入端均接收所述多项式运算电路所在的分段处理电路中的限幅电路输出的信号Vin；第一个乘法器71的另一个输入端接收所述多项式运算电路所在的分段处理电路中的限幅电路输出的信号Vin，第l个乘法器71的另一个输入端接收第l-1个乘法器输出的信号，l＝2,…,m；第p个乘法器71输出的信号为所述多项式生成电路所在的分段处理电路中的限幅电路输出的信号的p+1次方，p＝1,…,m-1。一般来说，p不大于2，如果p大于2，可以增加分段处理电路的数目，以将输入信号再多分几段，从而使得p减小，即使得预设阶数m减小。例如，曲线拟合电路中有两个分段处理电路时，p＝4，那么，可以将曲线拟合电路中的分段处理电路增加至3个，从而使p减小。
可选地，如图8所示，所述预设阶数为m，所述加权电路包括n*m个乘法器81和n个第二加法电路82；其中，n*m个乘法器81分为n组，每组为m个乘法器81；n为自然数；
第k组的各个乘法器81的一个输入端接收所述多项式运算电路输出的各阶计算项的值中的一个；在第k组的一个乘法器81的一个输入端接收所述多项式运算电路输出的l阶计算项的值时，该乘法器81的另一个输入端接收所述加权系数中的第k组系数中的l阶计算项的系数；k＝1，…，n；l为不大于m的自然数；
每个第二加法电路82将一组的各个乘法器81输出的信号相加后输出，作为所述加权电路所在的分段处理电路的一个输出信号。
在图8中，以两个第二加法电路82为例进行说明，也就是以每个分段处理电路有两个输出信号为例进行说明。在图8中，第二加法电路82在将各阶计算项进行加权求和时，并没有加上常数项，因此，曲线拟合电路的一个输出信号等于第一加法电路32接收到的n个信号之和再加上一个常数项；而如果第二加法电路82在将各阶计算项进行加权求和时，加上了常数项，那么，曲线拟合电路的一个输出信号等于第一加法电路32接收到的n个信号之和。其中，不同的第一加法电路32接收同一个分段处理电路的不同的输出信号，
图8中的各个乘法器均为4象限乘法器，即图8中的每个乘法器接收到的信号均是可正可负的。由于每阶计算项的系数是慢变的，且一般来自于数字配置，因此，乘法器的两个输入口可不对称设计，仅需实现乘法功能即可。
本发明实施例提供的一种模拟预失真器，包括本发明实施例提供的曲线拟合电路。
本发明实施例提供一种射频信号发射机，包括本发明实施例提供的曲线拟合电路。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图 一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (11)

  1. 一种曲线拟合电路，其特征在于，包括n个分段处理电路和q个第一加法电路；n大于或等于2；q为自然数；
    每个分段处理电路，接收输入信号，并按照预设规则截取所述输入信号中的一部分，以及根据截取的部分生成待处理信号，并采用多项式拟合的方法根据所述待处理信号生成q个输出信号；其中，不同分段处理电路截取的部分不完全相同；
    每个第一加法电路，接收各个分段处理电路的q个输出信号中的一个信号，并根据接收到的n个信号之和得到所述曲线拟合电路的一个输出信号；其中，不同第一加法电路接收同一个分段处理电路的q个输出信号中的不同输出信号。
  2. 如权利要求1所述的曲线拟合电路，其特征在于，所述每个第一加法电路，具体用于：
    接收各个分段处理电路输出的q个输出信号中的一个信号；并在每个分段处理电路的q个输出信号中均不包括常数项时，将接收到的n个信号之和加上常数项作为所述曲线拟合电路的一个输出信号；以及至少一个分段处理电路的q个输出信号中包括常数项时，将接收到的n个信号之和作为所述曲线拟合电路的一个输出信号。
  3. 如权利要求1所述的曲线拟合电路，其特征在于，每个分段处理电路具体用于：
    接收输入信号，并根据所述输入信号的幅值和该分段处理电路的幅值预设范围确定截取的部分，以及根据截取的部分生成待处理信号，并采用多项式拟合的方法根据所述待处理信号生成q个输出信号。
  4. 如权利要求1所述的曲线拟合电路，其特征在于，每个分段处理电路具体用于：
    接收输入信号，并截取所述输入信号的两点之间的部分，以及根据截取 的部分生成待处理信号，并采用多项式拟合的方法根据所述待处理信号生成q个输出信号。
  5. 如权利要求4所述的电路，其特征在于，每个分段处理电路包括限幅电路、多项式运算电路和加权电路；
    所述限幅电路，接收输入信号，并在所述输入信号的幅值在所述限幅电路所在的分段处理电路的幅值预设范围内时，生成幅值随着所述输入信号的幅值单调变化的待处理信号并输出；并在所述输入信号的幅值小于所述幅值预设范围的最小值时，输出第一预设值；以及在所述输入信号的幅值大于所述幅值预设范围的最大值时，输出第二预设值；其中，所述第一预设值等于所述输入信号的幅值为所述幅值预设范围的最小值时生成的待处理信号的幅值，所述第二预设值等于所述输入信号的幅值为所述幅值预设范围的最大值时生成的待处理信号的幅值；
    所述多项式运算电路，根据所述限幅电路输出的待处理信号的幅值生成阶数不高于预设阶数的各阶计算项的值；
    所述加权电路，接收各阶计算项的值，并根据加权系数中的各阶计算项的系数与所述各阶计算项的值生成所述分段处理电路的输出信号。
  6. 如权利要求5所述的电路，其特征在于，所述限幅电路包括预调整电路和限幅放大器电路；
    所述预调整电路，接收输入信号，并将所述输入信号放大和/或对所述输入信号进行偏移调整后输出；
    所述限幅放大器电路，接收所述预调整电路输出的信号，并在所述预调整电路输出的信号的幅值在所述限幅放大器电路的限幅范围内时，生成幅值随着所述预调整电路输出的信号的幅值单调变化的待处理信号并输出；并在所述预调整电路输出的信号的幅值小于所述限幅放大器电路的限幅范围的最小值时，输出所述第一预设值；以及在所述预调整电路输出的信号的幅值大于所述限幅放大器电路的限幅范围的最大值时，输出所述第二预设值；
    其中，所述限幅放大器电路的限幅范围与所述限幅放大器电路所在的分 段处理电路的幅值预设范围之间的对应关系，与所述预调整电路接收到的输入信号与所述预调整电路输出的信号之间的对应关系相同。
  7. 如权利要求6所述的电路，其特征在于，所述限幅放大器电路包括第一三极管、第二三极管、第三三极管、第四三极管、第一电阻、第二电阻、第三电阻、第四电阻、第五电阻、第六电阻和第七电阻；
    所述第一电阻的一端接收限幅信号，所述第一电阻的另一端分别连接第一三极管的集电极、第一三极管的基极和第二三极管的基极，所述第一三极管的发射极通过第二电阻接地，所述第二三极管的发射极通过第三电阻接地，所述第二三极管的集电极输出与所述限幅信号的幅值相关的信号；
    所述第三三极管的基极接收第一输入信号，所述第四三极管的基极接收第二输入信号，所述第三三极管的集电极依次通过第四电阻和第五电阻连接所述第四三极管的集电极，所述第三三极管的发射极依次通过第六电阻和第七电阻连接所述第四三极管的发射极，所述第六电阻与所述第七电阻相连的一端接收与所述限幅信号的幅值相关的信号，所述第四电阻与所述第三三极管的集电极相连的一端的信号为所述限幅放大器电路输出的两路信号中的一路信号，所述第五电阻与所述第四三极管的集电极相连的一端的信号为所述限幅放大器电路输出的两路信号中的另一路信号；
    所述第一输入信号与所述第二输入信号之差等于所述预调整电路输出的信号；所述限幅放大器电路输出的两路信号之差为所述限幅放大器电路所在的限幅电路输出的待处理信号。
  8. 如权利要求5所述的电路，其特征在于，所述预设阶数为m，所述多项式运算电路包括m-1个乘法器，每个乘法器的一个输入端均接收所述多项式运算电路所在的分段处理电路中的限幅电路输出的信号；第一个乘法器的另一个输入端接收所述多项式运算电路所在的分段处理电路中的限幅电路输出的信号，第l个乘法器的另一个输入端接收第l-1个乘法器输出的信号，l＝2,…,m；第p个乘法器输出的信号为所述多项式生成电路所在的分段处理电路中的限幅电路输出的信号的p+1次方，p＝1,…,m-1。
  9. 如权利要求5所述的电路，其特征在于，所述预设阶数为m，所述加权电路包括n*m个乘法器和n个第二加法电路；其中，n*m个乘法器分为n组，每组为m个乘法器；n为自然数；
    第k组的各个乘法器的一个输入端接收所述多项式运算电路输出的各阶计算项的值中的一个；在第k组的一个乘法器的一个输入端接收所述多项式运算电路输出的l阶计算项的值时，该乘法器的另一个输入端接收所述加权系数中的第k组系数中的l阶计算项的系数；k＝1，…，n；l为不大于m的自然数；
    每个第二加法电路将一组的各个乘法器输出的信号相加后输出，作为所述加权电路所在的分段处理电路的一个输出信号。
  10. 一种模拟预失真器，其特征在于，包括权利要求1～9任一所述的曲线拟合电路。
  11. 一种射频信号发射机，其特征在于，包括权利要求1～9任一所述的曲线拟合电路。
PCT/CN2014/090095 2014-10-31 2014-10-31 一种曲线拟合电路、模拟预失真器和射频信号发射机 WO2016065633A1 (zh)

Priority Applications (6)

Application Number Priority Date Filing Date Title
CN201480024986.4A CN105745641B (zh) 2014-10-31 2014-10-31 一种曲线拟合电路、模拟预失真器和射频信号发射机
JP2017523242A JP6442053B2 (ja) 2014-10-31 2014-10-31 曲線当てはめ回路、アナログ前置補償器、および無線周波数信号送信器
KR1020177012917A KR101926665B1 (ko) 2014-10-31 2014-10-31 커브피팅 회로, 아날로그 전치보상기 및 무선 주파수 신호 송신기
EP14904793.8A EP3197045B1 (en) 2014-10-31 2014-10-31 Curve fitting circuit, analog predistorter and radio frequency signal transmitter
PCT/CN2014/090095 WO2016065633A1 (zh) 2014-10-31 2014-10-31 一种曲线拟合电路、模拟预失真器和射频信号发射机
US15/581,823 US10141896B2 (en) 2014-10-31 2017-04-28 Curve fitting circuit, analog predistorter, and radio frequency signal transmitter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2014/090095 WO2016065633A1 (zh) 2014-10-31 2014-10-31 一种曲线拟合电路、模拟预失真器和射频信号发射机

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/581,823 Continuation US10141896B2 (en) 2014-10-31 2017-04-28 Curve fitting circuit, analog predistorter, and radio frequency signal transmitter

Publications (1)

Publication Number Publication Date
WO2016065633A1 true WO2016065633A1 (zh) 2016-05-06

Family

ID=55856445

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/090095 WO2016065633A1 (zh) 2014-10-31 2014-10-31 一种曲线拟合电路、模拟预失真器和射频信号发射机

Country Status (6)

Country Link
US (1) US10141896B2 (zh)
EP (1) EP3197045B1 (zh)
JP (1) JP6442053B2 (zh)
KR (1) KR101926665B1 (zh)
CN (1) CN105745641B (zh)
WO (1) WO2016065633A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10742240B2 (en) 2017-01-25 2020-08-11 Huawei Technologies Co., Ltd. Signal processing method and device

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9590668B1 (en) 2015-11-30 2017-03-07 NanoSemi Technologies Digital compensator
US10812166B2 (en) 2016-10-07 2020-10-20 Nanosemi, Inc. Beam steering digital predistortion
CN110574288A (zh) 2017-02-25 2019-12-13 纳诺塞米有限公司 多频带数字预失真器
US10141961B1 (en) 2017-05-18 2018-11-27 Nanosemi, Inc. Passive intermodulation cancellation
US10581470B2 (en) 2017-06-09 2020-03-03 Nanosemi, Inc. Linearization system
US11115067B2 (en) 2017-06-09 2021-09-07 Nanosemi, Inc. Multi-band linearization system
US10931318B2 (en) * 2017-06-09 2021-02-23 Nanosemi, Inc. Subsampled linearization system
WO2019014422A1 (en) 2017-07-12 2019-01-17 Nanosemi, Inc. SYSTEMS AND METHODS FOR CONTROLLING RADIOS MADE WITH DIGITAL PREDISTORSION
WO2019070573A1 (en) 2017-10-02 2019-04-11 Nanosemi, Inc. DIGITAL PREDISTORSION ADJUSTMENT BASED ON DETERMINATION OF CHARGE CHARACTERISTICS
EP3791470A1 (en) 2018-05-11 2021-03-17 Nanosemi, Inc. Digital compensator for a non-linear system
US10644657B1 (en) 2018-05-11 2020-05-05 Nanosemi, Inc. Multi-band digital compensator for a non-linear system
EP3804127A1 (en) 2018-05-25 2021-04-14 NanoSemi, Inc. Digital predistortion in varying operating conditions
US10931238B2 (en) 2018-05-25 2021-02-23 Nanosemi, Inc. Linearization with envelope tracking or average power tracking
US11863210B2 (en) 2018-05-25 2024-01-02 Nanosemi, Inc. Linearization with level tracking
US10992326B1 (en) 2020-05-19 2021-04-27 Nanosemi, Inc. Buffer management for adaptive digital predistortion

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6425111B1 (en) * 1999-12-30 2002-07-23 The Board Of Trustees Of The Leland Stanford Junior University Saturation region transistor modeling for geometric programming
CN101068431A (zh) * 2007-06-11 2007-11-07 北京天碁科技有限公司 一种射频校准的方法及装置
CN101141206A (zh) * 2007-09-13 2008-03-12 中兴通讯股份有限公司 一种用于td-scdma中信干比测量的装置及其实现方法
CN103175547A (zh) * 2011-12-21 2013-06-26 北京普源精电科技有限公司 一种数据采集装置的参数拟合方法
US20130282332A1 (en) * 2012-04-24 2013-10-24 Askey Computer Corp. Method of obtaining linear curve fitting conversion equation for use with non-linear measurement system
CN103970719A (zh) * 2013-01-30 2014-08-06 华为技术有限公司 一种拟合方法及拟合装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4086804A (en) * 1976-10-26 1978-05-02 Sperry Rand Corporation Precision pneumatic pressure supply system
US4990803A (en) * 1989-03-27 1991-02-05 Analog Devices, Inc. Logarithmic amplifier
JP3841195B2 (ja) * 1998-12-02 2006-11-01 富士通株式会社 差動増幅器
US6678710B1 (en) * 2000-11-03 2004-01-13 Sun Microsystems, Inc. Logarithmic number system for performing calculations in a processor
US7301618B2 (en) * 2005-03-29 2007-11-27 Eastman Kodak Company Method and apparatus for uniformity and brightness correction in an OLED display
EP2117117B1 (en) 2006-12-27 2016-08-10 Sharp Kabushiki Kaisha Modulation digital-analog converter, digital signal processing method, and av device
JP5233651B2 (ja) 2008-12-18 2013-07-10 富士通株式会社 歪補償装置及び方法
JP2010157936A (ja) * 2008-12-27 2010-07-15 Sumitomo Electric Ind Ltd 歪補償回路及び無線基地局
US9084554B2 (en) * 2009-03-19 2015-07-21 The Regents Of The University Of California Multi-phase pseudo-continuous arterial spin labeling
JP5212316B2 (ja) * 2009-09-03 2013-06-19 富士通株式会社 無線通信装置及び無線通信方法
CN102143106B (zh) 2010-02-01 2013-08-21 富士通株式会社 自适应数字预失真装置及方法
US8320868B2 (en) * 2010-02-11 2012-11-27 Mediatek Singapore Pte. Ltd. Integrated circuits, communication units and methods of cancellation of intermodulation distortion
CN102551712B (zh) * 2011-06-13 2013-11-06 广州安德生物科技有限公司 基于生物电阻抗的非侵入式排尿报警装置及监测方法
US9470771B2 (en) * 2012-06-08 2016-10-18 Liposcience, Inc. NMR measurements of NMR biomarker GlycA
CN103257269B (zh) * 2013-04-26 2015-04-01 国家电网公司 基于实测电流特性曲线拟合的谐波源建模方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6425111B1 (en) * 1999-12-30 2002-07-23 The Board Of Trustees Of The Leland Stanford Junior University Saturation region transistor modeling for geometric programming
CN101068431A (zh) * 2007-06-11 2007-11-07 北京天碁科技有限公司 一种射频校准的方法及装置
CN101141206A (zh) * 2007-09-13 2008-03-12 中兴通讯股份有限公司 一种用于td-scdma中信干比测量的装置及其实现方法
CN103175547A (zh) * 2011-12-21 2013-06-26 北京普源精电科技有限公司 一种数据采集装置的参数拟合方法
US20130282332A1 (en) * 2012-04-24 2013-10-24 Askey Computer Corp. Method of obtaining linear curve fitting conversion equation for use with non-linear measurement system
CN103970719A (zh) * 2013-01-30 2014-08-06 华为技术有限公司 一种拟合方法及拟合装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10742240B2 (en) 2017-01-25 2020-08-11 Huawei Technologies Co., Ltd. Signal processing method and device

Also Published As

Publication number Publication date
JP6442053B2 (ja) 2018-12-19
US10141896B2 (en) 2018-11-27
JP2017532914A (ja) 2017-11-02
CN105745641B (zh) 2019-02-19
EP3197045A4 (en) 2017-07-26
CN105745641A (zh) 2016-07-06
KR101926665B1 (ko) 2018-12-07
KR20170070156A (ko) 2017-06-21
EP3197045A1 (en) 2017-07-26
US20170302233A1 (en) 2017-10-19
EP3197045B1 (en) 2018-09-19

Similar Documents

Publication Publication Date Title
WO2016065633A1 (zh) 一种曲线拟合电路、模拟预失真器和射频信号发射机
KR100890346B1 (ko) 디지털 보정 기능을 갖는 스위칭 증폭기 및 그에 대한 방법
US8976893B2 (en) Predistortion according to an artificial neural network (ANN)-based model
US8854128B2 (en) Amplifying device and signal processing device
JP2014011653A (ja) 歪補償装置および歪補償方法
US8536923B2 (en) Integrator distortion correction circuit
JP2011182068A (ja) べき級数型ディジタルプリディストータとその歪補償制御方法
JP4996503B2 (ja) 歪補償回路及びプリディストーション型歪補償増幅器
JP2017139762A (ja) 高調波歪み分離方法、非線形特性確定方法、装置及びシステム
EP3306817B1 (en) Predistortion system and method
CN107431495B (zh) 数字预失真校正方法及装置
US6801582B2 (en) Apparatus and method for improving an output signal from a nonlinear device through dynamic signal pre-distortion based upon Lagrange interpolation
JPWO2015125195A1 (ja) オーディオ信号増幅装置
US7889810B2 (en) Method and apparatus for a nonlinear feedback control system
CN109618270B (zh) 麦克风输入偏置校准方法及麦克风偏置装置
WO2020057371A1 (zh) 一种电压转脉宽调制信号电路
CN107918434B (zh) 功率放大电路的偏置电流产生电路
JP2012060254A (ja) 電力増幅システム
CN108254147B (zh) 振动台反馈信号分频段调幅系统
US8417193B2 (en) Transmitting device and method for determining target predistortion setting value
US2735616A (en) hoadley
US11047890B2 (en) Minimizing phase mismatch and offset sensitivity in a dual-path system
JP2004363713A (ja) 送信装置
Liu et al. An algorithm for loop delay estimation in digital predistortion system
CN107070414B (zh) 一种数字化预失真线性化器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14904793

Country of ref document: EP

Kind code of ref document: A1

REEP Request for entry into the european phase

Ref document number: 2014904793

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2014904793

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2017523242

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20177012917

Country of ref document: KR

Kind code of ref document: A