WO2016061884A1 - 一种三栅型显示面板 - Google Patents

一种三栅型显示面板 Download PDF

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Publication number
WO2016061884A1
WO2016061884A1 PCT/CN2014/093887 CN2014093887W WO2016061884A1 WO 2016061884 A1 WO2016061884 A1 WO 2016061884A1 CN 2014093887 W CN2014093887 W CN 2014093887W WO 2016061884 A1 WO2016061884 A1 WO 2016061884A1
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Prior art keywords
sub
lines
pixel
pixel units
fan
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English (en)
French (fr)
Inventor
杜鹏
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to RU2017117191A priority Critical patent/RU2653128C1/ru
Priority to GB1705787.8A priority patent/GB2545845B/en
Priority to JP2017520952A priority patent/JP6542886B2/ja
Priority to DE112014006976.0T priority patent/DE112014006976T5/de
Priority to KR1020177013407A priority patent/KR101963055B1/ko
Priority to US14/416,456 priority patent/US9263477B1/en
Publication of WO2016061884A1 publication Critical patent/WO2016061884A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/831—Electrodes characterised by their shape
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0213—Addressing of scan or signal lines controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours

Definitions

  • the present invention relates to the field of display technologies, and in particular to a three-gate display panel.
  • the source side When designing a Trigate Panel, traditionally to save cost, the source side often uses a high pin count design. For example, only one set of fanouts and one integrated circuit chip (IC) are used on the source side. However, the difference in resistance (Rmax-Rmin) on the fan-out area thus designed is generally large.
  • the main problem caused by the difference in the impedance of the fan-out area on the source side is that color shift occurs on both sides of the panel when displaying the mixed color picture.
  • the data line continuously charges two sub-pixels, and then charges the two sub-pixels of the next pixel. Due to the large impedance of the fan-out area, the RC delay of the signal is more serious. Therefore, the charging of the first charged sub-pixel is not as good as the second sub-pixel.
  • the impedance of the fan-out area is the largest, that is, the difference in the charging condition of the sub-pixels on both sides of the panel will result in color shift.
  • the present invention provides a three-gate type display panel capable of eliminating color shift or not generating color shift under mixed color screen display conditions, the panel comprising: a plurality of pixel units including three representing different colors a sub-pixel unit, wherein each of the sub-pixel units is provided with a thin film transistor whose source is connected to the charging electrode of each sub-pixel through the self-capacitance of the sub-pixel unit; the scanning line (G1, G2, ..
  • the fan-out area includes a plurality of fan-out lines, and the output ends of the fan-out lines are aligned with the scan lines, and are cross-connected with the respective scan lines, so that high-level pulses are sequentially applied to the fan-out lines.
  • the scanning lines are sequentially turned on in the order of G2, G1, ..., G2n, G(2n-1).
  • the three sub-pixel units represent red, yellow, and blue, respectively.
  • sub-pixel units of adjacent two columns of pixel units are arranged in the same color order.
  • each of the data lines is connected to a drain of a thin film transistor of each sub-pixel provided on one side of the data line.
  • each of the data lines is connected to a drain of a thin film transistor of a sub-pixel unit of a different color provided on both sides of the data line.
  • sub-pixel units of adjacent two columns of pixel units are arranged in the reverse order of color.
  • the data lines simultaneously charge the four sub-pixel units under the pulse control of the scan lines.
  • the invention changes the wiring mode on the panel, and the data line charges four sub-pixels at a time during operation. In this way, only half of the sub-pixel units are inconsistent in charging, thereby reducing the charging difference of sub-pixels of different colors, reducing the color shift under the mixed color picture, and improving the display quality of the tri-gate panel.
  • the sub-pixel unit colors of the adjacent two columns of pixel units are arranged in the reverse order, the charging difference of the different color sub-pixel units can be further reduced under the same pulse timing, thereby reducing the color shift as a whole.
  • the wiring design according to the present invention can relax the impedance limitation of the source side fan-out area at the time of design, so that the height of the fan-out end can be compressed to a greater extent, so that the panel of the narrow frame can be more advantageously designed.
  • FIG. 1 shows a wiring diagram of a fan-out terminal and a pixel unit of a conventional three-gate type display panel
  • Figure 2 shows the pixel charging of the middle area of the panel and the areas on both sides of the panel when the purple is to be displayed in the conventional three-gate type display panel;
  • FIG. 3 shows a timing chart of scan pulses supplied to the fan-out terminals of the three-gate type display panel
  • FIG. 4 shows a schematic diagram of a fan-out terminal interleaved with a pixel scan line in accordance with an embodiment of the present invention
  • Figure 5 shows a pulse timing diagram appearing on the line scan line arranged in accordance with Figure 4;
  • FIG. 6 shows a timing diagram for charging four pixel electrodes at a time to display, for example, purple, in accordance with an embodiment of the present invention
  • Figure 7 shows a three-gate panel layout structure in accordance with a second embodiment of the present invention.
  • Figure 8 shows a three-gate panel layout structure in accordance with a third embodiment of the present invention.
  • FIG. 9 shows the charging of the D1 data line and the D2 data line in accordance with the present invention.
  • FIG. 1 shows a wiring diagram of a fan-out terminal and a pixel unit of a conventional three-gate type display panel using a high pin count design on the source side.
  • D1 to D5 are data lines
  • G1 to G10 are gate lines
  • numbers in circles indicate the number of fanout lines.
  • FIG. 2 shows the charging of pixels corresponding to the display of the red-blue mixed color screen on the three-gate type display panel shown in FIG. 1.
  • the gate lines (or scan lines) are turned on one by one from top to bottom. Since the impedance difference between the source fan-out terminals in the middle and on both sides of the display panel is relatively large, the delay of the signal RC on the data line is also different. The data signal RC delay on both sides of the display panel is more severe, as shown in the waveform of Figure 2.
  • the red and blue sub-pixels are working, the data line first charges the blue sub-pixel, and then the red sub-pixel is charged.
  • the charging condition of all the blue sub-pixels is inferior to that of the red sub-pixels compared with the middle position of the panel.
  • the end result is that the sides of the panel will be reddish when displaying a purple screen. If the scanning direction is reversed, the sides will be bluish. Similarly, the same problem occurs when displaying a yellow or aqua blue screen.
  • Fig. 3 shows a timing chart of scan pulses supplied to the fan-out terminals of the three-gate type display panel.
  • each terminal of the fan-out area is connected to the scan line, and therefore, the timing of the scan pulse of the fan-out terminal coincides with the timing of the pulse appearing on the scan line.
  • Vgh represents a high potential
  • Vgl indicates a low potential
  • the scanning line signal is low
  • the thin film transistor TFT connected thereto is turned off.
  • the scan line inside the panel can be made according to 1, 2, 3, ..., 2n-1, 2n. Turning on one by one, it will cause the problem of color shift caused by the inconsistent charging time shown in the lower part of Fig. 2.
  • the present invention provides a wiring manner of a display panel, as shown in FIG. Figure 4 shows A schematic diagram of a fan-out terminal interleaved with a pixel scan line in accordance with an embodiment of the present invention.
  • the display panel includes: a plurality of pixel units including three sub-pixel units representing different colors, a thin film transistor is disposed on each of the sub-pixel units, and a source of the thin film transistor passes through the sub-pixel unit itself Capacitors are connected to the charging electrodes of the respective sub-pixels; the scanning lines (G1, G2, ..., G(2n-1), G2n) are sequentially arranged along the first direction of the display panel, such as the row direction or the horizontal direction, to The gates of the respective thin film transistors on the pixel unit are connected.
  • Data lines (D1, D2, ..., Dm) are disposed along a second direction of the display panel, such as a column direction or a vertical direction, to be connected to the drain of the thin film transistor provided on the sub-pixel unit.
  • the fan-out area includes a plurality of fan-out lines, and the output ends of the fan-out lines are aligned with the scan lines, and are cross-connected with the respective scan lines, so that when a high-level pulse is sequentially applied to each fan-out line,
  • the scanning lines are sequentially turned on in the order of G2, G1, ..., G2n, G(2n-1).
  • the three sub-pixel units represent red, yellow, and blue, respectively.
  • the present invention is not limited thereto, and the sub-pixel unit may also be a combination of other colors according to actual conditions.
  • each of the data lines is connected to a drain of a thin film transistor of each sub-pixel provided on one side of the data line.
  • the data line Under the pulse control of the scan line, the data line simultaneously charges four sub-pixel units.
  • the waveform of the charge is shown in Figure 6.
  • the sub-pixel unit color arrangement order of the adjacent two columns of pixel units is the same.
  • the color arrangement order of the sub-pixel units of the adjacent two columns of pixel units may also be reversed, as shown in FIG.
  • the pixel colors of the odd-numbered data lines are RGB arrays (ie, red, green, and blue) from top to bottom
  • the pixel colors corresponding to the even-numbered data lines are BGR arrays (ie, blue, green, and red).
  • the data line also continuously charges 4 pixels.
  • the purple picture is taken as an example.
  • the odd number of data lines are charged, the first red pixel is in poor charging condition, but the even number of data is inferior.
  • the line is charging, the charging condition of the first blue pixel is poor. As a whole, the difference in pixel charging of different colors has disappeared, and the color shift on both sides of the panel can be greatly improved.
  • the routing number of the fan-out area is in one-to-one correspondence with the number of the scanning lines inside the panel, and the same number is connected together, so they are all in accordance with 1, 2, 3, ... 2n.
  • the order of -1, 2n is turned on sequentially.
  • the structure in Figure 4 changes this connection.
  • the 2n-1 traces of the fan-out area are connected to the 2nth scan line inside the panel, the 2n traces of the fan-out area and the 2n- inside the panel. 1 scan connection.
  • the routing signal of the fan-out area is consistent with the previous conventional design, but due to the change of the connection mode, the order of opening the scanning lines inside the panel will change, and the corresponding waveform is shown in FIG. 5.
  • the scanning lines inside the panel are opened in the order of 2, 1, 4, 3, ... 2n, 2n-1.
  • the pixel color and data line waveform corresponding to each scan line in FIG. 5 is as shown in FIG. 6.
  • the data lines (D1-D5) charge four sub-pixels at a time, reducing the difference in charging conditions of different color sub-pixels as a whole. For example, in the purple picture showing the red-blue color mixture, the scanning line is turned on from top to bottom.
  • the waveforms of the data signals in the middle and on both sides of the panel are as shown in Fig. 6.
  • the data lines charge four sub-pixels at a time. On both sides of the panel, the charging of the first sub-pixel of the four sub-pixels is worse than the other three sub-pixels due to the RC delay.
  • FIG. 7 is a second embodiment of the present invention.
  • each of the data lines is connected to the drains of the thin film transistors of the sub-pixel units of different colors provided on both sides of the data line, so that the data lines are interleaved.
  • the ground is charged to each sub-pixel located on both sides to improve the color shift on both sides of the panel. From the viewpoint of improving the color shift effect, it is the same as that of FIG. However, charging the pixel unit by interleaving two data lines can reduce the power consumption of a single data line, thereby extending the life of the display panel.
  • the new display panel wiring method reduces the charging difference of different color sub-pixels, thereby avoiding the color shift on both sides of the mixed color picture and improving the display effect.
  • the limitation of the impedance of the source side fan-out area during design is relaxed, which is also advantageous for achieving a narrow bezel design.

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Abstract

一种三栅型显示面板，包括若干像素单元，像素单元包含三个表示不同颜色的子像素单元，在各自像素单元上设有薄膜晶体管，薄膜晶体管的源极通过子像素单元的自身电容连接到各个子像素的充电电极上。扫描线（G1, G2,……, G2n, G(2n-1)）沿显示面板的第一方向依次设置，以与子像素单元上的各个薄膜晶体管的栅极连接。数据线（D1, D2,……, Dm）沿显示面板的第二方向设置，以与子像素单元上设置的薄膜晶体管的漏极连接。扇出区，其包括多条扇出线，各条扇出线的输出端与扫描线排列一致，并与各条扫描线两两交叉连接。三栅型显示面板减小了不同颜色子像素的充电差异，从而避免了混色画面两侧的色偏，改善显示效果，同时放宽了设计时源侧扇出区阻抗的限制从而利于窄边框的设计。

Description

一种三栅型显示面板
相关申请的交叉引用
本申请要求享有2014年10月20日提交的名称为“一种三栅型显示面板”的中国专利申请CN201410559614.3的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，具体说，涉及一种三栅型显示面板。
背景技术
在设计三栅型显示面板(Trigate Panel)时，传统上为了节省成本，源侧(source)往往采用高脚数(high pin count)的设计。例如，在源侧只使用一组扇出端子(fanout)和一个集成电路芯片(IC)。但是这样设计出的扇出区上的电阻差异(Rmax-Rmin)一般比较大。
在实际工作时，源侧的扇出区的阻抗差异太大带来的主要问题就是显示混色画面时面板两侧有色偏产生。在混色画面下，数据线会连续对两个子像素进行充电，然后再对下一像素的两个子像素进行充电，由于扇出区阻抗较大，信号的RC延迟比较严重。因此，第一个充电的子像素的充电情况不如第二个子像素理想。特别是在扇出区走线阻抗最大的地方，也就是在面板两侧上子像素充电情况的差异将会导致色偏。
因此，需要设计一种在混色画面显示条件下能够消除色偏或者不产生色偏的三栅型显示面板。
发明内容
为了解决上述技术问题，本发明提供了一种在混色画面显示条件下能够消除色偏或者不产生色偏的三栅型显示面板，该面板包括：若干像素单元，其包含三个表示不同颜色的子像素单元，在各个子像素单元上设有薄膜晶体管，所述薄膜晶体管的源极通过所述子像素单元的自身电容连接到各个子像素的充电电极上；扫描线(G1，G2，...，G(2n-1)，G2n)，其沿显示面板的第一方向依次设置，以与子像素单元上的各个薄膜晶体管的栅极连接；数据线，其沿显示面板的第二方向设置，以与子像素单元上设置的薄膜晶体管的漏极连接； 扇出区，其包括多条扇出线，各条扇出线的输出端与所述扫描线排列一致，并与各条扫描线两两交叉连接，使得在给各条扇出线依次施加高电平脉冲时，所述扫描线按G2，G1，...，G2n，G(2n-1)的顺序依次导通。
根据本发明的一个实施例，三个子像素单元分别表示红色、黄色、蓝色。
根据本发明的一个实施例，相邻两列像素单元的子像素单元颜色排列顺序相同。
根据本发明的一个实施例，每条数据线与设在该数据线一侧的各子像素的薄膜晶体管的漏极连接。
根据本发明的一个实施例，每条数据线与设在该数据线两侧的表示不同颜色的子像素单元的薄膜晶体管的漏极连接。
根据本发明的一个实施例，相邻两列像素单元的子像素单元颜色排列顺序相反。
根据本发明的一个实施例，在扫描线的脉冲控制下，数据线同时给四个子像素单元进行充电。
本发明改变了面板上的布线方式，工作时数据线一次对四个子像素进行充电。这样只有一半的子像素单元充电情况不一致，从而减小了不同颜色的子像素的充电差异，减轻混色画面下的色偏，改善了三栅型面板的显示品质。当将相邻两列像素单元的子像素单元颜色以相反的顺序排列时，在同样的脉冲时序下，可进一步地减小不同颜色子像素单元的充电差异，从而从整体上减小色偏。
另外，按照本发明的布线设计可以放宽设计时源侧扇出区的阻抗限制，这样可以更大程度地压缩扇出端的高度，从而可以更加有利地设计窄边框的面板。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。在附图中：
图1显示了传统三栅型显示面板的扇出端子与像素单元的布线图；
图2显示了在传统的三栅型显示面板中要显示紫色时面板中间区域与面板两侧区域的像素充电情况；
图3显示了提供给三栅型显示面板的扇出端子的扫描脉冲时序图；
图4显示了根据本发明的一个实施例的扇出端子与像素扫描线交错连接的示意图；
图5显示了按照图4布置的线路扫描线上出现的脉冲时序图；
图6显示了根据本发明的实施例一次对4个像素电极进行充电以显示例如紫色的时序图；
图7显示了根据本发明的第二实施例的三栅型面板布局结构；
图8显示了根据本发明的第三实施例的三栅型面板布局结构；以及
图9显示了根据本发明以D1数据线和D2数据线进行充电的情况。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
图1显示了在源侧采用高脚数(high pin count)设计的传统三栅型显示面板的扇出端子与像素单元的布线图。其中，D1～D5为数据线(Data Line)，G1～G10为扫描线(Gate Line)，圈中的数字表示扇出区(Fanout)线路的编号。
图2显示了对应于图1所示的三栅型显示面板上显示红蓝混色画面时像素的充电情况。栅极线(或者说扫描线)自上而下逐条开启。由于显示面板中间和两侧的源扇出端子阻抗差异比较大，因此数据线(data line)上信号RC延迟的情况也各不相同。显示面板两侧的数据信号RC延迟更加严重，如图2中所示的波形。红、蓝两色的子像素在工作时，数据线先对蓝色子像素进行充电，然后是对红色子像素充电。由于在面板两侧信号波形的延迟比较严重，因此与面板中间位置的相比，所有的蓝色子像素的充电情况会比红色子像素充电的情况差。最终的结果就是面板两侧在显示紫色画面时会偏红，如果扫描方向相反，则会出现画面两侧偏蓝的现象。同样，在显示黄色、水蓝色画面时也会存在同样的问题。
图3显示了提供给三栅型显示面板的扇出端子的扫描脉冲时序图。按照图1所示的传统布线方式，扇出区各个端子与扫描线对应连接，因此，扇出端子的扫描脉冲时序与扫描线上出现的脉冲时序一致。其中，Vgh表示高电位，当扫描线信号为高电位时，与之相连的薄膜晶体管TFT打开，相关像素进行充电。Vgl表示低电位，当扫描线信号为低电位时，与之相连的薄膜晶体管TFT关闭。从圈中标识的数字可以看出，按照图1所示的扇出区与扫描线之间的走线关系可以使面板内部的扫描线按照1，2，3，……，2n-1，2n逐条开启，因此会造成图2中下方所示充电时间不一致导致色偏的问题。
为解决上述问题，本发明提供了一种显示面板的布线方式，如图4所示。图4显示了 根据本发明的一个实施例的扇出端子与像素扫描线交错连接的示意图。
在图4显示的电路中，显示面板包括：若干像素单元，其包含三个表示不同颜色的子像素单元，在各个子像素单元上设有薄膜晶体管，薄膜晶体管的源极通过子像素单元的自身电容连接到各个子像素的充电电极上；扫描线(G1，G2，...，G(2n-1)，G2n)沿显示面板的第一方向例如行方向或者水平方向依次设置，以与子像素单元上的各个薄膜晶体管的栅极连接。数据线(D1，D2，...，Dm)，其沿显示面板的第二方向例如列方向或者纵向设置，以与子像素单元上设置的薄膜晶体管的漏极连接。扇出区，其包括多条扇出线，各条扇出线的输出端与扫描线排列一致，并与各条扫描线两两交叉连接，使得在给各条扇出线依次施加高电平脉冲时，扫描线按G2，G1，...，G2n，G(2n-1)的顺序依次导通。
在本发明的一个实施例中，三个子像素单元分别表示红色、黄色、蓝色。当然本发明并不限于此，根据实际情况下子像素单元还可以是其它颜色的组合。
在本发明的一个实施例中，每条数据线与设在该数据线一侧的各子像素的薄膜晶体管的漏极连接。在扫描线的脉冲控制下，数据线同时给四个子像素单元进行充电。充电的波形见图6。
在如图4所示的面板布局电路中，相邻两列像素单元的子像素单元颜色排列顺序是相同的。当然相邻两列像素单元的子像素单元颜色排列顺序也可以是相反的，如图8所示。在图8中，奇数条的数据线从上往下对应的像素颜色为RGB排列(即红绿蓝排列)，偶数条的数据线对应的像素颜色则是BGR排列(即蓝绿红排列)。以D1数据线和D2数据线充电的情况为例，如图9所示。
在这种布线方式下，数据线也是连续对4个像素进行充电，同样以紫色画面为例，奇数条的数据线在充电时，第一个红色的像素充电情况较差，但偶数条的数据线在充电时，则是第一个蓝色像素的充电情况较差，整体来看，不同颜色的像素充电差异已经消失，面板两侧的色偏相比较而言可以得到很大的改善。
在图1呈现的传统设计中，扇出区的走线编号与面板内部扫描线的编号是一一对应的，相同编号的连接在一起，因此它们都是按照1，2，3，……2n-1，2n的顺序依次开启。而图4中的结构改变了这种连接方式，扇出区的第2n-1条走线和面板内部的第2n条扫描线连接，扇出区第2n条走线和面板内部的第2n-1条扫描连接。扇出区的走线信号与前面的传统设计一致，但由于连接方式的改变，所以面板内部扫描线的开启顺序会发生变化，对应的波形如图5所示。
从时序上来看，面板内部的扫描线开启顺序为2，1，4，3，……2n，2n-1。
图5中每一条扫描线所对应的像素颜色和数据线波形如图6所示，在这种布线方式下， 数据线(D1-D5)一次对4个子像素进行充电，减小了整体上不同颜色子像素充电情况的差异。同样以显示红蓝混色的紫色画面为例，扫描线自上而下开启。则面板中间和两侧数据信号的波形如图6，数据线一次对4个子像素进行充电。在面板的两侧，由于RC延迟比较严重，4个子像素中第一个子像素的充电情况比另外3个子像素差。但是从整体来看，面板两侧只有一半数量的红色子像素和蓝色子像素充电情况不一致，而另外一半的子像素充电情况是相同的。而传统的三栅型显示面板设计，面板两侧所有的红色子像素和蓝色子像素充电的情况都不同。因此采用这个布线方式可以有效地改善不同颜色子像素充电情况的差异，可以极大程度的减轻面板两侧色偏。
图7是本发明的第二个实施例，在这个实施例中，每条数据线与设在该数据线两侧的表示不同颜色的子像素单元的薄膜晶体管的漏极连接，使得数据线交错地给位于两侧的各个子像素充电，从而改善面板两侧的色偏。从改善色偏效果而言，其与图4是相同的。但是，采用两条数据线交错给像素单元充电可以减小单条数据线的功耗，从而延长显示面板的寿命。
采用新的显示面板布线方式，减小了不同颜色子像素的充电差异，从而避免了混色画面两侧的色偏，改善显示效果。放宽了设计时源侧扇出区阻抗的限制，对实现窄边框设计也是有利的。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所揭露的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (7)

  1. 一种三栅型显示面板，其包括：
    若干像素单元，其包含三个表示不同颜色的子像素单元，在各个子像素单元上设有薄膜晶体管，所述薄膜晶体管的源极通过所述子像素单元的自身电容连接到各个子像素的充电电极上；
    扫描线(G1，G2，...，G(2n-1)，G2n)，其沿显示面板的第一方向依次设置，以与子像素单元上的各个薄膜晶体管的栅极连接；
    数据线，其沿显示面板的第二方向设置，以与子像素单元上设置的薄膜晶体管的漏极连接；
    扇出区，其包括多条扇出线，各条扇出线的输出端与所述扫描线排列一致，并与各条扫描线两两交叉连接，使得在给各条扇出线依次施加高电平脉冲时，所述扫描线按G2，G1，...，G2n，G(2n-1)的顺序依次导通。
  2. 如权利要求1所述的三栅型显示面板，其中，三个子像素单元分别表示红色、黄色、蓝色。
  3. 如权利要求2所述的三栅型显示面板，其中，相邻两列像素单元的子像素单元颜色排列顺序相同。
  4. 如权利要求2所述的三栅型显示面板，其中，每条数据线与设在该数据线一侧的各子像素的薄膜晶体管的漏极连接。
  5. 如权利要求3所述的三栅型显示面板，其中，每条数据线与设在该数据线两侧的表示不同颜色的子像素单元的薄膜晶体管的漏极连接。
  6. 如权利要求4所述的三栅型显示面板，其中，相邻两列像素单元的子像素单元颜色排列顺序相反。
  7. 如权利要求1所述的三栅型显示面板，其中，在扫描线的脉冲控制下，数据线同时给四个子像素单元进行充电。
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