WO2016033997A1 - 一种抗色偏显示面板 - Google Patents

一种抗色偏显示面板 Download PDF

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Publication number
WO2016033997A1
WO2016033997A1 PCT/CN2015/080606 CN2015080606W WO2016033997A1 WO 2016033997 A1 WO2016033997 A1 WO 2016033997A1 CN 2015080606 W CN2015080606 W CN 2015080606W WO 2016033997 A1 WO2016033997 A1 WO 2016033997A1
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sub
pixels
pixel
row
pixel array
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PCT/CN2015/080606
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English (en)
French (fr)
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王聪
杜鹏
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深圳市华星光电技术有限公司
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Priority to US14/777,257 priority Critical patent/US9952474B2/en
Publication of WO2016033997A1 publication Critical patent/WO2016033997A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0232—Special driving of display border areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours

Definitions

  • the present invention relates to a liquid crystal display panel, and more particularly to an anti-color shift display panel.
  • the charging effect of the first Sub-pixel will be worse than that of the second Sub-pixel.
  • Fanout has the largest resistance value, the RC signal delay is the most serious, and the color shift is the most obvious.
  • FIG. 1A shows the case where the traditional wiring method Trigate display panel of the source side adopts the High Pin Count display red-blue mixed color picture (the green sub-pixels are not charged at this time), and the scanning lines are turned on one by one from top to bottom (ie, the scanning direction is From top to bottom, the Source Fanout impedance difference between the middle and the sides of the display panel is large, so the delay of the signal RC on the data line is also different, and the data signal RC delay on both sides of the display panel is more serious.
  • Red and blue Sub-pixels are the first to work The blue Sub-pixel is charged, then the red Sub-pixel is charged (between the adjacent two rows of green Sub-pixels). Referring to FIGS.
  • the display panel is two compared with the intermediate position of the display panel (the A area shown in FIG. 1B).
  • the charging condition of all the blue Sub-pixels on the side will be worse than that of the red Sub-pixel.
  • the final result is that the sides of the panel will be reddish when displaying the purple screen. If the scanning direction is opposite, the screen will be biased. The phenomenon of blue. Similarly, the same problem occurs when displaying a yellow, water blue screen.
  • D1 to D5 are data lines
  • G1 to G10 are gate lines
  • numbers in circles represent fan-out areas (Fanout) The number of the line.
  • the charging sequence of the data line is R ⁇ G ⁇ B ⁇ R ⁇ G ⁇ B.
  • FIG. 3 is a schematic diagram of a waveform of a scan line signal, in which Vgh is a high potential, and when the scan line signal is at a high potential, a transistor (TFT) connected thereto is turned on, and the relevant pixel is charged. Vg1 is low and the connected TFT is turned off when the scan line signal is low.
  • the signal given by the Panout area is that the scan lines inside the display panel are opened one by one according to 1, 2, 3, ... 2n-1, 2n, thus causing Figure 1D shows the problem of color cast on both sides.
  • the invention is directed to the defect that the existing three-gate liquid crystal display panel is prone to color shift during the color mixing process, and provides an anti-color shift display panel.
  • the technical solution adopted by the present invention is to provide a color-resistant display panel comprising a sub-pixel array, a plurality of data lines and a plurality of scan lines, each of the sub-pixel arrays including a transistor
  • the data lines are arranged in a column direction, the scan lines and the data lines Interleaving, each sub-pixel in the sub-pixel array is located between two adjacent scan lines and two adjacent data lines, wherein each scan line does not alternately shuttle between the sub-pixels in the sub-pixel array
  • Each row of sub-pixels in the sub-pixel array includes a plurality of sub-pixel groups, each of the sub-pixel groups includes two sub-pixels, and the gates of the transistors of the two sub-pixels are respectively connected to two adjacent scan lines and sources.
  • the poles are connected to the same data line, and the drains are connected with a liquid crystal capacitor and a storage capacitor, and the other ends of the liquid crystal capacitor and the storage capacitor connected to the transistor are connected to a common line.
  • the scan lines are arranged in a square waveform, and each sub-pixel in one row of sub-pixels in the sub-pixel array is sequentially bypassed.
  • the rising edge positions of the scanning lines of the respective waveforms correspond to each other, and the falling edge positions correspond.
  • the scan lines are arranged in a periodic stepped manner, and are shuttled between two adjacent sub-pixels in the column of the sub-pixels.
  • the Nth stepped scan line sequentially bypasses the Nth row, the Mth subpixel, the N+1th row, and the M+1th subpixel in the subpixel array, N+1 rows, M+2 sub-pixels, and N+1th row, M+3th sub-pixels, and scan lines of each cycle are connected to each other, where N and M are both natural numbers.
  • each row of sub-pixels in the sub-pixel array displays one of red, green, and blue, and adjacent three rows of sub-pixels display complementary colors.
  • the anti-color shift display panel of the present invention has the following beneficial effects: when performing normal display, one data line can charge two sub-pixels displaying the same color, so that the number of sub-pixels in which the color shift occurs accounts for the number of collated sub-pixels.
  • the proportional decrease reduces the charging difference of sub-pixels of different colors, improves the charging rate, and effectively suppresses the degree of color shift. Especially for the two sides of the panel where the RC delay is more serious, the degree of color shift is greatly reduced.
  • 1A is a schematic view showing a red-blue color mixing screen of a conventional three-gate liquid crystal display panel
  • 1B is a schematic view showing a side region and an intermediate region of a conventional three-gate liquid crystal display panel
  • 1C is a schematic diagram of data signals in a middle region of a conventional three-gate liquid crystal display panel
  • 1D is a schematic diagram of data signals of two sides of a conventional three-gate liquid crystal display panel
  • 2 is a wiring manner of a conventional three-gate liquid crystal display panel
  • FIG. 3 is a schematic diagram of a scan line signal waveform of a conventional three-gate liquid crystal display panel
  • FIG. 4 is a schematic view showing the wiring of the first example of the anti-color shift display panel of the present invention.
  • 5A is a first example of a color-resistant display panel of the present invention. in a red and blue mixed color screen, a pixel color and a data line waveform corresponding to each scan line in a middle portion of the panel;
  • 5B is a first example of the anti-color-biased display panel of the present invention, in the red and blue mixed color screen, the pixel color and the data line waveform corresponding to each scan line in the two sides of the panel;
  • Fig. 6 is a schematic view showing the wiring of the second example of the anti-color shift display panel of the present invention.
  • the anti-color shift display panel includes a sub-pixel array, a plurality of data lines, and a plurality of scan lines.
  • Each of the sub-pixel arrays includes a transistor, and the transistor may be a thin film field effect transistor (TFT).
  • TFT thin film field effect transistor
  • the data lines are arranged in the column direction.
  • the scan lines are interleaved with the data lines, and the scan lines are shuttled between the sub-pixels in the sub-pixel array without interlacing.
  • Each of the data lines and each of the scan lines is arranged such that each sub-pixel in the sub-pixel array is located between two adjacent scan lines and two adjacent data lines.
  • each row of sub-pixels includes a plurality of sub-pixel groups, each of the sub-images
  • the prime group is composed of two sub-pixels, and the gates of the transistors of the two sub-pixels in each sub-pixel group are respectively connected to two adjacent scan lines, the source is connected to the same data line, and the drain is connected with the liquid crystal capacitor and the memory.
  • the energy capacitor, the liquid crystal capacitor, and the other end of the storage capacitor connected to the transistor are connected to a common line.
  • Each row of sub-pixels in the sub-pixel array displays one of red, green, and blue, and adjacent three rows of sub-pixels display complementary colors.
  • the number of rows of sub-pixel arrays, the number of columns, and the number of sub-pixels in each row are determined according to actual requirements.
  • the scan lines are arranged in a square waveform, and each sub-pixel in one row of sub-pixels in the sub-pixel array is sequentially bypassed, and the rising edge positions of the scan lines of the respective waveforms correspond to each other, and the falling edge positions correspond.
  • the anti-color shift display panel in the present embodiment will be described in detail by taking, as an example, seven data lines D1-D7, nine scanning lines G1-G9, and nine rows and eight columns of sub-pixel arrays.
  • the trace number of the Fanout area has a one-to-one correspondence with the number of the scan lines inside the panel, so they are all in the order of 1, 2, 3, ..., n-1, n. Turn it on in turn.
  • the sub-pixels of 1 to 9 rows display colors in the order of red (R), green (G), blue (B), R, G, B, R, G, B.
  • the structure of the scan line is changed to be converted into a square waveform, and the Nth scan line is in accordance with the signal of the scan line.
  • the transmission direction ie, the left-to-right direction facing the drawing
  • the structure of the data line does not change.
  • the display is green, including 4 sub-pixel groups
  • the first sub-pixel group includes transistors Q1 and Q2
  • the second sub-pixel group includes transistors Q3 and Q4,
  • the third sub-pixel group includes transistor Q5 and Q6.
  • the second scan line sequentially bypasses the sub-pixels including transistors Q1, Q2, Q3, Q4, Q5, and Q6.
  • the first data line D1 when displaying normally, the first data line D1
  • the charging sequence is R->B->B->G->G->R->R->B->B->G->G, and the rest of the cases are analogous.
  • FIG. 5A is a diagram showing a pixel color and a data line waveform corresponding to each scan line in the middle area of the panel in the red and blue mixed color picture according to the first embodiment of the anti-color shift display panel. Since the RC delay in the middle area of the panel is not serious, the color is The bias is not obvious.
  • FIG. 5B is a diagram showing the pixel color and data line waveform corresponding to each scanning line in the two sides of the panel under the red and blue mixed color screen in the first embodiment of the anti-color shift display panel, as shown in FIG. 5B.
  • the same data line charges four sub-pixels at a time, although in the two sides of the panel where the RC delay is severe, the charging condition of the first sub-pixel of the four sub-pixels is worse than the other three sub-pixels, but from the whole It can be seen that only half of the red sub-pixels and the blue sub-pixels are inconsistently charged, and the other half of the red sub-pixels and the blue sub-pixels are charged the same, thus effectively improving the difference in charging conditions of different color sub-pixels, which is large. To a lesser extent, the color cast on both sides of the panel is reduced.
  • one data line when performing normal display, one data line can charge two sub-pixels displaying the same color, so that the number of sub-pixels in which the color shift occurs accounts for the collation
  • the proportion of the number of pixels is decreased, and the degree of color shift is effectively suppressed.
  • the degree of color shift is greatly reduced.
  • the difference from the first embodiment is that the scan lines are arranged in a periodic stepped manner and are shuttled between adjacent two rows of sub-pixels in the sub-pixel array. Specifically, in one cycle, the Nth stepped scan line sequentially bypasses the Nth row and the Mth subpixel in the subpixel array, the N+1th row, the M+1th subpixel, and the N+th 1 row, M+2 sub-pixels, and N+1th row, M+3 sub-pixels, and scan lines of each period are connected to each other. Both N and M are natural numbers.
  • the anti-color shift display panel in the present embodiment will be described in detail by taking a sub-pixel array of seven scanning lines G1-G7, seven data lines D1-D7, and eight rows and eight columns as an example.
  • the trace number of the Fanout area has a one-to-one correspondence with the number of the scan lines inside the panel, so they are all in the order of 1, 2, 3, ..., n-1, n.
  • the sub-pixels of 1 to 8 rows display colors in the order of R, G, B, R, G, B, R, G.
  • the structure of the scanning line is changed to a step-like shape that changes periodically, as compared with the conventional three-gate liquid crystal display panel.
  • the Nth scan line shuttles between the Nth row of subpixels and the (N+1)th row of subpixels.
  • the second scanning line G2 shuttles between the second and third rows of sub-pixels. Specifically, the second scanning line G2 sequentially bypasses the second row and the first sub-pixel (including the sub-pixel of the transistor Q7). The third row, the second sub-pixel (including the sub-pixel of the transistor Q8), the third row, the third sub-pixel (including the sub-pixel of the transistor Q9), and the third row and the fourth sub-pixel (including the sub-pixel of the transistor Q10) . The next cycle starts from the second row, the fifth sub-pixel (including the sub-pixel of the transistor Q11), and the scanning lines of the respective periods are connected to each other (i.e., one scanning line is continuous).
  • the timing of the scan line turn-on remains unchanged, starting from G1 to G7.
  • the charging order of the sub-pixels is: G ⁇ G ⁇ R ⁇ R ⁇ B ⁇ B. Therefore, in the two-color mixed color picture, the same data line can simultaneously charge four sub-pixels, as in the case of a red and blue mixed color purple picture, see FIG. 5B, the data line is charged, the first red Sub-pixel (transistor) charging is poor, but the color mixing picture of the two sub-pixels is saturated. As a whole, the sub-pixel charging difference of different colors has disappeared, and the color shift on both sides of the panel is greatly improved.
  • one data line when performing normal display, one data line can charge two sub-pixels displaying the same color, so that the number of sub-pixels in which the color shift occurs accounts for the collation
  • the proportion of the number of pixels is decreased, and the degree of color shift is effectively suppressed.
  • the degree of color shift is greatly reduced.

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Abstract

一种抗色偏显示面板，包括子像素阵列、多条数据线以及多条扫描线，数据线沿列方向排布，子像素阵列中的每个子像素位于两相邻的扫描线以及两相邻的数据线之间，各扫描线互不交错地穿梭在所述子像素阵列中的子像素之间，且子像素阵列中的每一行子像素包括多个包含两个子像素的子像素组，且两个子像素的晶体管的栅极分别连接两条相邻的扫描线、源极连接同一条数据线、漏极均连接有液晶电容和储能电容。在进行正常显示时，一条数据线能够为显示同种颜色的两个子像素进行充电，使得出现色偏的子像素数量占整理混色子像素数量的比例下降，有效地抑制了色偏的程度。

Description

一种抗色偏显示面板 技术领域
本发明涉及液晶显示面板，更具体地说，涉及一种抗色偏显示面板。
背景技术
在传统的三栅极型(Trigate)液晶显示面板中，往往是将晶体管源极(Source)IC侧采用高引脚(High Pin Count)的设计，这样可以降低成本。但是在Source侧仅采用单个IC和一组扇出区(Fanout)，会出现Fanout阻值差异很大的情况。在实际工作中，如果Fanout阻值差异过大，带来的问题就是在混色画面中，显示面板两侧会出现色偏的现象。例如，在显示一个两色混色的画面时，数据线会持续对两个子像素(Sub-pixel)进行充电，然后再对下一个像素的两个Sub-pixel进行充电。如果Fanout阻值过大，RC信号的延迟就会严重，在充电的过程中，第一个Sub-pixel的充电效果就会比第二个Sub-pixel的要差。特别是在显示面板的两端，Fanout的阻值最大，RC信号延迟最严重，色偏最为明显。
图1A是Source侧采用High Pin Count设计的传统布线方式Trigate显示面板显示红蓝混色画面的情况(此时绿色的子像素不会被充电)，扫描线自上而下逐条开启(即扫描方向为自上而下)，显示面板中间和两侧的Source Fanout阻抗差异较大，所以数据线上信号RC延迟的情况也各不相同，显示面板两侧的数据信号RC延迟更为严重。红、蓝两色的Sub-pixel在工作时是先 对蓝色Sub-pixel进行充电，然后是红色Sub-pixel充电(在相邻的两行绿色的Sub-pixel之间)。参见图1B-1D，由于在显示面板两侧(图1B中所示B区域)信号波形的延迟比较严重，所以与显示面板中间位置(图1B中所示A区域)的相比，显示面板两侧所有的蓝色Sub-pixel的充电情况会比红色Sub-pixel充电的情况差，最终的结果就是面板两侧在显示紫色画面时会偏红，如果扫描方向相反，则会出现画面两侧偏蓝的现象。同样，在显示黄色，水蓝色画面时也会存在同样的问题。
图2是三栅极型液晶显示面板一种传统的布线方式，其中D1～D5为数据线(Data Line)，G1～G10为扫描线(Gate Line)，圈中的数字表示扇出区(Fanout)线路的编号。在传统的设计中，data line的充电顺序为R→G→B→R→G→B。
图3是扫描线信号波形的示意图，其中Vgh是高电位，扫描线信号为高电位时，与之相连的晶体管(TFT)打开，相关像素进行充电。Vg1是低电位，扫描线信号为低电位时，相连的TFT关闭。从圈中标识的数字可以看出，Fanout区走线给出的信号是让显示面板内部的扫描线按照1，2，3，......2n-1，2n逐条开启，因此会造成图1D中两侧色偏的问题。
发明内容
本发明针对现有的三栅极型液晶显示面板在混色过程中容易出现色偏的缺陷，提供一种抗色偏显示面板。
本发明解决其技术问题采用的技术方案是：提供一种抗色偏显示面板，包括子像素阵列、多条数据线以及多条扫描线，所述子像素阵列中的每一个子像素包括一晶体管，所述数据线沿列方向排布，所述扫描线与所述数据线 交错，所述子像素阵列中的每个子像素位于两相邻的扫描线以及两相邻的数据线之间，其中，各扫描线互不交错地穿梭在所述子像素阵列中的子像素之间，所述子像素阵列中的每一行子像素包括多个子像素组，每个所述子像素组包括两个子像素且两个子像素的晶体管的栅极分别连接两条相邻的扫描线、源极连接同一条数据线、漏极均连接有液晶电容和储能电容，所述液晶电容和所述储能电容与所述晶体管连接的另一端接公共线。
优选地，所述扫描线呈方波形设置，依次绕过所述子像素阵列中一行子像素中的各子像素。
优选地，各方波形的扫描线的上升沿位置相对应，下降沿位置相对应。
优选地，所述扫描线呈周期性阶梯状设置，穿梭在所述子像素这列中相邻的两行子像素之间。
优选地，在一个周期中，第N条呈阶梯状的扫描线依次绕过所述子像素阵列中的第N行、第M个子像素，第N+1行、第M+1个子像素，第N+1行、第M+2个子像素，以及第N+1行、第M+3个子像素，且每个周期的扫描线相互连接，其中N和M均为自然数。
优选地，所述子像素阵列中的每一行子像素显示红色、绿色和蓝色中的一种颜色，且相邻的三行子像素显示的颜色互补相同。
本发明的抗色偏显示面板具有以下有益效果：在进行正常显示时，一条数据线能够为显示同种颜色的两个子像素进行充电，使得出现色偏的子像素数量占整理混色子像素数量的比例下降，减少了不同颜色的子像素的充电差异，提高了充电率，有效地抑制了色偏的程度，特别是对于RC延迟较为严重的面板两侧区域，色偏的程度将大大下降。
附图说明
图1A为传统的三栅极型液晶显示面板显示红蓝混色画面的示意图；
图1B为传统的三栅极型液晶显示面板两侧区域和中间区域的示意图；
图1C为传统的三栅极型液晶显示面板中间区域的数据信号示意图；
图1D为传统的三栅极型液晶显示面板两侧区域的数据信号示意图；
图2为传统的三栅极型液晶显示面板的布线方式；
图3为传统的三栅极型液晶显示面板的扫描线信号波形的示意图；
图4为本发明的抗色偏显示面板第一示例的布线示意图；
图5A为本发明的抗色偏显示面板第一示例在红色和蓝色混色画面下，面板中间区域每一条扫描线所对应的像素颜色和数据线波形；
图5B为本发明的抗色偏显示面板第一示例在红色和蓝色混色画面下，面板两侧区域每一条扫描线所对应的像素颜色和数据线波形；
图6为本发明的抗色偏显示面板第二示例的布线示意图。
具体实施方式
以下结合附图和实施例对本发明做进一步的解释说明。
在本发明的抗色偏显示面板的第一实施例中，抗色偏显示面板包括子像素阵列、多条数据线以及多条扫描线。子像素阵列中的每一个子像素包括一个晶体管，晶体管可以是薄膜场效应晶体管(TFT)。数据线沿列方向排布。扫描线与数据线交错，且各扫描线互不交错地穿梭在子像素阵列中的子像素之间。各数据线和各扫描线的排布方式，使得子像素阵列中的每个子像素位于两相邻的扫描线以及两相邻的数据线之间。
具体的，在子像素阵列中，每一行子像素包括多个子像素组，每个子像 素组由两个子像素组成，且每个子像素组中的两个子像素的晶体管的栅极分别连接两条相邻的扫描线、源极连接同一条数据线、漏极均连接有液晶电容和储能电容，液晶电容和所述储能电容与所述晶体管连接的另一端接公共线。
子像素阵列中的每一行子像素显示红色、绿色和蓝色中的一种颜色，且相邻的三行子像素显示的颜色互补相同。子像素阵列的行数、列数以及每行中子像素的数量根据实际要求而定。
在本实施例中，扫描线呈方波形设置，且依次绕过子像素阵列中一行子像素中的各子像素，并且各方波形的扫描线的上升沿位置相对应，下降沿位置相对应。
以下以7条数据线D1-D7、9条扫描线G1-G9以及9行8列的子像素阵列为例，详细说明本实施例中的抗色偏显示面板。如图4所示，Fanout区的走线编号与面板内部扫描线的编号是一一对应的，因此它们都是按照1、2、3、......、n-1、n的顺序依次开启。1至9行的子像素显示的颜色依次为：红(R)、绿(G)、蓝(B)、R、G、B、R、G、B。与传统的三栅极型液晶显示面板相比，本发明的抗色偏显示面板的第一实施例中，扫描线的结构发生改变，转变为方波形，第N条扫描线按照扫描线的信号传输方向(即面对附图的从左往右方向)依次绕过第N行子像素中的每一个子像素，并且各扫描线相互分离，不交错，其中N为自然数。数据线的结构不发生变化。
以第二行子像素为例，其显示绿色，包括4个子像素组，第一子像素组包括晶体管Q1和Q2，第二子像素组包括晶体管Q3和Q4，第三子像素组包括晶体管Q5和Q6。第二扫描线依次绕过了包含晶体管Q1、Q2、Q3、Q4、Q5和Q6的子像素。另外，以第一数据线D1为例，当正常显示时，第一数据线D1 的充电顺序为R->B->B->G->G->R->R->B->B->G->G，其余情况依次类推。
以显示红色和蓝色混色得紫色为例，扫描线自上而下开启，即扫描方向为自上而下。图5A为抗色偏显示面板第一个实施例在红色和蓝色混色画面下，面板中间区域每一条扫描线所对应的像素颜色和数据线波形，由于面板中间区域RC延迟不严重，因此色偏情况不明显。图5B为抗色偏显示面板第一个实施例在红色和蓝色混色画面下，面板两侧区域每一条扫描线所对应的像素颜色和数据线波形，如图5B所示，在这种布线方式下，同一条数据线一次对4个子像素进行充电，虽然在RC延迟比较严重的面板两侧区域，4个子像素中第一个子像素的充电情况比另外3个子像素差，但是从整体来看，只有一半的红色子像素和蓝色子像素充电情况不一致，另外一半的红色子像素和蓝色子像素充电情况是相同的，因此有效地改善了不同颜色子像素充电情况的差异，很大程度上减轻了面板两侧的色偏。
在本发明的抗色偏显示面板的第一实施例中，在进行正常显示时，一条数据线能够为显示同种颜色的两个子像素进行充电，使得出现色偏的子像素数量占整理混色子像素数量的比例下降，有效地抑制了色偏的程度，特别是对于RC延迟较为严重的面板两侧区域，色偏的程度将大大下降。
在本发明的抗色偏显示面板第二实施例中，与第一实施例的区别在于，扫描线呈周期性阶梯状设置，且穿梭在子像素阵列中相邻的两行子像素之间。具体的，在一个周期中，第N条呈阶梯状的扫描线依次绕过子像素阵列中的第N行、第M个子像素，第N+1行、第M+1个子像素，第N+1行、第M+2个子像素，以及第N+1行、第M+3个子像素，且每个周期的扫描线相互连接。N和M均为自然数。
以下以7条扫描线G1-G7、7条数据线D1-D7以及8行8列的子像素阵列为例，详细说明本实施例中的抗色偏显示面板。如图6所示，Fanout区的走线编号与面板内部扫描线的编号是一一对应的，因此它们都是按照1、2、3、......、n-1、n的顺序依次开启。1至8行的子像素显示的颜色依次为：R、G、B、R、G、B、R、G。与传统的三栅极型液晶显示面板相比，本发明的抗色偏显示面板的第二实施例中，扫描线的结构发生改变，转变为周期性变化的阶梯状。第N条扫描线在第N行子像素以及第N+1行子像素之间穿梭。
以第二扫描线G2为例，其在第2和3行子像素之间穿梭，具体的，第二扫描线G2依次绕过第2行、第1个子像素(包含晶体管Q7的子像素)，第3行、第2个子像素(包含晶体管Q8的子像素)，第3行、第3个子像素(包含晶体管Q9的子像素)以及第3行、第4个子像素(包含晶体管Q10的子像素)。下一个周期从第2行、第5个子像素(包含晶体管Q11的子像素)开始，且各周期的扫描线相互连接(即一条扫描线为连续的)。
扫描线开启的时序保持不变，从G1到G7依次开启。以数据线D1为例，子像素的充电顺序为：G→G→R→R→B→B。因此，在两色混色画面下，同一条数据线能够同时给4个子像素充电，同样以红色、蓝色混色得紫色的画面为例，参见图5B，数据线在充电时，第一个红色的子像素(晶体管)充电情况较差，但是中间两个子像素的混色画面充电达到饱和，整体来看，不同颜色的子像素充电差异已经消失，面板两侧的色偏得到了很大地改善。
在本发明的抗色偏显示面板的第二实施例中，在进行正常显示时，一条数据线能够为显示同种颜色的两个子像素进行充电，使得出现色偏的子像素数量占整理混色子像素数量的比例下降，有效地抑制了色偏的程度，特别是对于RC延迟较为严重的面板两侧区域，色偏的程度将大大下降。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的权利要求范围之内。

Claims (14)

  1. 一种抗色偏显示面板，包括子像素阵列、多条数据线以及多条扫描线，所述子像素阵列中的每一个子像素包括一晶体管，所述数据线沿列方向排布，所述扫描线与所述数据线交错，所述子像素阵列中的每个子像素位于两相邻的扫描线以及两相邻的数据线之间，其中：各扫描线互不交错地穿梭在所述子像素阵列中的子像素之间，所述子像素阵列中的每一行子像素包括多个子像素组，每个所述子像素组包括两个子像素且两个子像素的晶体管的栅极分别连接两条相邻的扫描线、源极连接同一条数据线、漏极均连接有液晶电容和储能电容，所述液晶电容和所述储能电容与所述晶体管连接的另一端接公共线；
    所述扫描线呈周期性阶梯状设置，穿梭在所述子像素这列中相邻的两行子像素之间；在一个周期中，第N条呈阶梯状的扫描线依次绕过所述子像素阵列中的第N行、第M个子像素，第N+1行、第M+1个子像素，第N+1行、第M+2个子像素，以及第N+1行、第M+3个子像素，且每个周期的扫描线相互连接，其中N和M均为自然数。
  2. 根据权利要求1所述的抗色偏显示面板，其中：所述扫描线呈方波形设置，依次绕过所述子像素阵列中一行子像素中的各子像素；
  3. 根据权利要求2所述的抗色偏显示面板，其中：各方波形的扫描线的上升沿位置相对应，下降沿位置相对应；
  4. 根据权利要求1所述的抗色偏显示面板，其中：所述子像素阵列中的每一行子像素显示红色、绿色和蓝色中的一种颜色，且相邻的三行子像素显示的颜色互补相同。
  5. 一种抗色偏显示面板，包括子像素阵列、多条数据线以及多条扫描线，所述子像素阵列中的每一个子像素包括一晶体管，所述数据线沿列方向排布，所述扫描线与所述数据线交错，所述子像素阵列中的每个子像素位于两相邻的扫描线以及两相邻的数据线之间，其中：各扫描线互不交错地穿梭在所述子像素阵列中的子像素之间，所述子像素阵列中的每一行子像素包括多个子像素组，每个所述子像素组包括两个子像素且两个子像素的晶体管的栅极分别连接两条相邻的扫描线、源极连接同一条数据线、漏极均连接有液晶电容和储能电容，所述液晶电容和所述储能电容与所述晶体管连接的另一端接公共线；
    所述扫描线呈方波形设置，依次绕过所述子像素阵列中一行子像素中的各子像素；各方波形的扫描线的上升沿位置相对应，下降沿位置相对应。
  6. 根据权利要求5所述的抗色偏显示面板，其中：所述扫描线呈周期性阶梯状设置，穿梭在所述子像素这列中相邻的两行子像素之间；
  7. 根据权利要求6所述的抗色偏显示面板，其中：在一个周期中，第N条呈阶梯状的扫描线依次绕过所述子像素阵列中的第N行、第M个子像素，第N+1行、第M+1个子像素，第N+1行、第M+2个子像素，以及第N+1行、第M+3个子像素，且每个周期的扫描线相互连接，其中N和M均为自然数。
  8. 根据权利要求5所述的抗色偏显示面板，其中：所述子像素阵列中的每一行子像素显示红色、绿色和蓝色中的一种颜色，且相邻的三行子像素显示的颜色互补相同。
  9. 一种抗色偏显示面板，包括子像素阵列、多条数据线以及多条扫描线，所述子像素阵列中的每一个子像素包括一晶体管，所述数据线沿列方向排布，所述扫描线与所述数据线交错，所述子像素阵列中的每个子像素位于 两相邻的扫描线以及两相邻的数据线之间，其中：各扫描线互不交错地穿梭在所述子像素阵列中的子像素之间，所述子像素阵列中的每一行子像素包括多个子像素组，每个所述子像素组包括两个子像素且两个子像素的晶体管的栅极分别连接两条相邻的扫描线、源极连接同一条数据线、漏极均连接有液晶电容和储能电容，所述液晶电容和所述储能电容与所述晶体管连接的另一端接公共线。
  10. 根据权利要求9所述的抗色偏显示面板，其中：所述扫描线呈方波形设置，依次绕过所述子像素阵列中一行子像素中的各子像素。
  11. 根据权利要求10所述的抗色偏显示面板，其中：各方波形的扫描线的上升沿位置相对应，下降沿位置相对应。
  12. 根据权利要求9所述的抗色偏显示面板，其中：所述扫描线呈周期性阶梯状设置，穿梭在所述子像素这列中相邻的两行子像素之间。
  13. 根据权利要求12所述的抗色偏显示面板，其中：在一个周期中，第N条呈阶梯状的扫描线依次绕过所述子像素阵列中的第N行、第M个子像素，第N+1行、第M+1个子像素，第N+1行、第M+2个子像素，以及第N+1行、第M+3个子像素，且每个周期的扫描线相互连接，其中N和M均为自然数。
  14. 根据权利要求9所述的抗色偏显示面板，其中：所述子像素阵列中的每一行子像素显示红色、绿色和蓝色中的一种颜色，且相邻的三行子像素显示的颜色互补相同。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104238217B (zh) * 2014-09-05 2017-03-01 深圳市华星光电技术有限公司 一种抗色偏显示面板
CN108333841B (zh) * 2018-02-13 2021-04-09 厦门天马微电子有限公司 显示面板、显示装置及其驱动方法
CN110047901B (zh) * 2019-04-28 2021-08-31 厦门天马微电子有限公司 一种显示面板和电子设备
CN110333632B (zh) * 2019-06-29 2022-04-12 上海中航光电子有限公司 一种阵列基板、显示面板及显示装置
CN111028813B (zh) * 2019-12-31 2022-05-13 厦门天马微电子有限公司 一种显示面板的驱动方法、驱动装置及显示装置
CN114578623B (zh) * 2022-03-14 2022-11-15 重庆惠科金渝光电科技有限公司 像素结构及显示面板
CN114509900B (zh) * 2022-04-20 2022-07-08 惠科股份有限公司 显示面板、显示模组与显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102290026A (zh) * 2011-07-19 2011-12-21 南京中电熊猫液晶显示科技有限公司 像素架构
CN102332245A (zh) * 2011-10-14 2012-01-25 深圳市华星光电技术有限公司 液晶显示装置及其驱动方法
KR20130067923A (ko) * 2011-12-14 2013-06-25 엘지디스플레이 주식회사 액정표시장치
CN103293809A (zh) * 2013-05-28 2013-09-11 深圳市华星光电技术有限公司 抗色偏显示面板
CN104238217A (zh) * 2014-09-05 2014-12-24 深圳市华星光电技术有限公司 一种抗色偏显示面板

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0862156B1 (en) * 1996-09-19 2005-04-20 Seiko Epson Corporation Method of production of a matrix type display device
KR20040089141A (ko) * 2003-04-10 2004-10-21 삼성전자주식회사 액정표시장치
KR100788392B1 (ko) * 2003-07-03 2007-12-31 엘지.필립스 엘시디 주식회사 횡전계 방식 액정 표시 장치의 구동방법
JP4276965B2 (ja) * 2004-02-04 2009-06-10 シャープ株式会社 表示装置
TWI382452B (zh) * 2004-03-19 2013-01-11 Samsung Display Co Ltd 薄膜電晶體陣列面板及其製造方法
US20050231447A1 (en) * 2004-04-14 2005-10-20 Shuo-Hsiu Hu Pixel arrangement in a display system
CN101661941B (zh) * 2008-08-25 2011-07-20 北京京东方光电科技有限公司 Tft-lcd阵列基板结构及其制备方法
US8018399B2 (en) * 2009-11-18 2011-09-13 Century Display(ShenZhen) Co., Ltd. Pixel array
US9052558B2 (en) * 2009-12-24 2015-06-09 Sharp Kabushiki Kaisha Display device, method of driving display device, liquid crystal display, and television receiver
KR101192583B1 (ko) * 2010-10-28 2012-10-18 삼성디스플레이 주식회사 액정 표시 패널, 액정 표시 장치 및 액정 표시 장치의 구동 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102290026A (zh) * 2011-07-19 2011-12-21 南京中电熊猫液晶显示科技有限公司 像素架构
CN102332245A (zh) * 2011-10-14 2012-01-25 深圳市华星光电技术有限公司 液晶显示装置及其驱动方法
KR20130067923A (ko) * 2011-12-14 2013-06-25 엘지디스플레이 주식회사 액정표시장치
CN103293809A (zh) * 2013-05-28 2013-09-11 深圳市华星光电技术有限公司 抗色偏显示面板
CN104238217A (zh) * 2014-09-05 2014-12-24 深圳市华星光电技术有限公司 一种抗色偏显示面板

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