WO2016192367A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2016192367A1
WO2016192367A1 PCT/CN2015/097262 CN2015097262W WO2016192367A1 WO 2016192367 A1 WO2016192367 A1 WO 2016192367A1 CN 2015097262 W CN2015097262 W CN 2015097262W WO 2016192367 A1 WO2016192367 A1 WO 2016192367A1
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sub
pixels
pixel
array substrate
row
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PCT/CN2015/097262
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English (en)
French (fr)
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郭仁炜
董学
卢鹏程
李牧冰
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US15/100,175 priority Critical patent/US20170117334A1/en
Publication of WO2016192367A1 publication Critical patent/WO2016192367A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • the present disclosure relates to the field of communications, and in particular, to an array substrate and a display device.
  • the common pixel design method used in the display screen is RGB or RGBW.
  • the display is composed of three or four sub-pixels, and the physical resolution is the same as the actual resolution that the human eye can feel.
  • the main purpose of the present disclosure is to provide a technical solution capable of producing a higher PPI display panel without adding a large number of data lines and gate lines, thereby reducing process difficulty and improving product yield.
  • the present disclosure provides an array substrate including a plurality of gate lines and a plurality of data lines, and a plurality of pixel regions defined by the plurality of gate lines and the plurality of data lines a sub-pixel, wherein each sub-pixel has the same specification, each sub-pixel and the adjacent sub-pixel have different colors, and at most two sub-pixels adjacent to each sub-pixel form a square pixel unit.
  • Two adjacent rows of sub-pixels are staggered by 1/2 sub-pixels in a column direction;
  • the plurality of data lines include a first data line, the first data line being from a column of sub-pixels and another column of sub-pixels adjacent thereto The gap between them passes through and connects the two columns of sub-pixels.
  • the plurality of data lines further includes a second data line connecting the first column of sub-pixels and/or the last column of sub-pixels.
  • the plurality of first data lines are bent data lines with the same bending direction.
  • the second data line is a direct data line.
  • the gate lines corresponding to the odd row sub-pixels and the gate lines corresponding to the even-numbered row sub-pixels are collectively disposed in a gap between the odd-numbered row sub-pixels and the even-numbered row sub-pixels.
  • the sub-pixels comprise RGB sub-pixels.
  • the sub-pixels in the odd rows are arranged with RGB sub-pixels as repeating units, and the RGB sub-pixels in the even rows are arranged in a repeating unit of BRG sub-pixels.
  • the BRG sub-pixels in the even rows are staggered 1/2 sub-pixels backwards or forwards compared to the RGB sub-pixels in the odd rows.
  • the square pixel unit is composed of 1, 1.5 or 2 sub-pixels.
  • the plurality of sub-pixels include adjacent X-th row sub-pixels and X+1-th row sub-pixels, X is greater than or equal to 1; the X-th row sub-pixel corresponding to the gate line and the X+th
  • the gate lines corresponding to one row of sub-pixels are collectively disposed in a gap between the X-th row sub-pixel and the X+1-th row sub-pixel in a two-two combination.
  • the plurality of sub-pixels further includes an X+2 row sub-pixel, and only the X-th row sub-pixel corresponding to the X-th row sub-pixel and the X+2-row sub-pixel a gate line and a gate line corresponding to the (X+1)th sub-pixel.
  • the X-th row sub-pixel is an odd-numbered row of sub-pixels.
  • the present disclosure also provides a display device including the above array substrate.
  • the array substrate and the display device of the present disclosure can perform calculation processing on the original input picture, perform brightness redistribution on the obtained information, and input the allocated information correspondingly by controlling the open position of the sub-pixel.
  • the sub-pixels in the physical position are combined with the way of connecting the data lines to the sub-pixels and the gate lines, which makes it easier to design and produce a higher PPI display panel, which reduces the process difficulty and improves the product yield. .
  • FIG. 1 is a schematic diagram of a connection mode of a data line and a gate line in an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of polarities of an input signal corresponding to connection mode one according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a second connection mode of data lines and gate lines in an array substrate according to an embodiment of the present disclosure
  • connection mode two is a schematic diagram of polarities of an input signal corresponding to connection mode two, in accordance with an embodiment of the present disclosure.
  • the virtual drive technology can improve the screen resolution perceived by the human eye, so that the viewer does not feel the actual resolution reduction due to the decrease of the physical resolution, thereby ensuring a higher PPI.
  • this virtual driving technology still has many shortcomings in the sub-pixel arrangement and the connection design of the gate lines and the data lines, which makes it impossible to display pictures with higher resolution with fewer sub-pixels, for example, currently using A.
  • the -Si process is used to make QHD (2560*14440*3) products of 6 inches or less, the LTPS process and OLED are caused by the fact that the number of data lines on the panel cannot be reduced, and the connection between the conventional data lines and the gate lines is adopted. Bottlenecks in the design and production of this A-Si process exist in the process.
  • an embodiment of the present disclosure provides an array substrate including a plurality of gate lines and a plurality of pieces of data. a line, and a plurality of sub-pixels located in a pixel region defined by the plurality of gate lines and the plurality of data lines, wherein each sub-pixel has the same specification, each sub-pixel and adjacent sub-pixel
  • the colors are different, and at most 2 sub-pixels adjacent to each row of sub-pixels form a square pixel unit, and adjacent two rows of sub-pixels are staggered by 1/2 sub-pixels in the column direction;
  • the plurality of data lines include a data line, the first data line passing through a gap between a column of sub-pixels and another column of sub-pixels adjacent thereto, and connecting the two columns of sub-pixels.
  • each of the square pixel units is designed to be composed of only one sub-pixel, 1.5 or two sub-pixels, and sub-pixels in two adjacent rows, with 0.5 sub-pixels as a basic unit.
  • the method of staggering 1/2 (0.5) sub-pixels is adopted, so that when the data lines are wired, the shape and length of the data lines are more regular, and the process difficulty is not increased.
  • the array substrate adopting such a pixel arrangement method is combined with a virtual computing technology (the input information is subjected to brightness redistribution through the actual physical position, and the input information is collectively output to the actual physical position) to realize virtual display. That is to say, for the current R sub-pixel, there are a plurality of adjacent B sub-pixels around it, and if it is necessary to display blue, the red luminance value corresponding to the R sub-pixel can be reduced to a minimum ratio or even 0,
  • the blue luminance value to be displayed is allocated to a plurality of adjacent B sub-pixels in different proportions, so that although the R sub-pixel does not display the blue luminance value, it is surrounded by a plurality of B sub-pixels.
  • the final visual effect is like the R sub-pixel also shows blue.
  • the embodiment of the present disclosure can flexibly utilize the selective opening of sub-pixels without reducing the pixel size, and can display the same information with fewer pixels, thereby improving the output of the display image. Resolution.
  • red vertical line image For another example, if a red vertical line image needs to be displayed, a row of red sub-pixels on one side of the red vertical line image may be opened, or a red sub-pixel on both sides of the red vertical line image may be turned on, so that the red vertical display may be displayed.
  • Line image for complementary color rendering so that the red vertical line image displayed It is clearer and improves the display effect.
  • two red vertical line images are displayed and the two red vertical lines are arranged closer together, one red red sub-pixel in the middle of the two red vertical lines can be opened to display the two red colors.
  • the vertical line image is rendered so that the two red vertical lines are directional and the visual resolution is improved.
  • the plurality of data lines may further include a second data line for connecting the first column of sub-pixels and/or the last column of sub-pixels. That is to say, the data line can only adopt the first data line, and the first data line needs to be arranged between two adjacent columns of sub-pixels to simultaneously connect two columns of sub-pixels, so that the number of data lines can be made. Cut in half.
  • the data line on the far side is connected to only one column of sub-pixels. Therefore, for the data line on the far side, a second data line different from the first data line can be used.
  • the plurality of first data lines may be bent data lines with the same bending direction, and the second data lines may be straight data lines.
  • the difference from the related art is also the connection manner of the gate lines.
  • the gate lines corresponding to the odd-numbered sub-pixels and the gate lines corresponding to the even-numbered sub-pixels are collectively arranged in a combination of two and two. In the gap between the odd row subpixel and the even row subpixel.
  • the gate line connecting the first row of sub-pixels and the gate line connecting the second row of sub-pixels are disposed in parallel between the first row of sub-pixels and the second row of sub-pixels, and are connected to the third row of sub-pixels.
  • the gate lines of the pixels and the gate lines connecting the fourth row of sub-pixels are disposed in parallel between the third row of sub-pixels and the fourth row of sub-pixels, and so on, up to the last set of gate lines.
  • connection manner of the data line and the gate line is mainly used in two different manners according to different data lines:
  • FIG. 1 is a case of the first method
  • FIG. 1 is an array substrate according to an embodiment of the present disclosure.
  • the data lines are bent, and the gate lines are arranged in a group from the first row, and the gate lines are supplied with two adjacent rows of sub-pixels, and are collectively arranged in the gaps of the adjacent row of sub-pixels.
  • n may be 2560 rows, m may be 720x3, ie 2160 columns, in another embodiment (by 1.5 sub-pixels in RGB form a square pixel unit), n can be 3840, m can be 4320, in yet another embodiment (a square pixel unit is composed of sub-pixels in 2 RGB), n can be 7680 , m can be 5760.
  • FIG. 2 is a schematic diagram showing the polarity of an input signal corresponding to the connection mode one according to an embodiment of the present disclosure. As shown in FIG. 2, the polarities of S1 and S2 are alternately corresponding to "+" and "-".
  • FIG. 3 is a schematic diagram of a second mode
  • FIG. 3 is a schematic diagram of a second method of connecting data lines and gate lines in an array substrate according to an embodiment of the present disclosure.
  • G1 to Gn represent lateral gate lines, S1.
  • Sm To Sm is a longitudinal data line, wherein S1 is designed as a straight data line, and S2 to Sm are all designed as a bent data line bent to the right, and the gate line is adopted from the first line to each two adjacent
  • the row of sub-pixel-powered gate lines is grouped and arranged centrally in the gaps of the adjacent row of sub-pixels.
  • the sub-pixels in the embodiments of the present disclosure may include RGB sub-pixels, sub-pixels in odd rows adopt RGB sub-pixels as repeating units, and RGB sub-pixels in even rows are arranged in BRG Subpixels are arranged for repeating units.
  • the BRG sub-pixels in the even rows are shifted back or forward by 1/2 sub-pixels compared to the RGB sub-pixels in the odd rows.
  • FIG. 4 is a schematic diagram showing the polarity of an input signal corresponding to the connection mode 2 according to an embodiment of the present disclosure. As shown in FIG. 4, the polarities of S1 and S2 are alternately corresponding to "+" and "-".
  • an embodiment of the present disclosure further provides a display device, including the above array substrate provided by the embodiment of the present disclosure.
  • the display device can be applied to any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like. Since the principle of solving the problem of the display device is similar to that of the array substrate, the implementation of the display device can be referred to the implementation of the above array substrate, and the repeated description is omitted.
  • the original input picture may be subjected to calculation processing, and the obtained information is subjected to brightness redistribution, and the allocated information is correspondingly input into the sub-pixel on the actual physical position by controlling the open position of the sub-pixel, and the pair is combined.
  • the way in which the data lines are connected to the sub-pixels and the gate lines is optimized, making it easier to design and produce higher PPI display panels, reducing process difficulty and improving product yield.

Abstract

一种阵列基板及显示装置。该阵列基板包括：多条栅线（G）和多条数据线（S），以及位于由多条栅线（G）和多条数据线（S）限定出的像素区域中的多个亚像素。每个亚像素的规格相同，每个亚像素与相邻亚像素的颜色各不相同，每行亚像素中相邻的至多2个亚像素组成一个方形像素单元，相邻两行亚像素在列方向上错开1/2个亚像素；多条数据线（S）包括第一数据线，第一数据线从一列亚像素和与其相邻的另一列亚像素之间的空隙穿过，并连接该两列亚像素。

Description

阵列基板及显示装置
相关申请的交叉引用
本申请主张在2015年6月1日在中国提交的中国专利申请号No.201510293849.7的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及通信领域，尤其是涉及一种阵列基板及显示装置。
背景技术
目前，显示屏采用的常见像素设计方式是RGB或RGBW等方式，由三个或四个亚像素组成一个像素进行显示，物理分辨率与人眼能够感受到的实际分辨率是相同的。
但是，随着客户对显示屏的感受要求的增加，显示屏厂商需要制作出分辨率(Pixels Per Inch，简称为PPI)更高的显示面板，这对显示面板的设计和制作工艺均提出了类似极限的挑战，例如，在有机发光二极管(Organic Light-Emitting Diode，简称为OLED)做亚像素的过程中，有机物树脂图案(resin pattern)的形成工艺难度较大，这主要体现在需要形成较多数量的数据线和栅线，这导致在制作具有更高PPI的显示面板时遇见瓶颈。
因此，如何提供一种在制作具有更高PPI的显示面板时无需增加大量的数据线和栅线，成为相关技术中亟待解决的问题。
发明内容
本公开的主要目的在于提供一种能够在制作更加高PPI的显示面板无需增加大量数据线和栅线的技术方案，以降低工艺难度，提高产品良率。
为了达到上述目的，本公开提供了一种阵列基板，包括多条栅线和多条数据线，以及位于由所述多条栅线和所述多条数据线限定出的像素区域中的多个亚像素，其中，每个亚像素的规格相同，每个亚像素与相邻亚像素的颜色各不相同，每行亚像素中相邻的至多2个亚像素组成一个方形像素单元， 相邻两行亚像素在列方向上错开1/2个亚像素；所述多条数据线包括第一数据线，所述第一数据线从一列亚像素和与其相邻的另一列亚像素之间的空隙穿过，并连接该两列亚像素。
可选地，所述多条数据线还包括第二数据线，连接第一列亚像素和/或最后一列亚像素。
可选地，所述多条第一数据线为弯折方向一致的弯折数据线。
可选地，所述第二数据线为直数据线。
可选地，奇数行亚像素对应的栅线和偶数行亚像素对应的栅线以两两组合的方式，集中设置在所述奇数行亚像素与所述偶数行亚像素之间的空隙中。
可选地，所述亚像素包括RGB亚像素。
可选地，奇数行中的亚像素采用以RGB亚像素为重复单元进行排列，且偶数行中的RGB亚像素排列方式为以BRG亚像素为重复单元进行排列。
可选地，与奇数行中的RGB亚像素相比，偶数行中的BRG亚像素向后或向前错开1/2个亚像素。
可选地，所述方形像素单元由1个、1.5个或2个亚像素构成。
可选地，所述多个亚像素包括相邻的第X行亚像素和第X+1行亚像素，X大于等于1；所述第X行亚像素对应的栅线和所述第X+1行亚像素对应的栅线以两两组合的方式，集中设置在所述第X行亚像素与所述第X+1行亚像素之间的空隙中。
可选地，所述多个亚像素还包括第X+2行亚像素，所述第X行亚像素与所述第X+2行亚像素之间仅存在所述第X行亚像素对应的栅线和所述第X+1行亚像素对应的栅线。
可选地，所述第X行亚像素为奇数行亚像素。
本公开还提供了一种显示装置，该显示装置包括上述阵列基板。
与相关技术相比，本公开所述的阵列基板及显示装置，可以对原始输入图片进行计算处理，将得到的信息进行亮度再分配，通过控制亚像素的开启位置将分配后的信息对应输入实际物理位置上的亚像素中，同时结合对数据线连接亚像素和栅线的方式进行优化，使得在设计和生产较高PPI的显示面板时更加容易实现，降低了工艺难度，提高了产品良率。
附图说明
图1是根据本公开实施例的阵列基板中数据线与栅线的连接方式一的示意图；
图2是根据本公开实施例的对应于连接方式一的输入信号的极性示意图；
图3是根据本公开实施例的阵列基板中数据线与栅线的连接方式二的示意图；
图4是根据本公开实施例的对应于连接方式二的输入信号的极性示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域的普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
目前，虚拟驱动技术(Pentile技术)在当前显示领域中的应用十分广泛，其最突出的优点是通过像素公用的方式使得视觉分辨率高于显示面板的物理分辨率，也就是说，用较少的像素可以显示较为清晰的画面而人眼感受到的视觉分辨率却不会降低，这种虚拟驱动技术已经在知名手机厂商的一些高端产品上得到了应用。
因此，通过虚拟驱动技术可以提高人眼感受到的屏幕分辨率，使得观看者不会由于物理分辨率的降低感受到实际分辨率的降低，从而可以保证较高的PPI。
但是，这种虚拟驱动技术在亚像素排列以及栅线和数据线的连接方式设计方面还是存在许多不足，导致无法用更少的亚像素显示出具有更高分辨率的画面，例如，目前使用A-Si工艺制作6寸以下QHD(2560*14440*3)产品时，由于无法减少面板上的数据线的数量，采用传统的数据线和栅线之间的连接方式等特点，导致LTPS工艺，OLED工艺中都存在这A-Si设计及生产过程中的瓶颈。
基于此，本公开实施例提供了一种阵列基板，包括多条栅线和多条数据 线，以及位于由所述多条栅线和所述多条数据线限定出的像素区域中的多个亚像素，其中，每个亚像素的规格相同，每个亚像素与相邻亚像素的颜色各不相同，每行亚像素中相邻的至多2个亚像素组成一个方形像素单元，相邻两行亚像素在列方向上错开1/2个亚像素；所述多条数据线包括第一数据线，所述第一数据线从一列亚像素和与其相邻的另一列亚像素之间的空隙穿过，并连接该两列亚像素。
而在本实施例中，以0.5个亚像素为基本单位，将每个所述方形像素单元设计成只1个亚像素、1.5个或2个亚像素组成，同时在相邻两行的亚像素设计中，采用错开1/2(0.5)个亚像素的方式，这样是为了在对所述数据线进行布线时，方便数据线的形状和长度较为规整，且不会增加工艺上的难度。
同时由于每条数据线同时为两列相邻的亚像素输入数据，因此，使得数据线的数量减少一半，使得设计和工艺上容易实现。
采用这样的像素排列方式的阵列基板，配合虚拟计算技术(通过实际物理位置对应输入信息，将输入信息进行亮度再分配，集中输出到实际物理位置)实现虚拟显示。也就是说，对于当前的R亚像素而言，其周围存在多个相邻的B亚像素，如果需要显示蓝色，可以将R亚像素对应的红色亮度值降到最低比甚至是0，将需要显示的蓝色亮度值按照不同的比例分配到多个相邻的B亚像素中，这样一来，虽然R亚像素虽然没显示蓝色亮度值，但由于其周围环绕着多个B亚像素，最后显示出来的视觉效果就好像R亚像素也显示了蓝色。
以下举例说明如何显示具体的图像信息：
例如，在接收到显示一个白色图像时，控制需要显示白色图像的像素单元所在位置处呈品字形分布的三个相邻的亚像素开启，以显示白色图像，相对于传统显示白色图像时需要开启相邻三列RGB的亚像素，本公开实施例可以在不减小像素尺寸的前提下灵活的运用亚像素的选择性开启，可以以较少的像素显示同样的信息，从而提高显示图像的输出分辨率。
又例如，如果需要显示一红色竖线图像时，可以对应开启红色竖线图像一侧的一列红色亚像素，或者，可以开启红色竖线图像两侧的红色亚像素，这样可以对显示的红色竖线图像进行补色渲染，使显示的红色竖线图像表现 的更清晰，提高显示效果，另外，若显示两条红色竖线图像时，且两条红色竖线排列较近，可以开启两条红色竖线中间一列红色亚像素，以对显示的两条红色竖线图像进行渲染，使两条红色竖线表现具有方向性，提高了视觉分辨率。
在本公开实施例中，所述多条数据线还可以包括第二数据线，该第二数据用于连接第一列亚像素和/或最后一列亚像素。也就是说，数据线可以只采用第一数据线一种布线方式，该第一数据线需要布置在相邻两列亚像素之间，以同时连接两列亚像素，这样可以使得数据线的数量减少一半。
但需要注意的是，最边侧的数据线只连接了一列亚像素，因此，对于最边侧的数据线而言，可以使用不同于第一数据线的第二数据线。
在本公开实施例中，所述多条第一数据线可以为弯折方向一致的弯折数据线，所述第二数据线可以为直数据线。
在本公开实施例中，与相关技术不同之处还在于栅线的连接方式，具体地，奇数行亚像素对应的栅线和偶数行亚像素对应的栅线以两两组合的方式，集中设置在所述奇数行亚像素与所述偶数行亚像素之间的空隙中。
也就是说，连接第一行亚像素的栅线和连接第二行亚像素的栅线是以并行的方式均设置在第一行亚像素和第二行亚像素之间，连接第三行亚像素的栅线和连接第四行亚像素的栅线是以并行的方式均设置在第三行亚像素和第四行亚像素之间，以此类推，直至最后一组栅线为止。
基于此，在本公开实施例中，数据线和栅线的连接方式主要根据数据线的不同采用两种不同的方式：
连接方式一，数据线全部采用弯折方式一致的弯折数据线，为便于理解，这里可以参考图1，图1是方式一的一种情况，图1是根据本公开实施例的阵列基板中数据线与栅线的连接方式一的示意图，如图1所示，G1到Gn代表横向的栅线，S1到Sm+1是纵向的数据线，其中，数据线全部设计为向左弯折的弯折数据线，而栅线采用了从第一行开始，以每两个相邻行亚像素供电的栅线为一组，将其集中布置该相邻行亚像素的空隙中。
在本公开的一个实施例中(由1个RGB中的亚像素构成一个方形像素单元)，n可以是2560行，m可以是720x3即2160列，在另一个实施例中(由 1.5个RGB中的亚像素构成一个方形像素单元)，n可以是3840，m可以是4320，在又一个实施例中(由2个RGB中的亚像素构成一个方形像素单元)，n可以是7680，m可以是5760。
有关方形像素单元的具体结构，可参见中国专利申请号No.201510149457.3，其全部内容通过引用包含于此。
图2是根据本公开实施例的对应于连接方式一的输入信号的极性示意图，如图2所示，S1和S2的极性进行“+”和“-”的交替对应。
连接方式二，第一列和/或最后一列亚像素采用直数据线进行连接，其余列的亚像素全部采用弯折方式一致的弯折数据线进行连接，为便于理解，这里可以参考图3，图3是方式二的一种情况，图3是根据本公开实施例的阵列基板中数据线与栅线的连接方式二的示意图，如图3所示，G1到Gn代表横向的栅线，S1到Sm是纵向的数据线，其中，S1设计为直数据线，S2到Sm全部设计为向右弯折的弯折数据线，而栅线采用了从第一行开始，以每两个相邻行亚像素供电的栅线为一组，将其集中布置该相邻行亚像素的空隙中。
可选地，本公开实施例中的所述亚像素可以包括RGB亚像素，奇数行中的亚像素采用以RGB亚像素为重复单元进行排列，且偶数行中的RGB亚像素排列方式为以BRG亚像素为重复单元进行排列。
其中，与奇数行中的RGB亚像素相比，偶数行中的BRG亚像素向后或向前错开1/2个亚像素。
图4是根据本公开实施例的对应于连接方式二的输入信号的极性示意图，如图4所示，S1和S2的极性进行“+”和“-”的交替对应。
由于上述实施例可以减少数据线的数量，且重新设计数据线和栅线的连接方式，因此能够将A-Si设计中的瓶颈工艺比较容易的实现。
除此之外，随着制作工艺的不同，例如低温多晶硅技术(Low Temperature Poly-silicon，简称为LTPS)工艺，OLED工艺，上述实施例同样也是可以适用的，可以为制作出更高PPI的产品搭建基础。
在此基础上，还可以进一步只使用一个IC芯片驱动整个显示面板(包含上述阵列基板)的方案，这种一体化IC的设计方式的优点是在减少数据线的数量的同时，能够降低面板IC的功耗，使IC能够在低功耗的条件下驱动显 示面板。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述阵列基板。该显示装置可以应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。由于该显示装置解决问题的原理与阵列基板相似，因此该显示装置的实施可以参见上述阵列基板的实施，重复之处不再赘述。
通过本公开实施例，可以对原始输入图片进行计算处理，将得到的信息进行亮度再分配，通过控制亚像素的开启位置将分配后的信息对应输入实际物理位置上的亚像素中，同时结合对数据线连接亚像素和栅线的方式进行优化，使得在设计和生产较高PPI的显示面板时更加容易实现，降低了工艺难度，提高了产品良率。
以上所述是本公开的优选实施方式，应当指出，对于本领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为包含在本公开的保护范围之内。

Claims (13)

  1. 一种阵列基板，包括多条栅线和多条数据线，以及位于由所述多条栅线和所述多条数据线限定出的像素区域中的多个亚像素，其中，每个亚像素的规格相同；其中：
    每个亚像素与相邻亚像素的颜色各不相同，每行亚像素中相邻的至多2个亚像素组成一个方形像素单元，相邻两行亚像素在列方向上错开1/2个亚像素；
    所述多条数据线包括第一数据线，所述第一数据线从一列亚像素和与该列亚像素相邻的另一列亚像素之间的空隙穿过，并连接该两列亚像素。
  2. 根据权利要求1所述的阵列基板，其中，所述多条数据线还包括第二数据线，连接第一列亚像素和/或最后一列亚像素。
  3. 根据权利要求2所述的阵列基板，其中，所述多条第一数据线为弯折方向一致的弯折数据线。
  4. 根据权利要求2所述的阵列基板，其中，所述第二数据线为直数据线。
  5. 根据权利要求2所述的阵列基板，其中，奇数行亚像素对应的栅线和偶数行亚像素对应的栅线以两两组合的方式，集中设置在所述奇数行亚像素与所述偶数行亚像素之间的空隙中。
  6. 根据权利要求1至5中任一项所述的阵列基板，其中，所述亚像素包括RGB亚像素。
  7. 根据权利要求6所述的阵列基板，其中，奇数行中的亚像素采用以RGB亚像素为重复单元进行排列，且偶数行中的RGB亚像素排列方式为以BRG亚像素为重复单元进行排列。
  8. 根据权利要求6所述的阵列基板，其中，与奇数行中的RGB亚像素相比，偶数行中的BRG亚像素向后或向前错开1/2个亚像素。
  9. 根据权利要求1所述的阵列基板，其中，所述方形像素单元由1个、1.5个或2个亚像素构成。
  10. 根据权利要求1所述的阵列基板，其中，所述多个亚像素包括相邻的第X行亚像素和第X+1行亚像素，X大于等于1；
    所述第X行亚像素对应的栅线和所述第X+1行亚像素对应的栅线以两两组合的方式，集中设置在所述第X行亚像素与所述第X+1行亚像素之间的空隙中。
  11. 根据权利要求10所述的阵列基板，其中，所述多个亚像素还包括第X+2行亚像素，所述第X行亚像素与所述第X+2行亚像素之间仅存在所述第X行亚像素对应的栅线和所述第X+1行亚像素对应的栅线。
  12. 根据权利要求10或11所述的阵列基板，其中，所述第X行亚像素为奇数行亚像素。
  13. 一种显示装置，包括：权利要求1至12中任一项所述的阵列基板。
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CN105097873A (zh) * 2015-06-01 2015-11-25 京东方科技集团股份有限公司 阵列基板及显示装置

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