WO2016041406A2 - 可以查空的双单元结构的otp或mtp存储模块 - Google Patents

可以查空的双单元结构的otp或mtp存储模块 Download PDF

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WO2016041406A2
WO2016041406A2 PCT/CN2015/084037 CN2015084037W WO2016041406A2 WO 2016041406 A2 WO2016041406 A2 WO 2016041406A2 CN 2015084037 W CN2015084037 W CN 2015084037W WO 2016041406 A2 WO2016041406 A2 WO 2016041406A2
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sense amplifier
cell
signal
checking
otp
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PCT/CN2015/084037
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French (fr)
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WO2016041406A3 (zh
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方钢锋
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苏州锋驰微电子有限公司
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Publication of WO2016041406A3 publication Critical patent/WO2016041406A3/zh

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  • the present invention relates to an OTP (One Time Programmable) or MTP (Multiple Programmable) memory module, and more particularly to an OTP or MTP memory module of a double cell structure that can be checked.
  • OTP One Time Programmable
  • MTP Multiple Programmable
  • Non-volatile memory compatible with CMOS logic processes Due to the process used in non-traditional dedicated non-volatile memory processes, data retention or reliability requirements are often not met and some methods are needed to compensate. The reliability of OTP/MTP operating in dual-cell mode is much higher, but in some cases, the results of the sense amplifier comparison will be garbled. If the OTP or MTP memory unit is erased after UV rays, it is impossible to determine whether or not the erase is clean.
  • the object of the present invention is to overcome the deficiencies in the prior art and provide an OTP or MTP storage module with a double unit structure that can be checked to better ensure data reliability.
  • the OTP or MTP storage module capable of checking the double unit structure includes a memory array, a sense amplifier and a controller, and further includes a data selector for checking, and the output of the memory array is sequentially Connecting the check data selector and the sense amplifier, wherein the controller is respectively connected to the memory array, the check data selector, and the sense amplifier; in the memory array, two adjacent memory cells are a group, and the a differential two-cell structure in which the final output of the two-cell structure is one bit through the sense amplifier; the data selector for checking selects a signal of the cell into the sense amplifier according to the received check-in signal and the cell selection signal, and the reference Compared with the signal, the larger than the reference signal is “1”, and the reference signal is “0”, so the two units are checked separately; when not checked, the signals of the two units enter the sense amplifier. Compare "1" and "0" with each other.
  • the differential dual unit structure includes a first unit and a second unit.
  • the output through the sense amplifier is “1" when the first unit When it is “0" and the second cell is “1”, the output through the sense amplifier is "0".
  • bit line data selector between the memory array and the empty data selector, and is also coupled to the controller for selecting cell signals on different bit lines to enter the sense amplifier.
  • the invention has the advantages of working in the differential dual unit mode and improving the reliability of the OTP or MTP storage module. Checking the space is very convenient for the application of OTP or MTP chip. It is not necessary to remember whether the OTP or MTP unit is empty, and the chip can be high. It is achieved by the performance of the performance, and the initial state of the chip is unknown before writing.
  • Figure 1 is the signal margin of a single unit mode of operation.
  • Figure 2 is the signal boundary of the differential dual unit mode of operation.
  • Figure 3 is two bits of a differential dual unit structure, each bit containing two units.
  • Figure 4 is the output of two bits of a differential dual unit structure.
  • Figure 5 shows garbled characters when both units are erased.
  • Figure 6 is an OTP or MTP memory module incorporating a double-cell structure.
  • Figure 7 is a schematic diagram of the structure of an OTP memory cell.
  • Figure 8 is a combination of two OTP memory cells in a dual cell.
  • Figure 9 is a 2 x 2 array of the dual cells shown in Figure 8.
  • each bit containing two OTP/MTP memory cells.
  • Cell3 and cell2 are a group, and cell1 and cell0 are a group.
  • cell3 and cell2 form a differential dual-cell structure.
  • the output bit ⁇ 1> of the SA sense amplifier
  • Cell1 and cell0 form a differential dual-cell structure.
  • the output bit ⁇ 0> of the SA is "0"
  • the output bit ⁇ 0> of the SA is "0"
  • each bi-cell structure is finally output as one bit.
  • Figure 1 shows the signal boundary of a single-cell operation.
  • the Program signal is the programming signal
  • the Erase signal is the erase signal
  • the reference is the reference signal. If an OTP or MTP memory cell is a program unit ("1"), another OTP or MTP memory cell is an erase unit ("0"). This doubles the signal, as shown in Figure 2. There is also the elimination of the uncertainty of the reference signal. Since it is a comparison between two memory cells, as long as the program cell and the erase cell are slightly different, the SA can distinguish between "1” or "0", which is easy to compare. But when two units in a bit are program or erase, the result is garbled, as shown in Figure 5.
  • OTP or MTP memory unit is erased after UV rays, it cannot be determined whether it is erased or not. In order to consider the cost of the test, it is necessary to check the air. It is checked that the state of each unit is program cell or erase cell.
  • a MUX data selector
  • a signal for checking the null is given, and a unit selection signal is also checked.
  • Left or right unit if you look at the left unit, the current of the left unit will be selected, open, and enter SA to compare with the reference current. More than the reference current is the program, otherwise it is erase, so you can compare the state of the left unit. If you need to check the status of the right cell, select the current of the right cell. Let the current in the right cell enter the SA and compare it with the reference current. When the status is not checked, let the currents of the left and right units enter the SA, and let them compare themselves, then they can be separated as "1" or "0".
  • the differential dual cell structure of the present invention is described below by taking a simple OTP memory cell as an example.
  • the OTP or MTP memory module of the present invention as a core part of a memory chip, comprises: a memory array, a data selector for checking, a sense amplifier and a controller, and an output of the memory array is sequentially connected to the data selector for checking And a sense amplifier, the controller is connected to the memory array, the check data selector, and the sense amplifier, respectively.
  • the empty data selector can also function as the original bit line data selector (BL MUX) in the memory module, or it can be additionally added.
  • the memory array is connected to the SA through the BL MUX and the empty MUX.
  • the BL MUX is used to select cell signals on different bit lines into the sense amplifier.
  • Figure 7 shows an OTP memory cell, including two PMOS transistors.
  • PL is Program line
  • WL is Word line
  • BL Bit line
  • two PMOS transistors are lined.
  • the bottoms are connected together by NWell (N-well).
  • N-well N-well
  • Figure 9 after the selection of WL (1), the upper left BL (1) and BLb (1) output a bit of data through SA comparison, the upper right BL (0) and BLb (0) SA compares and outputs one bit of data; after WL(0) selection, the left lower BL(1) and BLb(1) output one bit data through SA comparison, and the upper right BL(0) and BLb(0) output one bit through SA comparison. data. A total of 4 digits of data.

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  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

本发明提供了一种可以查空的双单元结构的OTP或MTP存储模块，包括存储器阵列、读出放大器和控制器，还包括查空用数据选择器；所述存储器阵列中，相邻两个存储单元为一组，构成差动的双单元结构，双单元结构经读出放大器的最终输出为一个比特；查空用数据选择器根据接收的查空信号和单元选择信号，选择一个单元的信号进入读出放大器，与参比信号进行比较，大于参比信号即为"1"，小于参比信号即为"0"，如此分别完成两个单元的查空；不查空时，双单元的信号都进入读出放大器，相互对比分出"1"和"0"。本发明的优点是：在差动的双单元方式下工作，提高了OTP或MTP存储模块的可靠性。同时利用查空，不会发生写入前对于芯片初始状态是未知的。

Description

可以查空的双单元结构的OTP或MTP存储模块 技术领域
本发明涉及一种OTP(一次可编程)或MTP(多次可编程)存储模块，尤其是一种可以查空的双单元结构的OTP或MTP存储模块。
背景技术
与CMOS逻辑工艺兼容的非挥发性记忆体由于其采用的工艺非传统的专用非挥发性记忆体工艺，对于数据保持或可靠性的要求通常不一定能够满足，需要一些方法来弥补。采用双单元方式工作的OTP/MTP的可靠性会高很多，但在某些情况下，读出放大器比较出来的结果会出现乱码。如OTP或MTP存储单元在UV射线擦除后，则无法判定是否擦除干净。
发明内容
本发明的目的是克服现有技术中存在的不足，提供一种可以查空的双单元结构的OTP或MTP存储模块，更好的保证数据的可靠性。
按照本发明提供的技术方案，所述的可以查空的双单元结构的OTP或MTP存储模块，包括存储器阵列、读出放大器和控制器，还包括查空用数据选择器，存储器阵列的输出依次连接所述查空用数据选择器和读出放大器，控制器分别与存储器阵列、查空用数据选择器、读出放大器相连；所述存储器阵列中，相邻两个存储单元为一组，构成差动的双单元结构，双单元结构经读出放大器的最终输出为一个比特；查空用数据选择器根据接收的查空信号和单元选择信号，选择一个单元的信号进入读出放大器，与参比信号进行比较，大于参比信号即为“1”，小于参比信号即为“0”，如此分别完成两个单元的查空；不查空时，双单元的信号都进入读出放大器，相互对比分出“1”和“0”。
所述差动的双单元结构包括第一单元和第二单元，当第一单元为“1”，第二单元为“0”时，经过读出放大器的输出为“1”，当第一单元为“0”，第二单元为“1”时，经过读出放大器的输出为“0”。
在存储器阵列和查空用数据选择器之间还具有位线数据选择器，亦与所述控制器相连，用于选择不同位线上的单元信号进入读出放大器。
本发明的优点是：在差动的双单元方式下工作，提高了OTP或MTP存储模块的可靠性。查空对于OTP或MTP芯片的应用方便很多，不需要记好OTP或MTP单元是不是空的，芯片就能够以高可 靠性的性能来实现，不会发生写入前对于芯片初始状态是未知的。
附图说明
图1是单单元工作方式的信号边界(signal margin)。
图2是差动双单元工作方式的信号边界。
图3是差动双单元结构的两个bit，每个bit包含两个单元。
图4是差动双单元结构的两个bit的输出。
图5是当双单元都被擦除的时候出现乱码。
图6是加入了查空的双单元结构的OTP或MTP存储模块。
图7是一个OTP存储单元结构示意。
图8是两个OTP存储单元组合成双单元。
图9是图8所示双单元组成的2×2阵列。
具体实施方式
下面结合附图和实施例对本发明作进一步说明。
如图3所示，是本发明存储器阵列中的两个比特(bit<1:0>)，每个比特包含两个OTP/MTP存储单元(cell)。cell3和cell2为一组，cell1和cell0为一组。
如图4，cell3和cell2构成差动的(differential)双单元结构，当cell3为“1”，cell2为“0”时，经过SA(sense amplifier，读出放大器)的输出bit<1>为“1”。cell1和cell0构成差动的双单元结构，当cell1为“0”，cell0为“1”时，经过SA的输出bit<0>为“0”，即每个双单元结构最终输出为一个比特。
如图1所示为单单元工作方式的信号边界，Program signal是编程信号，Erase signal是擦除信号，reference是参比信号。若一个OTP或MTP存储单元是program的单元(“1”)，另一个OTP或MTP存储单元是erase的单元(“0”)。这样就把信号放大了一倍，如图2所示。还有把参比(reference)信号的不确定部分也消除了。由于是两个存储单元之间比较，只要program的单元和erase的单元有一点点的不同，SA就可以区分出是“1”或“0”，是容易比较出来的。但当在一个bit中的两个单元都是program或erase时，比较出来的结果就是乱码，如图5所示。如OTP或MTP存储单元在UV射线擦除后，就不能判定是不是擦除干净了。为了测试的成本考虑，要做查空。检验出每个单元的状态是program cell或erase cell。
为了能查空，在SA和存储器阵列之间加了一个查空用的MUX(数据选择器)，如图6，当需要查空时，给出查空的信号，还有单元选择信号(查左边还是右边的单元)，如是查左边单元，左边单元的电流就会被选上，打开，进入SA跟参比(reference)电流相比较。大于参比电流的就是program，不然就是erase，这样就可以比较出左边单元的状态了。如需要查右边单元的状态，就选上右边单元的电流。 让右边单元的电流进入SA，同参比电流去比较。当不查状态时，就让左和右单元的电流都进入SA，让它们自己对比，就可以分出是“1”或“0”了。
以下以一种简单的OTP存储单元为例来讲解本发明所述的差动的双单元结构。
本发明的OTP或MTP存储模块，作为一个存储芯片的核心部分，包括：存储器阵列、查空用数据选择器、读出放大器和控制器，存储器阵列的输出依次连接所述查空用数据选择器和读出放大器，控制器分别与存储器阵列、查空用数据选择器、读出放大器相连。查空用数据选择器可以同时充当存储模块中原有的位线数据选择器(BL MUX)的功能，也可以另外加设，存储器阵列经过BL MUX和查空用MUX再连接到SA。BL MUX用于选择不同位线上的单元信号进入读出放大器。
如图7为一个OTP存储单元，包括两个PMOS管，图中PL为Program line(编程线)，WL为Word line(字线)，BL为Bit line(位线)，两个PMOS管的衬底通过NWell(N阱)连接在一起。该单元结构只是一个示意，本发明适用于各种不同物理结构的存储单元构成的存储器。
图8中，两个OTP存储单元组成differential的结构，一个是Program，一个是Erase。
2×2个图8的结构构成图9，经过WL(1)的选择，左上的BL(1)和BLb(1)经SA比较输出一位数据，右上BL(0)和BLb(0)经SA比较输出一位数据；再经过WL(0)选择，左下的BL(1)和BLb(1)经SA比较输出一位数据，右上BL(0)和BLb(0)经SA比较输出一位数据。共计4位数据。

Claims (3)

  1. 可以查空的双单元结构的OTP或MTP存储模块，包括存储器阵列、读出放大器和控制器，其特征是：还包括查空用数据选择器，存储器阵列的输出依次连接所述查空用数据选择器和读出放大器，控制器分别与存储器阵列、查空用数据选择器、读出放大器相连；所述存储器阵列中，相邻两个存储单元为一组，构成差动的双单元结构，双单元结构经读出放大器的最终输出为一个比特；查空用数据选择器根据接收的查空信号和单元选择信号，选择一个单元的信号进入读出放大器，与参比信号进行比较，大于参比信号即为“1”，小于参比信号即为“0”，如此分别完成两个单元的查空；不查空时，双单元的信号都进入读出放大器，相互对比分出“1”和“0”。
  2. 如权利要求1所述可以查空的双单元结构的OTP或MTP存储模块，其特征是，所述差动的双单元结构包括第一单元和第二单元，当第一单元为“1”，第二单元为“0”时，经过读出放大器的输出为“1”，当第一单元为“0”，第二单元为“1”时，经过读出放大器的输出为“0”。
  3. 如权利要求1所述可以查空的双单元结构的OTP或MTP存储模块，其特征是，在存储器阵列和查空用数据选择器之间具有位线数据选择器，亦与所述控制器相连，用于选择不同位线上的单元信号进入读出放大器。
PCT/CN2015/084037 2014-09-19 2015-07-15 可以查空的双单元结构的otp或mtp存储模块 WO2016041406A2 (zh)

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