WO2016035217A1 - 電力変換システム - Google Patents
電力変換システム Download PDFInfo
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- WO2016035217A1 WO2016035217A1 PCT/JP2014/073584 JP2014073584W WO2016035217A1 WO 2016035217 A1 WO2016035217 A1 WO 2016035217A1 JP 2014073584 W JP2014073584 W JP 2014073584W WO 2016035217 A1 WO2016035217 A1 WO 2016035217A1
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- power conversion
- slave
- semiconductor power
- time
- power converter
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/539—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
- H02M7/5395—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/493—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode the static converters being arranged for operation in parallel
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0009—Devices or circuits for detecting current in a converter
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0043—Converters switched with a phase shift, i.e. interleaved
Definitions
- the present invention relates to a power conversion system including a plurality of power conversion devices that operate in parallel.
- the inventors of the present application have one PWM semiconductor power conversion device as a master, another PWM semiconductor power conversion device as a slave, and a synchronization signal from the master PWM semiconductor power conversion device as a slave PWM semiconductor power conversion device.
- a PWM semiconductor power conversion system that synchronizes the PWM carrier wave of the master PWM semiconductor power conversion device and the PWM carrier wave of the slave PWM semiconductor power conversion device by transmitting to (see Patent Document 1 below) has been proposed.
- the PWM carrier wave of each PWM semiconductor power converter can be synchronized.
- the switching element or the circuit that drives the switching element for example, located after the PWM carrier wave generation unit has a characteristic change due to individual differences or the ambient environment exemplified by temperature, the synchronization state may not be complete. Without the possibility of recirculation current.
- the present invention has been made in view of the above, and an object of the present invention is to provide a power conversion system that can suppress the circulating current with a simple configuration.
- a power conversion system includes one master power converter and one or more slave power converters, and the master power converter.
- the master power conversion device and Each of the slave power conversion devices includes a time counter and a carrier wave generation unit that generates a carrier wave for PWM-modulating the voltage command value in synchronization with the time counter.
- the device of the slave power conversion device A synchronization data generating unit that generates synchronization data for synchronizing the value of the time counter with the time counter of the master power converter, and a communication unit that transmits the synchronization data to the slave power converter.
- the slave power converter includes: a communication unit that receives the synchronization data from the master power converter; and the slave power converter when the communication unit of the slave power converter completes reception of the synchronization data.
- the circulating current can be suppressed with a simple configuration, and the current capacity utilization factor of the power converter can be improved.
- Functional block diagram showing the configuration of the power conversion system of Embodiment 1 of the present invention Functional block diagram showing a functional configuration of a control device provided in the semiconductor power conversion device Waveform diagram showing examples of voltage command value, triangle wave and gate signal Timing chart explaining time counter correction processing Timing chart explaining time counter correction processing Flowchart explaining operation of master semiconductor power converter Flowchart explaining operation of slave semiconductor power converter
- Functional block diagram showing configurations of delay circuit, gate timing adjustment circuit, and main circuit Functional block diagram showing the configuration of the U-phase gate timing adjustment circuit The figure which shows an example of the frequency spectrum of the electric current of a U-phase main circuit Functional block diagram showing an example of another filter circuit Diagram showing delay time of delay line
- FIG. 1 is a functional block diagram showing the configuration of the power conversion system according to Embodiment 1 of the present invention.
- the power conversion system 1 according to the first embodiment includes a plurality of semiconductor power conversion devices 1a, 1b, and 1c.
- the semiconductor power conversion devices 1a, 1b and 1c are connected in parallel to a load 2 such as a motor.
- a load 2 such as a motor.
- Each of the semiconductor power conversion devices 1a, 1b and 1c generates a PWM voltage for driving the load 2.
- the semiconductor power conversion device 1 a is connected to the host control device 3 via a wired or wireless communication path 4.
- Some semiconductor power converters that have been widely used in recent years are capable of communicating with a host control device 3 for performing operation settings, for example, using a communication standard such as RS-485 or USB (Universal Serial Bus). .
- the communication standard of the communication path 4 between the semiconductor power conversion device 1a and the host control device 3 is not particularly limited, but here, the communication standard of the communication means already provided as described above is used.
- the host controller 3 transmits a voltage command value, which is a command value of a voltage applied to the load 2, to the semiconductor power conversion device 1 a via the communication path 4.
- the semiconductor power conversion devices 1a, 1b and 1c are connected to each other via a wired or wireless communication path C.
- the communication standard of the communication path C between the semiconductor power conversion devices 1a, 1b, and 1c is not particularly limited, but here, the communication standard of the communication means already provided as described above is used.
- the semiconductor power conversion device 1a transmits the voltage command value received from the host control device 3 to the semiconductor power conversion devices 1b and 1c via the communication path C.
- the host controller 3 is connected to the semiconductor power converters 1a, 1b, and 1c via the communication path C, and the host controller 3 sends the voltage command value to the semiconductor via the communication path C. You may transmit to power converter device 1a, 1b, and 1c.
- the semiconductor power conversion device 1a includes a control device 11a and a main circuit 12a.
- the semiconductor power conversion device 1b includes a control device 11b and a main circuit 12b.
- the semiconductor power conversion device 1c A control device 11c and a main circuit 12c.
- the control devices 11a, 11b, and 11c each perform PWM modulation processing on the voltage command value supplied from the host control device 3, and output gate signals obtained as a result of the PWM modulation processing on the voltage command value, respectively.
- Gate signals output from the control devices 11a, 11b, and 11c are input to the main circuits 12a, 12b, and 12c, respectively.
- the main circuits 12a, 12b and 12c generate PWM voltages to be supplied to the load 2 based on the input gate signal, respectively.
- each of the semiconductor power conversion devices 1b and 1c communicates with the semiconductor power conversion device 1a to change the phase of the carrier wave of the own semiconductor power conversion device.
- First control is performed to synchronize with the phase of the carrier wave of the semiconductor power conversion device 1a.
- each of the semiconductor power conversion devices 1b and 1c performs second control for adjusting the phase of the gate signal of the own semiconductor power conversion device based on the state of the own semiconductor power conversion device.
- the first control will be described first, and then the second control will be described.
- FIG. 2 is a functional block diagram showing a functional configuration of a control device provided in the semiconductor power conversion device.
- the function structure of the control apparatus 11a with which the semiconductor power converter device 1a is provided, and the control apparatus 11b with which the semiconductor power converter device 1b is provided is shown. Since the functional configuration of the control device 11b and the functional configuration of the control device 11c are the same, the functional configuration of the control device 11b will be described and the description of the control device 11c will be omitted.
- the control device 11a includes a controller 111a and a delay circuit 112a.
- the controller 111a includes a time counter 113a that is a period counter, a triangular wave generator 114a that generates a triangular wave synchronized with the time counter 113a, and a triangular wave generated by the triangular wave generator 114a that receives a voltage command value input from the host controller 3.
- a PWM modulator 115a for generating a gate signal based on PWM modulation.
- the semiconductor power conversion system 1 can perform the second control more suitably by including the delay circuit 112a in the control device 11a.
- the predetermined delay time of the delay circuit 112a will be described in the description of the second control.
- the control device 11b includes a controller 111b and a gate timing adjustment circuit 112b.
- the controller 111b includes a time counter 113b that is a cycle counter that counts at the same cycle as the time counter 113a, a triangular wave generator 114b that generates a triangular wave synchronized with the time counter 113b, and a power supply voltage value that is input to the PWM modulator 115a.
- a PWM modulation unit 115b for generating a gate signal by PWM-modulating the same voltage command value based on the triangular wave generated by the triangular wave generation unit 114b.
- the controller 111b performs the first control.
- the gate timing adjustment circuit 112b performs second control.
- a triangular wave is used as a carrier wave for PWM modulation.
- a carrier wave other than a triangular wave such as a sawtooth wave
- the first control can be performed in the same manner. it can.
- the triangular wave generator 114a of the control device 11a and the triangular wave generator 114b of the control device 11b generate triangular waves synchronized with the time counters 113a and 113b, respectively.
- the time counters 113a and 113b are not synchronized with each other and the triangular wave generators 114a and 114b generate triangular waves that are not synchronized with each other will be described.
- FIG. 3 is a waveform diagram showing an example of a voltage command value, a triangular wave, and a gate signal.
- the voltage command value 20 input to the controllers 111a and 111b shown in FIG. 2 the triangular wave 21 generated by the triangular wave generator 114a, the gate signal 22 generated by the PWM modulator 115a, and the triangular wave generator 114b are generated.
- the triangular wave 31 and the gate signal 32 generated by the PWM modulator 115b are shown.
- the same voltage command value 20 is input to the controller 111a and the controller 111b.
- the triangular wave 31 generated by the triangular wave generator 114b is delayed by ⁇ t from the triangular wave 21 generated by the triangular wave generator 114a. That is, the triangular wave 21 and the triangular wave 31 are not synchronized with each other.
- the gate signal 32 generated by the PWM modulator 115b is delayed by ⁇ t from the gate signal 22 generated by the PWM modulator 115a. Then, due to the delay of the gate signal 32, a time when the state of the gate signal 22 and the state of the gate signal 32 are different occurs.
- both the gate signal 22 and the gate signal 32 are at the low level from the time t2 to the time t3.
- the gate signal 22 is at a low level, while the gate signal 32 is at a high level.
- the gate signal 22 is at a high level, while the gate signal 32 is at a low level. That is, the state of the gate signal 22 and the state of the gate signal 32 are different between time t1 and time t2 and between time t3 and time t4.
- the PWM voltage output from the main circuit 12 a is generated based on the gate signal 22, and the PWM voltage output from the main circuit 12 b is generated based on the gate signal 32.
- the state of the gate signal 22 and the state of the gate signal 32 are different, the PWM voltage output from the semiconductor power conversion device 1a is different from the PWM voltage output from the semiconductor power conversion device 1b. Accordingly, a reflux current flows between the semiconductor power conversion device 1a and the semiconductor power conversion device 1b, and the current supplied to the load 2 decreases, so that the current capacity utilization rate of the semiconductor power conversion system 1 decreases. That is, it is important to synchronize the gate signals 22 and 32 of the semiconductor power conversion devices 1a, 1b, and 1c.
- the time counter 113b included in each of the other two semiconductor power conversion devices 1b and 1c is synchronized with the time counter 113a.
- the gate signals 22 and 32 are generated by PWM modulating the voltage command value 20 based on the triangular waves 21 and 31 generated by the time counters 113a and 113b, respectively. Therefore, by synchronizing the time counter 113b with the time counter 113a, the gate signals 22 and 32 of the semiconductor power conversion devices 1a, 1b, and 1c can be synchronized.
- the semiconductor power conversion device 1a transmits synchronization data to the semiconductor power conversion devices 1b and 1c when the time counter 113a returns to zero.
- the semiconductor power conversion devices 1b and 1c receive the communication time required for the communication between the semiconductor power conversion device 1a and the semiconductor power conversion devices 1b and 1c, respectively, and the synchronization data.
- the value of the time counter 113b is adjusted based on the comparison with the value of the time counter 113b provided in each of the semiconductor power conversion devices 1b and 1c at the time.
- the synchronization data generation unit 121 generates two synchronization data to be transmitted to the slave semiconductor power conversion devices 1b and 1c, respectively, when the time counter 113a returns to zero.
- the synchronization data transmitted to the slave semiconductor power conversion device 1b describes the communication time between the master semiconductor power conversion device 1a and the slave semiconductor power conversion device 1b stored in the communication time storage unit 122.
- the synchronization data transmitted to the slave semiconductor power conversion device 1c describes the communication time between the master semiconductor power conversion device 1a and the slave semiconductor power conversion device 1c stored in the communication time storage unit 122. ing.
- the synchronization data receiving unit 133 is a communication interface for receiving the synchronization data transmitted from the master semiconductor power conversion device 1a.
- the synchronous data receiving unit 133 also has a role of receiving a voltage command value from the master semiconductor power conversion device 1a and transmitting the received voltage command value to the PWM modulation unit 115b.
- the error detection unit 131 detects errors in the synchronization data based on the error detection code added to the received synchronization data.
- the time counter correction processing unit 132 reads the communication time from the synchronization data that the error detection unit 131 has determined to have no error. Then, the time counter correction processing unit 132 compares the communication time with the value of the time counter 113b when the synchronization data reception is completed, and sets the value of the time counter 113b in the time advance direction or the time return direction based on the comparison result. A time counter correction process that is a correction process is executed.
- the time counter 113a of the master semiconductor power converter 1a and the time counter 113b of the slave semiconductor power converter 1b are synchronized, the time counter 113b at the timing 51 when the slave semiconductor power converter 1b has finished receiving the synchronization data.
- the value is the same as tcom.
- the slave semiconductor power converter 1b when the time counter 113b of the slave semiconductor power converter 1b is ahead of the time counter 113a of the master semiconductor power converter 1a, the slave semiconductor power converter 1b has received the synchronization data.
- the value of the time counter 113b at the timing 51 indicates ts1 which is a value larger than tcom. Therefore, the time counter correction processing unit 132 resets the time counter 113b to zero again after the time counter 113b has returned to zero and the time tc1, which is the difference between ts1 and tcom, has further elapsed.
- the time counter 113b of the slave semiconductor power conversion device 1b is returned by the amount of advance, and is synchronized with the time counter 113a of the master semiconductor power conversion device 1a.
- the slave semiconductor power converter 1b has received the synchronization data.
- the value of the time counter 113b at the timing 51 indicates ts2, which is a value smaller than tcom. Therefore, the time counter correction processing unit 132 resets the time counter 113b to zero earlier than the scheduled time when the time counter 113b next returns to zero by tc2, which is the difference between ts2 and tcom.
- the time counter 113b of the slave semiconductor power conversion device 1b advances by the amount of delay and is synchronized with the time counter 113a of the master semiconductor power conversion device 1a.
- FIG. 6 is a flowchart for explaining the operation of the master semiconductor power conversion device.
- FIG. 7 is a flowchart for explaining the operation of the slave semiconductor power conversion device.
- step S4 the error detection code generation unit 123 generates two error detection codes for the two synchronization data, and assigns the generated two error detection codes to the two synchronization data, respectively.
- step S5 the synchronization data transmission unit 124 starts transmitting the two synchronization data to which the error detection code is given to the slave semiconductor power converters 1b and 1c.
- step S6 the synchronous data transmission unit 124 ends the transmission of the synchronous data.
- the master semiconductor power conversion device 1a proceeds to step S1 and enters a state of waiting until the next time counter zero return interrupt occurs.
- step S11 the slave semiconductor power conversion device 1b performs a standby process for waiting for the start of an operation for synchronizing the slave semiconductor power conversion device 1b with the master semiconductor power conversion device 1a.
- step S12 the synchronization data receiving unit 133 starts receiving synchronization data.
- step S13 the time counter correction processing unit 132 reads the value ts of the time counter 113b of the slave semiconductor power conversion device 1b, that is, the slave time counter 113b.
- step S15 the error detection unit 131 determines whether or not there is an error in the received synchronization data based on the error detection code added to the received synchronization data. If there is an error in step S15, that is, if the answer is Yes in step S15, the slave semiconductor power conversion device 1b goes to step S11 and waits until the next synchronization data is received.
- step S16 If the value ts of the time counter 113b is the same as the communication time tcom in step S16, that is, if Yes in step S16, the time counter 113a and the time counter 113b are synchronized, that is, the master semiconductor power Conversion device 1a and slave semiconductor power conversion device 1b are synchronized. Therefore, the slave semiconductor power conversion device 1b moves to step S11 and waits until the next synchronization data is received.
- the time counter correction processing unit 132 further determines in step S17 whether or not the value ts of the time counter 113b is greater than the communication time tcom, that is, whether ts> tcom.
- step S18 the time counter correction processing unit 132 executes a time return direction correction process that is a correction process in the direction of returning the time to the time counter 113b.
- step S19 the time counter correction processing unit 132 executes time advance direction correction processing, which is correction processing in the time advance direction, on the time counter 113b.
- the slave semiconductor power conversion device 1b proceeds to step S11 after the process of step S18 or step S19, and waits until the next synchronization data is received.
- the communication time storage unit 122 that is, the master semiconductor power conversion device 1a stores the communication time.
- the communication time storage unit 122 is deleted, and each of the slave semiconductor power conversion devices 1b and 1c stores the communication time required for communication of synchronous data from the master semiconductor power conversion device 1a to the own semiconductor power conversion devices 1b and 1c.
- a communication time storage unit may be included. That is, the master semiconductor power conversion device 1a transmits synchronization data not including the communication time to the slave semiconductor power conversion devices 1b and 1c, and each of the slave semiconductor power conversion devices 1b and 1c includes the stored communication time and its own semiconductor. The values of the time counter 113b of the power conversion devices 1b and 1c may be compared.
- the synchronization data generation unit 121 performs processing time required before and after transmission / reception of the synchronization data size or synchronization data for each synchronization data. Based on the above, the communication time described in the synchronization data may be calculated.
- the communication time described in the synchronization data may not be expressed in the same unit as the count values of the time counters 113a and 113b.
- the time counter correction processing unit 132 converts the communication time so that the unit of communication time read from the received synchronization data becomes equal to the unit of count value,
- the time counter 113b may be corrected based on the communication time.
- the time counters 113a and 113b are period counters, and the synchronization data is generated when the time counter 113a returns to zero.
- the timing for generating the synchronization data may not be the timing at which the time counter 113a returns to zero.
- the synchronization data generating unit 121 generates synchronization data when the time counter 113a reaches a predetermined value
- the time counter correction processing unit 132 is the time when the synchronization data receiving unit 133 has completed receiving the synchronization data.
- the time counter 113b may be corrected based on the difference between the value obtained by subtracting a predetermined value from the value of the time counter 113b and the communication time.
- time counters 113a and 113b may be counters that continue counting up or counting down for a long time instead of the period counter.
- the time counters 113a and 113b are preferably realized by hardware from the viewpoint of obtaining good count accuracy, but may be realized by software.
- the synchronization data transmission unit 124 and the synchronization data reception unit 133 receive the voltage command value supplied from the host controller 3 and transmit the received voltage command value to the PWM modulation unit 115a and the PWM modulation unit 115b, respectively.
- the controllers 111a and 111b may have a configuration in which a communication function unit for transmitting and receiving voltage command values and a communication function unit for transmitting and receiving synchronization data are separated.
- the master semiconductor power conversion device 1a is given an error detection code when the time counter 113a included in the own semiconductor power conversion device 1a reaches a predetermined value.
- Two synchronous data are generated and transmitted to the slave semiconductor power converters 1b and 1c, respectively.
- Each of the slave semiconductor power conversion devices 1b and 1c performs error detection on the received synchronization data based on the error detection code assigned to the received synchronization data.
- the slave semiconductor power conversion devices 1b and 1c have the value of the time counter 113b included in the own semiconductor power conversion devices 1b and 1c at the time when the reception of the synchronization data is completed.
- the semiconductor power conversion system 1 Based on the communication time of the synchronous data calculated in advance, the value of the time counter 113b included in the own semiconductor power conversion devices 1b and 1c is corrected. Therefore, since the synchronization process is performed at the time when the time counter 113a reaches a predetermined value, the semiconductor power conversion system 1 does not affect the synchronization accuracy even when the communication path C having a low data transmission / reception speed is used. That is, the semiconductor power conversion system 1 can use the low-speed and inexpensive communication path C. Furthermore, since the semiconductor power conversion system 1 does not perform synchronization processing when a data transfer error occurs due to noise or the like, it does not synchronize at an incorrect timing due to the influence of noise, and a required noise countermeasure level. Can be lowered. That is, the semiconductor power conversion system 1 has a simple configuration as much as possible and allows a plurality of semiconductor power conversion devices to operate in synchronization with each other without being affected by noise as much as possible.
- the time counters 113a and 113b of the semiconductor power conversion devices 1a, 1b, and 1c can be synchronized.
- the switching timing synchronization of the switching element is lost due to the influence of the individual difference or characteristic change, and a circulating current is generated.
- each of the semiconductor power conversion devices 1b and 1c adjusts the timing of the gate signal supplied to the main circuits 12b and 12c based on the state of the own semiconductor power conversion devices 1b and 1c.
- Each of the semiconductor power conversion devices 1b and 1c repeatedly executes the second control described below at a predetermined cycle.
- FIG. 8 is a functional block diagram showing the configuration of the delay circuit, the gate timing adjustment circuit, and the main circuit.
- FIG. 8 shows the U phase of the delay circuit 112a, the main circuit 12a, the gate timing adjustment circuit 112b, and the main circuit 12b.
- the delay circuit 112a, the main circuit 12a, the gate timing adjustment circuit 112b, and the main circuit 12b further include a circuit for the V phase.
- the circuit configuration is the same as the circuit configuration for the U phase.
- the delay circuit 112a, the main circuit 12a, the gate timing adjustment circuit 112b, and the main circuit 12b further include circuits for V phase and W phase.
- the circuit configuration for the V phase and the W phase is the same as the circuit configuration for the U phase.
- the U-phase main circuit 12au of the master semiconductor power conversion device 1a shown in FIG. 1 includes two switching elements 12au1 connected in series between a high potential side DC power bus P and a low potential side DC power bus N, and 12 au 2 is provided. DC power is supplied from the DC power source 5 between the DC power bus P on the high potential side and the DC power bus N on the low potential side.
- the diode 12au3 for freewheel is connected in reverse parallel to the switching element 12au1.
- a diode 12au4 for freewheeling is connected in reverse parallel to the switching element 12au2.
- the connection point between the switching element 12au1 and the switching element 12au2 is connected to the load 2 via the output line 12au5.
- the output line 12au5 has an inductance component Lm.
- the inductance component Lm is a component of the output line 12au5 and is not a circuit element.
- the U-phase delay circuit 112au is supplied with the high-potential side gate signal G0p and the low-potential side gate signal G0n from the controller 111a.
- the U-phase delay circuit 112au sends the high-potential-side gate signal G1p and the low-potential-side gate signal G1n after delaying the gate signals G0p and G0n by a predetermined delay time respectively to the gate terminal of the switching element 12au1. This is supplied to the gate terminal of the switching element 12au2.
- the U-phase main circuit 12bu of the slave semiconductor power conversion device 1b shown in FIG. 1 includes two switching elements 12bu1 connected in series between a high potential side DC power bus P and a low potential side DC power bus N, and 12bu2 is provided.
- a diode 12bu3 for freewheel is connected in reverse parallel to the switching element 12bu1.
- a diode 12bu4 for freewheeling is connected in reverse parallel to the switching element 12bu2.
- the connection point between the switching element 12bu1 and the switching element 12bu2 is connected to the load 2 via the output line 12bu5.
- the output line 12bu5 has an inductance component Ls.
- the inductance component Ls is a component that the output line 12bu5 has and is not a circuit element.
- the output line 12bu5 is provided with a current sensor 12bu6 that detects the current Is flowing through the output line 12bu5.
- the direction of the current Is detected by the current sensor 12bu6 is a direction from the U-phase main circuit 12bu toward the load 2 and the U-phase main circuit 12au.
- the U-phase gate timing adjustment circuit 112bu is supplied with a high-potential side gate signal G2p and a low-potential side gate signal G2n from the controller 111b. Based on the current Is detected by the current sensor 12bu6, the U-phase gate timing adjustment circuit 112bu adjusts the timing of the gate signals G2p and G2n in the time advance direction or the time return direction, respectively.
- the low potential side gate signal G3n is supplied to the gate terminal of the switching element 12bu1 and the gate terminal of the switching element 12bu2, respectively.
- FIG. 9 is a functional block diagram showing the configuration of the U-phase gate timing adjustment circuit.
- the U-phase gate timing adjustment circuit 112bu includes a bandpass filter 112bu1, a positive threshold holding unit 112bu2, a negative threshold holding unit 112bu3, comparators 112bu4 and 112bu5, latches 112bu6 and 112bu7, The delay amount adjusting unit 112bu8 and delay lines 112bu9 and 112bu10 are provided.
- the band-pass filter 112bu1 removes the noise component and the load current component from the U-phase main circuit 12bu to the load 2 from the current Is, passes the circulating current component, and compares the non-inverting input terminal of the comparator 112bu4 and the comparison. To the inverting input terminal of the device 112bu5.
- FIG. 10 is a diagram showing an example of the frequency spectrum of the current of the U-phase main circuit.
- the current Is of the U-phase main circuit 12bu has a load current component 60 in the low frequency region, a circulating current component 61 in the middle frequency region, and a noise component 62 in the high frequency region.
- the frequency of the load current component 60 is about 0 Hz to 1 kHz.
- the frequency of the noise component 62 is higher than several hundred kHz.
- the current change of the current Is is a normal change of current flowing to the load 2.
- the value of the current change when the switching timing of the master semiconductor power converter 1a and the switching timing of the slave semiconductor power converter 1b coincide is the voltage between the DC power bus P and the DC power bus N, and the load 2 inductance.
- the change in current when the switching timing of the master semiconductor power converter 1a and the switching timing of the slave semiconductor power converter 1b coincide with each other is the switching timing of the master semiconductor power converter 1a and the switching timing of the slave semiconductor power converter 1b. Compared with the change in the reflux current when the and do not match, the frequency is low.
- the band-pass filter 112bu1 removes the load current component 60 and the noise component 62 and passes the circulating current component 61. Thereby, the band pass filter 112bu1 can supply only the circulating current component 61 to the comparators 112bu4 and 112bu5, and can improve the accuracy of the gate timing adjustment.
- FIG. 11 is a functional block diagram illustrating an example of another filter circuit.
- the filter circuit 70 shown in FIG. 11 includes a low-pass filter 71 that removes a high-frequency component of the current Is, and a differentiation element 72 that removes a low-frequency component by differentiating the output of the low-pass filter 71.
- the positive threshold holding unit 112bu2 supplies the positive threshold allowed for the circulating current component of the current Is to the inverting input terminal of the comparator 112bu4.
- the negative threshold holding unit 112bu3 supplies a negative threshold allowed for the circulating current component of the current Is to the non-inverting input terminal of the comparator 112bu5.
- the comparator 112bu4 compares the amplitude of the circulating current component of the current Is supplied to the non-inverting input terminal with the positive threshold value supplied to the inverting input terminal. When the amplitude of the circulating current component of the current Is exceeds the positive threshold, the comparator 112bu4 supplies a high level signal to the latch 112bu6, and the amplitude of the circulating current component of the current Is sets the positive threshold. If not exceeded, a low level signal is supplied to the latch 112bu6.
- the comparator 112bu5 compares the negative threshold supplied to the non-inverting input terminal with the amplitude of the circulating current component of the current Is supplied to the inverting input terminal.
- the comparator 112bu5 supplies a high level signal to the latch 112bu7 when the negative threshold exceeds the amplitude of the circulating current component of the current Is, and the negative threshold has the amplitude of the circulating current component of the current Is. If not, a low level signal is supplied to the latch 112bu7.
- the latch 112bu6 operates in synchronization with the clock signal and holds the output signal of the comparator 112bu4 for a certain period of time.
- the latch 112bu7 operates in synchronization with the clock signal and holds the output signal of the comparator 112bu5 for a certain time.
- the delay amount adjusting unit 112bu8 controls the delay times of the delay lines 112bu9 and 112bu10 based on the signals supplied from the latches 112bu6 and 112bu7.
- the delay amount adjustment unit 112bu8 controls the delay time of the delay lines 112bu9 and 112bu10 to half of T in the initial stage.
- the delay time of the delay lines 112bu9 and 112bu10 at the initial time is not limited to half of T, and may be other values in the range from 0 to T.
- FIG. 12 is a diagram showing the delay time of the delay line.
- the delay amount adjusting unit 112 bu 8 adjusts the delay time of the delay lines 112 bu 9 and 112 bu 10 in the direction of time advance direction 80 by half of T.
- the delay time of the delay lines 112bu9 and 112bu10 can be adjusted in the direction of the time delay direction 81 with an adjustment width of half of T.
- the predetermined delay time of the U-phase delay circuit 112au in FIG. 8 may be set to the same time as the delay time of the delay lines 112bu9 and 112bu10 at the initial time. Thereby, the phase of the gate signals G1p and G1n at the initial time can be matched with the phase of the gate signals G3p and G3n.
- FIG. 13 is a diagram showing the adjustment direction of the delay amount adjustment unit.
- the delay amount adjusting unit 112bu8 controls the delay lines 112bu9 and 112bu10 in a direction to delay the phases of the gate signals G3p and G3n. That is, the delay amount adjustment unit 112bu8 controls the delay lines 112bu9 and 112bu10 so as to increase the delay time of the delay lines 112bu9 and 112bu10.
- the delay amount adjusting unit 112bu8 can bring the timing when the output voltage Vs of the U-phase main circuit 12bu is at a high level close to the timing when the output voltage Vm of the U-phase main circuit 12au is at a high level. Thereby, the delay amount adjusting unit 112bu8 can reduce the circulating current component of the current Is.
- the U-phase gate timing adjustment circuit 112bu repeatedly executes the gate timing adjustment operation at a predetermined cycle. Therefore, the gate timing adjustment circuit 112bu can gradually reduce the circulating current component of the current Is.
- the delay amount adjustment unit 112bu8 may increase or decrease the delay time of the delay lines 112bu9 and 112bu10 by a predetermined time. It is also conceivable to increase the width as the amplitude of the circulating current component of the current Is increases.
- the method of increasing the predetermined time can steadily direct the reflux current in the convergence direction, so it is effective when the number of semiconductor power conversion devices is large, for example, when the number of semiconductor power conversion devices exceeds two. It is thought that On the other hand, in the method of increasing the increase width as the amplitude of the circulating current component of the current Is increases, the convergence time of the circulating current can be shortened, but it is also possible that the circulating current diverges, so the number of semiconductor power conversion devices is small. In this case, for example, when the number of semiconductor power conversion devices is two, the convergence time of the circulating current can be shortened, and the possibility that the circulating current diverges can be suppressed.
- the delay amount adjusting unit 112bu8 controls the delay lines 112bu9 and 112bu10 in the direction in which the phase of the gate signals G3p and G3n is advanced. That is, the delay amount adjustment unit 112bu8 controls the delay lines 112bu9 and 112bu10 so as to reduce the delay time of the delay lines 112bu9 and 112bu10.
- the delay amount adjusting unit 112bu8 can bring the timing when the output voltage Vs of the U-phase main circuit 12bu is at a high level close to the timing when the output voltage Vm of the U-phase main circuit 12au is at a high level. Thereby, the delay amount adjusting unit 112bu8 can reduce the circulating current component of the current Is.
- the delay amount adjusting unit 112bu8 controls the delay lines 112bu9 and 112bu10 in the direction in which the phase of the gate signals G3p and G3n is advanced. That is, the delay amount adjustment unit 112bu8 controls the delay lines 112bu9 and 112bu10 so as to reduce the delay time of the delay lines 112bu9 and 112bu10.
- the delay amount adjusting unit 112bu8 can bring the timing when the output voltage Vs of the U-phase main circuit 12bu is at a high level close to the timing when the output voltage Vm of the U-phase main circuit 12au is at a high level. Thereby, the delay amount adjusting unit 112bu8 can reduce the circulating current component of the current Is.
- the delay amount adjusting unit 112bu8 controls the delay lines 112bu9 and 112bu10 in a direction to delay the phases of the gate signals G3p and G3n. That is, the delay amount adjustment unit 112bu8 controls the delay lines 112bu9 and 112bu10 so as to increase the delay time of the delay lines 112bu9 and 112bu10.
- the delay amount adjusting unit 112bu8 can bring the timing when the output voltage Vs of the U-phase main circuit 12bu is at a high level close to the timing when the output voltage Vm of the U-phase main circuit 12au is at a high level. Thereby, the delay amount adjusting unit 112bu8 can reduce the circulating current component of the current Is.
- FIGS. 14 to 17 are timing diagrams for explaining the effect of the U-phase gate timing adjustment circuit.
- the change timing from the low level to the high level of the output voltage 91 of the U-phase main circuit 12bu is delayed from the change timing from the low level to the high level of the output voltage 90 of the U-phase main circuit 12au.
- the circulating current component 92 of Is flows in the negative direction.
- the U-phase gate timing adjustment circuit 112bu advances the timing of the gate signals G3p and G3n by time t11, the switching timing of the switching elements 12bu1 and 12bu2 is also time t11. Just go ahead.
- the U-phase gate timing adjustment circuit 112bu changes the change timing of the output voltage 94 of the U-phase main circuit 12bu from the low level to the high level, and changes the output voltage 93 of the U-phase main circuit 12au from the low level to the high level.
- the timing can be approached, and the circulating current component 95 of the current Is can be reduced.
- the U-phase gate timing adjustment circuit 112bu repeatedly executes the gate timing adjustment operation at a predetermined cycle. Therefore, the gate timing adjustment circuit 112bu can gradually reduce the circulating current component 95 of the current Is.
- the change timing of the output voltage 97 of the U-phase main circuit 12bu from the low level to the high level is ahead of the change timing of the output voltage 96 of the U-phase main circuit 12au from the low level to the high level.
- the circulating current component 98 of Is is flowing in the positive direction.
- the U-phase gate timing adjustment circuit 112bu delays the timing of the gate signals G3p and G3n by the time t12, the switching timing of the switching elements 12bu1 and 12bu2 is also the time t12. Only late. As a result, the U-phase gate timing adjustment circuit 112bu changes the change timing of the output voltage 100 of the U-phase main circuit 12bu from the low level to the high level, and changes the output voltage 99 of the U-phase main circuit 12au from the low level to the high level. The timing can be approached, and the circulating current component 101 of the current Is can be reduced.
- the U-phase gate timing adjustment circuit 112bu repeatedly executes the gate timing adjustment operation at a predetermined cycle. Therefore, the U-phase gate timing adjustment circuit 112bu can gradually reduce the circulating current component 101 of the current Is.
- the slave semiconductor power conversion devices 1b and 1c can adjust the switching timing of the switching elements 12bu1 and 12bu2 based on the circulating current of the self-semiconductor power conversion device. Thereby, the slave semiconductor power converters 1b and 1c can suppress the circulating current of the own semiconductor power converter.
- the second control can be performed independently by each of the slave semiconductor power conversion devices 1b and 1c without communicating with other semiconductor power conversion devices. Therefore, the second control does not cause a limitation such as wiring routing. In addition, the second control does not need to calculate the difference in current between the semiconductor power converters. In the second control, the master semiconductor power converter 1a does not need to include a current sensor.
- the first control and the second control are performed independently, the above-described effects can be obtained.
- the first control is performed alone, it is difficult to suppress the circulating current when there is a factor that impairs the switching timing synchronization of the switching elements in the circuit subsequent to the time counters 113a and 113b.
- the case where there is a factor that impairs the switching timing synchronization of the switching elements in the circuit subsequent to the time counters 113a and 113b is, for example, the switching elements 12au1, 12au2, 12bu1, and 12bu2 or a circuit that drives these switching elements. This is a case where a difference exists or a characteristic change occurs due to an ambient environment exemplified by temperature.
- the second control when the second control is performed alone, it is considered that the circulating current can be gradually reduced and suppressed if the amount of switching timing deviation of the switching elements 12au1, 12au2, 12bu1, and 12bu2 is small.
- the amount of switching timing of the switching elements 12 au 1, 12 au 2, 12 bu 1 and 12 bu 2 is large, there is a possibility that the circulating current cannot be reduced and the circulating current is diverged.
- the semiconductor power conversion system 1 shown in FIG. 1 can exhibit a synergistic effect that cannot be obtained by the first control alone or the second control alone, by combining the first control and the second control. .
- the semiconductor power conversion system 1 can synchronize the phase of the triangular wave generator 114a and the phase of the triangular wave generator 114b by the first control. Thereby, the semiconductor power conversion system 1 can suppress the shift amount of the switching timing of the switching elements 12au1, 12au2, 12bu1, and 12bu2.
- the first control suppresses the amount of switching timing of the switching elements 12 au 1, 12 au 2, 12 bu 1 and 12 bu 2. There is a synergistic effect that it can be suppressed.
- the switching elements 12au1, 12au2, 12bu1 and 12bu2 and the diodes 12au3, 12au4, 12bu3 and 12bu4 generally use Si-based semiconductors made of silicon (Si: silicon) as a mainstream.
- Si silicon
- a wide band gap semiconductor made of silicon carbide (SiC: silicon carbide), gallium nitride (GaN), or diamond may be used.
- Switching elements and diodes formed of wide band gap semiconductors have high voltage resistance and high allowable current density. Therefore, a more miniaturized power semiconductor module can be realized, and by using the miniaturized power semiconductor module, the semiconductor power conversion devices 1a, 1b and 1c can be miniaturized.
- switching elements and diodes formed of wide band gap semiconductors have high heat resistance. Therefore, since the heat sink fins of the heat sinks of the semiconductor power conversion devices 1a, 1b, and 1c can be reduced in size, the semiconductor power conversion devices 1a, 1b, and 1c can be further reduced in size.
- switching elements and diodes formed of wide band gap semiconductors have low power loss. Therefore, it is possible to increase the efficiency of the switching elements and the diodes, and consequently increase the efficiency of the power semiconductor modules and the semiconductor power conversion devices 1a, 1b, and 1c.
- the switching elements 12 au 1, 12 au 2, 12 bu 1 and 12 bu 2 and the diodes 12 au 3, 12 au 4, 12 bu 3 and 12 bu 4 are formed of a wide band gap semiconductor, the switching speed is fast, so that the frequency of the carrier wave can be increased. Therefore, the timing adjustment resolution of the gate timing adjustment circuit 112b can be increased, and more accurate parallel operation is possible.
- each of the semiconductor power conversion devices 1a, 1b, and 1c may include all of the controller 111a, the delay circuit 112a, the controller 111b, and the gate timing adjustment circuit 112b.
- Each of the semiconductor power conversion devices 1a, 1b, and 1c may be set as a master or a slave based on a mechanical switch or an electrical signal.
- the controller 111a and the delay circuit 112a are operated.
- each of the semiconductor power conversion devices 1a, 1b, and 1c operates the controller 111b and the gate timing adjustment circuit 112b when set as a slave.
- the semiconductor power conversion system 1 can be realized only by manufacturing one type of semiconductor power conversion device. This makes it possible to share parts, share manufacturing processes, and facilitate inventory management, thereby reducing costs.
- FIG. FIG. 18 is a functional block diagram showing the configuration of the semiconductor power conversion system according to the second embodiment of the present invention.
- the control device 11a of the master semiconductor power conversion device 1a includes a controller 111a, a delay line 116a, and a delay time adjustment unit 117a.
- the delay line 116a can take a delay time from 0 to T similarly to the delay lines 112bu9 and 112bu10 (see FIG. 9) of the slave semiconductor power converters 1b and 1c.
- the delay time of the delay line 116a is set to half of T at the initial time.
- the gate timing adjustment circuit 112b of the slave semiconductor power converters 1b and 1c sends the delay time of the delay lines 112bu9 and 112bu10 of the own semiconductor power converter to the communication unit 133b at a predetermined timing or a predetermined cycle.
- the communication unit 133b transmits the delay time received from the gate timing adjustment circuit 112b to the communication unit 124a of the master semiconductor power conversion device 1a via the communication path C.
- the communication unit 124a sends the delay times received from the slave semiconductor power conversion devices 1b and 1c to the delay time adjustment unit 117a.
- the delay time adjustment unit 117a further receives a delay time from the delay line 116a at a predetermined timing or a predetermined period.
- the delay time adjustment unit 117a has a predetermined timing or a predetermined cycle, and the delay time of the delay line 116a of the master semiconductor power converter 1a and the delay lines 112bu9 of each of the slave semiconductor power converters 1b and 1c. And the delay time of 112bu10 are adjusted.
- FIG. 19 is a diagram illustrating an example of the delay time of the semiconductor power conversion device.
- the delay time 110 of the delay line 116a of the master semiconductor power converter 1a is set to half of T.
- Delay time 111 of delay lines 112bu9 and 112bu10 of slave semiconductor power converter 1b is set longer than delay time 110 of delay line 116a of master semiconductor power converter 1a by gate timing adjustment circuit 112b.
- the delay time 112 of the delay lines 112bu9 and 112bu10 of the slave semiconductor power converter 1c is set shorter than the delay time 110 of the delay line 116a of the master semiconductor power converter 1a by the gate timing adjustment circuit 112b.
- the delay time 111 of the delay lines 112bu9 and 112bu10 of the slave semiconductor power converter 1b is set much larger than the delay time 110 of the master semiconductor power converter 1a. Therefore, the margin 113 that can further increase the delay time 111 of the delay lines 112bu9 and 112bu10 of the slave semiconductor power converter 1b is very small. That is, there is very little room for adjustment of the delay lines 112bu9 and 112bu10 of the slave semiconductor power conversion device 1b.
- the delay time 112 of the delay lines 112bu9 and 112bu10 of the slave semiconductor power converter 1c is set slightly shorter than the delay time 110 of the master semiconductor power converter 1a. Therefore, the margin 114 that can further reduce the delay time 112 of the delay lines 112bu9 and 112bu10 of the slave semiconductor power converter 1c is larger than the margin 113. That is, there is much room for adjustment of the delay lines 112bu9 and 112bu10 of the slave semiconductor power converter 1c.
- the delay time adjustment unit 117a includes the semiconductor power conversion devices 1a, 1b, and 1c so that the adjustment margin of the semiconductor power conversion device having the smallest adjustment margin in the semiconductor power conversion devices 1a, 1b, and 1c increases. An adjustment range for reducing or increasing all delay times is determined. After determining the adjustment width, the delay time adjustment unit 117a adjusts the delay time of the delay line 116a and transmits the adjustment width to the slave semiconductor power conversion devices 1b and 1c. The gate timing adjustment circuit 112b of each of the slave semiconductor power conversion devices 1b and 1c adjusts the delay time of the delay lines 112bu9 and 112bu10 of the own semiconductor power conversion device based on the adjustment width received from the master semiconductor power conversion device 1a. .
- FIG. 20 is a diagram illustrating an example of the delay time after adjustment of the semiconductor power conversion device.
- the margin 113 that can further increase the delay time 111 of the slave semiconductor power conversion device 1b is very small. Therefore, the delay time adjustment unit 117a determines the adjustment width 115 so as to reduce the delay time of each of the semiconductor power conversion devices 1a, 1b, and 1c.
- the delay time 110 of the master semiconductor power converter 1a is reduced by the adjustment width 115.
- the delay time 111 of the slave semiconductor power conversion device 1b is also reduced by the adjustment width 115.
- the margin 116 capable of increasing the delay time 111 of the slave semiconductor power conversion device 1b is obtained by adding the adjustment width 115 to the margin 113 before adjustment.
- the delay time 112 of the slave semiconductor power conversion device 1c is also reduced by the adjustment width 115.
- the margin 117 that can further reduce the delay time 112 of the slave semiconductor power conversion device 1c is obtained by subtracting the adjustment width 115 from the margin 114 before adjustment.
- the delay time adjustment unit 117a includes an adjustment margin for further increasing the delay time of the semiconductor power conversion device having the largest delay time among the semiconductor power conversion devices 1a, 1b, and 1c, and the semiconductor power conversion devices 1a, 1b, and The adjustment width can be determined so that the adjustment margin for further reducing the delay time of the semiconductor power conversion device having the smallest delay time in 1c is the same.
- the delay time adjustment unit 117a includes an adjustment margin 116 for further increasing the delay time 111 of the semiconductor power conversion device 1b having the largest delay time among the semiconductor power conversion devices 1a, 1b, and 1c, and the semiconductor
- the adjustment width 115 may be determined so that the adjustment margin 117 that further reduces the delay time 112 of the semiconductor power conversion device 1c having the smallest delay time among the power conversion devices 1a, 1b, and 1c is the same. it can.
- the balance with the adjustment room of the converter can be balanced, and the room for adjustment of the entire semiconductor power conversion system 1 can be increased.
- 1 Semiconductor power conversion system 1a, 1b, 1c Semiconductor power conversion device, 11a, 11b, 11c control device, 12a, 12b, 12c main circuit, 111a, 111b controller, 112a delay circuit, 112b gate timing adjustment circuit, 113a, 113b Time counter, 114a, 114b, triangular wave generator, 115a, 115b, PWM modulator, 121, synchronous data generator, 122, communication time storage, 123, error detection code generator, 124, synchronous data transmitter, 131, error detector, 132 time counter Correction processing unit, 133 synchronization data receiving unit, 112 au U-phase delay circuit, 112 bu U-phase gate timing adjustment circuit, 12 au, 12 bu U-phase main circuit, 112 bu 1 band pass filter, 112 bu 8 delay amount Integer unit, 112Bu9,112bu10,116a delay lines, 117a delay time adjustment unit, 124a, 133b communication unit.
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Abstract
Description
図1は、本発明の実施の形態1の電力変換システムの構成を示す機能ブロック図である。図1に示すように、実施の形態1の電力変換システム1は、複数の半導体電力変換装置1a、1b及び1cを備えている。半導体電力変換装置1a、1b及び1cは、例えばモータなどの負荷2に並列接続されている。半導体電力変換装置1a、1b及び1cの各々は、負荷2を駆動するためのPWM電圧を発生する。
図18は、本発明の実施の形態2の半導体電力変換システムの構成を示す機能ブロック図である。実施の形態2では、マスタ半導体電力変換装置1aの制御装置11aは、コントローラ111aと、ディレイライン116aと、遅延時間調整部117aと、を備える。ディレイライン116aは、スレーブ半導体電力変換装置1b及び1cのディレイライン112bu9及び112bu10(図9参照)と同様に、0からTまでの遅延時間を取り得る。ディレイライン116aの遅延時間は、初期時において、Tの半分に設定されている。
Claims (8)
- 1つのマスタの電力変換装置と1つ又は複数のスレーブの電力変換装置とを備え、前記マスタの電力変換装置と前記スレーブの電力変換装置とが同一の電圧指令値をPWM変調することによって得られるゲート信号に基づきPWM電圧を1つの負荷に並列に出力する電力変換システムにおいて、
前記マスタの電力変換装置及び前記スレーブの電力変換装置の各々は、
時刻カウンタと、
前記電圧指令値をPWM変調するためのキャリア波を前記時刻カウンタに同期して発生させるキャリア波発生部と、
を備え、
前記マスタの電力変換装置は、
前記マスタの電力変換装置の前記時刻カウンタが予め定められた値に達したとき、前記スレーブの電力変換装置の前記時刻カウンタの値を前記マスタの電力変換装置の前記時刻カウンタに同期させるための同期データを生成する同期データ生成部と、
前記同期データを前記スレーブの電力変換装置に送信する通信部と、
を備え、
前記スレーブの電力変換装置は、
前記マスタの電力変換装置から前記同期データを受信する通信部と、
前記スレーブの電力変換装置の前記通信部が前記同期データを受信完了した時点における前記スレーブの電力変換装置の前記時刻カウンタの値と予め求められている通信時間とに基づいて、前記スレーブの電力変換装置の前記時刻カウンタの値を補正する時刻カウンタ補正処理部と、
前記スレーブの電力変換装置の出力側の電流を検出する電流センサと、
前記電流センサによって検出された電流のうちの環流電流成分に基づいて、前記スレーブの電力変換装置の前記ゲート信号の位相を進める又は遅らせるゲートタイミング調整部と、
を備えることを特徴とする、電力変換システム。 - 前記ゲートタイミング調整部は、
前記ゲート信号がローレベルからハイレベルへ変化するときに、前記スレーブの電力変換装置から外部へ向かう方向の環流電流成分の振幅が予め定められた閾値を超えていたら、前記ゲート信号の位相を遅らせ、
前記ゲート信号がローレベルからハイレベルへ変化するときに、外部から前記スレーブの電力変換装置へ向かう方向の環流電流成分の振幅が予め定められた閾値を超えていたら、前記ゲート信号の位相を進め、
前記ゲート信号がハイレベルからローレベルへ変化するときに、前記スレーブの電力変換装置から外部へ向かう方向の環流電流成分の振幅が予め定められた閾値を超えていたら、前記ゲート信号の位相を進め、
前記ゲート信号がハイレベルからローレベルへ変化するときに、外部から前記スレーブの電力変換装置へ向かう方向の環流電流成分の振幅が予め定められた閾値を超えていたら、前記ゲート信号の位相を遅らせることを特徴とする、
請求項1に記載の電力変換システム。 - 前記ゲートタイミング調整部は、
環流電流成分の振幅が大きくなるほど、前記ゲート信号の位相を進める又は遅らせる幅を増やすことを特徴とする、
請求項1又は2に記載の電力変換システム。 - 前記ゲートタイミング調整部は、
前記電流センサによって検出された電流のうちのノイズ成分及び負荷へ流れる負荷電流成分を除去し、環流電流成分を通過させるフィルタ回路を備えることを特徴とする、
請求項1から3のいずれか1項に記載の電力変換システム。 - 前記マスタの電力変換装置は、
前記マスタの電力変換装置の前記ゲート信号の位相を進める又は遅らせるディレイラインと、
前記マスタの電力変換装置の前記ゲート信号並びに前記1つ又は複数のスレーブの電力変換装置の前記ゲート信号の遅延時間を調整する遅延時間調整部と、
を備え、
前記ゲートタイミング調整部は、
前記スレーブの電力変換装置の前記ゲート信号の位相を進める又は遅らせるディレイラインを備え、
前記スレーブの電力変換装置の前記通信部は、前記スレーブの電力変換装置の前記ディレイラインの遅延時間を前記遅延時間調整部に送信し、
前記遅延時間調整部は、全ての前記電力変換装置の前記ディレイラインの遅延時間に基づいて、全ての前記電力変換装置の中の前記ディレイラインの調整マージンが1番少ない前記電力変換装置の調整マージンが増加するように、全ての前記電力変換装置の前記ディレイラインの遅延時間を一律に少なくする又は一律に多くするための調整幅を決定して、前記マスタの電力変換装置が備える前記ディレイラインに設定するとともに、前記1つ又は複数のスレーブの電力変換装置の前記ゲートタイミング調整部に送信することを特徴とする、
請求項1から4のいずれか1項に記載の電力変換システム。 - 前記遅延時間調整部は、全ての前記電力変換装置の中の前記ディレイラインの遅延時間が1番多い前記電力変換装置の前記ディレイラインの遅延時間を更に多くする調整マージンと、全ての前記電力変換装置の中の前記ディレイラインの遅延時間が1番少ない前記半導体電力変換装置の前記ディレイラインの遅延時間を更に少なくする調整マージンと、が同じになるように、調整幅を決定することを特徴とする、
請求項5に記載の電力変換システム。 - 前記電力変換装置の各々は、
前記ゲート信号に基づいてスイッチングすることによりPWM電圧を出力するスイッチング素子を備え、
前記スイッチング素子は、ワイドバンドギャップ半導体素子であることを特徴とする、
請求項1から6のいずれか1項に記載の電力変換システム。 - 1つのマスタの電力変換装置と1つ又は複数のスレーブの電力変換装置とを備え、前記マスタの電力変換装置と前記スレーブの電力変換装置とが同一の電圧指令値をPWM変調することによって得られるゲート信号に基づきPWM電圧を1つの負荷に並列に出力する電力変換システムにおいて、
前記スレーブの電力変換装置の各々は、
前記ゲート信号に基づいてスイッチングすることによりPWM電圧を出力するスイッチング素子と、
前記スイッチング素子がスイッチングする第1のスイッチングのときにおいて、前記スレーブの電力変換装置の出力電流の環流電流成分が予め定められた閾値を超えていたら、前記第1のスイッチングの次の第2のスイッチングのときにおいて、前記スレーブの電力変換装置の出力側の電圧が変化するタイミングを前記スレーブの電力変換装置の他の電力変換装置の出力側の電圧が変化するタイミングに近づけるように前記スレーブの電力変換装置の前記ゲート信号を進める又は遅らせる制御を行うことにより、前記第2のスイッチングのときにおける前記スレーブの電力変換装置の出力電流の環流電流成分を前記第1のスイッチングのときにおける前記スレーブの電力変換装置の出力電流の環流電流成分よりも小さくする制御装置と、を備えることを特徴とする、電力変換システム。
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