WO2016033880A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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WO2016033880A1
WO2016033880A1 PCT/CN2014/092659 CN2014092659W WO2016033880A1 WO 2016033880 A1 WO2016033880 A1 WO 2016033880A1 CN 2014092659 W CN2014092659 W CN 2014092659W WO 2016033880 A1 WO2016033880 A1 WO 2016033880A1
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array substrate
layer
tunnel junction
junction structure
magnetic layer
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PCT/CN2014/092659
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English (en)
French (fr)
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张金中
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US14/769,222 priority Critical patent/US9646998B2/en
Publication of WO2016033880A1 publication Critical patent/WO2016033880A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H10N50/85—Magnetic active materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N59/00—Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display device.
  • OLED Organic Light-Emitting Diode
  • OLED display devices can be classified into: PMOLED (Passive Matrix Organic Light Emission Display) and AMOLED (Active Matrix Organic Light Emission Display). Two. Compared with PMOLED, AMOLED has a faster response speed and can meet the needs of display devices of various sizes, so many companies will focus more on AMOLED.
  • PMOLED Passive Matrix Organic Light Emission Display
  • AMOLED Active Matrix Organic Light Emission Display
  • the array substrate of the AMOLED mainly includes a low temperature polysilicon array substrate and an oxide array substrate according to different forming materials of a TFT (Thin Film Transistor) active layer.
  • TFT Thin Film Transistor
  • the low-temperature polysilicon array substrate the low-temperature polycrystalline silicon after crystallization is in a grain state, and a certain gap exists between the crystal grains, so that the threshold voltage of the TFT is easily drifted, and the uniformity of the array substrate is poor; further, in order to improve the array substrate Uniformity, the threshold voltage drift is eliminated by setting a plurality of TFTs, but the increase in the number of TFTs causes the switching speed of the pixels to be slow, and the fabrication process of the array substrate is complicated; and the low-temperature polysilicon is required for crystallization.
  • the oxide array substrate since the carrier mobility in the oxide is low after energization, the OLED as a current device does not well support the characteristics of higher carrier mobility, and thus the switching speed of the TFT is slow. .
  • the present disclosure provides an array substrate, a manufacturing method thereof, and a display device, for the purpose of reducing or eliminating at least one of the above technical problems.
  • An array substrate comprising: a substrate substrate and a pattern including a source and a drain on the substrate; further comprising: between the substrate and the pattern including the source and the drain
  • the tunnel junction structure forms an active layer of the array substrate and a tunneling effect occurs.
  • the tunnel junction structure may include: a first magnetic layer, an insulating layer, and a second magnetic layer which are sequentially stacked, and the first magnetic layer and the second magnetic layer are both high-density film forms.
  • the first magnetic layer may include an antiferromagnetic pinning layer and a ferromagnetic pinned layer which are sequentially stacked.
  • the material of the antiferromagnetic pinning layer may include at least one of lanthanum manganese, nickel manganese oxide, nickel oxide, iron manganese, and L 2 BaNiO 5 .
  • the material of the ferromagnetic pinned layer may include at least one of cobalt carbide, cobalt, iron, nickel carbide, and nickel cobalt oxide.
  • the material of the insulating layer may include at least one of magnesium oxide, aluminum oxide, and titanium oxynitride.
  • the insulating layer has a thickness of less than 10 nanometers.
  • the material of the second magnetic layer is a soft magnetic material, and the soft magnetic material may include at least one of cobalt carbide, cobalt, iron, nickel carbide, and nickel cobalt oxide.
  • the array substrate may include a plurality of pixels, and each of the pixels may include two thin film transistors and one storage capacitor.
  • the present invention also provides a method of fabricating an array substrate according to an embodiment of the present invention, comprising: forming a pattern including a source and a drain on a substrate, before forming the pattern including the source and the drain Forming a pattern including a tunnel junction structure on the underlying substrate, the tunnel junction structure forming an active layer of the array substrate and causing a tunneling effect.
  • the method may further include: sequentially forming a first magnetic layer, an insulating layer, and a second magnetic layer to form the tunnel junction structure, wherein the first magnetic layer and the second magnetic layer are both high-density film forms. .
  • Forming the pattern including the tunnel junction structure on the base substrate may include sequentially covering the first magnetic layer and the insulating layer on the base substrate by a chemical vapor deposition process or a sputtering process And a material of the second magnetic layer, the pattern including the tunnel junction structure is formed by a patterning process.
  • the present disclosure also provides a display device including the array substrate proposed in accordance with an embodiment of the present invention.
  • the TFT of the array substrate has a tunnel junction structure, and when the driving voltage is applied to the gate of the TFT, the magnetic moment directions of the two magnetic layers of the tunnel junction structure are the same, and the TFT In the state of spin electron tunneling, the TFT is turned on.
  • the gate voltage of the TFT is not applied with a driving voltage, the magnetic moments of the two magnetic layers of the tunnel junction structure are opposite, the TFT is in a spin-electronic shielding state, and the TFT is turned off, thereby realizing The switching function of the TFT.
  • the tunnel junction structure realizes the resistance difference by using the tunneling effect during the working process of the TFT, the direction of the current in the tunnel junction structure is always perpendicular to the film plane, so the carrier mobility of the array substrate provided by the present invention is higher. High, and thus the switching speed of the TFT is faster.
  • both magnetic layers constituting the tunnel junction structure are in a dense film form, rather than in a grain state in which the gap is large, the threshold voltage of the TFT including the tunnel junction structure in the present disclosure is less likely to drift, and the array The uniformity of the substrate is better than the prior art.
  • the uniformity of the array substrate in the present disclosure is good, it is not necessary to increase the uniformity of the array substrate by providing a plurality of TFTs in the prior art, and the array substrate in the present disclosure can use fewer TFTs. Thereby increasing the switching speed of the pixel.
  • the formation of the tunnel junction structure does not require a high-temperature crystallization process and can be deposited at a lower temperature, and the array substrate having the tunnel junction structure requires a reduction in the number of TFTs, these all simplify the fabrication process of the array substrate.
  • FIG. 7 are diagrams showing steps of a method for fabricating an array substrate according to an embodiment of the present invention.
  • Figure 8 is a cross-sectional view showing a tunnel junction structure according to an embodiment of the present invention.
  • FIG. 9 is a cross-sectional view showing a tunnel junction structure in a spin electron tunneling state according to an embodiment of the present invention.
  • FIG. 10 is a cross-sectional view showing a tunnel junction structure in a spin-electronic shielding state according to an embodiment of the present invention
  • FIG. 11 is a circuit diagram of an array substrate according to an embodiment of the present invention.
  • the embodiment provides an array substrate, the array substrate includes: a substrate substrate and a pattern including a source and a drain on the substrate, the array substrate further includes: a substrate on the substrate and including a source and a drain A tunnel junction structure between the pole patterns, which forms an active layer of the array substrate and undergoes a tunneling effect.
  • the tunnel junction structure includes a first magnetic layer 801, an insulating layer 803, and a second magnetic layer 802 which are sequentially stacked, and the first magnetic layer 801 and the second magnetic layer 802 are both high-density film forms. .
  • the array substrate includes a plurality of matrix-arranged TFTs.
  • the tunnel junction structure can be considered to form an active layer of the TFT.
  • the control principle of the TFT including the tunnel junction structure provided in this embodiment is as follows:
  • the first magnetic layer 801 and the second magnetic layer 802 of the tunnel junction structure on both sides of the insulating layer 803 are magnetized, and the magnetic moments of the two magnetic layers are the same. Therefore, the electron spin directions inside the two magnetic layers are the same.
  • the barrier layer generated by the insulating layer 803 for electrons in the same direction of spin is low, and the electron tunneling probability is large.
  • the electrons of the majority of the spin sub-bands in the second magnetic layer 802 pass through the barrier generated by the insulating layer 803 into the empty state of the majority of the sub-bands of the first magnetic layer 801, while the electrons of a few spin sub-bands are also from the first
  • the magnetic layer 801 enters the empty state of a minority of the sub-bands of the second magnetic layer 802, so that the TFT is in a spin-electron tunneling state, and the TFT is turned on.
  • the magnetic moments of the first magnetic layer 801 and the second magnetic layer 802 of the tunnel junction structure on both sides of the insulating layer 803 are opposite, so the first magnetic The spin of the electrons of the majority spin subband in layer 801 and the second magnet The spins of the electrons of a few spin subbands of the layer 802 are opposite and parallel.
  • the barrier layer generated by the insulating layer 803 for the electrons in the opposite direction of the spin is high, and the electron tunneling probability is extremely small.
  • the electrons of the majority of the spin sub-bands in the first magnetic layer 801 will enter the empty state of a minority of the sub-bands of the second magnetic layer 802, while the electrons of a few spin sub-bands also enter the second magnetic layer 802 from the first magnetic layer 801.
  • the majority of the subbands are in an empty state, so that the TFT is in a spin-electronic shield state and the TFT is turned off.
  • the switching action of the TFT is achieved by the above process. It can be seen from the above process that during the working process of the TFT, the tunnel junction structure of the TFT realizes the difference of the resistance by using the tunneling effect, and the direction of the current in the tunnel junction structure is always perpendicular to the plane of the film. Therefore, the array substrate provided in this embodiment is loaded. The mobility of the carriers is high, and the switching speed of the TFTs is faster.
  • the threshold voltage of the TFT including the tunnel junction structure in the embodiment is less likely to drift, and the array The uniformity of the substrate is better than the prior art.
  • the uniformity of the array substrate in the embodiment is good, it is not necessary to increase the uniformity of the array substrate by providing a plurality of TFTs in the prior art, and the array substrate in this embodiment can be used less. The TFT, thereby increasing the switching speed of the pixel.
  • the array substrate having the tunnel junction structure requires a reduced number of TFTs, which simplifies the fabrication process of the array substrate.
  • the first magnetic layer 801 of the tunnel junction structure may include an antiferromagnetic pinning layer 8011 and a ferromagnetic pinned layer 8012 which are sequentially stacked.
  • the material of the antiferromagnetic pinning layer 8011 may include an antiferromagnetic material, a synthetic antiferromagnetic material or a mixed antiferromagnetic material, and particularly may include manganese lanthanum, nickel manganese oxide, nickel oxide, manganese iron and L. 2 at least one of BaNiO 5 .
  • the material of the ferromagnetic pinned layer 8012 may be a soft magnetic material, and may particularly include at least one of cobalt carbide, cobalt, iron, nickel carbide, and nickel cobalt to ensure that the threshold voltage of the TFT is not easily drifted.
  • the uniformity of the substrate is better.
  • the material of the insulating layer 803 may include at least one of magnesium oxide, aluminum oxide, and titanium oxynitride.
  • the thickness of the insulating layer 803 can be set to be thinner than 10 nm to ensure that electrons can pass through the insulating layer 803 quickly, and the tunnel junction structure rapidly has a tunneling effect.
  • the material of the second magnetic layer 802 is generally a soft magnetic material, and may include at least one of cobalt carbide, cobalt, iron, nickel carbide, and nickel cobalt.
  • the second magnetic layer 802 of the tunnel junction structure is selected to be soft. Magnetic material to ensure that the threshold voltage of the TFT is not easy to drift, and the uniformity of the array substrate is better.
  • the electron tunneling probability is exponentially decayed with the height of the ferromagnetic barrier, spin polarization is generated even if the incident electron current having a zero spin polarization is transmitted through the ferromagnetic barrier. Further, the electrons can tunnel through the insulating layer, so that one of the two magnetic layers of the ferromagnetic tunnel junction structure has ferromagnetism to cause a tunneling effect, thereby making the first magnetic layer 801 and the second magnetic layer 802 of the tunnel junction structure The choice is even greater.
  • the array substrate in this embodiment may include a plurality of pixels, and each pixel may include two TFTs and one storage capacitor.
  • the pixel structure of the array substrate provided in this embodiment may be as shown in FIG. 7 , including: a buffer layer 101 on a substrate, the buffer layer 101 is a conductive layer; formed on the buffer layer 101 a pattern including a first tunnel junction structure 201 and a second tunnel junction structure 202; a gate insulating layer (not shown) overlying the pattern including the first tunnel junction structure 201 and the second tunnel junction structure 202; a pattern including a first gate 301, a second gate 302, and a gate line 303 formed over the gate insulating layer; a pattern covering the first gate 301, the second gate 302, and the gate line 303 An interlayer dielectric layer (not shown) having a plurality of interlayer dielectric layer vias 401 in the interlayer dielectric layer; and a first drain 501 and a second formed on the interlayer dielectric layer A pattern of the drain 502, the cross-bridge 503, the data line 504, and the VDD line 505, wherein the first drain 501 is electrically connected to the second gate
  • the second gate 302 and the buffer layer 101, the data line 504 and the VDD line 505 pass through the interlayer dielectric layer via 401 and the buffer layer 10, respectively. 1 electrically connected, the first tunnel junction structure 201, the first gate 301 and the first drain 501 belong to a control switch, and the second tunnel junction structure 202, the second gate 302 and the second drain 502 belong to a driving switch, including The pattern of the first drain 501, the second drain 502, the cross-bridge 503, the data line 504, and the VDD line 505 and the buffer layer 101 form a storage capacitor 506; the first drain 501 and the second drain 502 are covered.
  • planarization layer (not shown) across the pattern of the bridge 503, the data line 504, and the VDD line 505, the planarization layer having a planarization layer via 601 therein; and the cathode 701 formed over the planarization layer
  • the cathode 701 is electrically connected to the second drain 502 through the planarization layer via 601.
  • the equivalent circuit diagram of the above pixel structure can be as shown in FIG. 11, when the pixel needs to be displayed,
  • the gate line ie, the Gate line
  • the magnetic moment direction of the magnetic layer is such that the magnetic moment direction of the second magnetic layer is opposite to the magnetic moment direction of the first magnetic layer, so that the control switch T1 operates in the spin electronic shielding state, that is, the control switch T1 is turned off; Very little current passes through the gate of the drive switch T2, and the transverse magnetic field generated by the gate of the drive switch T2 is insufficient to change the direction of the magnetic moment of the second magnetic layer of the tunnel junction structure in the drive switch T2, thereby driving the switch T2 to operate in the spin
  • the electron tunneling state that is, the driving switch T2 is turned on. At this time, a bias voltage is applied to the source of the driving switch T2 through the VDD line, and the drain of the driving switch T2 outputs a signal to the OLED to form a pixel display.
  • the gate line turns off the control switch T1
  • the magnetic moment direction of the second magnetic layer of the tunnel junction structure of the control switch T1 is the same as the magnetic moment direction of the first magnetic layer, so that the control switch T1 operates at The spin electron tunneling state, that is, the control switch T1 is turned on; at this time, the current in the data line (ie, the SD line) passes through the control switch T1, and a large amount of current passes through the gate of the driving switch T2 to drive the gate of the switch T2.
  • the transverse magnetic field is sufficient to change the direction of the magnetic moment of the second magnetic layer of the tunnel junction structure in the driving switch T2, so that the driving switch T2 operates in the spin electronic shielding state, that is, the driving switch T2 is turned off, and at this time, the current on the VDD line cannot be Pass, that is, the drain of the driving switch T2 cannot output a signal to the OLED, and the pixel is not displayed.
  • a method of fabricating an array substrate comprising: forming a pattern including a source and a drain on a substrate, including forming a source and Before the pattern of the drain, a pattern including a tunnel junction structure is formed on the base substrate, and the tunnel junction structure forms an active layer of the array substrate and a tunneling effect occurs.
  • the first magnetic layer, the insulating layer and the second magnetic layer are sequentially laminated to form a tunnel junction structure, and the first magnetic layer 801 and the second magnetic layer 802 are both in a highly dense film form.
  • the forming material of the tunnel junction structure determines that the tunnel junction structure is formed without a high-temperature crystallization process, and can be deposited at a lower temperature; on the other hand, the tunnel junction structure
  • the film layer shape determines that the threshold voltage of the TFT is less likely to drift, and the uniformity of the array substrate is better, and it is not necessary to increase the uniformity of the substrate by providing a plurality of TFTs in the prior art, thereby reducing the number of TFTs required. Both aspects simplify the fabrication process of the array substrate.
  • the method for fabricating the array substrate provided in this embodiment is specifically described as an example of a pixel structure in which each pixel includes two TFTs and a storage capacitor. As shown in FIG. 1 to FIG. 7 , the manufacturing method includes:
  • Step S1 A pattern including the buffer layer 101 is formed on the base substrate as shown in FIG.
  • the process of forming the buffer layer 101 may include: firstly depositing a buffer layer material on the substrate substrate, depositing the buffer layer material by magnetron sputtering deposition, and the buffer layer material may include indium tin oxide or indium zinc oxide.
  • the transparent conductive material may have a thickness of 100 nm to 200 nm; then a part of the buffer layer material is removed by a patterning process to form a pattern including the buffer layer 101, and a wet etching process may be selected for the removal process.
  • the thickness of the base substrate is not particularly limited, and a base substrate having a thickness of 0.4 mm to 0.7 mm may be selected.
  • Step S2 forming a pattern including a tunnel junction structure on the substrate substrate subjected to the step 1, as shown in FIG.
  • the above step S2 may include sequentially covering the materials of the first magnetic layer, the insulating layer and the second magnetic layer on the substrate substrate by a chemical vapor deposition process or a sputtering process, and forming a pattern including the tunnel junction structure by a patterning process.
  • the chemical vapor deposition process used for the material covering the first magnetic layer, the insulating layer and the second magnetic layer may be a plasma enhanced chemical vapor deposition process, and the sputtering process may be specifically RF magnetic control. Sputtering process.
  • the pattern forming the tunnel junction structure by using a patterning process may specifically be: forming a first tunnel junction structure 201 and a second tunnel junction structure on a substrate substrate covering the materials of the first magnetic layer, the insulating layer and the second magnetic layer. a patterned photoresist layer of 202, wherein the photoresist layer is used as a mask to remove portions of the first magnetic layer, the insulating layer and the second magnetic layer, and the first tunnel junction structure 201 and the second tunnel junction structure are to be formed.
  • the material on the region of 202 forms a first tunnel junction structure 201 and a second tunnel junction structure 202.
  • the material for removing part of the first magnetic layer, the insulating layer and the second magnetic layer may be a dry etching process.
  • Step S3 forming a pattern including the first gate 301, the second gate 302, and the gate line 303 on the substrate subjected to the step 2, as shown in FIG.
  • the process of forming the first gate 301, the second gate 302, and the gate line 303 may include: depositing a metal material, removing a portion of the metal material by a patterning process, and retaining the first gate 301 and the second gate to be formed.
  • the metal material on the regions of the electrode 302 and the gate line 303 forms a pattern including the first gate 301, the second gate 302, and the gate line 303.
  • the material for forming the first gate 301, the second gate 302, and the gate line 303 is not specifically limited, and may include molybdenum, aluminum, argon, titanium, copper, etc. to ensure the first gate 301, The second gate 302 and the gate line 303 have good electrical conductivity.
  • the method further includes: forming a gate insulating layer to make the first tunnel junction structure 201 and the first gate 301 is electrically insulated, and the second tunnel junction structure 202 is electrically insulated from the second gate 302.
  • the material for forming the gate insulating layer in this embodiment may be an insulating material such as silicon dioxide or silicon nitride.
  • the thickness of the gate insulating layer may be 300 nm to 400 nm to ensure the insulation requirement between the tunnel junction structure and the gate.
  • Step S4 covering an interlayer dielectric layer (not shown) on the pattern including the first gate 301, the second gate 302, and the gate line 303, and forming a plurality of interlayer dielectric layers on the interlayer dielectric layer Via 401, as shown in FIG.
  • the interlayer dielectric layer may be a plasma enhanced chemical vapor deposition process, and the interlayer dielectric layer may be formed of an insulating material such as silicon dioxide or silicon nitride to include the first gate 301,
  • the pattern of the second gate 302 and the gate line 303 is electrically insulated from the subsequently formed pattern including the first drain, the second drain, the bridge, the data line, and the VDD line.
  • Forming a plurality of interlayer dielectric layer vias 401 may employ a patterning process.
  • Step S5 forming a pattern including the first drain 501, the second drain 502, the bridge 503, the data line 504, and the VDD line 505 on the array substrate subjected to the step S4, as shown in FIG.
  • the step may specifically include: depositing a metal material by a sputtering process, and the deposited metal material may include molybdenum, titanium, aluminum, etc., wherein if titanium and aluminum are selected, the film structure formed by the deposition may include titanium, aluminum, and Titanium is sequentially laminated to form a thin film; then a portion of the metal material is removed by a patterning process, and the metal material on the region where the first drain 501, the second drain 502, the bridge 503, the data line 504, and the VDD line 505 are to be formed is left.
  • a pattern including a first drain 501, a second drain 502, a bridge 503, a data line 504, and a VDD line 505 is formed.
  • the first drain 501 is electrically connected to the second gate 302 through the interlayer dielectric via 401.
  • the bridge 503 is used to electrically connect the second gate 302 and the buffer layer 101, and the data line 504 and the VDD line 505 are respectively.
  • the first tunnel junction structure 201, the first gate 301 and the first drain 501 belong to the control switch, and the second tunnel junction structure 202 and the second gate 302 are electrically connected to the buffer layer 101 through the interlayer dielectric layer via 401.
  • the second drain 502 belongs to the driving switch, and includes a first drain 501, a second drain 502, a bridge 503, a data line 504, and a VDD line 505.
  • the pattern and buffer layer 101 form a storage capacitor 506 to prevent leakage current from adversely affecting pixel display.
  • Step S6 forming a planarization layer (not shown) on the array substrate subjected to the step S5, and then forming a planarization layer via 601 penetrating the planarization layer, as shown in FIG.
  • the step may specifically include: coating a resin material on the array substrate subjected to step S5 to form a planarization layer, the resin material may be a photosensitive resin or a non-photosensitive resin; and then removing a part of the resin material by a patterning process to form a planarization
  • the via hole 601 may be subjected to a dry etching process during the removal process.
  • Step S7 A pattern including the cathode 701 is formed on the array substrate subjected to the step S6, as shown in FIG.
  • the above steps may include: depositing a cathode material on the array substrate subjected to step S6 by using a sputtering process, the cathode material may include a metal material such as magnesium and silver, and the thickness may be 10 nm to 30 nm; then part of the metal material is removed by a patterning process, and is retained.
  • the metal material on the region where the cathode 701 is formed forms a pattern including the cathode 701.
  • the cathode 701 is electrically connected to the second drain 502 through the planarization layer via 601.
  • an insulating material such as polyimide may be coated on the array substrate subjected to step 7, and then a pixel defining layer is formed by a patterning process.
  • steps S1 to S7 are directed to a method for fabricating an OLED display device, and those skilled in the art may further provide the foregoing aspects of the TFT of the array substrate provided by the present disclosure having a tunnel junction structure.
  • the technical solution is applied to the fabrication of a liquid crystal display device array substrate.
  • a display device comprising the array substrate provided according to the foregoing embodiment of the present invention, wherein the switching speed of the TFT is higher due to the higher carrier mobility of the array substrate of the display device Faster, so the display device in this embodiment has a faster switching speed; and, because the uniformity of the array substrate included is better, the display of the display device in the embodiment has better uniformity; Since the tunnel junction structure of the array substrate can be deposited at a low temperature without high-temperature crystallization, the number of TFTs required for each pixel structure is reduced, thereby simplifying the fabrication process of the display device in this embodiment.
  • the display device in this embodiment may be: a liquid crystal display panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, and the like. Or parts.

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Abstract

一种阵列基板及其制作方法、显示装置，该阵列基板包括：衬底基板及位于衬底基板上的包括源极和漏极（501、502）的图形，还包括：位于衬底基板与包括源极和漏极（501、502）的图形之间的隧道结结构（201、202），隧道结结构（201、202）形成阵列基板的有源层并发生隧穿效应。从而能够实现较高的载流子迁移率，TFT的开关速度更快；TFT的阈值电压不易发生漂移，具有较高的均匀性；每个像素能够使用更少的TFT，像素的开关速度更快，且制作工艺更简单。

Description

阵列基板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制作方法、显示装置。
背景技术
随着显示技术的不断发展，OLED(Organic Light-Emitting Diode，有机发光二极管)显示装置作为一种新兴的平板显示装置，以其体积轻薄、对比度高、色域高、功耗低、可以实现柔性显示等优点，必将成为下一代显示装置的发展趋势。
根据驱动方式的不同，OLED显示装置可分为：PMOLED(Passive Matrix Organic Light Emission Display，无源矩阵有机发光二极管显示装置)和AMOLED(Active Matrix Organic Light Emission Display，有源矩阵有机发光二极管显示装置)两种。相对于PMOLED，AMOLED的响应速度更快，且可满足各种尺寸显示装置的需求，因此很多企业将关注点更多的集中在AMOLED上。
现有技术中，根据TFT(Thin Film Transistor，薄膜晶体管)有源层的形成材料不同，AMOLED的阵列基板主要包括低温多晶硅阵列基板和氧化物阵列基板。其中，对于低温多晶硅阵列基板，晶化后的低温多晶硅为晶粒状态，晶粒间存在一定的间隙，造成TFT的阈值电压易漂移，阵列基板的均匀性较差；进一步的，为了提高阵列基板的均匀性，会通过设置多个TFT来消除阈值电压的漂移，但是TFT数量的增多又会造成像素的开关速度变慢，且造成阵列基板的制作工艺复杂；并且低温多晶硅晶化时所需的温度较高，也会增加制作工艺复杂度。对于氧化物阵列基板，由于通电后氧化物中载流子迁移率较低，不能很好地满足作为电流器件的OLED需要较高载流子迁移率支持的特性，进而造成TFT的开关速度较慢。
发明内容
本公开提供了一种阵列基板及其制作方法、显示装置，以实现减轻或消除上述至少一个技术问题的目的。
为此，本发明采用如下技术方案：
一种阵列基板，包括：衬底基板及位于所述衬底基板上的包括源极和漏极的图形，还包括：位于所述衬底基板与所述包括源极和漏极的图形之间的隧道结结构，所述隧道结结构形成所述阵列基板的有源层并发生隧穿效应。
在实施例中，所述隧道结结构可包括：依次层叠的第一磁性层、绝缘层和第二磁性层，第一磁性层和第二磁性层均为高致密性的薄膜形态。
所述第一磁性层可包括依次层叠的反铁磁钉扎层和铁磁被钉扎层。
所述反铁磁钉扎层的材料可包括锰化铱、锰化镍、氧化镍、锰化铁和L2BaNiO5中的至少一种。
所述铁磁被钉扎层的材料可包括铁化钴、钴、铁、铁化镍和钴化镍中的至少一种。
所述绝缘层的材料可包括氧化镁、三氧化二铝和三氧化二钛中的至少一种。
所述绝缘层的厚度小于10纳米。
所述第二磁性层的材料为软磁材料，所述软磁材料可包括铁化钴、钴、铁、铁化镍和钴化镍中的至少一种。
所述阵列基板可包括多个像素，每个像素可包括两个薄膜晶体管和一个存储电容。
本发明还提供了一种制作按照本发明实施例提出的阵列基板的方法，包括：在衬底基板上形成包括源极和漏极的图形，在所述形成包括源极和漏极的图形之前，在所述衬底基板上形成包括隧道结结构的图形，所述隧道结结构形成所述阵列基板的有源层并发生隧穿效应。
在实施例中，所述方法还可包括：第一磁性层、绝缘层和第二磁性层依次层叠形成所述隧道结结构，第一磁性层和第二磁性层均为高致密性的薄膜形态。
所述在所述衬底基板上形成包括隧道结结构的图形可包括：采用化学汽相淀积工艺或溅射工艺在所述衬底基板上依次覆盖所述第一磁性层、所述绝缘层和所述第二磁性层的材料，采用构图工艺形成所述包括隧道结结构的图形。
本公开还提供了一种显示装置，包括按照本发明实施例所提出的阵列基板。
本公开所提供的阵列基板及其制作方法、显示装置中，阵列基板的TFT具有隧道结结构，当TFT的栅极被施加驱动电压时，隧道结结构的两磁性层的磁矩方向相同，TFT处于自旋电子隧穿状态，TFT开启，当TFT的栅极未被施加驱动电压时，隧道结结构的两磁性层的磁矩方向相反，TFT处于自旋电子屏蔽状态，TFT关断，从而实现了TFT的开关作用。由于在TFT的工作过程中，其隧道结结构利用隧穿效应实现电阻差异，隧道结结构中电流的方向总是垂直于薄膜平面，因此本发明所提供的阵列基板的载流子的迁移率较高，进而TFT的开关速度较快。
并且，由于构成隧道结结构两磁性层均为致密性高的薄膜形态，而非以间隙较大的晶粒状态存在，因此本公开中的包括隧道结结构的TFT的阈值电压不易发生漂移，阵列基板的均匀性较现有技术更好。
另一方面，由于本公开中的阵列基板的均匀性较好，因此无需像现有技术中通过设置多个TFT来提高阵列基板的均匀性，本公开中的阵列基板能够使用更少的TFT，从而提高了像素的开关速度。
此外，由于形成隧道结结构无需高温晶化过程，且能够在较低温度下沉积，加上具有隧道结结构的阵列基板需要TFT的个数减少，这些均使得阵列基板的制作工艺得以简化。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显然，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1～图7为本发明实施例所提供的阵列基板的制作方法的各步骤图；
图8为本发明实施例所提供的隧道结结构的截面图；
图9为本发明实施例所提供的隧道结结构处于自旋电子隧穿状态时的截面图；
图10为本发明实施例所提供的隧道结结构处于自旋电子屏蔽状态时的截面图；
图11为本发明实施例所提供的阵列基板的电路图。
具体实施方式
为使本公开的上述目的、特征和优点能够更加明显易懂，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本公开保护的范围。
本实施例提供了一种阵列基板，该阵列基板包括：衬底基板及位于衬底基板上的包括源极和漏极的图形，该阵列基板还包括：位于衬底基板与包括源极和漏极的图形之间的隧道结结构，该隧道结结构形成阵列基板的有源层并发生隧穿效应。
如图8所示，该隧道结结构包括：依次层叠的第一磁性层801、绝缘层803和第二磁性层802，第一磁性层801和第二磁性层802均为高致密性的薄膜形态。
阵列基板包括多个矩阵式排布的TFT，可以认为上述隧道结结构形成TFT的有源层，本实施例所提供的包括隧道结结构的TFT的控制原理如下：
如图9所示，当TFT的栅极被施加驱动电压时，隧道结结构的位于绝缘层803两侧的第一磁性层801和第二磁性层802被磁化，两磁性层的磁矩方向相同，因此两磁性层内部的电子自旋方向相同，此时,绝缘层803对于自旋同方向的电子产生的势垒较低，电子的隧穿几率大。第二磁性层802中的多数自旋子带的电子将穿过绝缘层803产生的势垒进入第一磁性层801的多数子带的空态,同时少数自旋子带的电子也从第一磁性层801进入第二磁性层802少数子带的空态,从而TFT处于自旋电子隧穿状态，TFT开启。
如图10所示，当TFT的栅极未被施加驱动电压时，隧道结结构的位于绝缘层803两侧的第一磁性层801和第二磁性层802的磁矩方向相反，因此第一磁性层801中的多数自旋子带的电子的自旋与第二磁 性层802的少数自旋子带的电子的自旋方向相反且平行,此时,绝缘层803对于自旋反方向的电子产生的势垒较高，电子的隧穿几率极小。第一磁性层801中的多数自旋子带的电子将进入第二磁性层802的少数子带的空态,同时少数自旋子带的电子也从第一磁性层801进入第二磁性层802多数子带的空态,从而TFT处于自旋电子屏蔽状态，TFT关断。
通过上述过程实现了TFT的开关作用。由上述过程可见，在TFT的工作过程中，TFT的隧道结结构利用隧穿效应实现电阻差异，隧道结结构中电流的方向总是垂直于薄膜平面，因此本实施例所提供的阵列基板的载流子的迁移率较高，进而TFT的开关速度较快。
并且，由于隧道结结构两磁性层均为致密性高的薄膜形态，而非以间隙较大的晶粒状态存在，因此本实施例中的包括隧道结结构的TFT的阈值电压不易发生漂移，阵列基板的均匀性较现有技术更好。
另一方面，由于本实施例中的阵列基板的均匀性较好，因此无需像现有技术中通过设置多个TFT来提高阵列基板的均匀性，本实施例中的阵列基板能够使用更少的TFT，从而提高了像素的开关速度。
此外，由于形成隧道结结构无需高温晶化过程，且能够在较低温度下沉积，具有隧道结结构的阵列基板需要TFT的个数减少，这些均使得阵列基板的制作工艺得以简化。
本实施例中，上述隧道结结构的第一磁性层801可包括依次层叠的反铁磁钉扎层8011和铁磁被钉扎层8012。其中，反铁磁钉扎层8011的材料可包括反铁磁材料、合成反铁磁材料或混合反铁磁材料等，特别可包括锰化铱、锰化镍、氧化镍、锰化铁和L2BaNiO5中的至少一种。铁磁被钉扎层8012的材料可为软磁材料，特别可包括铁化钴、钴、铁、铁化镍和钴化镍中的至少一种，以保证TFT的阈值电压不易发生漂移，阵列基板的均匀性更好。
绝缘层803的材料可包括氧化镁、三氧化二铝和三氧化二钛中的至少一种。另外，可将绝缘层803的厚度设置的较薄，可以小于10纳米，以保证电子能够快速穿过绝缘层803，隧道结结构迅速发生隧穿效应。
第二磁性层802的材料一般为软磁材料，可包括铁化钴、钴、铁、铁化镍和钴化镍中的至少一种，隧道结结构的第二磁性层802选择软 磁材料，以保证TFT的阈值电压不易发生漂移，阵列基板的均匀性更好。
需要说明的是，由于电子隧穿几率与铁磁势垒高度呈指数衰减关系，因此，即使自旋极化率为零的入射电子流穿过铁磁势垒后也会产生自旋极化，进而使得电子能够隧穿绝缘层，因此铁磁隧道结结构的两磁性层之一具有铁磁性就能发生隧穿效应，从而使隧道结结构的第一磁性层801和第二磁性层802材料的选择范围更大。
由于本实施例所提供的阵列基板的TFT具有隧道结结构，TFT的阈值电压不易发生漂移，阵列基板的均匀性好，因此无需设置多个TFT来提高阵列基板的均匀性。本实施例中的阵列基板可包括多个像素，每个像素可包括两个TFT和一个存储电容。
具体的，本实施例所提供的阵列基板的像素结构可如图7所示，包括：位于衬底基板上的缓冲层101，该缓冲层101为能够导电的膜层；形成于缓冲层101上的包括第一隧道结结构201和第二隧道结结构202的图形；覆盖在包括第一隧道结结构201和第二隧道结结构202的图形上的栅极绝缘层(图中未示出)；形成于栅极绝缘层之上的包括第一栅极301、第二栅极302和栅极线303的图形；覆盖在包括第一栅极301、第二栅极302和栅极线303的图形上的层间介质层(图中未示出)，该层间介质层内具有的多个层间介质层过孔401；形成于层间介质层之上的包括第一漏极501、第二漏极502、跨桥503、数据线504和VDD线505的图形，其中，第一漏极501通过层间介质层过孔401与第二栅极302电性相连，跨桥503用于电连接第二栅极302与缓冲层101，数据线504和VDD线505分别通过层间介质层过孔401与缓冲层101电性相连，第一隧道结结构201、第一栅极301和第一漏极501属于控制开关，第二隧道结结构202、第二栅极302和第二漏极502属于驱动开关，包括第一漏极501、第二漏极502、跨桥503、数据线504和VDD线505的图形与缓冲层101构成一存储电容506；覆盖在包括第一漏极501、第二漏极502、跨桥503、数据线504和VDD线505的图形上的平坦化层(图中未示出)，该平坦化层内具有平坦化层过孔601；形成于平坦化层之上的包括阴极701的图形，该阴极701通过平坦化层过孔601与第二漏极502电性相连。
上述像素结构的等效电路图可如图11所示，当像素需要显示时， 栅极线(即Gate线)向控制开关T1的栅极施加一驱动信号，使控制开关T1开启，在控制开关T1内产生一横向磁场，该横向磁场影响控制开关T1中隧道结结构的第二磁性层的磁矩方向，使第二磁性层的磁矩方向与第一磁性层的磁矩方向相反，从而控制开关T1工作在自旋电子屏蔽状态，即控制开关T1关断；此时，只有极少的电流通过驱动开关T2的栅极，驱动开关T2的栅极产生的横向磁场不足以改变驱动开关T2中隧道结结构的第二磁性层的磁矩方向，从而驱动开关T2工作在自旋电子隧穿状态，即驱动开关T2开启，此时，通过VDD线向驱动开关T2的源极施加一偏置电压，驱动开关T2的漏极输出一信号给OLED，形成像素显示。
当像素不需要显示时，栅极线使控制开关T1关断，控制开关T1的隧道结结构的第二磁性层的磁矩方向与第一磁性层的磁矩方向相同，从而控制开关T1工作在自旋电子隧穿状态，即控制开关T1开启；此时，数据线(即SD线)中的电流通过控制开关T1，有大量电流通过驱动开关T2的栅极，驱动开关T2的栅极产生的横向磁场足以改变驱动开关T2中隧道结结构的第二磁性层的磁矩方向，从而使得驱动开关T2工作在自旋电子屏蔽状态，即驱动开关T2断开，此时，VDD线上的电流不能通过，即驱动开关T2的漏极不能输出信号给OLED，像素不显示。
在本发明的另一实施例中，提供了一种制作按照上述发明实施例提出的阵列基板的方法，包括：在衬底基板上形成包括源极和漏极的图形，在形成包括源极和漏极的图形之前，在衬底基板上形成包括隧道结结构的图形，隧道结结构形成阵列基板的有源层并发生隧穿效应。
在该实施例中，第一磁性层、绝缘层和第二磁性层依次层叠形成隧道结结构，第一磁性层801和第二磁性层802均为高致密性的薄膜形态。
本实施例所提供阵列基板的制作方法中，一方面，隧道结结构的形成材料决定了形成隧道结结构无需高温晶化过程，且能够在较低温度下沉积；另一方面，隧道结结构的膜层形态决定了TFT的阈值电压不易发生漂移，阵列基板的均匀性较好，无需像现有技术中通过设置多个TFT来提高基板均匀性，因此能够减少所需要的TFT的个数，这两方面均使阵列基板的制作工艺得以简化。
下面以每个像素包括两个TFT和一个存储电容的像素结构为例，对本实施例所提供的阵列基板的制作方法进行具体介绍，如图1～图7所示，该制作方法包括：
步骤S1：在衬底基板上形成包括缓冲层101的图形，如图1所示。
本步骤中，形成缓冲层101的过程可包括：首先在衬底基板上沉积缓冲层材料，沉积缓冲层材料可采用磁控溅射沉积法，缓冲层材料可包括氧化铟锡或氧化铟锌等透明导电材料，厚度可为100nm～200nm；之后采用构图工艺去除部分缓冲层材料，形成包括缓冲层101的图形，去除过程可选用湿法刻蚀工艺。
本实施例对衬底基板的厚度并不具体限定，可选用0.4mm～0.7mm厚的衬底基板。
步骤S2：在经过步骤1的衬底基板上形成包括隧道结结构的图形，如图2所示。
上述步骤S2可包括：采用化学汽相淀积工艺或溅射工艺在衬底基板上依次覆盖第一磁性层、绝缘层和第二磁性层的材料，采用构图工艺形成包括隧道结结构的图形。
其中，覆盖第一磁性层、绝缘层和第二磁性层的材料所采用的化学汽相淀积工艺具体可为等离子体增强化学气相淀积工艺，所采用的溅射工艺具体可为射频磁控溅射工艺。
采用构图工艺形成包括隧道结结构的图形具体可为：在覆盖了第一磁性层、绝缘层和第二磁性层的材料的衬底基板上形成具有第一隧道结结构201和第二隧道结结构202的图形的光刻胶层，以该光刻胶层为掩膜去除部分第一磁性层、绝缘层和第二磁性层的材料，保留待形成第一隧道结结构201和第二隧道结结构202的区域上的材料，形成第一隧道结结构201和第二隧道结结构202。前述过程中，去除部分第一磁性层、绝缘层和第二磁性层的材料可采用干法刻蚀工艺。
步骤S3：在经过步骤2的衬底基板上形成包括第一栅极301、第二栅极302和栅极线303的图形，如图3所示。
本步骤中，形成第一栅极301、第二栅极302和栅极线303的过程可包括：沉积金属材料，采用构图工艺去除部分金属材料，保留待形成第一栅极301、第二栅极302和栅极线303的区域上的金属材料，形成包括第一栅极301、第二栅极302和栅极线303的图形。
本实施例对第一栅极301、第二栅极302和栅极线303的形成材料并不具体限定，可包括钼、铝、氩、钛和铜等，以保证第一栅极301、第二栅极302和栅极线303具有良好的导电性。
需要说明的是，在形成包括第一栅极301、第二栅极302和栅极线303的图形之前还可包括：形成栅极绝缘层，以使第一隧道结结构201与第一栅极301电性绝缘，且第二隧道结结构202与第二栅极302电性绝缘。本实施例中栅极绝缘层的形成材料可为二氧化硅或氮化硅等绝缘材料。另外，栅极绝缘层的厚度可为300nm～400nm，以保证隧道结结构与栅极之间的绝缘需求。
步骤S4：在包括第一栅极301、第二栅极302和栅极线303的图形上覆盖层间介质层(图中未示出)，在层间介质层上形成多个层间介质层过孔401，如图4所示。
上述步骤中，覆盖层间介质层可采用等离子体增强化学气相淀积工艺，层间介质层的形成材料可为二氧化硅和氮化硅等绝缘材料，以使包括第一栅极301、第二栅极302和栅极线303的图形与后续形成的包括第一漏极、第二漏极、跨桥、数据线和VDD线的图形电性绝缘。形成多个层间介质层过孔401可采用构图工艺。
步骤S5：在经过步骤S4的阵列基板上形成包括第一漏极501、第二漏极502、跨桥503、数据线504和VDD线505的图形，如图5所示。
本步骤具体可包括：采用溅射工艺沉积金属材料，所沉积的金属材料可包括钼，钛和铝等，其中，若选用钛和铝，则沉积所形成的膜层结构可包括钛、铝和钛依次层叠所形成的薄膜；之后采用构图工艺去除部分金属材料，保留待形成第一漏极501、第二漏极502、跨桥503、数据线504和VDD线505的区域上的金属材料，形成包括第一漏极501、第二漏极502、跨桥503、数据线504和VDD线505的图形。
其中，第一漏极501通过层间介质层过孔401与第二栅极302电性相连，跨桥503用于电连接第二栅极302与缓冲层101，数据线504和VDD线505分别通过层间介质层过孔401与缓冲层101电性相连，第一隧道结结构201、第一栅极301和第一漏极501属于控制开关，第二隧道结结构202、第二栅极302和第二漏极502属于驱动开关，包括第一漏极501、第二漏极502、跨桥503、数据线504和VDD线505 的图形与缓冲层101构成一存储电容506，以防止漏电流对像素显示产生不良影响。
步骤S6：在经过步骤S5的阵列基板上形成平坦化层(图中未示出)，之后再形成贯穿平坦化层的平坦化层过孔601，如图6所示。
本步骤具体可包括：在经过步骤S5的阵列基板上涂覆树脂材料，形成平坦化层，树脂材料可为感光树脂，也可为非感光树脂；之后采用构图工艺去除部分树脂材料，形成平坦化层过孔601，去除过程中可采用干法刻蚀工艺。
步骤S7：在经过步骤S6的阵列基板上形成包括阴极701的图形，如图7所示。
上述步骤可包括：采用溅射工艺在经过步骤S6的阵列基板上沉积阴极材料，阴极材料可包括镁和银等金属材料，厚度可为10nm～30nm；之后采用构图工艺去除部分金属材料，保留待形成阴极701的区域上的金属材料，形成包括阴极701的图形。其中，阴极701通过平坦化层过孔601与第二漏极502电性相连。
本实施例还可以在经过步骤7的阵列基板上涂覆聚酰亚胺等绝缘材料，然后采用构图工艺形成像素限定层。
需要说明的是，上述步骤S1～步骤S7是针对OLED显示装置的制作方法，本领域的技术人员在本公开所提供的阵列基板的TFT具有隧道结结构的技术方案的基础上，还可将前述技术方案应用于液晶显示装置阵列基板的制作中。通过将上述步骤S1～步骤S7中的步骤S7更改为形成包括像素电极的图形，即可得到具有相同优点的阵列基板。
在本发明另一实施例中，提供了一种显示装置，其包括按照本发明前述实施例所提供的阵列基板，由于该显示装置的阵列基板的载流子迁移率较高，TFT的开关速度较快，因此本实施例中的显示装置具有较快的开关速度；并且，由于所包括的阵列基板的均匀性较好，因此本实施例中的显示装置的画面显示的均匀性较好；此外，由于阵列基板的隧道结结构能够在低温下沉积，无需高温晶化，每个像素结构所需的TFT个数减少，因此简化了本实施例中的显示装置的制作工艺。
需要说明的是，本实施例中的显示装置可以为：液晶显示面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种阵列基板，包括：衬底基板及位于所述衬底基板上的包括源极和漏极的图形，所述阵列基板还包括：位于所述衬底基板与所述包括源极和漏极的图形之间的隧道结结构，所述隧道结结构形成所述阵列基板的有源层并发生隧穿效应；
  2. 根据权利要求1所述的阵列基板，其中所述隧道结结构包括：依次层叠的第一磁性层、绝缘层和第二磁性层，第一磁性层和第二磁性层均为高致密性的薄膜形态。
  3. 根据权利要求1所述的阵列基板，其特征在于，所述第一磁性层包括依次层叠的反铁磁钉扎层和铁磁被钉扎层。
  4. 根据权利要求3所述的阵列基板，其特征在于，所述反铁磁钉扎层的材料包括锰化铱、锰化镍、氧化镍、锰化铁和L2BaNiO5中的至少一种。
  5. 根据权利要求3所述的阵列基板，其特征在于，所述铁磁被钉扎层的材料包括铁化钴、钴、铁、铁化镍和钴化镍中的至少一种。
  6. 根据权利要求1所述的阵列基板，其特征在于，所述绝缘层的材料包括氧化镁、三氧化二铝和三氧化二钛中的至少一种。
  7. 根据权利要求6所述的阵列基板，其特征在于，所述绝缘层的厚度小于10纳米。
  8. 根据权利要求1所述的阵列基板，其特征在于，所述第二磁性层的材料为软磁材料，所述软磁材料包括铁化钴、钴、铁、铁化镍和钴化镍中的至少一种。
  9. 根据权利要求1～8任一项所述的阵列基板，其特征在于，所述阵列基板包括多个像素，每个所述像素包括两个薄膜晶体管和一个存储电容。
  10. 一种制作如权利要求1～8任一项所述的阵列基板的方法，包括：
    在衬底基板上形成包括源极和漏极的图形，
    在所述形成包括源极和漏极的图形之前，在所述衬底基板上形成包括隧道结结构的图形，所述隧道结结构形成所述阵列基板的有源层并发生隧穿效应。
  11. 根据权利要求10所述的方法，包括：第一磁性层、绝缘层和第二磁性层依次层叠形成所述隧道结结构，其中第一磁性层和第二磁性层均为高致密性的薄膜形态。
  12. 根据权利要求10所述的方法，所述在所述衬底基板上形成包括隧道结结构的图形包括：采用化学汽相淀积工艺或溅射工艺在所述衬底基板上依次覆盖所述第一磁性层、所述绝缘层和所述第二磁性层的材料，采用构图工艺形成所述包括隧道结结构的图形。
  13. 一种显示装置，包括权利要求1～9任一项所述的阵列基板。
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