WO2016019698A1 - 晶片的正、背面间电性连接结构及其制造方法 - Google Patents

晶片的正、背面间电性连接结构及其制造方法 Download PDF

Info

Publication number
WO2016019698A1
WO2016019698A1 PCT/CN2015/000492 CN2015000492W WO2016019698A1 WO 2016019698 A1 WO2016019698 A1 WO 2016019698A1 CN 2015000492 W CN2015000492 W CN 2015000492W WO 2016019698 A1 WO2016019698 A1 WO 2016019698A1
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
circuit board
pads
flexible circuit
front surface
Prior art date
Application number
PCT/CN2015/000492
Other languages
English (en)
French (fr)
Inventor
朱贵武
卢旋瑜
Original Assignee
璩泽明
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 璩泽明 filed Critical 璩泽明
Publication of WO2016019698A1 publication Critical patent/WO2016019698A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to a positive and negative electrical connection structure of a wafer and a manufacturing method thereof, in particular to a method in which a flexible circuit board is bent from a front surface of a wafer and is wound around a side edge of the wafer.
  • the back surface of the wafer is such that the die pads provided on the front surface of the wafer can be electrically connected to the back surface of the wafer by the circuit connection of the flexible circuit board to be electrically connected and mounted on a printed circuit board.
  • the function of the active area is achieved by enabling the active area provided on the front side of the wafer to match the printed circuit board.
  • a surface mount technology (SMT) to electrically bond a wafer in a flip-chip manner and mount it on a printed circuit board (PCB) is a common configuration and existing technology for current wafers.
  • a plurality of die pads disposed on the front surface of the chip face the printed circuit board (PCB) and are electrically connected to respective preset contacts of the circuit layer disposed on the surface of the printed circuit board.
  • a positive pad is provided on the front surface of a wafer in addition to a plurality of die pads, it cannot be electrically connected and mounted in a flip-chip manner.
  • a fingerprint identification wafer such as the wafer 10 shown in FIG. 2 is taken as an example, but is not intended to limit the present invention.
  • the front surface 11 of the wafer 10 is provided with a plurality of die pads 110 and an active area (active).
  • the area 111 is, for example, a fingerprint active area, which is used to sense a fingerprint image (such as pressing a finger on the surface of the active area 111) and convert it into an electronic signal, and then pass the plurality of A die pad 110 transmits an electronic signal to an electrically connected printed circuit board for identification or related operations. Since the active area 111, such as the fingerprint recognition sensing area, is externally sensed, the surface of the active area 111 must face the opposite side of the printed circuit board, otherwise it will be hidden by the printed circuit board, thus the front side 11 of the wafer 10. A plurality of die pads 110 are not electrically connected and mounted on a printed circuit board (PCB) in a flip-chip manner.
  • PCB printed circuit board
  • a plurality of bonding pads 110 and a printed circuit board (PCB) on the front surface 11 of the wafer 10 may be electrically connected by other bonding methods, such as a wire bond method
  • the wire used is drawn from the surface of the die pad 110 in an arc to the back of the wafer 10.
  • the drop is like the difference between the second surface 22 in FIG. 1 and the sensing surface of the active region 111 (such as the front surface 11 of the wafer 10), but the actual drop will be as shown in FIG.
  • the size of 50 ⁇ m is large, which causes the difference and unevenness between the surface of the active area 111 and the surrounding surface, and relatively affects the sensing function and the use effect of the active area 111 such as the fingerprint identification sensing area.
  • electrical conductive vias are arranged between the front side 11 and the back side 12. The design of such vias is common in wafer packaging and related background art, but the process is relatively cumbersome and complicated. Not cost effective.
  • the main object of the present invention is to provide a positive and negative electrical connection structure of a wafer and a manufacturing method thereof, which are formed by bending a front surface of a wafer by a flexible circuit board and sticking around one side edge of the wafer. On the back side of the wafer, so that the die pads provided on the front side of the wafer can be displaced to the back surface of the wafer by the circuit communication of the flexible circuit board for electrical connection and mounting on a printed circuit board In order to enable the active area provided on the front side of the wafer to match the printed circuit board to achieve the function of using the active area.
  • the present invention provides a positive and negative electrical connection structure of a wafer, comprising a wafer and a flexible printed circuit (FPC) having a plurality of crystal pads on the front surface thereof (FPC) a die pad and at least one active area such as a fingerprint active area;
  • the flexible circuit board has a first surface and a second surface, and the first surface has a plurality of a connection pad corresponding to each of the die pads disposed on the front surface of the wafer;
  • the second surface is provided with a plurality of second connection pads for respectively corresponding to the first connection pads on the first surface Connecting, the plurality of second connection pads are respectively connected to the exposed contacts of the connection circuit preset on the printed circuit board used together, so that the chip can be provided by the flexible circuit board.
  • the second connection pads are mounted on a printed circuit board and electrically connected.
  • the positive and negative electrical connection structure of the wafer wherein the wafer is a fingerprint identification chip and a fingerprint identification sensing area is disposed on the front surface thereof.
  • the positive and negative electrical connection structure of the wafer wherein: a surface of each of the crystal pads disposed on the front surface of the wafer is provided with a layer of chemical nickel gold.
  • the positive and negative electrical connection structure of the wafer wherein: the flexible circuit board is provided with an adhesive layer on the first surface, so that the flexible circuit board is bent from the front surface of the wafer and bypasses the wafer When one side edge extends to the back side of the wafer, it can be adhered to the back surface by means of the adhesive layer.
  • the positive and negative electrical connection structures of the wafer wherein: the upper surface of the active region disposed on the front surface of the wafer is further provided with a high transmittance dielectric layer.
  • the positive and negative electrical connection structure of the wafer wherein the high transmittance dielectric layer is disposed on the front surface of the wafer and completely shields the active region but exposes each crystal pad.
  • the positive and negative electrical connection structure of the wafer wherein: the height of the high transmittance dielectric layer disposed on the active region is further flush with the height of the flexible circuit board falling on the front surface of the wafer.
  • the front sides of the wafer are formed in the same plane.
  • the present invention also provides a method for manufacturing an electrical connection structure between a front and a back of a wafer, comprising the following steps:
  • Step 1 Providing a wafer having a plurality of die pads and at least one active area on the front side of the wafer.
  • Step 2 providing a flexible circuit board having a first surface and a second surface, the first surface being provided with a plurality of first connection pads for respectively corresponding to the plurality of crystal pads (die The second surface is provided with a plurality of second connection pads for electrically connecting to the first connection pads on the first surface by the circuit design of the flexible circuit board, and the plurality of second connections The pads are connected to respective exposed contacts of a connection line preset on a printed circuit board.
  • Step 3 Correspondingly, each of the first connection pads disposed on the first surface of the flexible circuit board is electrically connected to each of the crystal pads on the front surface of the chip.
  • Step 4 bending the flexible circuit board and extending around one edge of the wafer to adhere to the back surface of the wafer, so that the second connection pads are disposed on the second surface of the flexible circuit board. Can face outward, can be electrically connected by a subsequent operation and mounted on a phase-matched printed circuit board, so that the active area provided on the front side of the wafer can be used in conjunction with the printed circuit board to achieve an active area Use features.
  • the present invention adopting the above technical solution has the advantages that it uses a flexible circuit board to extend from the front surface of a wafer and wraps around one side edge of the wafer to adhere thereto.
  • the back side of the wafer is such that the die pads provided on the front side of the wafer can be displaced to the back side of the wafer by the circuit communication of the flexible circuit board for electrical connection and mounting on a printed circuit board,
  • the action area provided on the front side of the wafer can be matched with the printed circuit board to achieve the function of using the active area.
  • FIG. 1 is a cross-sectional view showing an embodiment of an electrical connection structure between a front and a back of a wafer of the present invention
  • FIG. 2 is a top plan view of an embodiment of a wafer of the present invention.
  • 3A to 3E are schematic flow charts showing a method of manufacturing an electrical connection structure between a front and a back surface of a wafer of the present invention
  • FIG. 4 is a cross-sectional view showing a dielectric layer having a high transmittance disposed on the front surface of the sensing region provided on the front surface of the wafer of the present invention
  • FIG. 5 is a cross-sectional view showing the height of the high transmittance dielectric layer in FIG. 4 flush with the height of the flexible circuit board.
  • the positive and negative electrical connection structure of the wafer of the present invention comprises a wafer 10 and a flexible printed circuit (FPC) 20, which can be a fingerprint identification wafer and the active area (
  • the active area can be a fingerprint active area but is not intended to limit the invention.
  • the front surface 11 of the wafer 10 is provided with a plurality of die pads 110 and at least one sensor active area 111 (such as a fingerprint identification sensing area) as shown in FIG.
  • four sides of the wafer 10 are provided with four die pads 110 and arranged in a row, but are not intended to limit the present invention. Therefore, only one die pad 110 is shown in FIG. However, it is not intended to limit the invention. Taking the wafer 10 of FIG.
  • the wafer 10 is a fingerprint identification chip
  • the active area 111 is a fingerprint active area, which occupies a large area on the front surface 11 of the wafer 10. It is used to externally sense a fingerprint image, such as pressing a finger on the surface of the active area 111, and converting it into an electronic signal, and then transmitting the electronic signal to the connected electronic die through the plurality of die pads 110.
  • a printed circuit board (not shown) is provided for the identification function related work.
  • the wafer 10 and the flexible circuit board 20 of FIG. 2 are taken as an example, but the dimensions and proportions shown in FIG. 2 are not intended to limit the present invention.
  • the flexible circuit board 20 can be designed to form a long rectangular flexible circuit board. And having a predetermined circuit design according to the needs of use, having a first surface 21 and a second surface 22; a portion of the flexible circuit board 20 is deposited on the front surface 11 of the wafer 10, and then by the wafer 10 The front surface 11 is bent and extends around one side edge of the wafer 10 to extend and adhere to the back surface 12 of the wafer 10.
  • the flexible circuit board 20 covers the back surface 12 of the wafer 10 as shown in FIG.
  • the invention is shown, but not intended to limit the invention, that is, the flexible circuit board 20 also covers a portion of the back side 12 of the wafer 10 (not shown) as needed for design.
  • the first surface 21 is provided with a plurality of first connection pads 210 for respectively corresponding to a plurality of die pads 110 disposed on the front surface 11 of the wafer 10;
  • the second surface 22 is provided with a plurality of
  • the two connection pads 220 are respectively connected to the first connection pads 210 disposed on the first surface 21 by the circuit of the flexible circuit board 20, and the plurality of second connection pads 220 are connected to the plurality of first connections
  • the corresponding connection relationship between the pads 210 is based on the circuit design of the flexible circuit board 20.
  • the existing circuit board circuit design technology can be used, and therefore will not be described herein.
  • the plurality of first connection pads 210 disposed on the first surface 21 are separated from the plurality of second connection pads 220 disposed on the second surface 22.
  • a distance is located adjacent to the opposite ends of the length of the long rectangular flexible circuit board 20, but is not intended to limit the present invention, so that a portion of the flexible circuit board 20 can be dropped on the front side 11 of the wafer 10.
  • the flexible circuit board 20 can be bent from the front side 11 of the wafer 10 and bypass the side edge of the wafer 10 to extend to the back surface 12 of the wafer 10 such that the second surface 22 can be adhesively attached to the back surface. 12 on.
  • the plurality of second connection pads 220 are connected to the exposed contacts of the connection circuit preset on a printed circuit board (not shown) for use in conjunction with the arrow A in FIG.
  • the two connection pads 220 are correspondingly connected to the exposed contacts of the connection lines preset on a printed circuit board (not shown) in the direction indicated by the arrow A, so that the wafer 10 can rely on the flexible circuit board 20
  • the plurality of second connection pads 220 are mounted on a printed circuit board (not shown) and electrically connected.
  • the design of the printed circuit board or the corresponding connection method such as flip chip method, it is regarded as prior art in the present invention and will not be further described.
  • first connection pads 210 disposed on the first surface 21 of the flexible circuit board 20 and a plurality of crystal pads disposed on the front surface 11 of the wafer 10 are illustrated.
  • an electroless nickel layer (ENIG) may be first disposed on the surface of each die pad 110. Electroless nickel/immersion gold) 30, but not intended to limit the present invention; the chemical nickel gold layer (ENIG) 30 prevents oxidation of each die pad 110 and enhances the first connection pad 210 and the crystal pad ( Solder junction connection efficiency between die pad 110.
  • an adhesive layer 40 such as a double-sided adhesive can be preset on the first surface 21 of the flexible circuit board 20, but is not used to limit the present invention, so that the soft When the front surface 11 of the wafer 10 is bent around the side edge of the wafer 10 and extends to the back surface 12 of the wafer 10, the first surface 21 of the flexible circuit board 20 can rely on the adhesive layer 40. The adhesive is applied to the back surface 12.
  • the method for manufacturing the electrical connection structure between the front and the back of the wafer of the present invention comprises the following steps:
  • Step 1 providing a wafer 10 as shown in FIG. 3A.
  • the front surface 11 of the wafer 10 is provided with a plurality of die pads 110 and at least one active area 111. Further, each of the crystal pads 110 can be preset.
  • An electroless nickel/immersion gold (ENIG) 30 is shown in Figure 3B.
  • Step 2 providing a flexible circuit board 20 as shown in FIG. 3C, the flexible circuit board 20 has a first surface 21 and a second surface 22, and the first surface 21 is provided with a plurality of first connection pads 210.
  • the second surface 22 is provided with a plurality of second connection pads 220 for respectively corresponding to the first surface 21 by the circuit of the flexible circuit board 20
  • a connection pad 210 is correspondingly connected, and the plurality of second connection pads 220 are connected to corresponding exposed contacts of a connection circuit preset on a used printed circuit board; wherein the flexible circuit board 20 is A double-sided adhesive layer 40 can be pre-applied to the second surface 22 as shown in FIG. 3D.
  • Step 3 Correspondingly, each of the first connection pads 210 disposed on the first surface 21 of the flexible circuit board 20 is electrically connected to each of the crystal pads 110 on the front surface 11 of the wafer 10 or an electroless nickel gold layer (ENIG) thereof. 30 is shown in Figures 3C and 3D.
  • Step 4 As shown in FIG. 3E, the flexible circuit board 20 is bent and bypassed on one side edge of the wafer 10 to extend onto the back surface 12 of the wafer 10 and adhered (eg, using the adhesive layer 40).
  • the second connecting pad 220 disposed on the second surface 22 of the flexible circuit board 20 can face outward (as indicated by an arrow A in FIG. 1) for electrical operation by subsequent operations.
  • Connected and mounted on a phase-matched printed circuit board (not shown) such that the active area 111 provided on the front side 11 of the wafer 10 can be used in conjunction with the printed circuit board to achieve the use of the wafer 10, such as fingerprint recognition.
  • the fingerprint identification function of the wafer is a phase-matched printed circuit board (not shown) such that the active area 111 provided on the front side 11 of the wafer 10 can be used in conjunction with the printed circuit board to achieve the use of the wafer 10, such as fingerprint recognition.
  • a surface of the active area 111 is further provided with a high transmittance dielectric layer 50 for protecting the active area 111 without affecting its function; as shown in FIG. Dusuke
  • the layer 50 is disposed on the front surface 11 of the wafer 10 for comprehensively shielding the active region 111 but exposing the chemical nickel gold provided on each of the die pads 110 and/or the die pads 110.
  • Layer (ENIG) 30 is provided on the front surface 11 of the wafer 10 for comprehensively shielding the active region 111 but exposing the chemical nickel gold provided on each of the die pads 110 and/or the die pads 110.
  • the height of the high transmittance dielectric layer 50 disposed on the inductive active region 111 in FIG. 4 is further the height of the flexible circuit board 20 falling on the front surface 11 of the wafer 10 (ie, FIGS. 4 and 5).
  • the surface of the second surface 22 of the flexible circuit board 20 is flush as shown in FIG. 5 such that the front surface 11 of the wafer 10 is formed in the same plane to meet the assembly requirements of the wafer 10 such as a fingerprint identification wafer in practical applications. .

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

一种晶片的正、背面间电性连接结构及其制造方法，包含一晶片（10）及一软性电路板（20），该晶片（10）的正面上设有多个晶垫（110）及至少一作用区（111）；该软性电路板（20）的第一表面（21）上设有多个对应于该多个晶垫（110）的第一连接垫（210）；第二表面（22）上设有多个分别与第一表面（21）上各第一连接垫（210）对应连接的第二连接垫（220），该多个第二连接垫（220）用以与一印刷电路板上所预设电路的各接点对应连接；制造时，利用该软性电路板（20）以将其第一表面（21）上所设的各第一连接垫（210）对应电性连接在该晶片（10）正面的各晶垫（110）上，再使该软性电路板（20）弯曲延伸并绕过该晶片（10）一侧边缘以粘着贴覆在该晶片（10）的背面上，使该晶片（10）的正面上所设的作用区（111）能配合该印刷电路板使用而达成作用区（111）的使用功能，并达成制程简化及成本效益。

Description

晶片的正、背面间电性连接结构及其制造方法 技术领域
本发明涉及一种晶片的正、背面间电性连接结构及其制造方法，尤指一种利用一软性电路板由一晶片的正面弯曲延伸并绕过该晶片一侧边缘而粘着贴覆在该晶片的背面，以使晶片正面上所设各晶垫(die pad)能凭借该软性电路板的电路连通而移位至晶片的背面供可电性连结并安装在一印刷电路板上，以使该晶片正面上所设的作用区能配合该印刷电路板而达成作用区的使用功能。
背景技术
利用表面粘着技术(SMT)将一晶片以覆晶(flip-chip)方式电性连结并安装在一印刷电路板(PCB)上，乃为目前晶片常见的使用组态及现有技术，此时该晶片的正面上所设的多个晶垫(die pad)即面对该印刷电路板(PCB)且能对应电性连接于该印刷电路板表面上所设电路层的各预设接点上。
但当一晶片的正面上除了多个晶垫(die pad)之外，还设有其他作用区(active area)时，即无法以覆晶(flip-chip)方式电性连接并安装在一印刷电路板(PCB)上。在此以一指纹辨识晶片如图2所示的晶片10为例说明但非用以限制本发明，该晶片10的正面11上设有多个晶垫(die pad)110及一作用区(active area)111如指纹辨识感应作用区(sensor active area)，该感应作用区111用以对外感应一指纹影像(如将手指按压在作用区111表面上)并转换成电子信号，再通过该多个晶垫(die pad)110将电子信号传输至所电性连接的印刷电路板供进行辨识功能或相关作业。由于该作用区111如指纹辨识感应作用区是对外感应，故该作用区111的表面须朝向该印刷电路板的相对侧，否则会被该印刷电路板遮住，因此该晶片10的正面11上的多个晶垫(die pad)110无法以覆晶(flip-chip)方式电性连接并安装在印刷电路板(PCB)上。
虽然，该晶片10的正面11上多个晶垫(die pad)110与印刷电路板(PCB)之间可采用其他接合方式来进行电性连结，如采用导线连结(wire bond)方式，但所使用的导线是从晶垫(die pad)110表面呈弧状拉引至位于该晶片10的背 面12处的印刷电路板(PCB)，因此导线的最高点相对会高出该晶片10的正面11或其上的晶垫(die pad)110一段距离，又这些导线(wire)外围一般会再施作一绝缘外护层用以盖住并保护这些导线(wire)，以致这些导线(wire)或其外护层相对于该作用区(active area)111的感应面之间的落差加大，以图1为例说明，该落差就像是图1中第二表面22与该作用区111的感应面(如晶片10的正面11)之间的落差，但实际落差会比图1中所示的50μm大，造成作用区111的表面与周遭表面之间的落差及不平整，相对影响该作用区111如指纹辨识感应作用区的感应功能及使用效果。另，如在晶片10的封装中在正面11及背面12之间安排电性导通用导通孔，此类导通孔的设计常见于晶片封装及相关背景技术中，但制程相对麻烦且复杂，不符合成本效益。
由上可知，对一正面上同时设有多个晶垫(die pad)及其他作用区(active area)如指纹辨识晶片的指纹辨识感应作用区(sensor active area)的晶片而言，本领域的背景技术的结构及/或制程实难以符合实际使用时的需求，因此在本相关领域中，仍存在进一步改进的需要性。
发明内容
本发明主要目的乃在于提供一种晶片的正、背面间电性连接结构及其制造方法，其利用一软性电路板由一晶片的正面弯曲延伸并绕过该晶片一侧边缘而粘着贴覆在该晶片的背面，以使晶片正面上所设各晶垫(die pad)能凭借该软性电路板的电路连通而移位至晶片的背面供可电性连接并安装在一印刷电路板上，以使该晶片正面上所设的作用区能配合该印刷电路板而达成作用区的使用功能。
为达成上述目的，本发明提供一种晶片的正、背面间电性连接结构，包含一晶片及一软性电路板(FPC，Flexible Printed Circuit)，该晶片的正面上设有多个晶垫(die pad)及至少一作用区(active area)如指纹辨识感应作用区(sensor active area)；该软性电路板具有一第一表面及一第二表面，该第一表面上设有多个第一连接垫供分别对应于该晶片正面上所设的各晶垫(die pad)；该第二表面上设有多个第二连接垫供分别与第一表面上各第一连接垫对应电性连接，又该多个第二连接垫用以与一相配合使用的印刷电路板上所预设的连接电路的各外露接点对应连接，以使该晶片能凭借该软性电路板所设该多个第二连接垫而安装在一印刷电路板上并达成电性连接。
所述的晶片的正、背面间电性连接结构，其中：该晶片为一指纹辨识晶片且其正面上设有一指纹辨识感应作用区。
所述的晶片的正、背面间电性连接结构，其中：该晶片的正面上所设各晶垫的表面上设有一化学镍金层。
所述的晶片的正、背面间电性连接结构，其中：该软性电路板的第一表面上设有一粘胶层，以使该软性电路板由该晶片的正面弯曲并绕过该晶片一侧边缘而延伸至该晶片的背面时能凭借该粘胶层以粘着贴覆在该背面上。
所述的晶片的正、背面间电性连接结构，其中：该晶片正面所设的作用区的上表面进一步设置一高透光度介质层。
所述的晶片的正、背面间电性连接结构，其中：该高透光度介质层设置在该晶片的正面上并完全遮护该作用区但露出各晶垫。
所述的晶片的正、背面间电性连接结构，其中：该作用区上所设置的高透光度介质层的高度进一步与该软性电路板落在该晶片的正面上的高度齐平，以使该晶片的正面形成同一平面。
为达成上述目的，本发明还提供一种晶片的正、背面间电性连接结构的制造方法，包含下列步骤：
步骤1：提供一晶片，该晶片的正面上设有多个晶垫(die pad)及至少一作用区(active area)。
步骤2：提供一软性电路板，该软性电路板具有一第一表面及一第二表面，该第一表面上设有多个第一连接垫供分别对应于该多个晶垫(die pad)，该第二表面上设有多个第二连接垫供能凭借软性电路板的电路设计而分别与第一表面上各第一连接垫对应电性连接，又该多个第二连接垫用以与一印刷电路板上所预设的连接线路的各外露接点对应连接。
步骤3：将该软性电路板的第一表面上所设各第一连接垫对应电性连接在该晶片正面的各晶垫上。
步骤4：使该软性电路板弯曲延伸并绕过该晶片一侧边缘以粘着贴覆在该晶片的背面上，如此使该软性电路板的第二表面上所设的各第二连接垫能面对向外，供可凭借后续作业以电性连接并安装在一相配合印刷电路板上，以使该晶片的正面上所设的作用区能配合该印刷电路板使用而达成作用区的使用功能。
与现有技术相比较，采用上述技术方案的本发明具有的优点在于：其利用一软性电路板由一晶片的正面弯曲延伸并绕过该晶片一侧边缘而粘着贴覆在该 晶片的背面，以使晶片正面上所设各晶垫(die pad)能凭借该软性电路板的电路连通而移位至晶片的背面供可电性连接并安装在一印刷电路板上，以使该晶片正面上所设的作用区能配合该印刷电路板而达成作用区的使用功能。
附图说明
图1是本发明晶片的正、背面间电性连接结构一实施例的剖视示意图；
图2是本发明的晶片一实施例的上视示意图；
图3A～图3E是本发明晶片的正、背面间电性连接结构的制造方法的流程示意图；
图4是图1中本发明晶片的正面上所设感应作用区的上面设置一高透光度的介质层的剖视示意图；
图5是图4中该高透光度介质层的高度与该软性电路板的高度齐平的剖视示意图。
附图标记说明：10-晶片；11-正面；12-背面；110 晶垫；111 作用区；20-软性电路板；21-第一表面；210 第一连接垫；22-第二表面；220 第二连接垫；30-化学镍金层(ENIG)；40-粘胶层；50-高透光度介质层。
具体实施方式
为使本发明更加明确详实，兹列举较佳实施例并配合下列图示，将本发明的结构及其技术特征详述如后：
参考图1，本发明的晶片的正、背面间电性连接结构包含一晶片10及一软性电路板(FPC，Flexible Printed Circuit)20，该晶片10可为一指纹辨识晶片而该作用区(active area)可为一指纹辨识感应作用区(sensor active area)但非用以限制本发明。该晶片10的正面11上设有多个晶垫(die pad)110及至少一作用区(sensor active area)111(如指纹辨识感应作用区)如图2所示。在图2中，该晶片10的正面11上设有四个晶垫(die pad)110并排列成一排但非用以限制本发明，因此在图1中只显示一晶垫(die pad)110但非用以限制本发明。又以图2的晶片10为例说明，该晶片10是一指纹辨识晶片，该作用区111为一指纹辨识感应作用区(sensor active area)，其占有该晶片10的正面11上较大面积，其用以对外感应一指纹影像如将手指按压在该作用区111的表面上，并转换成电子信号，再通过该多个晶垫(die pad)110以将电子信号传输至所连结的 印刷电路板(图未示)供进行辨识功能相关作业。
再以图2的晶片10及软性电路板20为例说明，但图2所示的尺寸及比例并非用以限制本发明，该软性电路板20可设计形成一长矩形软性电路板，并依使用需要而具有预定的电路设计，其具有一第一表面21及一第二表面22；该软性电路板20的一部分是落在该晶片10的正面11上，再由该晶片10的正面11弯曲并延伸绕过该晶片10一侧边缘而延伸至并粘着贴覆在该晶片10的背面12上，其中该软性电路板20得盖住该晶片10的背面12的全部如图1所示，但非用以限制本发明，也就是，该软性电路板20也可视设计需要而盖住该晶片10的背面12的一部分(图未示)。该第一表面21上设有多个第一连接垫210供分别对应于该晶片10的正面11上所设的多个晶垫(die pad)110；该第二表面22上设有多个第二连接垫220供凭借软性电路板20的电路而分别与该第一表面21上所设的各第一连接垫210对应连接，至于该多个第二连接垫220与该多个第一连接垫210之间的对应连接关系，乃是建立在该软性电路板20的电路设计上，对本发明而言乃是利用现有的电路板线路设计技术可达成者，故在此不再赘述。
以图2的晶片10及软性电路板20为例说明，该第一表面21上所设的多个第一连接垫210与该第二表面22上所设的多个第二连接垫220分开一段距离而分别位在靠近该长矩形软性电路板20的长度向二相对端处但非用以限制本发明，如此可使该软性电路板20的一部分落在该晶片10的正面11上，并使该软性电路板20能由该晶片10的正面11弯曲并绕过该晶片10一侧边缘而延伸至该晶片10的背面12以使其第二表面22能粘着贴覆在该背面12上。该多个第二连接垫220用以与一相配合使用的印刷电路板(图未示)上所预设的连接电路的各外露接点对应连接如图1中箭头A所示，该多个第二连接垫220即是依箭头A所示方向对应连接至一印刷电路板(图未示)上所预设的连接线路的各外露接点上，以使该晶片10能凭借该软性电路板20所设的该多个第二连接垫220而安装在一印刷电路板上(图未示)并达成电性连接。至于该印刷电路板的设计或所采用的对应连接工法如覆晶方式，在本发明中视为现有技术，故不另再说明。
此外，以图2所示结构为例说明，在该软性电路板20的第一表面21上所设的多个第一连接垫210与该晶片10的正面11上所设的多个晶垫(die pad)110对应连接的前，各晶垫(die pad)110的表面上可先设一化学镍金层(ENIG， electroless nickel/immersion gold)30，但非用以限制本发明；该化学镍金层(ENIG)30得防止各晶垫(die pad)110氧化，并可增进该第一连接垫210与晶垫(die pad)110之间的焊结连接效率。
此外，以图2所示结构为例说明，在该软性电路板20的第一表面21上可预设一粘胶层40如双面背胶但非用以限制本发明，以使该软性电路板20由该晶片10的正面11弯曲绕过该晶片10一侧边缘而延伸至该晶片10的背面12时，该软性电路板20的第一表面21即能凭借该粘胶层40而粘着贴覆在该背面12上。
本发明的晶片的正、背面间电性连接结构的制造方法包含下列步骤：
步骤1：提供一晶片10如图3A所示，该晶片10的正面11上设有多个晶垫(die pad)110及至少一作用区(active area)111；又各晶垫110可预设一化学镍金层(ENIG，electroless nickel/immersion gold)30如图3B所示。
步骤2：提供一软性电路板20如图3C所示，该软性电路板20具有一第一表面21及一第二表面22，该第一表面21上设有多个第一连接垫210供分别对应于该多个晶垫(die pad)110，该第二表面22上设有多个第二连接垫220供可凭借软性电路板20的电路而分别与第一表面21上各第一连接垫210对应连接，又该多个第二连接垫220用以与一配合使用的印刷电路板上所预设的连接电路的各外露接点对应连接；其中，该软性电路板20的第二表面22上可预贴一双面背胶层40如图3D所示。
步骤3：将该软性电路板20的第一表面21上所设各第一连接垫210对应电性连接在该晶片10的正面11上的各晶垫110或其化学镍金层(ENIG)30上如图3C、3D所示。
步骤4：如图3E所示，使该软性电路板20弯曲并绕过该晶片10一侧边缘以延伸至该晶片10的背面12上并粘着贴覆(如利用该粘胶层40)在该背面12上；如此，使该软性电路板20的第二表面22上所设各第二连接垫220能面向外(如图1中箭头A所示)，供可凭借后续作业以电性连接并安装在一相配合印刷电路板(图未示)上，以使该晶片10的正面11上所设的作用区111能配合该印刷电路板使用而达成该晶片10的使用功能如指纹辨识晶片的指纹辨识功能。
此外，如图4所示，该作用区111的表面上进一步设置一高透光度介质层50，用以保护该作用区111且不影响其使用功能；如图4所示，该高透光度介 质层50设置在该晶片10的正面11上，用以全面遮护该作用区111但露出各晶垫(die pad)110及/或各晶垫(die pad)110上所设的化学镍金层(ENIG)30。
此外，在图4中该感应作用区111上所设置的高透光度介质层50的高度进一步与该软性电路板20落在该晶片10的正面11上的高度(即图4、5中该软性电路板20的第二表面22的表面)齐平如图5所示，以使该晶片10的正面11形成同一平面，以符合该晶片10如指纹辨识晶片在实际应用上的组装需要。
以上说明对本发明而言只是说明性的，而非限制性的，本领域普通技术人员理解，在不脱离权利要求所限定的精神和范围的情况下，可作出许多修改、变化或等效，但都将落入本发明的保护范围之内。

Claims (8)

  1. 一种晶片的正、背面间电性连接结构，其特征在于，其包含：
    一晶片，其正面上设有多个晶垫及至少一作用区；以及
    一软性电路板，其具有一第一表面及一第二表面，该第一表面上设有多个第一连接垫供分别对应于该晶片正面所设的各晶垫，该第二表面上设有多个第二连接垫供分别与该第一表面上各第一连接垫对应连接，其中该多个第二连接垫用以与一相配合使用的印刷电路板上所预设的连接电线路的各外露接点对应连接，以使该晶片能凭借该软性电路板所设该多个第二连接垫而安装在该印刷电路板上并达成电性连接；
    其中该软性电路板由该晶片的正面弯曲并绕过该晶片一侧边缘而延伸至该晶片的背面并粘着贴覆在该背面上，以使晶片正面上所设各晶垫能凭借该软性电路板的电路连通而移位至晶片的背面并面向外以供电性连接并安装在该印刷电路板上。
  2. 如权利要求1所述的晶片的正、背面间电性连接结构，其特征在于：该晶片为一指纹辨识晶片且其正面上设有一指纹辨识感应作用区。
  3. 如权利要求1所述的晶片的正、背面间电性连接结构，其特征在于：该晶片的正面上所设各晶垫的表面上设有一化学镍金层。
  4. 如权利要求2所述的晶片的正、背面间电性连接结构，其特征在于：该软性电路板的第一表面上设有一粘胶层，以使该软性电路板由该晶片的正面弯曲并绕过该晶片一侧边缘而延伸至该晶片的背面时能凭借该粘胶层以粘着贴覆在该背面上。
  5. 如权利要求1所述的晶片的正、背面间电性连接结构，其特征在于：该晶片正面所设的作用区的上表面进一步设置一高透光度介质层。
  6. 如权利要求5所述的晶片的正、背面间电性连接结构，其特征在于：该高透光度介质层设置在该晶片的正面上并完全遮护该作用区但露出各晶垫。
  7. 如权利要求5所述的晶片的正、背面间电性连接结构，其特征在于：该作用区上所设置的高透光度介质层的高度进一步与该软性电路板落在该晶片的正面上的高度齐平，以使该晶片的正面形成同一平面。
  8. 一种晶片的正、背面间电性连接结构的制造方法，其特征在于，其包含下列步骤：
    步骤1：提供一晶片，该晶片的正面上设有多个晶垫及至少一作用区；
    步骤2：提供一软性电路板，该软性电路板具有一第一表面及一第二表面，该第一表面上设有多个第一连接垫供分别对应于该该晶片的正面上所设的各晶垫，该第二表面上设有多个第二连接垫供分别与第一表面上各第一连接垫对应连接，其中该多个第二连接垫用以与一配合使用的印刷电路板上所预设连接电路的各外露接点对应连接；
    步骤3：使该软性电路板的第一表面上所设各第一连接垫与该晶片的正面上所设的各晶垫上对应电性连接；
    步骤4：使该软性电路板弯曲并绕过该晶片一侧边缘以延伸至该晶片的背面上并粘着贴覆在该背面上，如此使该软性电路板的第二表面上所设的各第二连接垫能向外面对该印刷电路板。
PCT/CN2015/000492 2014-08-08 2015-07-07 晶片的正、背面间电性连接结构及其制造方法 WO2016019698A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410389808.3 2014-08-08
CN201410389808.3A CN105374792B (zh) 2014-08-08 2014-08-08 晶片的正、背面间电性连接结构及其制造方法

Publications (1)

Publication Number Publication Date
WO2016019698A1 true WO2016019698A1 (zh) 2016-02-11

Family

ID=55263091

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/000492 WO2016019698A1 (zh) 2014-08-08 2015-07-07 晶片的正、背面间电性连接结构及其制造方法

Country Status (2)

Country Link
CN (1) CN105374792B (zh)
WO (1) WO2016019698A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201066417Y (zh) * 2007-06-15 2008-05-28 群康科技(深圳)有限公司 触控式液晶显示装置
CN103198765A (zh) * 2013-01-25 2013-07-10 友达光电股份有限公司 面板模块
CN103972201A (zh) * 2013-01-30 2014-08-06 奇景光电股份有限公司 封装结构与显示模组
CN204067348U (zh) * 2014-08-08 2014-12-31 茂邦电子有限公司 晶片的正、背面间电性连接结构

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201066417Y (zh) * 2007-06-15 2008-05-28 群康科技(深圳)有限公司 触控式液晶显示装置
CN103198765A (zh) * 2013-01-25 2013-07-10 友达光电股份有限公司 面板模块
CN103972201A (zh) * 2013-01-30 2014-08-06 奇景光电股份有限公司 封装结构与显示模组
CN204067348U (zh) * 2014-08-08 2014-12-31 茂邦电子有限公司 晶片的正、背面间电性连接结构

Also Published As

Publication number Publication date
CN105374792A (zh) 2016-03-02
CN105374792B (zh) 2018-07-10

Similar Documents

Publication Publication Date Title
JP5258567B2 (ja) 半導体装置及びその製造方法
US9760754B2 (en) Printed circuit board assembly forming enhanced fingerprint module
JP2006060128A (ja) 半導体装置
TWI481001B (zh) 晶片封裝結構及其製造方法
JP2005072554A (ja) 半導体装置及びその製造方法
CN105867034B (zh) 硅基液晶面板及相关方法
US20080187191A1 (en) Flim type package for fingerprint sensor
CN107170769B (zh) 一种影像传感芯片的封装结构及其封装方法
US10121043B2 (en) Printed circuit board assembly with image sensor mounted thereon
TW200411892A (en) Semiconductor device and laminated semiconductor device
US20050280018A1 (en) Light-emitting diode
KR20130089473A (ko) 반도체 패키지
CN105097758B (zh) 衬底、其半导体封装及其制造方法
TWI625829B (zh) 晶片之正、背面間電性連接結構及其製造方法
KR20150129939A (ko) 반도체 패키지 및 그 제조 방법
CN106611752B (zh) 芯片正背面之间的电性连接结构及其制造方法
CN107437046B (zh) 指纹传感器封装结构及其制作方法
WO2016019698A1 (zh) 晶片的正、背面间电性连接结构及其制造方法
WO2017066896A1 (zh) 芯片正背面之间的电性连接结构及其制造方法
TWI588963B (zh) The positive and the back of the wafer are electrically connected and the manufacturing method thereof
TW200534407A (en) Sliding type thin fingerprint sensor package
JP2004288815A (ja) 半導体装置及びその製造方法
TWI625077B (zh) Chip package structure
CN103508407A (zh) 具微机电组件的封装结构及其制法
JP3973309B2 (ja) 半導体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15830536

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15830536

Country of ref document: EP

Kind code of ref document: A1