WO2016017884A1 - Dispositif électroluminescent et système d'éclairage - Google Patents

Dispositif électroluminescent et système d'éclairage Download PDF

Info

Publication number
WO2016017884A1
WO2016017884A1 PCT/KR2015/001518 KR2015001518W WO2016017884A1 WO 2016017884 A1 WO2016017884 A1 WO 2016017884A1 KR 2015001518 W KR2015001518 W KR 2015001518W WO 2016017884 A1 WO2016017884 A1 WO 2016017884A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor layer
concentration
pit
light emitting
layer
Prior art date
Application number
PCT/KR2015/001518
Other languages
English (en)
Korean (ko)
Inventor
백광선
백지현
황정현
한대섭
Original Assignee
엘지이노텍 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지이노텍 주식회사 filed Critical 엘지이노텍 주식회사
Publication of WO2016017884A1 publication Critical patent/WO2016017884A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers

Definitions

  • Embodiments relate to a light emitting device, a method of manufacturing the light emitting device, a light emitting device package and an illumination system.
  • a light emitting device is a p-n junction diode in which electrical energy is converted into light energy, and may be formed by combining elements of group III and group V on the periodic table. LED can realize various colors by adjusting the composition ratio of compound semiconductors.
  • the n-layer electrons and the p-layer holes combine to emit energy corresponding to the energy gap of the conduction band and the valence band. It is mainly emitted in the form of heat or light, and when it is emitted in the form of light, it becomes a light emitting device.
  • nitride semiconductors are receiving great attention in the field of optical devices and high power electronic devices due to their high thermal stability and wide bandgap energy.
  • blue light emitting devices, green light emitting devices, and ultraviolet light emitting devices using nitride semiconductors are commercially used and widely used.
  • the light emitting device has a lattice constant difference between a growth substrate, for example, a sapphire substrate and a GaN layer, which is a nitride semiconductor, and has a large potential in the crystal due to a difference in thermal expansion coefficient.
  • a growth substrate for example, a sapphire substrate
  • GaN layer which is a nitride semiconductor
  • the embodiment provides a light emitting device, a manufacturing method of a light emitting device, a light emitting device package, and an illumination system that can improve or prevent ESD and improve brightness.
  • the light emitting device may include a first conductivity type first semiconductor layer 112 having a first concentration; A first conductivity type second semiconductor layer 122 having a second concentration on the first semiconductor layer 112; A third semiconductor layer 123 including a pit P2 on the second semiconductor layer 122; An active layer 114 on the third semiconductor layer 123; And a second conductivity type semiconductor layer 116 on the active layer 114.
  • the light emitting device may include a first conductivity type first semiconductor layer 112 having a first concentration; A third semiconductor layer 123 including a pit P3 on the first semiconductor layer 112; A first conductivity type second semiconductor layer 122 having a second concentration on the third semiconductor layer 123; An active layer 114 on the second semiconductor layer 122; And a second conductivity type semiconductor layer 116 on the active layer 114.
  • the lighting system according to the embodiment may include a light emitting unit having the light emitting device.
  • the manufacturing method of the light emitting device, the light emitting device package and the lighting system according to the embodiment it is possible to improve the ESD resistance and to reduce or improve the brightness.
  • FIG. 1 is a cross-sectional view of a light emitting device according to the first embodiment.
  • FIG. 2 is a partially enlarged view of a light emitting device according to the prior art.
  • FIG. 3 is an enlarged first view of a light emitting device according to the first embodiment
  • Figure 4 is a ESD yield improvement comparison table of the light emitting device according to the embodiment.
  • FIG. 5 is an enlarged view of a second part of the light emitting device according to the first embodiment
  • FIG. 6 is a sectional view of a light emitting device according to a second embodiment
  • FIG. 7 is an enlarged third view of a light emitting device according to the second embodiment.
  • FIG. 8 is an enlarged view of a fourth portion of the light emitting device according to the second embodiment.
  • each layer, region, pattern, or structure is “on / over” or “under” the substrate, each layer, layer, pad, or pattern.
  • “on / over” and “under” include both “directly” or “indirectly” formed. do.
  • the criteria for the above / above or below of each layer will be described based on the drawings.
  • FIG. 1 is a cross-sectional view of a light emitting device 100 according to the first embodiment.
  • the light emitting device 100 includes a first conductivity type first semiconductor layer 112 having a first concentration, and a second conductivity type second semiconductor layer having a second concentration on the first semiconductor layer 112 ( 122, a third semiconductor layer 123 including a pit P2 on the second semiconductor layer 122, and an active layer 114 and the active layer 114 on the third semiconductor layer 123.
  • the second conductive semiconductor layer 116 may be included thereon.
  • the third semiconductor layer 123 may be a first conductivity type semiconductor layer.
  • the first concentration or the second concentration refers to the concentration of the first conductivity type element doped in the first semiconductor layer 112 or the second semiconductor layer 122.
  • the active layer 114 may include a plurality of active layers each having a quantum well and a quantum wall. For example, as shown in FIG. 3, the active layer 114 may include a first active layer 114a, a second active layer 114b, and a third active layer 114c, but is not limited thereto.
  • the light emitting device may be applied to a horizontal light emitting device.
  • an embodiment provides a light emitting structure 110 including a first conductivity type first semiconductor layer 112, an active layer 114, and a second conductivity type semiconductor layer 116 on a substrate 105. It may include.
  • An aluminum gallium-based nitride semiconductor layer 140 may be disposed between the active layer 114 and the second conductive semiconductor layer 116.
  • An embodiment may include a buffer layer 106 between the substrate 105 and the light emitting structure 110, and on the ohmic layer 142, ohmic layer 142 on the second conductive semiconductor layer 116.
  • the first electrode 151 may be included on the second electrode 152 and the exposed first semiconductor layer 112.
  • the embodiment is not only applicable to the horizontal light emitting device, but also to the vertical light emitting device.
  • FIG. 2 is a partially enlarged view of a light emitting device R according to the prior art.
  • the pit P1 is introduced on the first conductive semiconductor layer 12 to improve the ESD resistance, and the active layer 14 is formed on the first conductive semiconductor layer 12.
  • the structure of the 2nd conductivity type semiconductor layer 18 which fills (P1) is included.
  • the density of the pit P1 in order to improve ESD resistance, the density of the pit P1 must be secured, and the size S1 of the pit P1 must be 120 nm or more to secure the density of the pit P1.
  • the size S1 of the pit P1 may mean the maximum horizontal width of the pit P1.
  • the first thickness t1 of the active layer 14 formed in the pit P1 is lower than that of the active layer 14 formed in the region other than the pit P1. It is formed smaller than the second thickness t2.
  • the pit P1 size S1 should exceed about 120 nm in order to improve ESD resistance, and this pit P1 size limitation is a technical contradiction which causes a substantial reduction of the emission area A1. There is this.
  • the embodiment is to provide a light emitting device that can improve the ESD resistance and at the same time does not reduce or improve the brightness.
  • the light emitting device includes a first conductivity type second semiconductor layer 122 having a second concentration and a first conductivity type first semiconductor layer 112 having a first concentration.
  • An organic coupling relationship between the third semiconductor layer 123 including the pit P2 on the second semiconductor layer 122 and the active layer 114 may be included on the third semiconductor layer 123.
  • the active layer 114 may include a plurality of active layers, for example, a first active layer 114a, a second active layer 114b, and a third active layer 114c.
  • Each of the first active layer 114a, the second active layer 114b, and the third active layer 114c may include a quantum well (not shown) and a quantum wall (not shown), respectively.
  • the third semiconductor layer 123 may include a pit P2 recessed from an upper surface thereof. Accordingly, the pits P2 may be formed in the first active layer 114a, the second active layer 114b, and the third active layer 114c formed on the third semiconductor layer 123.
  • Side cross-sections of the pits P2 may be formed in a V shape, and a planar shape may be formed in a hexagonal shape.
  • the pit P may be formed in a hexagonal horn pillar shape, but is not limited thereto.
  • One or a plurality of potentials (not shown) to be propagated may be connected to each pit P2.
  • pits P2 may be formed.
  • the pits P2 may be formed when the third semiconductor layer 123 is formed to a predetermined thickness and then grown using a mask pattern.
  • the third semiconductor layer 123 may have a thickness greater than the depth of the pit P2.
  • the pit P2 which reduces the light emitting area is minimized to maintain the brightness and at the same time to enhance the ESD resistance, the second under the third semiconductor layer 123 including the pit P2.
  • the ESD resistance may be improved by increasing the pit density and the internal capacitance of the pit P2.
  • the first conductivity type second semiconductor layer 122 having the third concentration or the second concentration having the higher doping concentration is disposed below the third semiconductor layer 123 having the third concentration, and the first conductivity type second is formed. Since the first conductivity-type second concentration of the semiconductor layer 122 is higher than the third concentration of the third semiconductor layer 123, the pit P2 of the third semiconductor layer 123 may be formed due to the implantation of impurities at a high concentration. The density increases, and the increase in the density of the pits P2 leads to an increase in internal capacitance, and as the internal capacitance increases, the ESD resistance may improve.
  • the size S2 of the pit P2 formed in the third semiconductor layer 123 may be about 100 nm or less, for example, about 50 nm to about 100 nm. According to the exemplary embodiment, as the size S2 of the pit P2 formed in the third semiconductor layer 123 is formed in a range of about 50 nm to 100 nm, the size S2 of the pit P2 is minimized and optimized to substantially emit light.
  • the high quality active layer region A2 that contributes to can be significantly increased.
  • any one of the active layers 114 formed in the pit P2 for example, the third thickness t3 of the third active layer 114c may be formed in the region other than the pit P2. It is formed smaller than the fourth thickness t4, and the high quality active layer region A2 having the fourth thickness t4 can be significantly increased compared to the prior art.
  • the first conductivity type second semiconductor layer 122 of the second concentration is doped at a higher concentration than the first conductivity type first semiconductor layer 112 of the first concentration, so that the density of the pit P2 is increased to prevent ESD.
  • the electron injection efficiency can be increased to increase the internal light emitting efficiency.
  • the second concentration of the first conductivity type element of the second semiconductor layer 122 may range from about 7 ⁇ 10 ⁇ 18 to 9 ⁇ 10 ⁇ 18 (atoms / cm 3 ).
  • the second concentration of the second semiconductor layer 122 is less than 7 ⁇ 10 ⁇ 18, the amount of the dopant may be small, which may result in insufficient contribution to the improvement of the ESD resistance, and the second concentration of the second semiconductor layer 122 may be 9 ⁇ . If it exceeds 10 -18 , it may cause the overflow of electrons and lower the overall brightness.
  • the second semiconductor layer 122 may include an n-type GaN semiconductor layer having a second concentration
  • the third semiconductor layer 123 may include an n-type GaN semiconductor layer having a third concentration.
  • the third concentration of the third semiconductor layer 123 may be lower than the second concentration of the second semiconductor layer 122.
  • a pit is formed in an InGaN / GaN structure, and a large crystal structure of In is introduced into the GaN semiconductor layer, thereby causing lattice bonding.
  • lattice defects are caused by forming a pit in the GaN semiconductor layer.
  • FIG. 4 is an ESD yield improvement comparison table of the light emitting device according to the embodiment.
  • Including the organic bonding of the active layer 114 in the ESD yield was significantly increased to 80.3% compared to 52.7% of the comparative example.
  • the light emitting device of the embodiment has the advantage that the ESD yield is improved and the high quality active layer region is increased, so that the low current characteristic (Vf) is excellent.
  • FIG. 5 is an enlarged view of a second portion E2 of the light emitting device of the modified embodiment of the first embodiment.
  • the second semiconductor layer 122a having the second concentration is formed in a region overlapping the pit P2, thereby minimizing and optimizing the size S2 of the pit P2, thereby providing an ESD yield. This improvement and luminous efficiency can be increased.
  • the second semiconductor layer 122a having the second concentration may be formed to have a size greater than or equal to the size S2 of the pit P2. That is, the width of the second semiconductor layer 122a may be equal to or greater than the width of the pit P2.
  • the ESD resistance can be improved by increasing the pit P2 density.
  • FIG. 6 is a cross-sectional view of the light emitting device 102 according to the second embodiment
  • FIG. 7 is an enlarged view of a third portion E3 of the light emitting device according to the second embodiment.
  • the light emitting device 102 includes a first conductive type first semiconductor layer 112 having a first concentration and a third semiconductor layer including pits P3 on the first semiconductor layer 112. 123, a first conductivity type second semiconductor layer 122 having a second concentration on the third semiconductor layer 123, and an active layer 114 and the active layer (on the second semiconductor layer 122).
  • the second conductive semiconductor layer 116 may be included on the 114.
  • the second embodiment can employ the technical features of the first embodiment.
  • the light emitting device 102 includes a third semiconductor layer 123 including a pit P3 and a first conductivity having a second concentration on the third semiconductor layer 123.
  • An organic coupling relationship between the type second semiconductor layer 122 and the active layer 114 may be formed on the second semiconductor layer 122.
  • the third semiconductor layer 123 may include a plurality of pits P3 recessed from an upper surface thereof.
  • a first pit forming layer 123a and a second pit forming layer 123b may be included on the third semiconductor layer 123, and the first pit forming layer 123a and the second pit forming layer 123b may be included.
  • a plurality of pits P3 may be formed in the.
  • the first pit forming layer 123a and the second pit forming layer 123b may be formed of the same material as that of the third semiconductor layer 123, and may be formed by growing at a temperature lower than that of the third semiconductor layer 123. (P3) can be formed.
  • the upper portion of the third semiconductor layer 123 including the pit P3 to maintain the brightness while minimizing the pit P3 size S2 that reduces the light emitting area and at the same time enhances the ESD resistance.
  • the ESD resistance may be improved by increasing the density and the internal capacitance of the pit P3.
  • the pit P3 is formed on the active layer 114 by arranging the first conductivity type second semiconductor layer 122 having the second concentration on the third semiconductor layer 123 including the pit P3.
  • the area of the high quality active layer 114 contributing to light emission can be maximized.
  • the active layer 114 is illustrated as if there is no pit P3, but a pit smaller than the pit P3 formed in the third semiconductor layer may be provided.
  • the first conductivity type second semiconductor layer 122 of the second concentration is doped at a higher concentration than the first conductivity type first semiconductor layer 112 of the first concentration, thereby improving ESD resistance and injecting electrons.
  • the internal luminous efficiency can be increased by increasing the efficiency.
  • the second semiconductor layer 122 may include an n-type GaN semiconductor layer having a second concentration
  • the third semiconductor layer 123 having the pits P3 may be an n-type GaN semiconductor layer having a third concentration. It may include.
  • the third concentration of the third semiconductor layer 123 may be lower than the second concentration of the second semiconductor layer 122.
  • FIG 8 is an enlarged view of a fourth portion E4 of the light emitting device 102 according to the second embodiment.
  • the second semiconductor layer 122 in the second embodiment may include a n-GaN 122a / u-GaN1 122b superlattice structure having a second concentration.
  • the second semiconductor layer 122 may include a superlattice structure of an n-type GaN semiconductor layer (n-GaN) 122a and an undoped GaN semiconductor layer (u-GaN1 122b) having a second concentration. Can be.
  • the manufacturing method of the light emitting device, the light emitting device package and the lighting system according to the embodiment it is possible to improve the ESD resistance and to reduce or improve the brightness.
  • the substrate 105 is prepared as shown in FIG. 9.
  • the substrate 105 may be formed of a material having excellent thermal conductivity, and may be a conductive substrate or an insulating substrate.
  • the substrate 105 may use at least one of sapphire (Al 2 O 3 ), SiC, Si, GaAs, GaN, ZnO, GaP, InP, Ge, and Ga 2 0 3 .
  • An uneven structure may be formed on the substrate 105, but is not limited thereto.
  • a buffer layer 106 may be formed on the substrate 105.
  • the buffer layer 106 may mitigate lattice mismatch between the material of the light emitting structure 110 and the substrate 105 to be formed later, and the material of the buffer layer may be a Group III-V compound semiconductor such as GaN, InN, AlN, It may be formed of at least one of InGaN, AlGaN, InAlGaN, AlInN.
  • a first conductivity type first semiconductor layer 112 having a first concentration may be formed on the substrate 105 or the buffer layer 106.
  • the first conductivity type first semiconductor layer 112 may be formed of a semiconductor compound. It may be implemented as a compound semiconductor, such as Group 3-5, Group 2-6, and the first conductivity type dopant may be doped. When the first conductivity type first semiconductor layer 112 is an n-type semiconductor layer, the first conductive dopant is an n-type dopant and may include Si, Ge, Sn, Se, Te, but is not limited thereto. .
  • the first conductivity type first semiconductor layer 112 may include a semiconductor material having a composition formula of In x Al y Ga 1-xy N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1). It may include.
  • the first conductivity type first semiconductor layer 112 may be formed of any one or more of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP, InP. have.
  • the first conductive second semiconductor layer 122 having the second concentration and the second semiconductor layer 122 having the second concentration are formed on the first conductive first semiconductor layer 112 having the first concentration.
  • the third semiconductor layer 123 including the pits P2 and the active layer 114 may be formed on the third semiconductor layer 123.
  • the active layer 114 may be formed of at least one of a single quantum well structure, a multi quantum well structure (MQW), a quantum-wire structure, or a quantum dot structure.
  • the active layer 114 may be formed by injecting trimethyl gallium gas (TMGa), ammonia gas (NH 3 ), nitrogen gas (N 2 ), and trimethyl indium gas (TMIn) to form a multi-quantum well structure. It is not limited to this.
  • the quantum wells / barrier barriers of the active layer 114 are at least one pair of InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InGaN / AlGaN, InAlGaN / GaN, GaAs (InGaAs) / AlGaAs, GaP (InGaP) / AlGaP. It may be formed as a structure, but is not limited thereto.
  • the active layer 114 may include a plurality of active layers, for example, a first active layer 114a, a second active layer 114b, and a third active layer 114c.
  • Each of the first active layer 114a, the second active layer 114b, and the third active layer 114c may include a quantum well (not shown) and a quantum wall (not shown), respectively.
  • the third semiconductor layer 123 may include a pit P2 recessed from an upper surface thereof. Accordingly, the pits P2 may be formed in the first active layer 114a, the second active layer 114b, and the third active layer 114c formed on the third semiconductor layer 123.
  • Side cross-sections of the pits P2 may be formed in a V shape, and a planar shape may be formed in a hexagonal shape.
  • the pit P may be formed in a hexagonal horn pillar shape, but is not limited thereto.
  • One or a plurality of potentials (not shown) to be propagated may be connected to each pit P2.
  • the pits P2 having a V shape may be formed.
  • V-shaped pits P2 may be formed.
  • the third semiconductor layer 123 may have a thickness greater than the depth of the pit P2.
  • the second semiconductor layer 122 may be formed of an n-type GaN semiconductor layer having a second concentration ranging from about 7 ⁇ 10 ⁇ 18 to 9 ⁇ 10 ⁇ 18 (atoms / cm 3 ).
  • the second concentration of the second semiconductor layer 122 is less than 7 ⁇ 10 ⁇ 18, the amount of the dopant may be small, which may result in insufficient contribution to the improvement of the ESD resistance, and the second concentration of the second semiconductor layer 122 may be 9 ⁇ . If it exceeds 10 -18 , it may cause the overflow of electrons and lower the overall brightness.
  • the first conductivity type second semiconductor layer 122 of the second concentration is doped at a higher concentration than the first conductivity type first semiconductor layer 112 of the first concentration, thereby increasing the density of the pit P2.
  • the electron injection efficiency can be increased to increase the internal light emitting efficiency.
  • the size S2 of the pit P2 formed in the third semiconductor layer 123 may be about 100 nm or less, for example, about 50 nm to about 100 nm. According to the exemplary embodiment, as the size S2 of the pit P2 formed in the third semiconductor layer 123 is formed in a range of about 50 nm to 100 nm, the size S2 of the pit P2 is minimized and optimized to substantially emit light.
  • the high quality active layer region A2 that contributes to can be significantly increased.
  • the ESD resistance may be improved by increasing the density and internal capacitance of the pit P2.
  • the second semiconductor layer 122 may include an n-type GaN semiconductor layer having a second concentration
  • the third semiconductor layer 123 may include an n-type GaN semiconductor layer having a third concentration.
  • the third concentration of the third semiconductor layer 123 may be lower than the second concentration of the second semiconductor layer 122.
  • a pit is formed in an InGaN / GaN structure, and a large crystal structure of In is introduced into the GaN semiconductor layer, thereby causing lattice bonding.
  • lattice defects are caused by forming a pit in the GaN semiconductor layer.
  • the second semiconductor layer 122a having the second concentration is formed in an area overlapping the pit P2, thereby minimizing and optimizing the size S2 of the pit P2. Therefore, the ESD yield can be improved and the luminous efficiency can be increased.
  • the second semiconductor layer 122a having the second concentration may be formed to have a size greater than or equal to the size S2 of the pit P2.
  • the light emitting device 102 includes a third semiconductor layer 123 including a pit P3 and a second concentration on the third semiconductor layer 123.
  • the first conductive type second semiconductor layer 122 and the second semiconductor layer 122 may include an organic coupling relationship between the active layer 114.
  • the upper portion of the third semiconductor layer 123 including the pit P3 to maintain the brightness while minimizing the pit P3 size S2 that reduces the light emitting area and at the same time enhances the ESD resistance.
  • the ESD resistance may be improved by increasing the pit density and internal capacitance of the pit P2.
  • the pit P3 is formed on the active layer 114 by arranging the first conductivity type second semiconductor layer 122 having the second concentration on the third semiconductor layer 123 including the pit P3.
  • the area of the high quality active layer 114 contributing to light emission can be maximized.
  • the second semiconductor layer 122 in the second embodiment may include a n-GaN 122a / u-GaN1 122b superlattice structure having a second concentration.
  • the second semiconductor layer 122 may include a superlattice structure of an n-type GaN semiconductor layer (n-GaN) 122a and an undoped GaN semiconductor layer (u-GaN1 122b) having a second concentration. Can be.
  • an aluminum gallium-based nitride semiconductor layer 140 is formed on the active layer 114 to improve luminous efficiency by acting as electron blocking and cladding of the active layer. Can be.
  • the aluminum gallium-based nitride semiconductor layer 140 may be formed of Al x In y Ga (1-xy) N (0 ⁇ x ⁇ 1,0 ⁇ y ⁇ 1) based semiconductor, and the active layer ( It may have a higher energy band gap than the energy band gap of 114).
  • the second conductivity-type semiconductor layer 116 may be formed of a semiconductor compound on the aluminum gallium-based nitride semiconductor layer 140.
  • the second conductivity type semiconductor layer 116 may include a semiconductor material having a composition formula of In x Al y Ga 1-xy N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1). Can be.
  • the second conductive semiconductor layer 116 is a p-type semiconductor layer
  • the second conductive dopant may be a p-type dopant and may include Mg, Zn, Ca, Sr, and Ba.
  • the first conductivity type first semiconductor layer 112 may be an n-type semiconductor layer
  • the second conductivity type semiconductor layer 116 may be a p-type semiconductor layer, but is not limited thereto.
  • the light emitting structure 110 may be implemented as any one of an n-p junction structure, a p-n junction structure, an n-p-n junction structure, and a p-n-p junction structure.
  • an ohmic layer 142 is formed on the second conductivity type semiconductor layer 116.
  • the ohmic layer 142 may be formed by stacking a single metal, a metal alloy, a metal oxide, or the like in multiple layers so as to efficiently inject holes.
  • the ohmic layer 142 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), or IGTO.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • IZTO indium zinc tin oxide
  • IAZO indium aluminum zinc oxide
  • IGZO indium gallium zinc oxide
  • IGTO indium gallium zinc oxide
  • the ohmic layer 142, the second conductivity-type semiconductor layer 116, and the aluminum gallium-based nitride semiconductor have a exposed region H through which the first conductivity-type first semiconductor layer 112 is exposed.
  • a portion of the layer 140, the active layer 114, the third semiconductor layer 123, and the second semiconductor layer 122 may be removed.
  • the second electrode 152 is formed on the ohmic layer 142 and the first electrode 151 is formed on the exposed first conductive type first semiconductor layer 112. According to the light emitting device can be formed.
  • the manufacturing method of the light emitting device, the light emitting device package and the lighting system according to the embodiment it is possible to improve the ESD resistance and to reduce or improve the brightness.
  • a plurality of light emitting devices may be arranged on a substrate in the form of a package, and a light guide plate, a prism sheet, a diffusion sheet, a fluorescent sheet, or the like, which is an optical member, may be disposed on a path of light emitted from the light emitting device package.
  • the light emitting device may be applied to a backlight unit, a lighting unit, a display device, an indicator device, a lamp, a street lamp, a vehicle lighting device, a vehicle display device, a smart watch, but is not limited thereto.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

Des exemples se rapportent à un dispositif électroluminescent, à un procédé de fabrication d'un dispositif électroluminescent, à un boîtier de dispositif électroluminescent, et à un système d'éclairage. Le dispositif électroluminescent selon les exemples peut comprendre : une première couche semiconductrice d'un premier type de conductivité d'une première concentration; une deuxième couche semiconductrice d'un premier type de conductivité d'une seconde concentration sur la première couche semiconductrice; une troisième couche semiconductrice sur la deuxième couche semiconductrice, la troisième couche semiconductrice comprenant des creux; une couche active sur la troisième couche semiconductrice; et une couche semiconductrice d'un second type de conductivité sur la couche active.
PCT/KR2015/001518 2014-07-31 2015-02-16 Dispositif électroluminescent et système d'éclairage WO2016017884A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020140098438A KR102315594B1 (ko) 2014-07-31 2014-07-31 발광소자 및 조명시스템
KR10-2014-0098438 2014-07-31

Publications (1)

Publication Number Publication Date
WO2016017884A1 true WO2016017884A1 (fr) 2016-02-04

Family

ID=55217754

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2015/001518 WO2016017884A1 (fr) 2014-07-31 2015-02-16 Dispositif électroluminescent et système d'éclairage

Country Status (2)

Country Link
KR (1) KR102315594B1 (fr)
WO (1) WO2016017884A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102606859B1 (ko) * 2017-01-05 2023-11-27 쑤저우 레킨 세미컨덕터 컴퍼니 리미티드 반도체 소자 및 이를 포함하는 반도체 소자 패키지

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011061011A (ja) * 2009-09-10 2011-03-24 Sony Corp 半導体発光素子及びその製造方法、画像表示装置、並びに、電子機器
KR20110049520A (ko) * 2009-11-05 2011-05-12 삼성엘이디 주식회사 반도체 발광소자 및 이를 제조하는 방법
JP2013157648A (ja) * 2006-01-12 2013-08-15 Mitsubishi Chemicals Corp ＧａＮ系発光素子およびその製造方法
JP2013183126A (ja) * 2012-03-05 2013-09-12 Sharp Corp 窒化物半導体発光素子および窒化物半導体発光素子の製造方法
US20140106493A1 (en) * 2011-09-29 2014-04-17 Toshiba Techno Center Inc. P-type doping layers for use with light emitting devices

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5853921B2 (ja) * 2012-09-26 2016-02-09 豊田合成株式会社 Ｉｉｉ族窒化物半導体発光素子およびその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013157648A (ja) * 2006-01-12 2013-08-15 Mitsubishi Chemicals Corp ＧａＮ系発光素子およびその製造方法
JP2011061011A (ja) * 2009-09-10 2011-03-24 Sony Corp 半導体発光素子及びその製造方法、画像表示装置、並びに、電子機器
KR20110049520A (ko) * 2009-11-05 2011-05-12 삼성엘이디 주식회사 반도체 발광소자 및 이를 제조하는 방법
US20140106493A1 (en) * 2011-09-29 2014-04-17 Toshiba Techno Center Inc. P-type doping layers for use with light emitting devices
JP2013183126A (ja) * 2012-03-05 2013-09-12 Sharp Corp 窒化物半導体発光素子および窒化物半導体発光素子の製造方法

Also Published As

Publication number Publication date
KR102315594B1 (ko) 2021-10-21
KR20160015761A (ko) 2016-02-15

Similar Documents

Publication Publication Date Title
WO2013018937A1 (fr) Dispositif électroluminescent à semi-conducteurs
WO2011083940A2 (fr) Diode électroluminescente et son procédé de fabrication
KR20090002214A (ko) 반도체 발광소자 및 그 제조방법
WO2014065571A1 (fr) Dispositif émettant de la lumière
KR101393897B1 (ko) 반도체 발광소자 및 그 제조방법
WO2014058224A1 (fr) Dispositif émetteur de lumière
WO2013015472A1 (fr) Dispositif électroluminescent à semi-conducteurs et son procédé de fabrication
WO2009126010A2 (fr) Dispositif électroluminescent
KR20070091500A (ko) 질화물 반도체 발광소자 및 그 제조방법
WO2017052344A1 (fr) Élément électroluminescent, boîtier d'élément électroluminescent et dispositif électroluminescent
WO2016018010A1 (fr) Dispositif électroluminescent et système d'éclairage
WO2016104958A1 (fr) Diode électroluminescente rouge et dispositif d'éclairage
WO2017116048A1 (fr) Élément électroluminescent et boîtier d'élément électroluminescent comprenant ce dernier
KR20160013552A (ko) 발광소자 및 조명시스템
KR20120100056A (ko) 발광 소자
WO2016072661A1 (fr) Élément électroluminescent ultraviolet et système d'éclairage
WO2016108423A1 (fr) Dispositif électroluminescent
WO2017135644A1 (fr) Dispositif électroluminescent ultraviolet et système d'éclairage
WO2016017884A1 (fr) Dispositif électroluminescent et système d'éclairage
WO2017018767A1 (fr) Diode électroluminescente ultraviolette et boîtier de diode électroluminescente
WO2016195342A1 (fr) Dispositif émetteur de lumière ultraviolette
WO2016133310A1 (fr) Dispositif électroluminescent et système d'éclairage le comprenant
KR101377969B1 (ko) 자외선 발광 질화물계 반도체 발광 소자
KR101876576B1 (ko) 질화물 반도체 발광소자 및 그 제조방법
WO2016163595A1 (fr) Dispositif électroluminescent à semi-conducteur au nitrure et son procédé de fabrication

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15827841

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15827841

Country of ref document: EP

Kind code of ref document: A1