WO2016000293A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2016000293A1
WO2016000293A1 PCT/CN2014/083859 CN2014083859W WO2016000293A1 WO 2016000293 A1 WO2016000293 A1 WO 2016000293A1 CN 2014083859 W CN2014083859 W CN 2014083859W WO 2016000293 A1 WO2016000293 A1 WO 2016000293A1
Authority
WO
WIPO (PCT)
Prior art keywords
scan line
charge
line
pixel row
charge sharing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2014/083859
Other languages
English (en)
French (fr)
Inventor
王醉
郭晋波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/404,133 priority Critical patent/US9640562B2/en
Priority to GB1700646.1A priority patent/GB2542993B/en
Priority to JP2016574419A priority patent/JP6408034B2/ja
Priority to KR1020167036704A priority patent/KR101907080B1/ko
Priority to EA201692492A priority patent/EA032445B1/ru
Publication of WO2016000293A1 publication Critical patent/WO2016000293A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136263—Line defects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/0421—Structural details of the set of electrodes
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
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    • G—PHYSICS
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    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
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    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
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    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display panel.
  • a shorting bar/short bar is usually designed on the outer side of the pixel area (Shorting) Bar) peripheral traces, and the scan lines are respectively extracted to the peripheral traces according to an odd number (ODD) and an even number (EVEN), that is, the odd and even scan lines on the entire display panel are respectively short on the periphery of the display panel Connected together.
  • This design is for TFT (Thin Film In the detection process of the Transistor (Thin Film Transistor) process, it is possible to check whether there is a short circuit or an open circuit in the display panel by giving different electrical signals of the odd and even scan lines, and other types of data can be checked with different data signals. bad.
  • the shorting bar is also used in the lighting detection process in the cell process and is disconnected or removed after the test so that it does not affect the normal display of the finished product.
  • a display panel includes: a display area, wherein the display area is provided with at least two array units, at least two of the array units are arranged in an array in a first direction, and the array unit comprises And at least one first pixel row, at least one first charge scan line, and at least one first charge share scan line, wherein the first charge scan line and the first charge share scan line are both the first pixel a row connection; at least one second pixel row, at least one second charge scan line, at least one second charge share scan line, wherein the second charge scan line and the second charge share scan line are both Two pixel row connections; at least one third pixel row, at least one third charge scan line, at least one third charge share scan line, wherein the third charge scan line and the third charge share scan line are both a third pixel row connection; at least a fourth pixel row, at least one fourth charge scan line, and at least a fourth charge share scan line, wherein the fourth charge scan line and the fourth charge are common Each of the scan lines is connected to the fourth pixel row;
  • the first predetermined value is 2 and the second predetermined value is 3.
  • the first charge sharing scan line is connected to the third charge scan line; the second charge share scan line is connected to the fourth charge scan line; and the third charge share scan line Connected to the fifth charge scan line; the fourth charge share scan line is connected to the sixth charge scan line; the fifth charge share scan line and another array adjacent in the first direction a first charge scan line connection in the cell; the sixth charge share scan line is coupled to a second charge scan line in the other array cell adjacent in the first direction.
  • the first charging scan line is connected to a fifth charge sharing scan line in another array unit adjacent in a reverse direction of the first direction; the second charging scan line is A sixth charge sharing scan line connection in another array unit adjacent in the reverse direction of the first direction.
  • the first detection line is connected to the first charge share scan line and the fourth charge share scan line; the second detection line and the third charge share scan line and the a sixth charge sharing scan line connection; the third sense line being coupled to the second charge share scan line and the fifth charge share scan line.
  • the first predetermined value is 4 and the second predetermined value is 3.
  • the first charge sharing scan line is connected to the fifth charge scan line; the second charge share scan line is connected to the sixth charge scan line; and the third charge share scan line Connecting with a first charging scan line in another array unit adjacent in the first direction; the fourth charge sharing scan line and the other array adjacent in the first direction a second charge scan line connection in the cell; the fifth charge share scan line is connected to a third charge scan line in the other array unit adjacent in the first direction; the sixth charge share A scan line is coupled to a fourth charge scan line of the other array unit adjacent in the first direction.
  • the first charging scan line is connected to a third charge sharing scan line in another array unit adjacent in a reverse direction of the first direction;
  • the second charging scan line is a fourth charge sharing scan line connection in another array unit adjacent in a reverse direction of the first direction;
  • the third charge scan line being another array unit adjacent in a reverse direction of the first direction And a fifth charge sharing scan line connection;
  • the fourth charge scan line is connected to a sixth charge share scan line in another array unit adjacent in a reverse direction of the first direction.
  • the first detection line is connected to the second charge sharing scan line and the fifth charge sharing scan line; the second detection line is shared with the first charge sharing scan line and a fourth charge sharing scan line connection; the third sense line being coupled to the third charge share scan line and the sixth charge share scan line.
  • a display panel includes: a display area, wherein the display area is provided with at least two array units, at least two of the array units are arranged in an array in a first direction, and the array unit comprises And at least one first pixel row, at least one first charge scan line, and at least one first charge share scan line, wherein the first charge scan line and the first charge share scan line are both the first pixel a row connection; at least one second pixel row, at least one second charge scan line, at least one second charge share scan line, wherein the second charge scan line and the second charge share scan line are both Two pixel row connections; at least one third pixel row, at least one third charge scan line, at least one third charge share scan line, wherein the third charge scan line and the third charge share scan line are both a third pixel row connection; at least a fourth pixel row, at least one fourth charge scan line, and at least a fourth charge share scan line, wherein the fourth charge scan line and the fourth charge are common Each of the scan lines is connected to the fourth pixel row;
  • the first charging scan line, the second charging scan line, the third charging scan line, the fourth charging scan line, the fifth charging scan line, and the sixth One of the charging scan lines is connected to the charge sharing scan line corresponding to the first number; any one of the first detection line, the second detection line, and the third detection line and the corresponding second number a charge-sharing scan line connection; wherein the first number is equal to a sum of a number corresponding to the pixel row and a first predetermined value, the first predetermined value being an even number greater than or equal to 2; The sum of the number corresponding to the pixel row and the second predetermined value, the second predetermined value being an odd number greater than or equal to 3.
  • the first predetermined value is 2 and the second predetermined value is 3.
  • the first charge sharing scan line is connected to the third charge scan line; the second charge share scan line is connected to the fourth charge scan line; and the third charge share scan line Connected to the fifth charge scan line; the fourth charge share scan line is connected to the sixth charge scan line; the fifth charge share scan line and another array adjacent in the first direction a first charge scan line connection in the cell; the sixth charge share scan line is coupled to a second charge scan line in the other array cell adjacent in the first direction.
  • the first charging scan line is connected to a fifth charge sharing scan line in another array unit adjacent in a reverse direction of the first direction; the second charging scan line is A sixth charge sharing scan line connection in another array unit adjacent in the reverse direction of the first direction.
  • the first detection line is connected to the first charge share scan line and the fourth charge share scan line; the second detection line and the third charge share scan line and the a sixth charge sharing scan line connection; the third sense line being coupled to the second charge share scan line and the fifth charge share scan line.
  • the first predetermined value is 4 and the second predetermined value is 3.
  • the first charge sharing scan line is connected to the fifth charge scan line; the second charge share scan line is connected to the sixth charge scan line; and the third charge share scan line Connecting with a first charging scan line in another array unit adjacent in the first direction; the fourth charge sharing scan line and the other array adjacent in the first direction a second charge scan line connection in the cell; the fifth charge share scan line is connected to a third charge scan line in the other array unit adjacent in the first direction; the sixth charge share A scan line is coupled to a fourth charge scan line of the other array unit adjacent in the first direction.
  • the first charging scan line is connected to a third charge sharing scan line in another array unit adjacent in a reverse direction of the first direction;
  • the second charging scan line is a fourth charge sharing scan line connection in another array unit adjacent in a reverse direction of the first direction;
  • the third charge scan line being another array unit adjacent in a reverse direction of the first direction And a fifth charge sharing scan line connection;
  • the fourth charge scan line is connected to a sixth charge share scan line in another array unit adjacent in a reverse direction of the first direction.
  • the first detection line is connected to the second charge sharing scan line and the fifth charge sharing scan line; the second detection line is shared with the first charge sharing scan line and a fourth charge sharing scan line connection; the third sense line being coupled to the third charge share scan line and the sixth charge share scan line.
  • At least one of the first detection lines, at least one of the second detection lines, and at least one of the third detection lines in the non-display area constitute a shorting bar, where the shorting bar is located
  • the linear direction is parallel to the first direction.
  • the short circuit phenomenon when the short circuit phenomenon occurs between the charging scan line and the charge sharing scan line corresponding to the same pixel row, the short circuit phenomenon can be detected in the TFT process stage of the display panel, which is beneficial to improve The detection efficiency and the detection accuracy of the short circuit phenomenon of the display panel are also beneficial to improving the yield of the display panel and reducing the manufacturing cost of the display panel.
  • FIG. 1 is a schematic view of a conventional display panel
  • FIG. 2 is a schematic view of a first embodiment of a display panel of the present invention
  • FIG 3 is a schematic view of a second embodiment of a display panel of the present invention.
  • FIG. 2 is a schematic view of a first embodiment of a display panel of the present invention.
  • the display panel of this embodiment may be an LCD (Liquid Crystal) Displays such as Display, Liquid Crystal Display, OLED (Organic Light Emitting Diode).
  • LCD Liquid Crystal
  • OLED Organic Light Emitting Diode
  • the display panel of this embodiment includes a display area (Active The area 201 and the at least one non-display area 202 are disposed on one side of the display area 201.
  • the two non-display areas 202 are respectively disposed on two sides of the display area 201.
  • a pixel array is disposed on the display panel, and the pixel array is located on the display area 201, and the pixel array is composed of pixels.
  • At least two array units (2011, 2012) are disposed on the display area 201, and at least two of the array units (2011, 2012) are arranged in an array in the first direction 203.
  • the array unit 2011 includes: at least one first pixel row P (N-3), at least one first charging (Charging) scan line (Scan) Line) C(N-3), at least one first charge sharing scan line.
  • the first charging scan line C(N-3) and the first charge sharing scan line S(N-3) are both connected to the first pixel row P(N-3).
  • the first pixel row P(N-3) includes at least one first pixel, and the first pixel includes a first main pixel portion (Main Pixel) and the first pixel part (Sub Pixel).
  • the first charge scan line C(N-3) is connected to one of the first main pixel portion and the first sub-pixel portion, and the first charge share scan line S(N-3) is The other of the first main pixel portion and the first sub-pixel portion is connected.
  • N is a positive integer.
  • the array unit 2011 further includes at least one second pixel row P(N-2), at least one second charging scan line C(N-2), and at least one second charge sharing scan line S(N-2).
  • the second charge scan line C(N-2) and the second charge share scan line S(N-2) are both connected to the second pixel row P(N-2).
  • the second pixel row P(N-2) includes at least one second pixel, and the second pixel includes a second main pixel portion and a second sub-pixel portion.
  • the second charge scan line C(N-2) is connected to one of the second main pixel portion and the second sub-pixel portion, and the second charge share scan line S(N-2) is The other of the second main pixel portion and the second sub-pixel portion is connected.
  • the second charge scan line C(N-2) is connected to the second main pixel portion, and the second charge share scan line S(N-2) is connected to the second sub-pixel portion, or
  • the second charge scan line C(N-2) is connected to the second sub-pixel portion, and the second charge share scan line S(N-2) is connected to the second main pixel portion.
  • the array unit 2011 further includes at least one third pixel row P(N-1), at least one third charging scan line C(N-1), and at least one third charge sharing scan line S(N-1).
  • the third charging scan line C(N-1) and the third charge sharing scan line S(N-1) are both connected to the third pixel row P(N-1).
  • the third pixel row P(N-1) includes at least one third pixel, and the third pixel includes a third main pixel portion and a third sub-pixel portion.
  • the third charge scan line C(N-1) is connected to one of the third main pixel portion and the third sub-pixel portion, and the third charge share scan line S(N-1) is The other of the third main pixel portion and the third sub-pixel portion is connected.
  • the array unit 2011 further includes at least one fourth pixel row P(N), at least one fourth charging scan line C(N), and at least one fourth charge sharing scan line S(N).
  • the fourth charge scan line C(N) and the fourth charge share scan line S(N) are both connected to the fourth pixel row P(N).
  • the fourth pixel row P(N) includes at least one fourth pixel, and the fourth pixel includes a fourth main pixel portion and a fourth sub-pixel portion.
  • the fourth charge scan line C(N) is connected to one of the fourth main pixel portion and the fourth sub-pixel portion, and the fourth charge share scan line S(N) and the fourth The other of the main pixel portion and the fourth sub-pixel portion is connected.
  • the array unit 2011 further includes at least one fifth pixel row P(N+1), at least one fifth charging scan line C(N+1), and at least one fifth charge sharing scan line S(N+1).
  • the fifth charge scan line C(N+1) and the fifth charge share scan line S(N+1) are both connected to the fifth pixel row P(N+1).
  • the fifth pixel row P(N+1) includes at least one fifth pixel, and the fifth pixel includes a fifth main pixel portion and a fifth sub-pixel portion.
  • the fifth charge scan line C(N+1) is connected to one of the fifth main pixel portion and the fifth sub-pixel portion, and the fifth charge share scan line S(N+1) is The other of the fifth main pixel portion and the fifth sub-pixel portion is connected.
  • the array unit 2011 further includes: at least a sixth pixel row P (N+2), at least a sixth charge scan line C (N+2), and at least a sixth charge share scan line S (N+2).
  • the sixth charge scan line C(N+2) and the sixth charge share scan line S(N+2) are both connected to the sixth pixel row P(N+2).
  • the sixth pixel row P(N+2) includes at least one sixth pixel, and the sixth pixel includes a sixth main pixel portion and a sixth sub-pixel portion.
  • the sixth charge scan line C(N+2) is connected to one of the sixth main pixel portion and the sixth sub-pixel portion, and the sixth charge share scan line S(N+2) is The other of the sixth main pixel portion and the sixth sub-pixel portion is connected.
  • the first direction 203 is perpendicular to a line where the first pixel row P(N-3) is located, the first pixel row P(N-3), the second pixel row P(N-2), The third pixel row P(N-1), the fourth pixel row P(N), the fifth pixel row P(N+1), and the sixth pixel row P(N+2) along The first directions 203 are sequentially arranged.
  • the non-display area 202 is provided with at least one first detection line 2021, at least one second detection line 2022, and at least one third detection line 2023.
  • the first detecting line 2021, the second detecting line 2022 and the third detecting line 2023 are all connected to the display area 201.
  • the first detecting line 2021, the second detecting line 2022, and the third detecting line 2023 are arranged in an array in a second direction, wherein the second direction is perpendicular to the first direction 203.
  • the array unit 2011 is connected to another array unit 2012 adjacent in the first direction 203.
  • the array unit 2011 is also connected to another array unit adjacent in the opposite direction of the first direction 203.
  • At least one of the first detection lines 2021, at least one of the second detection lines 2022, and at least one of the third detection lines 2023 in the non-display area 202 constitute a shorting bar (Shorting) Bar), the straight line direction of the shorting bar is parallel to the first direction 203, that is, the straight line where the first detecting line 2021, the second detecting line 2022, and the third detecting line 2023 are located
  • the first direction 203 is parallel.
  • Any one of the first detection line 2021, the second detection line 2022, and the third detection line 2023 is connected to a charge sharing scan line corresponding to the second number.
  • the pixel behavior of the first pixel row P(N-3), the second pixel row P(N-2), the third pixel row P(N-1), the fourth pixel One of a row P(N), the fifth pixel row P(N+1), and the sixth pixel row P(N+2) the charging scan line is the first charging scan line C (N-3), the second charging scan line C (N-2), the third charging scan line C (N-1), the fourth charging scan line C (N), the fifth One of a charge scan line C(N+1) and a sixth charge scan line C(N+2), the charge share scan line being the first charge share scan line S(N-3), The second charge sharing scan line S(N-2), the third charge sharing scan line S(N-1), the fourth charge sharing scan line S(N), the fifth charge sharing scan One of the line S(N+1) and the sixth charge share scan line S(N+2).
  • the first number is equal to a sum of a number corresponding to the pixel row and a first predetermined value, and the first predetermined value is an even number greater than or equal to 2, for example, the first predetermined value is 2, 4 , 6, 8, ..., and so on.
  • the second number is equal to a sum of a number corresponding to the pixel row and a second predetermined value, the second predetermined value being an odd number greater than or equal to 3, for example, the second predetermined value is 3, 5, 7 , 9, ..., and so on.
  • the first charging scan line C (N-3), the second charging scan line C (N-2), the third charging scan line C (N-1), and the fourth charging scan line C (N), the fifth charging scan line C(N+1) and the sixth charging scan line C(N+2) are divided into a plurality of first sets, and the number of the first set is the number
  • the second predetermined value for example, the second predetermined value is 3, and the number of the charging scan lines in each of the first sets is 2.
  • the charging scan lines in the same first set are all connected to the same charging scan line.
  • Any of the second predetermined numerical values (eg, 3) of charge scan lines adjacent in the first direction 203 are respectively connected to different detection lines.
  • the detection line is one of the first detection line 2021, the second detection line 2022, and the third detection line 2023.
  • the first charge sharing scan line S(N-3), the second charge share scan line S(N-2), the third charge share scan line S(N-1), the first The four charge sharing scan line S(N), the fifth charge share scan line S(N+1), and the sixth charge share scan line S(N+2) are also divided into the second predetermined value.
  • the second set for example, the second predetermined value is three, and the number of the charge-sharing scan lines in each of the second sets is two.
  • the charge sharing scan lines in the same second set are all connected to the same charge sharing scan line.
  • Any of the second predetermined numerical values (eg, 3) of charge-sharing scan lines adjacent in the first direction 203 are respectively connected to different detection lines.
  • the first predetermined value is 2 and the second predetermined value is 3.
  • the first charge sharing scan line S(N-3) is connected to the third charge scan line C(N-1).
  • the second charge sharing scan line S(N-2) is connected to the fourth charge scan line C(N).
  • the third charge sharing scan line S(N-1) is connected to the fifth charge scan line C(N+1).
  • the fourth charge sharing scan line S(N) is connected to the sixth charge scan line C(N+2).
  • the fifth charge share scan line S(N+1) is connected to a first charge scan line C(N+3) in another array unit 2012 adjacent in the first direction 203.
  • the sixth charge share scan line S(N+2) is connected to the second charge scan line C(N+4) in the other array unit 2012 adjacent in the first direction 203.
  • the second charge scan line C(N-2) is connected to the sixth charge share scan line S(N-4) of the other array unit adjacent in the reverse direction of the first direction 203.
  • the first detection line 2021 is connected to the first charge sharing scan line S(N-3) and the fourth charge sharing scan line S(N).
  • the second detection line 2022 is connected to the third charge share scan line S(N-1) and the sixth charge share scan line S(N+2).
  • the third detection line 2023 is connected to the second charge share scan line S(N-2) and the fifth charge share scan line S(N+1).
  • the short circuit phenomenon when a short circuit phenomenon occurs between the charge scan line and the charge share scan line corresponding to the same pixel row, the short circuit phenomenon can be detected in the TFT process stage of the display panel, which is advantageous for improving the The detection efficiency and the detection accuracy of the short circuit phenomenon of the display panel are also beneficial to improving the yield of the display panel and reducing the manufacturing cost of the display panel.
  • the display panel adopts a pixel design of an N+2 charging (sharing) bridge mode, and three independent shorting bars exist on the periphery of the pixel (Shorting Bar) traces 2021, 2022, and 2023, dividing the scan lines (charge scan lines/charge-shared scan lines) into three groups, and causing any adjacent three of the scan lines to be respectively led to different short-circuit strip traces, that is, Scan lines such as C(N-1), C(N+2), and C(N+5) as shown in FIG.
  • FIG. 3 is a schematic view of a second embodiment of the display panel of the present invention. This embodiment is similar to the first embodiment described above, except that:
  • the first predetermined value is 4 and the second predetermined value is 3.
  • the first charge sharing scan line S(N-3) is connected to the fifth charge scan line C(N+1).
  • the second charge sharing scan line S(N-2) is connected to the sixth charge scan line C(N+2).
  • the third charge-sharing scan line S(N-1) is connected to the first charge scan line C(N+3) in the other array unit 2012 adjacent in the first direction 203.
  • the fourth charge sharing scan line S(N) is connected to the second charge scan line C(N+4) in the other array unit 2012 adjacent in the first direction 203.
  • the fifth charge-sharing scan line S(N+1) is connected to the third charge scan line C(N+5) in the other array unit 2012 adjacent in the first direction 203.
  • the sixth charge sharing scan line S(N+2) is connected to the fourth charge scan line C(N+6) in the other array unit 2012 adjacent in the first direction 203.
  • the second charge scan line C(N-2) is connected to a fourth charge share scan line S(N-6) in another array unit adjacent in the reverse direction of the first direction 203.
  • the third charge scan line C(N-1) is connected to a fifth charge share scan line S(N-5) in another array unit adjacent in the reverse direction of the first direction 203.
  • the fourth charge scan line C(N) is connected to a sixth charge share scan line S(N-4) in another array unit adjacent in the reverse direction of the first direction 203.
  • the first detection line 2021 is connected to the second charge sharing scan line S(N-2) and the fifth charge sharing scan line S(N+1).
  • the second detection line 2022 is connected to the first charge sharing scan line S(N-3) and the fourth charge sharing scan line S(N).
  • the third detection line 2023 is connected to the third charge share scan line S(N-1) and the sixth charge share scan line S(N+2).
  • the display panel adopts a pixel design of an N+4 charge sharing bridge mode, and there are three independent short-circuit strip traces 2021, 2022, and 2023 at the periphery of the pixel, and the scan line (charge scan line/charge)
  • the shared scan lines are divided into three groups, and any adjacent three scan lines are respectively led out to different short circuit traces, that is, C(N-1), C(N+2) as shown in FIG.
  • a scan line such as C(N+5) is drawn to the first detection line 2021, and scan lines such as C(N-2), C(N+1), C(N+4) are taken out to the second detection.
  • a scan line such as a line 2022, C(N-3), C(N), C(N+3) is drawn to the third detection line 2023.
  • the short circuit between the charging scan line of any row and the charge sharing scan line can pass through the two shorting bars of the first detecting line 2021, the second detecting line 2022, and the third detecting line 2023. It is detected that the detection rate of the TFT process segment is improved, the product yield is improved, and the manufacturing cost is reduced.

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Abstract

一种显示面板，包括显示区（201）和非显示区（202），显示区上的阵列单元中的第一充电扫描线（C（N-3））、第二充电扫描线（C（N-2））、第三充电扫描线（C（N-1））、第四充电扫描线（C（N））、第五充电扫描线（C（N+1））、第六充电扫描线（C（N+2））以及第一电荷共享扫描线（S（N-3））、第二电荷共享扫描线（S（N-2））、第三电荷共享扫描线（S（N-1））、第四电荷共享扫描线（S（N））、第五电荷共享扫描线（S（N+1））、第六电荷共享扫描线（S（N+2））分别与第一像素行（P（N-3））、第二像素行（P（N-2））、第三像素行（P（N-1））、第四像素行（P（N））、第五像素行（P（N+1））、第六像素行（P（N+2））连接；所述非显示区上的第一检测线（2021）、第二检测线（2022）和第三检测线（2023）均与显示区（201）相连。

Description

显示面板 技术领域
本发明涉及显示技术领域，特别涉及一种显示面板。
 背景技术
在传统的显示面板的线路设计中，通常会在像素区域的外侧设计短路条/短路棒（Shorting Bar）的外围走线，并将扫描线按照奇数（ODD）和偶数（EVEN）分别引出至该外围走线，即，整个显示面板上的奇数和偶数扫描线在所述显示面板的外围各自短接在一起。这种设计是为了在TFT（Thin Film Transistor，薄膜晶体管）制程的检测环节中，可以通过给奇数和偶数扫描线不同的电讯号来检查所述显示面板内是否存在短路或断路的情况，配合不同的数据信号还可以检查出其他类型的不良。短路条也会被用于液晶盒（Cell）制程中的点灯检测环节，并在检测后被断开或去除，使其不会影响到成品的正常显示。
如图1所示，如果同一行的充电扫描线（Charge Gate Line/Charge Scan Line）103和电荷共享扫描线（Share Gate Line/Share Scan Line）104间发生短路（第二短路位置102或第一短路位置101），由于该电荷共享扫描线与后面第N+偶数的充电扫描线相连（其中，N为正整数），使得二者在顺序上皆为奇数或偶数，那么仅通过上述奇偶分别引出的短路条的检测方式是无法在TFT制程段将短路现象检出的，只能依靠Cell点灯甚至成品检测的方式方能检出，因此会导致产品良率降低。
故，有必要提出一种新的技术方案，以解决上述技术问题。
 技术问题
本发明的目的在于提供一种显示面板，其能使得显示面板中出现的短路现象能够高效地和精确地被检测出，提高所述显示面板的良率。
 技术解决方案
一种显示面板，所述显示面板包括：一显示区，其中，所述显示区上设置有至少两阵列单元，至少两所述阵列单元沿第一方向以阵列的形式排列，所述阵列单元包括：至少一第一像素行、至少一第一充电扫描线、至少一第一电荷共享扫描线，其中，所述第一充电扫描线和所述第一电荷共享扫描线均与所述第一像素行连接；至少一第二像素行、至少一第二充电扫描线、至少一第二电荷共享扫描线，其中，所述第二充电扫描线和所述第二电荷共享扫描线均与所述第二像素行连接；至少一第三像素行、至少一第三充电扫描线、至少一第三电荷共享扫描线，其中，所述第三充电扫描线和所述第三电荷共享扫描线均与所述第三像素行连接；至少一第四像素行、至少一第四充电扫描线、至少一第四电荷共享扫描线，其中，所述第四充电扫描线和所述第四电荷共享扫描线均与所述第四像素行连接；至少一第五像素行、至少一第五充电扫描线、至少一第五电荷共享扫描线，其中，所述第五充电扫描线和所述第五电荷共享扫描线均与所述第五像素行连接；以及至少一第六像素行、至少一第六充电扫描线、至少一第六电荷共享扫描线，其中，所述第六充电扫描线和所述第六电荷共享扫描线均与所述第六像素行连接；其中，所述第一方向与所述第一像素行所在的直线垂直，所述第一像素行、所述第二像素行、所述第三像素行、所述第四像素行、所述第五像素行和所述第六像素行沿所述第一方向依次排列；以及至少一非显示区，其中，所述非显示区设置于所述显示区的一侧，所述非显示区上设置有：至少一第一检测线；至少一第二检测线；以及至少一第三检测线；其中，所述第一检测线，所述第二检测线和所述第三检测线均与所述显示区相连；所述第一充电扫描线、所述第二充电扫描线、所述第三充电扫描线、所述第四充电扫描线、所述第五充电扫描线、所述第六充电扫描线中的任意一者与对应第一编号的电荷共享扫描线连接；所述第一检测线、所述第二检测线、所述第三检测线中的任意一者与对应第二编号的电荷共享扫描线连接；其中，所述第一编号等于像素行所对应的编号与第一预定数值之和，所述第一预定数值为大于或等于2的偶数；所述第二编号等于所述像素行所对应的编号与第二预定数值之和，所述第二预定数值为大于或等于3的奇数；所述非显示区中的至少一所述第一检测线、至少一所述第二检测线和至少一所述第三检测线构成一短路条，所述短路条所在的直线方向与所述第一方向平行。
在上述显示面板中，所述第一预定数值为2，所述第二预定数值为3。
在上述显示面板中，所述第一电荷共享扫描线与所述第三充电扫描线连接；所述第二电荷共享扫描线与所述第四充电扫描线连接；所述第三电荷共享扫描线与所述第五充电扫描线连接；所述第四电荷共享扫描线与所述第六充电扫描线连接；所述第五电荷共享扫描线与在所述第一方向上相邻的另一阵列单元中的第一充电扫描线连接；所述第六电荷共享扫描线与所述在所述第一方向上相邻的另一阵列单元中的第二充电扫描线连接。
在上述显示面板中，所述第一充电扫描线与在所述第一方向的反方向上相邻的另一阵列单元中的第五电荷共享扫描线连接；所述第二充电扫描线与所述在所述第一方向的反方向上相邻的另一阵列单元中的第六电荷共享扫描线连接。
在上述显示面板中，所述第一检测线与所述第一电荷共享扫描线和所述第四电荷共享扫描线连接；所述第二检测线与所述第三电荷共享扫描线和所述第六电荷共享扫描线连接；所述第三检测线与所述第二电荷共享扫描线和所述第五电荷共享扫描线连接。
在上述显示面板中，所述第一预定数值为4，所述第二预定数值为3。
在上述显示面板中，所述第一电荷共享扫描线与所述第五充电扫描线连接；所述第二电荷共享扫描线与所述第六充电扫描线连接；所述第三电荷共享扫描线与所述在所述第一方向上相邻的另一阵列单元中的第一充电扫描线连接；所述第四电荷共享扫描线与所述在所述第一方向上相邻的另一阵列单元中的第二充电扫描线连接；所述第五电荷共享扫描线与所述在所述第一方向上相邻的另一阵列单元中的第三充电扫描线连接；所述第六电荷共享扫描线与所述在所述第一方向上相邻的另一阵列单元中的第四充电扫描线连接。
在上述显示面板中，所述第一充电扫描线与在所述第一方向的反方向上相邻的另一阵列单元中的第三电荷共享扫描线连接；所述第二充电扫描线所述在所述第一方向的反方向上相邻的另一阵列单元中的第四电荷共享扫描线连接；所述第三充电扫描线所述在所述第一方向的反方向上相邻的另一阵列单元中的第五电荷共享扫描线连接；所述第四充电扫描线所述在所述第一方向的反方向上相邻的另一阵列单元中的第六电荷共享扫描线连接。
在上述显示面板中，所述第一检测线与所述第二电荷共享扫描线和所述第五电荷共享扫描线连接；所述第二检测线与所述第一电荷共享扫描线和所述第四电荷共享扫描线连接；所述第三检测线与所述第三电荷共享扫描线和所述第六电荷共享扫描线连接。
一种显示面板，所述显示面板包括：一显示区，其中，所述显示区上设置有至少两阵列单元，至少两所述阵列单元沿第一方向以阵列的形式排列，所述阵列单元包括：至少一第一像素行、至少一第一充电扫描线、至少一第一电荷共享扫描线，其中，所述第一充电扫描线和所述第一电荷共享扫描线均与所述第一像素行连接；至少一第二像素行、至少一第二充电扫描线、至少一第二电荷共享扫描线，其中，所述第二充电扫描线和所述第二电荷共享扫描线均与所述第二像素行连接；至少一第三像素行、至少一第三充电扫描线、至少一第三电荷共享扫描线，其中，所述第三充电扫描线和所述第三电荷共享扫描线均与所述第三像素行连接；至少一第四像素行、至少一第四充电扫描线、至少一第四电荷共享扫描线，其中，所述第四充电扫描线和所述第四电荷共享扫描线均与所述第四像素行连接；至少一第五像素行、至少一第五充电扫描线、至少一第五电荷共享扫描线，其中，所述第五充电扫描线和所述第五电荷共享扫描线均与所述第五像素行连接；以及至少一第六像素行、至少一第六充电扫描线、至少一第六电荷共享扫描线，其中，所述第六充电扫描线和所述第六电荷共享扫描线均与所述第六像素行连接；其中，所述第一方向与所述第一像素行所在的直线垂直，所述第一像素行、所述第二像素行、所述第三像素行、所述第四像素行、所述第五像素行和所述第六像素行沿所述第一方向依次排列；以及至少一非显示区，其中，所述非显示区设置于所述显示区的一侧，所述非显示区上设置有：至少一第一检测线；至少一第二检测线；以及至少一第三检测线；其中，所述第一检测线，所述第二检测线和所述第三检测线均与所述显示区相连。
在上述显示面板中，所述第一充电扫描线、所述第二充电扫描线、所述第三充电扫描线、所述第四充电扫描线、所述第五充电扫描线、所述第六充电扫描线中的任意一者与对应第一编号的电荷共享扫描线连接；所述第一检测线、所述第二检测线、所述第三检测线中的任意一者与对应第二编号的电荷共享扫描线连接；其中，所述第一编号等于像素行所对应的编号与第一预定数值之和，所述第一预定数值为大于或等于2的偶数；所述第二编号等于所述像素行所对应的编号与第二预定数值之和，所述第二预定数值为大于或等于3的奇数。
在上述显示面板中，所述第一预定数值为2，所述第二预定数值为3。
在上述显示面板中，所述第一电荷共享扫描线与所述第三充电扫描线连接；所述第二电荷共享扫描线与所述第四充电扫描线连接；所述第三电荷共享扫描线与所述第五充电扫描线连接；所述第四电荷共享扫描线与所述第六充电扫描线连接；所述第五电荷共享扫描线与在所述第一方向上相邻的另一阵列单元中的第一充电扫描线连接；所述第六电荷共享扫描线与所述在所述第一方向上相邻的另一阵列单元中的第二充电扫描线连接。
在上述显示面板中，所述第一充电扫描线与在所述第一方向的反方向上相邻的另一阵列单元中的第五电荷共享扫描线连接；所述第二充电扫描线与所述在所述第一方向的反方向上相邻的另一阵列单元中的第六电荷共享扫描线连接。
在上述显示面板中，所述第一检测线与所述第一电荷共享扫描线和所述第四电荷共享扫描线连接；所述第二检测线与所述第三电荷共享扫描线和所述第六电荷共享扫描线连接；所述第三检测线与所述第二电荷共享扫描线和所述第五电荷共享扫描线连接。
在上述显示面板中，所述第一预定数值为4，所述第二预定数值为3。
在上述显示面板中，所述第一电荷共享扫描线与所述第五充电扫描线连接；所述第二电荷共享扫描线与所述第六充电扫描线连接；所述第三电荷共享扫描线与所述在所述第一方向上相邻的另一阵列单元中的第一充电扫描线连接；所述第四电荷共享扫描线与所述在所述第一方向上相邻的另一阵列单元中的第二充电扫描线连接；所述第五电荷共享扫描线与所述在所述第一方向上相邻的另一阵列单元中的第三充电扫描线连接；所述第六电荷共享扫描线与所述在所述第一方向上相邻的另一阵列单元中的第四充电扫描线连接。
在上述显示面板中，所述第一充电扫描线与在所述第一方向的反方向上相邻的另一阵列单元中的第三电荷共享扫描线连接；所述第二充电扫描线所述在所述第一方向的反方向上相邻的另一阵列单元中的第四电荷共享扫描线连接；所述第三充电扫描线所述在所述第一方向的反方向上相邻的另一阵列单元中的第五电荷共享扫描线连接；所述第四充电扫描线所述在所述第一方向的反方向上相邻的另一阵列单元中的第六电荷共享扫描线连接。
在上述显示面板中，所述第一检测线与所述第二电荷共享扫描线和所述第五电荷共享扫描线连接；所述第二检测线与所述第一电荷共享扫描线和所述第四电荷共享扫描线连接；所述第三检测线与所述第三电荷共享扫描线和所述第六电荷共享扫描线连接。
在上述显示面板中，所述非显示区中的至少一所述第一检测线、至少一所述第二检测线和至少一所述第三检测线构成一短路条，所述短路条所在的直线方向与所述第一方向平行。
 有益效果
相对现有技术，本发明在对应同一像素行的充电扫描线和电荷共享扫描线之间出现短路现象时，所述短路现象在所述显示面板的TFT制程阶段即可被检测出，有利于提高所述显示面板的短路现象的检测效率和检测精确度，同时也有利于提高所述显示面板的良率，降低所述显示面板的制造成本。
 附图说明
图1为传统的显示面板的示意图；
图2为本发明的显示面板的第一实施例的示意图；
图3为本发明的显示面板的第二实施例的示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。
参考图2，图2为本发明的显示面板的第一实施例的示意图。
本实施例的显示面板可以是LCD（Liquid Crystal Display，液晶显示器）、OLED（Organic Light Emitting Diode，有机发光二极管显示器）等显示器。
本实施例的显示面板包括一显示区（Active Area）201和至少一非显示区202，所述非显示区202设置于所述显示区201的一侧，例如，两所述非显示区202分别设置于所述显示区201的两侧。所述显示面板上设置有像素阵列，所述像素阵列位于所述显示区201上，所述像素阵列由像素组成。
具体地，所述显示区201上设置有至少两阵列单元（2011，2012），至少两所述阵列单元（2011，2012）沿第一方向203以阵列的形式排列。
所述阵列单元2011包括：至少一第一像素行P(N-3)、至少一第一充电（Charging）扫描线（Scan Line）C(N-3)、至少一第一电荷共享（Sharing）扫描线。其中，所述第一充电扫描线C(N-3)和所述第一电荷共享扫描线S(N-3)均与所述第一像素行P(N-3)连接。所述第一像素行P(N-3)包括至少一第一像素，所述第一像素包括第一主像素部（Main Pixel）和第一次像素部（Sub Pixel）。所述第一充电扫描线C(N-3)与所述第一主像素部、所述第一次像素部中的一者连接，所述第一电荷共享扫描线S(N-3)与所述第一主像素部、所述第一次像素部中的另一者连接。其中，N为正整数。
所述阵列单元2011还包括：至少一第二像素行P(N-2)、至少一第二充电扫描线C(N-2)、至少一第二电荷共享扫描线S(N-2)。其中，所述第二充电扫描线C(N-2)和所述第二电荷共享扫描线S(N-2)均与所述第二像素行P(N-2)连接。所述第二像素行P(N-2)包括至少一第二像素，所述第二像素包括第二主像素部和第二次像素部。所述第二充电扫描线C(N-2)与所述第二主像素部、所述第二次像素部中的一者连接，所述第二电荷共享扫描线S(N-2)与所述第二主像素部、所述第二次像素部中的另一者连接。例如，所述第二充电扫描线C(N-2)与所述第二主像素部连接，所述第二电荷共享扫描线S(N-2)与所述第二次像素部连接，或者，所述第二充电扫描线C(N-2)与所述第二次像素部连接，所述第二电荷共享扫描线S(N-2)与所述第二主像素部连接。
所述阵列单元2011还包括：至少一第三像素行P(N-1)、至少一第三充电扫描线C(N-1)、至少一第三电荷共享扫描线S(N-1)。其中，所述第三充电扫描线C(N-1)和所述第三电荷共享扫描线S(N-1)均与所述第三像素行P(N-1)连接。所述第三像素行P(N-1)包括至少一第三像素，所述第三像素包括第三主像素部和第三次像素部。所述第三充电扫描线C(N-1)与所述第三主像素部、所述第三次像素部中的一者连接，所述第三电荷共享扫描线S(N-1)与所述第三主像素部、所述第三次像素部中的另一者连接。
所述阵列单元2011还包括：至少一第四像素行P(N)、至少一第四充电扫描线C(N)、至少一第四电荷共享扫描线S(N)。其中，所述第四充电扫描线C(N)和所述第四电荷共享扫描线S(N)均与所述第四像素行P(N)连接。所述第四像素行P(N)包括至少一第四像素，所述第四像素包括第四主像素部和第四次像素部。所述第四充电扫描线C(N)与所述第四主像素部、所述第四次像素部中的一者连接，所述第四电荷共享扫描线S(N)与所述第四主像素部、所述第四次像素部中的另一者连接。
所述阵列单元2011还包括：至少一第五像素行P(N+1)、至少一第五充电扫描线C(N+1)、至少一第五电荷共享扫描线S(N+1)。其中，所述第五充电扫描线C(N+1)和所述第五电荷共享扫描线S(N+1)均与所述第五像素行P(N+1)连接。所述第五像素行P(N+1)包括至少一第五像素，所述第五像素包括第五主像素部和第五次像素部。所述第五充电扫描线C(N+1)与所述第五主像素部、所述第五次像素部中的一者连接，所述第五电荷共享扫描线S(N+1)与所述第五主像素部、所述第五次像素部中的另一者连接。
所述阵列单元2011还包括：至少一第六像素行P(N+2)、至少一第六充电扫描线C(N+2)、至少一第六电荷共享扫描线S(N+2)。其中，所述第六充电扫描线C(N+2)和所述第六电荷共享扫描线S(N+2)均与所述第六像素行P(N+2)连接。所述第六像素行P(N+2)包括至少一第六像素，所述第六像素包括第六主像素部和第六次像素部。所述第六充电扫描线C(N+2)与所述第六主像素部、所述第六次像素部中的一者连接，所述第六电荷共享扫描线S(N+2)与所述第六主像素部、所述第六次像素部中的另一者连接。
所述第一方向203与所述第一像素行P(N-3)所在的直线垂直，所述第一像素行P(N-3)、所述第二像素行P(N-2)、所述第三像素行P(N-1)、所述第四像素行P(N)、所述第五像素行P(N+1)和所述第六像素行P(N+2)沿所述第一方向203依次排列。
所述非显示区202上设置有至少一第一检测线2021，至少一第二检测线2022，至少一第三检测线2023。其中，所述第一检测线2021，所述第二检测线2022和所述第三检测线2023均与所述显示区201相连。所述第一检测线2021、所述第二检测线2022、所述第三检测线2023沿第二方向以阵列的形式排列，其中，所述第二方向与所述第一方向203垂直。
在本实施例中，所述阵列单元2011与在所述第一方向203上相邻的另一阵列单元2012相连。所述阵列单元2011还与在所述第一方向203的反方向上相邻的另一阵列单元相连。
所述非显示区202中的至少一所述第一检测线2021、至少一所述第二检测线2022和至少一所述第三检测线2023构成一短路条（Shorting Bar），所述短路条所在的直线方向与所述第一方向203平行，即，所述第一检测线2021、所述第二检测线2022、所述第三检测线2023所在的直线与所述第一方向203平行。
在本实施例中，所述第一充电扫描线C(N-3)、所述第二充电扫描线C(N-2)、所述第三充电扫描线C(N-1)、所述第四充电扫描线C(N)、所述第五充电扫描线C(N+1)、所述第六充电扫描线C(N+2)中的任意一者与对应第一编号的电荷共享扫描线连接。所述第一检测线2021、所述第二检测线2022、所述第三检测线2023中的任意一者与对应第二编号的电荷共享扫描线连接。
其中，所述像素行为所述第一像素行P(N-3)、所述第二像素行P(N-2)、所述第三像素行P(N-1)、所述第四像素行P(N)、所述第五像素行P(N+1)和所述第六像素行P(N+2)中的一者，所述充电扫描线为所述第一充电扫描线C(N-3)、所述第二充电扫描线C(N-2)、所述第三充电扫描线C(N-1)、所述第四充电扫描线C(N)、所述第五充电扫描线C(N+1)和所述第六充电扫描线C(N+2)中的一者，所述电荷共享扫描线为所述第一电荷共享扫描线S(N-3)、所述第二电荷共享扫描线S(N-2)、所述第三电荷共享扫描线S(N-1)、所述第四电荷共享扫描线S(N)、所述第五电荷共享扫描线S(N+1)和所述第六电荷共享扫描线S(N+2)中的一者。
其中，所述第一编号等于所述像素行所对应的编号与第一预定数值之和，所述第一预定数值为大于或等于2的偶数，例如，所述第一预定数值为2、4、6、8，……，等等。所述第二编号等于所述像素行所对应的编号与第二预定数值之和，所述第二预定数值为大于或等于3的奇数，例如，所述第二预定数值为3、5、7、9，……，等等。
所述第一充电扫描线C(N-3)、所述第二充电扫描线C(N-2)、所述第三充电扫描线C(N-1)、所述第四充电扫描线C(N)、所述第五充电扫描线C(N+1)和所述第六充电扫描线C(N+2)分为若干个第一集合，所述第一集合的数量为所述第二预定数值，例如，所述第二预定数值是3，则每一所述第一集合中的所述充电扫描线的数量则为2。同一所述第一集合中的所述充电扫描线均与同一充电扫描线连接。在所述第一方向203上相邻的任意所述第二预定数值（例如，3）条的充电扫描线分别与不同的检测线连接。其中，所述检测线为所述第一检测线2021、所述第二检测线2022、所述第三检测线2023中的一者。
同样，所述第一电荷共享扫描线S(N-3)、所述第二电荷共享扫描线S(N-2)、所述第三电荷共享扫描线S(N-1)、所述第四电荷共享扫描线S(N)、所述第五电荷共享扫描线S(N+1)和所述第六电荷共享扫描线S(N+2)也分为数量为所述第二预定数值的第二集合，例如，所述第二预定数值为3，则每一所述第二集合中的所述电荷共享扫描线的数量为2。同一所述第二集合中的所述电荷共享扫描线均与同一电荷共享扫描线连接。在所述第一方向203上相邻的任意所述第二预定数值（例如，3）条的电荷共享扫描线分别与不同的所述检测线连接。
在本实施例中，以所述第一预定数值为2，所述第二预定数值为3为例来说明。
具体地，所述第一电荷共享扫描线S(N-3)与所述第三充电扫描线C(N-1)连接。所述第二电荷共享扫描线S(N-2)与所述第四充电扫描线C(N)连接。所述第三电荷共享扫描线S(N-1)与所述第五充电扫描线C(N+1)连接。所述第四电荷共享扫描线S(N)与所述第六充电扫描线C(N+2)连接。所述第五电荷共享扫描线S(N+1)与在所述第一方向203上相邻的另一阵列单元2012中的第一充电扫描线C(N+3)连接。所述第六电荷共享扫描线S(N+2)与所述在所述第一方向203上相邻的另一阵列单元2012中的第二充电扫描线C(N+4)连接。
在本实施例中，所述第一充电扫描线C(N-3)与在所述第一方向203的反方向上相邻的另一阵列单元中的第五电荷共享扫描线S(N-5)连接。所述第二充电扫描线C(N-2)与所述在所述第一方向203的反方向上相邻的另一阵列单元中的第六电荷共享扫描线S(N-4)连接。
在本实施例中，所述第一检测线2021与所述第一电荷共享扫描线S(N-3)和所述第四电荷共享扫描线S(N)连接。所述第二检测线2022与所述第三电荷共享扫描线S(N-1)和所述第六电荷共享扫描线S(N+2)连接。所述第三检测线2023与所述第二电荷共享扫描线S(N-2)和所述第五电荷共享扫描线S(N+1)连接。
在上述技术方案中，在对应同一像素行的充电扫描线和电荷共享扫描线之间出现短路现象时，所述短路现象在所述显示面板的TFT制程阶段即可被检测出，有利于提高所述显示面板的短路现象的检测效率和检测精确度，同时也有利于提高所述显示面板的良率，降低所述显示面板的制造成本。
如图2所示，所述显示面板采用N+2充电（Charging）共享（Sharing）桥接方式的像素设计，在所述像素外围存在三条独立的短路条（Shorting Bar）走线2021、2022和2023，将扫描线（充电扫描线/电荷共享扫描线）分为三组，并使任意相邻三条所述扫描线分别引出至不同的短路条走线，即，如图3所示的C（N-1）、C（N+2）、C（N+5）等扫描线引出至所述第一检测线2021，C（N-2）、C（N+1）、C（N+4）等扫描线引出至所述第二检测线2022，C（N-3）、C（N）、C（N+3）等扫描线引出至所述第三检测线2023。如此一来，任意行的充电扫描线（Charging）与电荷共享扫描线（Sharing）间的短路都可以通过所述第一检测线2021、所述第二检测线2022、所述第三检测线2023中的两条短路条检测出，提高了TFT（Thin Film Transistor，薄膜晶体管）制程段检出率，提升了产品良率，降低制造成本。
参考图3，图3为本发明的显示面板的第二实施例的示意图。本实施例与上述第一实施例相似，不同之处在于：
在本实施例中，所述第一预定数值为4，所述第二预定数值为3。
具体地，所述第一电荷共享扫描线S(N-3)与所述第五充电扫描线C(N+1)连接。所述第二电荷共享扫描线S(N-2)与所述第六充电扫描线C(N+2)连接。所述第三电荷共享扫描线S(N-1)与所述在所述第一方向203上相邻的另一阵列单元2012中的第一充电扫描线C(N+3)连接。所述第四电荷共享扫描线S(N)与所述在所述第一方向203上相邻的另一阵列单元2012中的第二充电扫描线C(N+4)连接。所述第五电荷共享扫描线S(N+1)与所述在所述第一方向203上相邻的另一阵列单元2012中的第三充电扫描线C(N+5)连接。所述第六电荷共享扫描线S(N+2)与所述在所述第一方向203上相邻的另一阵列单元2012中的第四充电扫描线C(N+6)连接。
在本实施例中，所述第一充电扫描线C(N-3)与在所述第一方向203的反方向上相邻的另一阵列单元中的第三电荷共享扫描线S(N-7)连接。所述第二充电扫描线C(N-2)所述在所述第一方向203的反方向上相邻的另一阵列单元中的第四电荷共享扫描线S(N-6)连接。所述第三充电扫描线C(N-1)所述在所述第一方向203的反方向上相邻的另一阵列单元中的第五电荷共享扫描线S(N-5)连接。所述第四充电扫描线C(N)所述在所述第一方向203的反方向上相邻的另一阵列单元中的第六电荷共享扫描线S(N-4)连接。
在本实施例中，所述第一检测线2021与所述第二电荷共享扫描线S(N-2)和所述第五电荷共享扫描线S(N+1)连接。所述第二检测线2022与所述第一电荷共享扫描线S(N-3)和所述第四电荷共享扫描线S(N)连接。所述第三检测线2023与所述第三电荷共享扫描线S(N-1)和所述第六电荷共享扫描线S(N+2)连接。
如图3所示，所述显示面板采用N+4充电共享桥接方式的像素设计，在所述像素外围存在三条独立的短路条走线2021、2022和2023，将扫描线（充电扫描线/电荷共享扫描线）分为三组，并使任意相邻三条所述扫描线分别引出至不同的短路条走线，即，如图3所示的C（N-1）、C（N+2）、C（N+5）等扫描线引出至所述第一检测线2021，C（N-2）、C（N+1）、C（N+4）等扫描线引出至所述第二检测线2022，C（N-3）、C（N）、C（N+3）等扫描线引出至所述第三检测线2023。如此一来，任意行的充电扫描线与电荷共享扫描线间的短路都可以通过所述第一检测线2021、所述第二检测线2022、所述第三检测线2023中的两条短路条检测出，提高了TFT制程段检出率，提升了产品良率，降低制造成本。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其中
    所述显示面板包括：
    一显示区，其中，所述显示区上设置有至少两阵列单元，至少两所述阵列单元沿第一方向以阵列的形式排列，所述阵列单元包括：
    至少一第一像素行、至少一第一充电扫描线、至少一第一电荷共享扫描线，其中，所述第一充电扫描线和所述第一电荷共享扫描线均与所述第一像素行连接；
    至少一第二像素行、至少一第二充电扫描线、至少一第二电荷共享扫描线，其中，所述第二充电扫描线和所述第二电荷共享扫描线均与所述第二像素行连接；
    至少一第三像素行、至少一第三充电扫描线、至少一第三电荷共享扫描线，其中，所述第三充电扫描线和所述第三电荷共享扫描线均与所述第三像素行连接；
    至少一第四像素行、至少一第四充电扫描线、至少一第四电荷共享扫描线，其中，所述第四充电扫描线和所述第四电荷共享扫描线均与所述第四像素行连接；
    至少一第五像素行、至少一第五充电扫描线、至少一第五电荷共享扫描线，其中，所述第五充电扫描线和所述第五电荷共享扫描线均与所述第五像素行连接；以及
    至少一第六像素行、至少一第六充电扫描线、至少一第六电荷共享扫描线，其中，所述第六充电扫描线和所述第六电荷共享扫描线均与所述第六像素行连接；
    其中，所述第一方向与所述第一像素行所在的直线垂直，所述第一像素行、所述第二像素行、所述第三像素行、所述第四像素行、所述第五像素行和所述第六像素行沿所述第一方向依次排列；以及
    至少一非显示区，其中，所述非显示区设置于所述显示区的一侧，所述非显示区上设置有：
    至少一第一检测线；
    至少一第二检测线；以及
    至少一第三检测线；
    其中，所述第一检测线，所述第二检测线和所述第三检测线均与所述显示区相连；
    所述第一充电扫描线、所述第二充电扫描线、所述第三充电扫描线、所述第四充电扫描线、所述第五充电扫描线、所述第六充电扫描线中的任意一者与对应第一编号的电荷共享扫描线连接；
    所述第一检测线、所述第二检测线、所述第三检测线中的任意一者与对应第二编号的电荷共享扫描线连接；
    其中，所述第一编号等于像素行所对应的编号与第一预定数值之和，所述第一预定数值为大于或等于2的偶数；
    所述第二编号等于所述像素行所对应的编号与第二预定数值之和，所述第二预定数值为大于或等于3的奇数；
    所述非显示区中的至少一所述第一检测线、至少一所述第二检测线和至少一所述第三检测线构成一短路条，所述短路条所在的直线方向与所述第一方向平行。
  2. 根据权利要求1所述的显示面板，其中
    所述第一预定数值为2，所述第二预定数值为3。
  3. 根据权利要求2所述的显示面板，其中
    所述第一电荷共享扫描线与所述第三充电扫描线连接；
    所述第二电荷共享扫描线与所述第四充电扫描线连接；
    所述第三电荷共享扫描线与所述第五充电扫描线连接；
    所述第四电荷共享扫描线与所述第六充电扫描线连接；
    所述第五电荷共享扫描线与在所述第一方向上相邻的另一阵列单元中的第一充电扫描线连接；
    所述第六电荷共享扫描线与所述在所述第一方向上相邻的另一阵列单元中的第二充电扫描线连接。
  4. 根据权利要求3所述的显示面板，其中
    所述第一充电扫描线与在所述第一方向的反方向上相邻的另一阵列单元中的第五电荷共享扫描线连接；
    所述第二充电扫描线与所述在所述第一方向的反方向上相邻的另一阵列单元中的第六电荷共享扫描线连接。
  5. 根据权利要求3所述的显示面板，其中
    所述第一检测线与所述第一电荷共享扫描线和所述第四电荷共享扫描线连接；
    所述第二检测线与所述第三电荷共享扫描线和所述第六电荷共享扫描线连接；
    所述第三检测线与所述第二电荷共享扫描线和所述第五电荷共享扫描线连接。
  6. 根据权利要求1所述的显示面板，其中
    所述第一预定数值为4，所述第二预定数值为3。
  7. 根据权利要求6所述的显示面板，其中
    所述第一电荷共享扫描线与所述第五充电扫描线连接；
    所述第二电荷共享扫描线与所述第六充电扫描线连接；
    所述第三电荷共享扫描线与所述在所述第一方向上相邻的另一阵列单元中的第一充电扫描线连接；
    所述第四电荷共享扫描线与所述在所述第一方向上相邻的另一阵列单元中的第二充电扫描线连接；
    所述第五电荷共享扫描线与所述在所述第一方向上相邻的另一阵列单元中的第三充电扫描线连接；
    所述第六电荷共享扫描线与所述在所述第一方向上相邻的另一阵列单元中的第四充电扫描线连接。
  8. 根据权利要求7所述的显示面板，其中
    所述第一充电扫描线与在所述第一方向的反方向上相邻的另一阵列单元中的第三电荷共享扫描线连接；
    所述第二充电扫描线所述在所述第一方向的反方向上相邻的另一阵列单元中的第四电荷共享扫描线连接；
    所述第三充电扫描线所述在所述第一方向的反方向上相邻的另一阵列单元中的第五电荷共享扫描线连接；
    所述第四充电扫描线所述在所述第一方向的反方向上相邻的另一阵列单元中的第六电荷共享扫描线连接。
  9. 根据权利要求7所述的显示面板，其中
    所述第一检测线与所述第二电荷共享扫描线和所述第五电荷共享扫描线连接；
    所述第二检测线与所述第一电荷共享扫描线和所述第四电荷共享扫描线连接；
    所述第三检测线与所述第三电荷共享扫描线和所述第六电荷共享扫描线连接。
  10. 一种显示面板，其中
    所述显示面板包括：
    一显示区，其中，所述显示区上设置有至少两阵列单元，至少两所述阵列单元沿第一方向以阵列的形式排列，所述阵列单元包括：
    至少一第一像素行、至少一第一充电扫描线、至少一第一电荷共享扫描线，其中，所述第一充电扫描线和所述第一电荷共享扫描线均与所述第一像素行连接；
    至少一第二像素行、至少一第二充电扫描线、至少一第二电荷共享扫描线，其中，所述第二充电扫描线和所述第二电荷共享扫描线均与所述第二像素行连接；
    至少一第三像素行、至少一第三充电扫描线、至少一第三电荷共享扫描线，其中，所述第三充电扫描线和所述第三电荷共享扫描线均与所述第三像素行连接；
    至少一第四像素行、至少一第四充电扫描线、至少一第四电荷共享扫描线，其中，所述第四充电扫描线和所述第四电荷共享扫描线均与所述第四像素行连接；
    至少一第五像素行、至少一第五充电扫描线、至少一第五电荷共享扫描线，其中，所述第五充电扫描线和所述第五电荷共享扫描线均与所述第五像素行连接；以及
    至少一第六像素行、至少一第六充电扫描线、至少一第六电荷共享扫描线，其中，所述第六充电扫描线和所述第六电荷共享扫描线均与所述第六像素行连接；
    其中，所述第一方向与所述第一像素行所在的直线垂直，所述第一像素行、所述第二像素行、所述第三像素行、所述第四像素行、所述第五像素行和所述第六像素行沿所述第一方向依次排列；以及
    至少一非显示区，其中，所述非显示区设置于所述显示区的一侧，所述非显示区上设置有：
    至少一第一检测线；
    至少一第二检测线；以及
    至少一第三检测线；
    其中，所述第一检测线，所述第二检测线和所述第三检测线均与所述显示区相连。
  11. 根据权利要求10所述的显示面板，其中
    所述第一充电扫描线、所述第二充电扫描线、所述第三充电扫描线、所述第四充电扫描线、所述第五充电扫描线、所述第六充电扫描线中的任意一者与对应第一编号的电荷共享扫描线连接；
    所述第一检测线、所述第二检测线、所述第三检测线中的任意一者与对应第二编号的电荷共享扫描线连接；
    其中，所述第一编号等于像素行所对应的编号与第一预定数值之和，所述第一预定数值为大于或等于2的偶数；
    所述第二编号等于所述像素行所对应的编号与第二预定数值之和，所述第二预定数值为大于或等于3的奇数。
  12. 根据权利要求11所述的显示面板，其中
    所述第一预定数值为2，所述第二预定数值为3。
  13. 根据权利要求12所述的显示面板，其中
    所述第一电荷共享扫描线与所述第三充电扫描线连接；
    所述第二电荷共享扫描线与所述第四充电扫描线连接；
    所述第三电荷共享扫描线与所述第五充电扫描线连接；
    所述第四电荷共享扫描线与所述第六充电扫描线连接；
    所述第五电荷共享扫描线与在所述第一方向上相邻的另一阵列单元中的第一充电扫描线连接；
    所述第六电荷共享扫描线与所述在所述第一方向上相邻的另一阵列单元中的第二充电扫描线连接。
  14. 根据权利要求13所述的显示面板，其中
    所述第一充电扫描线与在所述第一方向的反方向上相邻的另一阵列单元中的第五电荷共享扫描线连接；
    所述第二充电扫描线与所述在所述第一方向的反方向上相邻的另一阵列单元中的第六电荷共享扫描线连接。
  15. 根据权利要求13所述的显示面板，其中
    所述第一检测线与所述第一电荷共享扫描线和所述第四电荷共享扫描线连接；
    所述第二检测线与所述第三电荷共享扫描线和所述第六电荷共享扫描线连接；
    所述第三检测线与所述第二电荷共享扫描线和所述第五电荷共享扫描线连接。
  16. 根据权利要求11所述的显示面板，其中
    所述第一预定数值为4，所述第二预定数值为3。
  17. 根据权利要求16所述的显示面板，其中
    所述第一电荷共享扫描线与所述第五充电扫描线连接；
    所述第二电荷共享扫描线与所述第六充电扫描线连接；
    所述第三电荷共享扫描线与所述在所述第一方向上相邻的另一阵列单元中的第一充电扫描线连接；
    所述第四电荷共享扫描线与所述在所述第一方向上相邻的另一阵列单元中的第二充电扫描线连接；
    所述第五电荷共享扫描线与所述在所述第一方向上相邻的另一阵列单元中的第三充电扫描线连接；
    所述第六电荷共享扫描线与所述在所述第一方向上相邻的另一阵列单元中的第四充电扫描线连接。
  18. 根据权利要求17所述的显示面板，其中
    所述第一充电扫描线与在所述第一方向的反方向上相邻的另一阵列单元中的第三电荷共享扫描线连接；
    所述第二充电扫描线所述在所述第一方向的反方向上相邻的另一阵列单元中的第四电荷共享扫描线连接；
    所述第三充电扫描线所述在所述第一方向的反方向上相邻的另一阵列单元中的第五电荷共享扫描线连接；
    所述第四充电扫描线所述在所述第一方向的反方向上相邻的另一阵列单元中的第六电荷共享扫描线连接。
  19. 根据权利要求17所述的显示面板，其中
    所述第一检测线与所述第二电荷共享扫描线和所述第五电荷共享扫描线连接；
    所述第二检测线与所述第一电荷共享扫描线和所述第四电荷共享扫描线连接；
    所述第三检测线与所述第三电荷共享扫描线和所述第六电荷共享扫描线连接。
  20. 根据权利要求10所述的显示面板，其中
    所述非显示区中的至少一所述第一检测线、至少一所述第二检测线和至少一所述第三检测线构成一短路条，所述短路条所在的直线方向与所述第一方向平行。
PCT/CN2014/083859 2014-06-30 2014-08-07 显示面板 Ceased WO2016000293A1 (zh)

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