WO2015192724A1 - 一种片上供电网络 - Google Patents

一种片上供电网络 Download PDF

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Publication number
WO2015192724A1
WO2015192724A1 PCT/CN2015/080990 CN2015080990W WO2015192724A1 WO 2015192724 A1 WO2015192724 A1 WO 2015192724A1 CN 2015080990 W CN2015080990 W CN 2015080990W WO 2015192724 A1 WO2015192724 A1 WO 2015192724A1
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Prior art keywords
output
chip
voltage regulator
resistor
mos transistor
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PCT/CN2015/080990
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English (en)
French (fr)
Inventor
唐样洋
王新入
张臣雄
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华为技术有限公司
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Publication of WO2015192724A1 publication Critical patent/WO2015192724A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators

Definitions

  • the present invention relates to the field of power electronics, and in particular, to an on-chip power supply network.
  • the voltage regulator which adjusts the received voltage to output the voltage required by the circuit to its connected circuit.
  • the chip design area density rises rapidly.
  • the integrity of the power supply determines the functionality, logic, and power consumption of the load module. Low power integrity, ie large ripples, spikes, etc., will directly put a heavy burden on the system, not only in the system response speed, correctness, but also the energy loss of the entire system.
  • Figure 1 shows a conventional power supply network in which the load is on the chip (or within the chip) and the power supply to the load is accomplished by an off-chip voltage regulator.
  • the power supply of the off-chip voltage regulator is provided by an external battery or other means.
  • the off-chip voltage regulator can be a single output to supply the load, or multiple outputs to supply the load, as shown in Figure 1, multiple outputs, namely Vreg-1, Vreg-2, Vreg-3. In the case of multiple voltage outputs, there may be multiple off-chip voltage regulators.
  • L PB is the output equivalent inductance of the off-chip voltage regulator on the motherboard
  • R PB is the output equivalent resistance of the off-chip voltage regulator on the motherboard
  • ESL VR is the off-chip voltage regulator on the motherboard.
  • ESR VR is the equivalent resistance of the output parasitic capacitance of the off-chip voltage regulator on the motherboard
  • C VR is the output parasitic capacitance of the off-chip voltage regulator on the motherboard
  • L PP1 is The input equivalent inductance of the transmission package
  • R PP1 is the input equivalent resistance of the transmission package
  • L PP2 is the output equivalent inductance of the transmission package
  • R PP2 is the output equivalent resistance of the transmission package
  • ESL PKG is the parasitic capacitance of the transmission package.
  • ESR PKG is the equivalent resistance of the parasitic capacitance of the transmission package
  • C PKG is the parasitic capacitance of the transmission package
  • R Die is the input equivalent resistance of the load on the chip
  • ESR Die is the input parasitic capacitance of the load on the chip
  • the equivalent resistance, C Die is the load input parasitic capacitance on the chip.
  • the power loss in the transmission network is one of the factors that affect the power supply, such as battery life.
  • the power supply network shown in Figure 1 since the off-chip voltage regulator is far away from the load, the parasitic capacitance of the transmission network, the input equivalent inductance, the input equivalent resistance, the output equivalent inductance, and the output equivalent resistance are all Larger, so the power loss of the transmission network will be larger.
  • the existing power supply network because the off-chip voltage regulator is far from the load. Therefore, the power consumption in the transmission network is large, which reduces the service life of the power supply, such as the battery.
  • the embodiment of the invention provides an on-chip power supply network for solving the problem of large power loss in the transmission network caused by the existing power supply network.
  • an embodiment of the present invention provides an on-chip power supply network including at least one level on-chip voltage regulator and a load, the on-chip voltage regulator being located on a chip on which the load is located; each of the on-chip voltage regulators The number is at least one; each stage on-chip voltage regulator is connected to at least one on-chip voltage regulator of the subsequent one-stage on-chip voltage regulator; the first-stage on-chip voltage regulator receives the voltage of the power supply output, or receives the off-chip voltage adjustment Voltage output by the device; an on-chip voltage regulator in each of the on-chip voltage regulators other than the first-stage on-chip voltage regulator receives the voltage output from an on-chip voltage regulator in the voltage regulator of the previous stage on-chip; The off-chip voltage regulator is located outside the chip where the load is located; the last-stage on-chip voltage regulator outputs the voltage required by the load to the load; on each stage except the last-stage on-chip voltage regulator An on-chip voltage regulator in the voltage regulator, output to the on-chip voltage
  • the on-chip power supply network includes a two-stage on-chip voltage regulator and the load, and the number of the first-stage on-chip voltage regulators is at least two;
  • the load requires n different voltages, then the number of on-chip voltage regulators on the second stage is n;
  • the ratio of the voltage regulation range of the first-stage on-chip voltage regulator to the voltage regulation range of the second-stage on-chip voltage regulator connected to the first-stage on-chip voltage regulator is not less than a preset value.
  • an on-chip voltage adjustment in each of the on-chip voltage regulators except the last-stage on-chip voltage regulator includes a switch circuit, a drive circuit, a tank circuit, a first filter circuit and a feedback loop;
  • the tank circuit is configured to be connected to the first input power source for charging when the switch circuit is turned on, and Disconnecting from the first input power source to discharge when the switch circuit is turned off;
  • the first filter circuit is configured to filter a voltage output by the energy storage circuit;
  • the feedback loop is configured to use the first reference voltage and the Generating a driving signal according to a voltage outputted by the energy storage circuit, or generating the driving signal according to a first reference voltage and a current flowing through the energy storage circuit;
  • the driving circuit is configured to amplify a driving signal output by the feedback loop And outputting to the switch circuit;
  • the switch circuit is configured to switch between on and off under control of a signal output by the drive circuit; wherein, when on-
  • the switch circuit includes a first p-type power MOS transistor and a first n-type power MOS transistor; the first p-type a gate of the power MOS transistor and a gate of the first n-type power MOS transistor respectively receive a signal output by the driving circuit; a source of the first p-type power MOS transistor and the first n-type power MOS The source of the tube is respectively connected to the first input power source; the drain of the first p-type power MOS transistor is connected to the drain of the first n-type power MOS transistor as an output end of the switch circuit.
  • the feedback loop when the feedback loop is configured to generate the driving signal according to a first reference voltage and a voltage output by the energy storage circuit
  • the feedback loop includes a first resistor, a second resistor, a third resistor, a first capacitor, a first oscillator for outputting the first carrier, a first error amplifier, and a first pulse width modulation comparator; a resistor is connected in series with the second resistor, and one end of the series branch receives the energy storage a voltage output from the circuit, the other end of the series branch is grounded; the first capacitor is coupled between an inverting input of the first error amplifier and an output of the first error amplifier; the first error An inverting input terminal of the amplifier is connected to a connection point of the first resistor and the second resistor through the third resistor; a non-inverting input end of the first error amplifier receives the first reference voltage; An output of an error amplifier is coupled to an inverting input of the first pulse width modulation comparator; a
  • the feedback loop is configured to generate the driving signal according to a first reference voltage and a current flowing by the energy storage circuit
  • the feedback loop includes a fourth resistor, a fifth resistor, a second error amplifier, a compensator, a first comparator, an adder, a first voltage current converter, a second voltage current converter, and a second carrier a second oscillator and a second pulse width modulation comparator;
  • the first voltage current converter is configured to receive a voltage output by the switching circuit to the tank circuit, and convert the received voltage into a current output;
  • the second voltage current converter is configured to receive a voltage of a third carrier and convert the received voltage into a current output;
  • the adder is configured to determine a current and a current output by the first voltage current converter Determining a sum of currents output by the second voltage current converter and outputting a voltage according to a sum of the determined currents;
  • the fourth resistor is in series with the fifth resistor, and one end of the series branch receive
  • the on-chip voltage regulator further includes a second filter circuit; and the second filter circuit includes a second n-type power MOS transistor And a third error amplifier; a source receiving station of the second n-type power MOS transistor a voltage output by the storage circuit, a drain of the second n-type power MOS transistor is grounded, a gate of the second n-type power MOS transistor is connected to an output end of the third error amplifier, the third error An inverting input of the amplifier receives a voltage proportional to a voltage output by the tank circuit, and a non-inverting input of the third error amplifier receives the first reference voltage.
  • an on-chip voltage regulator in each of the on-chip voltage regulators other than the first-stage on-chip voltage regulator includes a second p-type power MOS transistor, a third n-type power MOS transistor, a fourth error amplifier, a sixth resistor, a seventh resistor, an eighth resistor, a second capacitor, and a third capacitor;
  • the seventh resistor is connected in series, one end of the series branch is connected to the drain of the second p-type power MOS transistor, the other end of the series branch is grounded; and the source of the second p-type power MOS transistor is connected to the second Inputting a power supply, a gate of the second p-type power MOS transistor is connected to an output end of the fourth error amplifier; wherein the second input power source is in a voltage regulator of a previous-stage on-chip voltage regulator of the on-chip voltage regulator An output of the on-chip voltage regulator connected to the on-chip voltage regulator;
  • an on-chip voltage adjustment in each of the on-chip voltage regulators other than the first-stage on-chip voltage regulator includes a ninth resistor, a tenth resistor, an eleventh resistor, a fourth capacitor, a fifth capacitor, a fourth n-type power MOS transistor, a digital controller, a third pulse width modulation comparator, and at least one third p-type power a MOS transistor; a source of the at least one third p-type power MOS transistor is connected to a third input power source, and a drain of the at least one third p-type power MOS transistor is connected as an output terminal of the on-chip voltage regulator The gates of the at least one third p-type power MOS transistor respectively receive a control signal output by the digital controller; wherein the third input power source is in a voltage regulator of a previous-stage on-chip voltage regulator of the on-chip voltage regulator An output of the on-chip voltage regulator connected to the on
  • the on-chip voltage regulator for powering the load since the on-chip voltage regulator for powering the load is located on the chip where the load is located, the distance between the on-chip voltage regulator and the load is relatively close, and the on-chip voltage is the same when the load power supply demand is the same.
  • the parasitic capacitance of the transmission network between the regulator and the load, the input equivalent inductance, the input equivalent resistance, the output equivalent inductance, and the output equivalent resistance are less than the parasitic capacitance of the transmission network between the off-chip voltage regulator and the load.
  • Input equivalent inductance, input equivalent resistance, output equivalent inductance, output equivalent resistance therefore, when the load power supply demand is the same, the power loss of the power supply network between the on-chip voltage regulator and the load is less than the off-chip voltage regulator and The power loss of the power supply network between the loads.
  • FIG. 1 is a schematic structural diagram of a power supply network in the prior art
  • FIG. 2 is an equivalent circuit diagram of the power supply network shown in FIG. 1;
  • FIG. 3 is a schematic structural diagram of an on-chip power supply network according to Embodiment 1 of the present invention.
  • FIG. 4 is a schematic structural diagram of an on-chip power supply network according to Embodiment 2 of the present invention.
  • FIG. 5 is a schematic structural diagram of an on-chip power supply network according to Embodiment 3 of the present invention.
  • FIG. 6 is a schematic structural diagram of a voltage regulator in an on-chip power supply network according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a voltage regulator in an on-chip power supply network according to an embodiment of the present disclosure; of two;
  • FIG. 8 is a third schematic structural diagram of a voltage regulator in an on-chip power supply network according to an embodiment of the present invention.
  • FIG. 9 is a fourth schematic structural diagram of a voltage regulator in an on-chip power supply network according to an embodiment of the present disclosure.
  • FIG. 10 is a fifth structural diagram of a voltage regulator in an on-chip power supply network according to an embodiment of the present invention.
  • the on-chip voltage regulator and the load are on the same chip, the distance between the on-chip voltage regulator and the load for powering the load is reduced, and the on-chip voltage regulator and load are reduced. The power loss between the transmission networks.
  • An on-chip power supply network provided by an embodiment of the present invention includes at least one on-chip voltage regulator and a load, and the on-chip voltage regulator is located on a chip on which the load is located;
  • the number of on-chip voltage regulators is at least one; each stage on-chip voltage regulator is connected to at least one on-chip voltage regulator of the subsequent one-stage on-chip voltage regulator;
  • the first-stage on-chip voltage regulator receives the voltage output from the power supply, or receives the voltage output from the off-chip voltage regulator; an on-chip voltage regulator in each of the on-chip voltage regulators except the first-stage on-chip voltage regulator, Receiving a voltage outputted by one of the on-chip voltage regulators of the previous stage; the off-chip voltage regulator is located outside the chip where the load is located;
  • a last stage on-chip voltage regulator outputs the voltage required by the load to the load; an on-chip voltage regulator in each stage of the on-chip voltage regulator except the last stage on-chip voltage regulator, to the on-chip voltage adjustment
  • the subsequent one-stage on-chip voltage regulator connected to the device outputs the voltage required by the voltage regulator on the subsequent one-stage on-chip.
  • FIG. 3 is an on-chip power supply network according to Embodiment 1 of the present invention.
  • the on-chip power supply network shown in FIG. 3 includes only a first-stage on-chip voltage regulator, that is, an on-chip voltage regulator 35.
  • the on-chip voltage regulator 35 receives the voltage V reg output from the off-chip voltage regulator 34, and the on-chip voltage regulator 35 is applied to the load.
  • 36 output voltages V reg-1 , V reg-2 and V reg-3 , load 36 requires three different voltages, on-chip voltage regulator 35 and load 36 on the same chip 32, off-chip voltage regulator 34 on the motherboard At 31, the off-chip voltage regulator 34 receives the voltage V in from the power supply 33.
  • the on-chip power supply network shown in FIG. 4 includes two levels of on-chip voltage regulators, namely a first stage on-chip voltage regulator 351 and a second stage on-chip voltage regulator 352.
  • the first stage on-chip voltage regulator 351 receives an off-chip voltage regulator.
  • first stage on-chip voltage regulator 351 outputs voltage V ivr to three second-stage on-chip voltage regulators 352, respectively, and three second-stage on-chip voltage regulators 352 respectively output voltage V reg to load 36 -1 , V reg-2 and V reg-3 , the load 36 requires three different voltages, the first stage on-chip voltage regulator 351, the second stage on-chip voltage regulator 352 and the load 36 are on the same chip 32, off-chip
  • the voltage regulator 34 is located on the motherboard 31, and the off-chip voltage regulator 34 receives the voltage V in from the power supply 33.
  • the distance load is relatively close.
  • the equivalent resistance R in I is the current on the equivalent resistance R is small.
  • the voltage outputted by the off-chip voltage regulator is greater when the on-chip power supply network provided by the first embodiment of the present invention and the second embodiment of the present invention is used, the voltage output by the off-chip voltage regulator when the power supply network shown in FIG. 1 is used, Therefore, in the case where the off-chip voltage regulator transmission power P is constant, the current flowing through the transmission network when using the on-chip power supply network provided by the first embodiment of the present invention and the second embodiment of the present invention is smaller than that of the power supply network shown in FIG. The current flowing through the transmission network, that is, the current I in the heat loss equation is smaller. Therefore, when the on-chip power supply network provided by the first embodiment of the present invention and the second embodiment of the present invention is used, the heat loss of the transmission network is smaller.
  • the on-chip power supply network may include a multi-stage on-chip voltage regulator, and there may be multiple voltage regulators on each level.
  • the on-chip power supply network includes a two-stage on-chip voltage regulator and the load, and the number of the first-stage on-chip voltage regulators is at least two; if the load requires n different Voltage, the number of on-chip voltage regulators of the second stage is n; the voltage regulation range of each first stage on-chip voltage regulator and the second stage on-chip voltage adjustment of the first stage on-chip voltage regulator
  • the ratio of the voltage regulation range of the device is not less than a preset value, for example, the preset value may be 10.
  • the voltage regulation range of an on-chip voltage regulator is the difference between the voltage of its input and the voltage of its output.
  • FIG. 5 is a schematic diagram of an on-chip power supply network according to Embodiment 3 of the present invention.
  • the on-chip power supply network shown in FIG. 5 includes two levels of on-chip voltage regulators, namely a first stage on-chip voltage regulator 351 and a second stage on-chip voltage regulator 352.
  • the two first stage on-chip voltage regulators 351 receive off-chip respectively.
  • a first-stage on-chip voltage regulator 351 outputs a voltage V ivr-1 to the two second-stage on-chip voltage regulators 352, and the other first-stage on-chip voltage regulator 351
  • the second stage on-chip voltage regulator 352 outputs a voltage V ivr-2
  • the three second stage on-chip voltage regulators 352 respectively output voltages V reg-1 , V reg-2 and V reg-3 to the load 36, and the load 36 requires three A different voltage
  • the first stage on-chip voltage regulator 351, the second stage on-chip voltage regulator 352 and the load 36 are located on the same chip 32
  • the off-chip voltage regulator 34 is located on the motherboard 31, and the off-chip voltage regulator 34 receives The voltage V in which the power supply 33 outputs.
  • the DC voltage set point of the power supply network also affects the heat loss of the transmission network. The lower the voltage at the DC voltage set point, the smaller the heat loss of the transmission network.
  • the supply voltage of the corresponding load decreases.
  • the main power consumption in the chip is determined by the dynamic power consumption and static power consumption of the transistor.
  • the dynamic power consumption is the square function of the supply voltage; the static power consumption is the multiple function of the supply voltage. Therefore, lowering the DC voltage set point of the power supply network can reduce the power consumption of the chip at a lower rate than the quadratic.
  • the on-chip power supply network provided by the third embodiment of the present invention
  • two first-stage on-chip voltage regulators 351 are used to supply power to the three second-stage on-chip voltage regulators 352
  • three second-stage on-chip voltage regulators 352 are assumed to be output.
  • the voltages are 1V, 1.5V and 2V, respectively, and a first-stage on-chip voltage regulator 351 supplies power to a second-stage on-chip voltage regulator 352 having an output of 1V and a second-stage on-chip voltage regulator 352 having an output of 1.5V.
  • the output voltage of the first-stage on-chip voltage regulator 351 only needs to be greater than 1.5V; the other first-stage on-chip voltage regulator 351 supplies power to the second-stage on-chip voltage regulator 352 whose output is 2V, then the first The on-chip voltage regulator 351 needs to output a ground voltage greater than 2V.
  • the on-chip power supply network provided by the second embodiment of the present invention
  • only one first-stage on-chip voltage regulator 351 is used to supply power to the three second-stage on-chip voltage regulators 352
  • three third-stage on-chip voltage regulators 352 are assumed to be output.
  • the voltages are 1V, 1.5V and 2V, respectively, and the voltage output by the first-stage on-chip voltage regulator 351 needs to be greater than 2V.
  • the on-chip power supply network provided in Embodiment 3 of the present invention can reduce the DC voltage setting point of the system, thereby reducing the power consumption of the chip and further reducing the transmission network. Heat loss.
  • one of the on-chip voltage regulators of each stage except the last-stage on-chip voltage regulator includes a switch circuit 61.
  • the storage circuit 63 is configured to be charged with the first input power source 66 when the switch circuit 61 is turned on to be charged, and is disconnected from the first input power source 66 to discharge when the switch circuit 61 is turned off;
  • a first filter circuit 64 configured to filter a voltage output by the storage circuit 63
  • the driving circuit 62 is configured to amplify the driving signal outputted by the feedback loop 65 and output it to the switching circuit 61;
  • a switch circuit 61 for switching between on and off under the control of a signal output by the drive circuit 62;
  • the first input power 66 is the power supply; when the on-chip voltage regulator is on the first stage chip When the voltage regulator and the on-chip voltage regulator receive the voltage output by the off-chip voltage regulator, the first input power source 66 is the output of the off-chip voltage regulator; when the on-chip voltage regulator is other than the first-stage on-chip voltage regulator The on-chip voltage regulator, the first input power supply 66 is the output of the on-chip voltage regulator connected to the on-chip voltage regulator in the on-chip voltage regulator of the on-chip voltage regulator.
  • the storage circuit 63 can be an inductor. Of course, other circuits capable of charging/discharging can be used.
  • the first filter circuit 64 can be a capacitor or a parallel structure of a resistor and a capacitor. In the following, only the tank circuit 63 is used as the inductor L S , and the first filter circuit is a parallel structure of the resistor R f and the capacitor C f as an example.
  • the switch circuit includes a first p-type power MOS transistor pM1 and a first n-type power MOS transistor nM1; a gate of the first p-type power MOS transistor pM1 and a first n-type The gate of the power MOS transistor nM1 receives the signal outputted by the driving circuit 62; the source of the first p-type power MOS transistor pM1 and the source of the first n-type power MOS transistor nM1 are respectively connected to the first input power source 66; the first p The drain of the type power MOS transistor pM1 is connected to the drain of the first n-type power MOS transistor nM1, and the output terminal of the switching circuit is connected to the tank circuit, that is, the inductor L s .
  • the feedback loop when the feedback loop is used to generate a driving signal according to the first reference voltage V ref1 and the voltage output by the tank circuit, as shown in FIG. 7, the feedback loop includes a first resistor R1, a second resistor R2, and a third resistor. R3, a first capacitor C1, a first oscillator 71 for outputting a first carrier, a first error amplifier EA1 and a first pulse width modulation comparator PWMC1;
  • the first resistor R1 is connected in series with the second resistor R2, and one end of the series branch receives the energy storage circuit, that is, the voltage output by the inductor L s , and the other end of the series branch is grounded;
  • the first capacitor C1 is connected between the inverting input terminal of the first error amplifier EA1 and the output terminal of the first error amplifier EA1;
  • the inverting input terminal of the first error amplifier EA1 is connected to the connection point of the first resistor R1 and the second resistor R2 through the third resistor R3; the non-inverting input terminal of the first error amplifier EA1 receives the first reference voltage V ref1 ;
  • the output of the amplifier EA1 is connected to the inverting input terminal of the first pulse width modulation comparator PWMC1; the non-inverting input terminal of the first pulse width modulation comparator PWMC1 receives the first carrier output by the first oscillator 71; the first pulse width modulation comparison
  • the PWMC1 outputs a drive signal to the drive circuit 62 through its output.
  • the feedback loop when the feedback loop is used to generate a driving signal according to the first reference voltage V ref1 and the current flowing through the tank circuit, as shown in FIG. 8 , the feedback loop includes a fourth resistor R4 and a fifth resistor R5. a second error amplifier EA2, a compensator 82, a first comparator Com1, an adder 81, a first voltage current converter V/I1, a second voltage current converter V/I2, a second oscillator 83 outputting a second carrier, and a second pulse width modulation comparator PWMC2;
  • the first voltage current converter V/I1 is configured to receive a voltage output by the switching circuit to the energy storage circuit, and convert the received voltage into a current output;
  • a second voltage current converter V/I2 for receiving a voltage of the third carrier Ca and converting the received voltage into a current output
  • the adder 81 is configured to determine a sum of a current output by the first voltage current converter V/I1 and a current output by the second voltage current converter V/I2, and output a voltage according to the determined sum of the currents;
  • the fourth resistor R4 is connected in series with the fifth resistor R5, and one end of the series branch receives the voltage output by the tank circuit, and the other end of the series branch is grounded;
  • the inverting input terminal of the second error amplifier EA2 is connected to the connection point of the fourth resistor R4 and the fifth resistor R5; the non-inverting input terminal of the second error amplifier EA2 receives the first reference voltage Vref1 ; the output terminal of the second error amplifier EA2 Connecting an inverting input terminal of the first comparator Com1;
  • the compensator 82 is connected between the inverting input of the second error amplifier EA2 and the output of the second error amplifier EA2; the compensator 82 is configured to compensate the voltage output by the second error amplifier EA2;
  • the non-inverting input of the first comparator Com1 receives the voltage output by the adder 81, the output of the first comparator Com1 is connected to the inverting output of the second pulse width modulation comparator PWMC2; the in-phase of the second pulse width modulation comparator PWMC2
  • the output terminal receives the second carrier output by the second oscillator 83; the second pulse width modulation comparator PWM2 outputs a drive signal to the drive circuit 62 through its output terminal.
  • an on-chip voltage regulator of each level of the on-chip voltage regulator except the last-stage on-chip voltage regulator is further
  • the second filter circuit includes a second n-type power MOS transistor nM2 and a third error amplifier EA3;
  • the source of the second n-type power MOS transistor nM2 receives the storage circuit, that is, the voltage output from the inductor L s , the drain of the second n-type power MOS transistor nM2 is grounded, and the gate of the second n-type power MOS transistor nM2 is connected.
  • the output terminal of the third error amplifier EA3, the inverting input terminal of the third error amplifier EA3 receives a voltage proportional to the voltage output by the tank circuit, and in FIG. 7, the connection point of the first resistor R1 and the second resistor R2 is connected.
  • the voltage, in FIG. 8, is the voltage of the connection point of the fourth resistor R4 and the fifth resistor R5, and the non-inverting input terminal of the third error amplifier EA3 receives the first reference voltage Vref1 .
  • an on-chip voltage regulator of each of the on-chip voltage regulators other than the first-stage on-chip voltage regulator includes a second p-type power MOS transistor pM2, a third n-type power MOS transistor nM3, fourth error amplifier EA4, sixth resistor R6, seventh resistor R7, eighth resistor R8, second capacitor C2 and third capacitor C3;
  • the sixth resistor R6 is connected in series with the seventh resistor R7, one end of the series branch is connected to the drain of the second p-type power MOS transistor pM2, and the other end of the series branch is grounded; the source of the second p-type power MOS transistor pM2 Connected to the second input power source 91, the gate of the second p-type power MOS transistor pM2 is connected to the output terminal of the fourth error amplifier EA4; wherein, the second input power source 91 is the previous one-stage on-chip voltage regulator of the on-chip voltage regulator An output of an on-chip voltage regulator connected to the on-chip voltage regulator;
  • the drain of the second p-type power MOS transistor pM2 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is grounded;
  • the inverting input terminal of the fourth error amplifier EA4 receives the second reference signal V ref2 , and the non-inverting input terminal of the fourth error amplifier EA4 is connected to the connection point of the sixth resistor R6 and the seventh resistor R7;
  • the gate of the third n-type power MOS transistor nM3 is connected to the output terminal of the fourth error amplifier EA4, and the source of the third n-type power MOS transistor nM3 is grounded through the parallel branch of the eighth resistor R8 and the third capacitor C3 in parallel.
  • the drain of the third n-type power MOS transistor nM3 is connected to the drain of the second p-type power MOS transistor pM2, and the drain of the second p-type power MOS transistor pM2 is the output terminal OUT of the on-chip voltage regulator.
  • an on-chip voltage regulator of each of the on-chip voltage regulators other than the first-stage on-chip voltage regulator includes a ninth resistor R9, a tenth resistor R10, and an eleventh resistor R11 as shown in FIG. a fourth capacitor C4, a fifth capacitor C5, a fourth n-type power MOS transistor nM4, a digital controller 92, a third pulse width modulation comparator PWMC3, and at least one third p-type power MOS transistor pM3;
  • the source of the at least one third p-type power MOS transistor pM3 is connected to the third input power source 111, and the drain of the at least one third p-type power MOS transistor pM3 is connected as the output terminal OUT of the on-chip voltage regulator
  • the gates of the at least one third p-type power MOS transistor respectively receive the control signals output by the digital controller 92; wherein the third input power source 111 is in the previous stage on-chip voltage regulator of the on-chip voltage regulator The output of the on-chip voltage regulator connected to the on-chip voltage regulator;
  • the ninth resistor R9 is connected in series with the tenth resistor R10, one end of the series branch is connected to the output terminal OUT of the on-chip voltage regulator, and the other end of the series branch is grounded;
  • One end of the fourth capacitor C4 is connected to the output terminal OUT of the on-chip voltage regulator, and the other end of the fourth capacitor C4 is grounded;
  • the digital controller 92 is configured to output a control signal according to the signal output by the third pulse width modulation comparator PWMC3, thereby controlling the MOS transistor in the at least one third p-type power MOS transistor pM3 between on and off. Switch
  • the third pulse width modulator comparator PWMC3 noninverting input terminal receives the third reference signal V ref3, the inverting input of the third pulse width modulator comparator PWMC3 the connection point of the ninth resistor R9 is connected to the tenth resistor R10;
  • the drain of the fourth n-type power MOS transistor nM4 is connected to the output of the on-chip voltage regulator OUT, the source of the fourth n-type power MOS transistor nM4 is grounded through the parallel branch of the eleventh resistor R11 and the fifth capacitor C5 in parallel, and the third pulse width modulation comparison of the gate connection of the fourth n-type power MOS transistor nM4 The output of PWMC3.
  • modules in the apparatus in the embodiments may be distributed in the apparatus of the embodiment according to the description of the embodiments, or the corresponding changes may be located in one or more apparatuses different from the embodiment.
  • the modules of the above embodiments may be combined into one module, or may be further split into multiple sub-modules.

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Abstract

一种片上供电网络，用以解决现有的供电网络所导致的传输网络中的电量损耗较大的问题。片上供电网络包括至少一级片上电压调整器（35）和负载（36）；每一级片上电压调整器连接其后一级片上电压调整器中的至少一个片上电压调整器；第一级片上电压调整器接收供电电源（33）输出的电压，或者接收片外电压调整器（34）输出的电压；除第一级片上电压调整器以外的每一级片上电压调整器中的一个片上电压调整器，接收前一级片上电压调整器中的一个片上电压调整器输出的电压；除最后一级片上电压调整器以外的每一级片上电压调整器中的一个片上电压调整器，向该片上电压调整器连接的后一级片上电压调整器输出后一级片上电压调整器所需的电压。

Description

一种片上供电网络
本申请要求于2014年6月17日提交中国专利局、申请号为201410270308.8、发明名称为“一种片上供电网络”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及电力电子技术领域，尤其涉及一种片上供电网络。
背景技术
随着半导体集成电路工艺技术的发展，电路功耗问题成了困扰散热、封装和便携的难题。自动调整电压频率的技术是一种最有效的节能方法。如今，多核CPU架构应用应成为主流，每个CPU的低功耗技术也成为普遍的自动调整电压频率的技术。
在供电系统中，很重要的器件即是电压调整器，电压调整器能够调整接收到的电压，从而向其连接的电路输出该电路所需的电压。伴随着工艺节点的持续缩小，芯片设计面积密度迅速上升，三个重要条件制约着现今电源设计、电压调整的发展：片上集成性，能源效率，以及电源完整性。尤其是电源的完整性，决定着负载模块的功能性，逻辑性，以及功耗问题。低电源完整性，即纹波大，尖刺脉冲多等，直接会给系统带来沉重负担，不光是在系统响应速度，及正确性，还有整个系统的能量损耗上。
图1为现有的供电网络，在该供电网络中，负载在芯片上(或为芯片内)，而负载的供电则由片外的电压调整器(off-chip voltage regulator)来完成。其中，片外电压调整器的供电由外部电池或者其他方式来提供。片外电压调整器可以是单路输出以供给负载，也可以是多路输出以供给负载，如图1中为多路输出，即Vreg-1，Vreg-2，Vreg-3。在多路电压输出的情况之下，片外的电压调整器可能是多个。
图2为图1所示的供电网络的等效电路图。其中，LPB为母板上的片外电压调整器的输出等效电感，RPB为母板上的片外电压调整器的输出等效电阻，ESLVR为母板上的片外电压调整器的输出寄生电容的等效电感，ESRVR 为母板上的片外电压调整器的输出寄生电容的等效电阻，CVR为母板上的片外电压调整器的输出寄生电容；LPP1为传输封装的输入等效电感，RPP1为传输封装的输入等效电阻，LPP2为传输封装的输出等效电感，RPP2为传输封装的输出等效电阻，ESLPKG为传输封装的寄生电容的等效电感，ESRPKG为传输封装的寄生电容的等效电阻，CPKG为传输封装的寄生电容；RDie为芯片上的负载的输入等效电阻，ESRDie为芯片上的负载的输入寄生电容的等效电阻，CDie为芯片上的负载输入寄生电容。
由于在供电网络中，传输网络中的电量损耗是影响供电电源、如电池使用寿命的因素之一。当采用图1所示的供电网络时，由于片外电压调整器距离负载较远，因此，传输网络的寄生电容，输入等效电感、输入等效电阻、输出等效电感、输出等效电阻都比较大，因此传输网络的电量损耗会比较大。
综上所述，现有的供电网络，由于片外电压调整器距离负载较远。因此，传输网络中的电量损耗较大，这会降低供电电源、如电池的使用寿命。
发明内容
本发明实施例提供了一种片上供电网络，用以解决现有的供电网络所导致的传输网络中的电量损耗较大的问题。
第一方面，本发明实施例提供一种片上供电网络，包括至少一级片上电压调整器和负载，所述片上电压调整器位于所述负载所在的芯片上；每一级片上电压调整器的个数至少为一个；每一级片上电压调整器连接其后一级片上电压调整器中的至少一个片上电压调整器；第一级片上电压调整器接收供电电源输出的电压，或者接收片外电压调整器输出的电压；除第一级片上电压调整器以外的每一级片上电压调整器中的一个片上电压调整器，接收前一级片上电压调整器中的一个片上电压调整器输出的电压；所述片外电压调整器位于所述负载所在的芯片之外；最后一级片上电压调整器向所述负载输出所述负载所需的电压；除最后一级片上电压调整器以外的每一级片上电压调整器中的一个片上电压调整器，向该片上电压调整器连接的后一级片上电压调整器输出所述后一级片上电压调整器所需的电压。
结合第一方面，在第一种可能的实现方式中，所述片上供电网络包括两级片上电压调整器和所述负载，第一级片上电压调整器的个数至少为两个；若所述负载需要n个不同的电压，则第二级片上电压调整器的个数为n；每 个第一级片上电压调整器的调压范围与该第一级片上电压调整器连接的第二级片上电压调整器的调压范围之比不小于预设值。
结合第一方面或者第一方面的第一种可能的实现方式，在第二种可能的实现方式中，除最后一级片上电压调整器以外的每一级片上电压调整器中的一个片上电压调整器包括开关电路、驱动电路、储能电路、第一滤波电路和反馈环；所述储能电路，用于在所述开关电路导通时与第一输入电源接通以充电，并在所述开关电路关断时与第一输入电源断开以放电；所述第一滤波电路，用于对所述储能电路输出的电压进行滤波；所述反馈环，用于根据第一参考电压和所述储能电路输出的电压生成驱动信号，或者根据第一参考电压和所述储能电路流过的电流生成所述驱动信号；所述驱动电路，用于将所述反馈环输出的驱动信号放大，并输出给所述开关电路；所述开关电路，用于在所述驱动电路输出的信号的控制下在导通和关断之间切换；其中，当片上电压调整器为第一级片上电压调整器、且该片上电压调整器接收所述供电电源输出的电压时，所述第一输入电源为所述供电电源；当片上电压调整器为第一级片上电压调整器、且该片上电压调整器接收所述片外电压调整器输出的电压时，所述第一输入电源为所述片外电压调整器的输出；当片上电压调整器为除第一级片上电压调整器以外的片上电压调整器时，所述第一输入电源为该片上电压调整器的前一级片上电压调整器中与该片上电压调整器相连的片上电压调整器的输出。
结合第一方面的第二种可能的实现方式，在第三种可能的实现方式中，所述开关电路包括第一p型功率MOS管和第一n型功率MOS管；所述第一p型功率MOS管的栅极和所述第一n型功率MOS管的栅极分别接收所述驱动电路输出的信号；所述第一p型功率MOS管的源极与所述第一n型功率MOS管的源极分别连接所述第一输入电源；所述第一p型功率MOS管的漏极与所述第一n型功率MOS管的漏极相连，作为所述开关电路的输出端。
结合第一方面的第二种可能的实现方式，在第四种可能的实现方式中，当所述反馈环用于根据第一参考电压和所述储能电路输出的电压生成所述驱动信号时，所述反馈环包括第一电阻、第二电阻、第三电阻、第一电容、用于输出第一载波的第一振荡器、第一误差放大器和第一脉冲宽度调制比较器；所述第一电阻与所述第二电阻串联，该串联支路的一端接收所述储能电 路输出的电压，该串联支路的另一端接地；所述第一电容连接在所述第一误差放大器的反相输入端与所述第一误差放大器的输出端之间；所述第一误差放大器的反相输入端通过所述第三电阻连接所述第一电阻和所述第二电阻相连的连接点；所述第一误差放大器的同相输入端接收所述第一参考电压；所述第一误差放大器的输出端连接所述第一脉冲宽度调制比较器的反相输入端；所述第一脉冲宽度调制比较器的同相输入端接收所述第一振荡器输出的第一载波；所述第一脉冲宽度调制比较器通过其输出端向所述驱动电路输出所述驱动信号。
结合第一方面的第二种可能的实现方式，在第五种可能的实现方式中，当所述反馈环用于根据第一参考电压和所述储能电路流过的电流生成所述驱动信号时，所述反馈环包括第四电阻、第五电阻、第二误差放大器、补偿器、第一比较器、加法器、第一电压电流转换器、第二电压电流转换器、输出第二载波的第二振荡器和第二脉冲宽度调制比较器；所述第一电压电流转换器，用于接收所述开关电路输出给所述储能电路的电压，并将接收到的电压转换为电流输出；所述第二电压电流转换器，用于接收第三载波的电压，并将接收到的电压转换为电流输出；所述加法器，用于确定所述第一电压电流转换器输出的电流与所述第二电压电流转换器输出的电流之和，并根据确定的电流之和输出电压；所述第四电阻与所述第五电阻串联，该串联支路的一端接收所述储能电路输出的电压，该串联支路的另一端接地；所述第二误差放大器的反相输入端连接所述第四电阻和所述第五电阻相连的连接点；所述第二误差放大器的同相输入端接收所述第一参考电压；所述第二误差放大器的输出端连接所述第一比较器的反相输入端；所述补偿器连接在所述第二误差放大器的反相输入端和所述第二误差放大器的输出端之间；所述补偿器用于对所述第二误差放大器输出的电压进行补偿；所述第一比较器的同相输入端接收所述加法器输出的电压，所述第一比较器的输出端连接所述第二脉冲宽度调制比较器的反相输出端；所述第二脉冲宽度调制比较器的同相输出端接收所述第二振荡器输出的第二载波；所述第二脉冲宽度调制比较器通过其输出端向所述驱动电路输出所述驱动信号。
结合第一方面的第二种可能的实现方式，在第六种可能的实现方式中，所述片上电压调整器还包括第二滤波电路；所述第二滤波电路包括第二n型功率MOS管和第三误差放大器；所述第二n型功率MOS管的源极接收所 述储能电路输出的电压，所述第二n型功率MOS管的漏极接地，所述第二n型功率MOS管的栅极连接所述第三误差放大器的输出端，所述第三误差放大器的反相输入端接收与所述储能电路输出的电压成正比的电压，所述第三误差放大器的同相输入端接收所述第一参考电压。
结合第一方面或者第一方面的第一种可能的实现方式，在第七种可能的实现方式中，除第一级片上电压调整器以外的每一级片上电压调整器中的一个片上电压调整器包括第二p型功率MOS管、第三n型功率MOS管、第四误差放大器、第六电阻、第七电阻、第八电阻、第二电容和第三电容；所述第六电阻与所述第七电阻串联，该串联支路的一端连接所述第二p型功率MOS管的漏极，该串联支路的另一端接地；所述第二p型功率MOS管的源极连接第二输入电源，所述第二p型功率MOS管的栅极连接所述第四误差放大器的输出端；其中，所述第二输入电源为该片上电压调整器的前一级片上电压调整器中与该片上电压调整器相连的片上电压调整器的输出；所述第二p型功率MOS管的漏极连接所述第二电容的一端，所述第二电容的另一端接地；所述第四误差放大器的反相输入端接收第二参考信号，所述第四误差放大器的同相输入端连接所述第六电阻与所述第七电阻相连的连接点；所述第三n型功率MOS管的栅极连接所述第四误差放大器的输出端，所述第三n型功率MOS管的源极通过所述第八电阻和所述第三电容并联后的并联支路接地，所述第三n型功率MOS管的漏极与所述第二p型功率MOS管的漏极相连，所述第二p型功率MOS管的漏极为该片上电压调整器的输出端。
结合第一方面或者第一方面的第一种可能的实现方式，在第八种可能的实现方式中，除第一级片上电压调整器以外的每一级片上电压调整器中的一个片上电压调整器包括第九电阻、第十电阻、第十一电阻、第四电容、第五电容、第四n型功率MOS管、数字控制器、第三脉冲宽度调制比较器和至少一个第三p型功率MOS管；所述至少一个第三p型功率MOS管的源极均连接第三输入电源，所述至少一个第三p型功率MOS管的漏极相连，作为该片上电压调整器的输出端，所述至少一个第三p型功率MOS管的栅极分别接收所述数字控制器输出的控制信号；其中，所述第三输入电源为该片上电压调整器的前一级片上电压调整器中与该片上电压调整器相连的片上电压调整器的输出；所述第九电阻与所述第十电阻串联，该串联支路的一端 连接该片上电压调整器的输出端，该串联支路的另一端接地；所述第四电容的一端连接该片上电压调整器的输出端，所述第四电容的另一端接地；所述数字控制器，用于根据所述第三脉冲宽度调制比较器输出的信号，输出控制信号；所述第三脉冲宽度调制比较器的同相输入端接收第三参考信号，所述第三脉冲宽度调制比较器的反相输入端连接所述第九电阻与所述第十电阻相连的连接点；所述第四n型功率MOS管的漏极连接该片上电压调整器的输出端，所述第四n型功率MOS管的源极通过所述第十一电阻和所述第五电容并联后的并联支路接地，所述第四n型功率MOS管的栅极连接所述第三脉冲宽度调制比较器的输出端。
本发明实施例的有益效果包括：
本发明实施例提供的片上供电网络，由于为负载供电的片上电压调整器位于负载所在的芯片上，因此，片上电压调整器与负载之间的距离较近，在负载供电需求相同时，片上电压调整器与负载之间的传输网络的寄生电容，输入等效电感、输入等效电阻、输出等效电感、输出等效电阻都会小于片外电压调整器与负载之间的传输网络的寄生电容，输入等效电感、输入等效电阻、输出等效电感、输出等效电阻，因此，在负载供电需求相同时，片上电压调整器与负载之间的供电网络的电量损耗小于片外电压调整器与负载之间的供电网络的电量损耗。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对本发明实施例中所需要使用的附图作简单地介绍，显而易见地，下面所描述的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中的供电网络的结构示意图；
图2为图1所示的供电网络的等效电路图；
图3为本发明实施例一提供的片上供电网络的结构示意图；
图4为本发明实施例二提供的片上供电网络的结构示意图；
图5为本发明实施例三提供的片上供电网络的结构示意图；
图6为本发明实施例提供的片上供电网络中的电压调整器的结构示意图之一；
图7为本发明实施例提供的片上供电网络中的电压调整器的结构示意图 之二；
图8为本发明实施例提供的片上供电网络中的电压调整器的结构示意图之三；
图9为本发明实施例提供的片上供电网络中的电压调整器的结构示意图之四；
图10为本发明实施例提供的片上供电网络中的电压调整器的结构示意图之五。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供的片上供电网络，由于片上电压调整器与负载位于同一芯片上，因此，减小了为负载供电的片上电压调整器与负载之间的距离，降低了片上电压调整器与负载之间的传输网络的电量损耗。
下面结合说明书附图，对本发明实施例提供的一种片上供电网络的具体实施方式进行说明。
本发明实施例提供的一种片上供电网络，包括至少一级片上电压调整器和负载，所述片上电压调整器位于所述负载所在的芯片上；
每一级片上电压调整器的个数至少为一个；每一级片上电压调整器连接其后一级片上电压调整器中的至少一个片上电压调整器；
第一级片上电压调整器接收供电电源输出的电压，或者接收片外电压调整器输出的电压；除第一级片上电压调整器以外的每一级片上电压调整器中的一个片上电压调整器，接收前一级片上电压调整器中的一个片上电压调整器输出的电压；所述片外电压调整器位于所述负载所在的芯片之外；
最后一级片上电压调整器向所述负载输出所述负载所需的电压；除最后一级片上电压调整器以外的每一级片上电压调整器中的一个片上电压调整器，向该片上电压调整器连接的后一级片上电压调整器输出所述后一级片上电压调整器所需的电压。
图3为本发明实施例一提供的片上供电网络。图3所示的片上供电网络 中仅包括一级片上电压调整器，即片上电压调整器35，片上电压调整器35接收片外电压调整器34输出的电压Vreg，片上电压调整器35向负载36输出电压Vreg-1，Vreg-2和Vreg-3，负载36需要三个不同的电压，片上电压调整器35与负载36位于同一芯片32上，片外电压调整器34位于母板31上，片外电压调整器34接收供电电源33输出的电压Vin。
图4为本发明实施例二提供的片上供电网络。图4所示的片上供电网络中包括两级片上电压调整器，即第一级片上电压调整器351和第二级片上电压调整器352，第一级片上电压调整器351接收片外电压调整器34输出的电压Vreg，第一级片上电压调整器351分别向三个第二级片上电压调整器352输出电压Vivr，三个第二级片上电压调整器352分别向负载36输出电压Vreg-1，Vreg-2和Vreg-3，负载36需要三个不同的电压，第一级片上电压调整器351、第二级片上电压调整器352与负载36位于同一芯片32上，片外电压调整器34位于母板31上，片外电压调整器34接收供电电源33输出的电压Vin。
本发明实施例一和本发明实施例二提供的片上供电网络，由于第一级片上电压调整器和第二级片上电压调整器都与负载位于同一芯片上，因此，距离负载较近，因此，其等效的寄生电容和等效电阻及等效电感值都较小，也就是电路的热损耗方程Pt-loss＝I2R(Pt-loss为等效电阻R上的热损耗值，I为等效电阻R上的电流)中的等效电阻R较小。另外，由于采用本发明实施例一和本发明实施例二提供的片上供电网络时片外电压调整器输出的电压要大于，采用图1所示的供电网络时片外电压调整器输出的电压，因此，在片外电压调整器传送功率P恒定的情况之下，采用本发明实施例一和本发明实施例二提供的片上供电网络时流过传输网络的电流小于采用图1所示的供电网络时流过传输网络的电流，即热损耗方程中的电流I要更小。因此，采用本发明实施例一和本发明实施例二提供的片上供电网络时，传输网络的热损耗会更小。
当然，本发明实施例提供的片上供电网络中可以包括多级片上电压调整器，每一级片上电压调整器可以有多个。
可选地，本发明实施例提供的片上供电网络，包括两级片上电压调整器和所述负载，第一级片上电压调整器的个数至少为两个；若所述负载需要n个不同的电压，则第二级片上电压调整器的个数为n；每个第一级片上电压调整器的调压范围与该第一级片上电压调整器连接的第二级片上电压调整 器的调压范围之比不小于预设值，例如，所述预设值可以为10。其中，一个片上电压调整器的调压范围为其输入的电压与其输出的电压之差。
图5为本发明实施例三提供的片上供电网络。图5所示的片上供电网络中包括两级片上电压调整器，即第一级片上电压调整器351和第二级片上电压调整器352，两个第一级片上电压调整器351分别接收片外电压调整器34输出的电压Vreg，一个第一级片上电压调整器351分别向两个第二级片上电压调整器352输出电压Vivr-1，另一个第一级片上电压调整器351向一个第二级片上电压调整器352输出电压Vivr-2，三个第二级片上电压调整器352分别向负载36输出电压Vreg-1，Vreg-2和Vreg-3，负载36需要三个不同的电压，第一级片上电压调整器351、第二级片上电压调整器352与负载36位于同一芯片32上，片外电压调整器34位于母板31上，片外电压调整器34接收供电电源33输出的电压Vin。
另外，供电网络的直流电压设置点也会影响传输网络的热损耗，直流电压设置点的电压越低，传输网络的热损耗越小。
另外，随着供电网络的直流电压设置点的降低，相应的负载的供电电压也会降低。而在芯片中主要的功耗由晶体管的动态功耗和静态功耗来决定。其中动态功耗是供电电压的平方函数；静态功耗则是供电电压的多次方函数。因此，降低供电网络的直流电压设置点可以使芯片的功耗以高于二次方的降低速率来降低。
采用本发明实施例三提供的片上供电网络时，由于采用两个第一级片上电压调整器351为三个第二级片上电压调整器352供电，假设三个第二级片上电压调整器352输出的电压分别为1V、1.5V和2V，其中一个第一级片上电压调整器351为输出为1V的第二级片上电压调整器352和输出为1.5V的第二级片上电压调整器352供电，那么该第一级片上电压调整器351输出地电压仅需要大于1.5V即可；另一个第一级片上电压调整器351为输出为2V的第二级片上电压调整器352供电，那么该第一级片上电压调整器351输出地电压需要大于2V。
采用本发明实施例二提供的片上供电网络时，由于仅采用一个第一级片上电压调整器351为三个第二级片上电压调整器352供电，假设三个第二级片上电压调整器352输出的电压分别为1V、1.5V和2V，那么这个第一级片上电压调整器351输出的电压需要大于2V。
因此，相比于本发明实施例二提供的片上供电网络，本发明实施例三提供的片上供电网络可以降低系统的直流电压设置点，因此，降低了芯片的功耗，并进一步降低传输网络的热损耗。
可选地，如图6所示，在本发明实施例提供的片上供电网络中，除最后一级片上电压调整器以外的每一级片上电压调整器中的一个片上电压调整器包括开关电路61、驱动电路62、储能电路63、第一滤波电路64和反馈环65；
储能电路63，用于在开关电路61导通时与第一输入电源66接通以充电，并在开关电路61关断时与第一输入电源66断开以放电；
第一滤波电路64，用于对储能电路63输出的电压进行滤波；
反馈环65，用于根据第一参考电压Vref1和储能电路63输出的电压生成驱动信号，或者根据第一参考电压Vref1和储能电路63流过的电流生成驱动信号；
驱动电路62，用于将反馈环65输出的驱动信号放大，并输出给开关电路61；
开关电路61，用于在驱动电路62输出的信号的控制下在导通和关断之间切换；
其中，当片上电压调整器为第一级片上电压调整器、且该片上电压调整器接收供电电源输出的电压时，第一输入电源66为该供电电源；当片上电压调整器为第一级片上电压调整器、且该片上电压调整器接收片外电压调整器输出的电压时，第一输入电源66为片外电压调整器的输出；当片上电压调整器为除第一级片上电压调整器以外的片上电压调整器时，第一输入电源66为该片上电压调整器的前一级片上电压调整器中与该片上电压调整器相连的片上电压调整器的输出。
其中，储能电路63可以为电感，当然，也可以为其它能够实现充电/放电的电路；第一滤波电路64可以为电容，也可以为电阻与电容的并联结构。下面仅以储能电路63为电感LS，第一滤波电路为电阻Rf和电容Cf的并联结构为例进行说明。
可选地，如图7和图8所示，开关电路包括第一p型功率MOS管pM1和第一n型功率MOS管nM1；第一p型功率MOS管pM1的栅极和第一n型功率MOS管nM1的栅极分别接收驱动电路62输出的信号；第一p型功 率MOS管pM1的源极与第一n型功率MOS管nM1的源极分别连接第一输入电源66；第一p型功率MOS管pM1的漏极与第一n型功率MOS管nM1的漏极相连，作为开关电路的输出端连接储能电路，即电感Ls。
可选地，反馈环用于根据第一参考电压Vref1和储能电路输出的电压生成驱动信号时，如图7所示，该反馈环包括第一电阻R1、第二电阻R2、第三电阻R3、第一电容C1、用于输出第一载波的第一振荡器71、第一误差放大器EA1和第一脉冲宽度调制比较器PWMC1；
第一电阻R1与第二电阻R2串联，该串联支路的一端接收储能电路，即电感Ls输出的电压，该串联支路的另一端接地；
第一电容C1连接在第一误差放大器EA1的反相输入端与第一误差放大器EA1的输出端之间；
第一误差放大器EA1的反相输入端通过第三电阻R3连接第一电阻R1和第二电阻R2相连的连接点；第一误差放大器EA1的同相输入端接收第一参考电压Vref1；第一误差放大器EA1的输出端连接第一脉冲宽度调制比较器PWMC1的反相输入端；第一脉冲宽度调制比较器PWMC1的同相输入端接收第一振荡器71输出的第一载波；第一脉冲宽度调制比较器PWMC1通过其输出端向驱动电路62输出驱动信号。
可选地，当反馈环用于根据第一参考电压Vref1和储能电路流过的电流生成驱动信号时，如图8所示，该反馈环包括第四电阻R4、第五电阻R5、第二误差放大器EA2、补偿器82、第一比较器Com1、加法器81、第一电压电流转换器V/I1、第二电压电流转换器V/I2、输出第二载波的第二振荡器83和第二脉冲宽度调制比较器PWMC2；
第一电压电流转换器V/I1，用于接收开关电路输出给储能电路的电压，并将接收到的电压转换为电流输出；
第二电压电流转换器V/I2，用于接收第三载波Ca的电压，并将接收到的电压转换为电流输出；
加法器81，用于确定第一电压电流转换器V/I1输出的电流与第二电压电流转换器V/I2输出的电流之和，并根据确定的电流之和输出电压；
第四电阻R4与第五电阻R5串联，该串联支路的一端接收储能电路输出的电压，该串联支路的另一端接地；
第二误差放大器EA2的反相输入端连接第四电阻R4和第五电阻R5相 连的连接点；第二误差放大器EA2的同相输入端接收第一参考电压Vref1；第二误差放大器EA2的输出端连接第一比较器Com1的反相输入端；
补偿器82连接在第二误差放大器EA2的反相输入端和第二误差放大器EA2的输出端之间；补偿器82用于对第二误差放大器EA2输出的电压进行补偿；
第一比较器Com1的同相输入端接收加法器81输出的电压，第一比较器Com1的输出端连接第二脉冲宽度调制比较器PWMC2的反相输出端；第二脉冲宽度调制比较器PWMC2的同相输出端接收第二振荡器83输出的第二载波；第二脉冲宽度调制比较器PWM2通过其输出端向驱动电路62输出驱动信号。
可选地，如图7或图8所示，在本发明实施例提供的片上供电网络中，除最后一级片上电压调整器以外的每一级片上电压调整器中的一个片上电压调整器还包括第二滤波电路；该第二滤波电路包括第二n型功率MOS管nM2和第三误差放大器EA3；
第二n型功率MOS管nM2的源极接收储能电路，即电感Ls输出的电压，第二n型功率MOS管nM2的漏极接地，第二n型功率MOS管nM2的栅极连接第三误差放大器EA3的输出端，第三误差放大器EA3的反相输入端接收与储能电路输出的电压成正比的电压，在图7中为第一电阻R1与第二电阻R2相连的连接点的电压，在图8中为第四电阻R4与第五电阻R5相连的连接点的电压，第三误差放大器EA3的同相输入端接收第一参考电压Vref1。
可选地，除第一级片上电压调整器以外的每一级片上电压调整器中的一个片上电压调整器，如图9所示，包括第二p型功率MOS管pM2、第三n型功率MOS管nM3、第四误差放大器EA4、第六电阻R6、第七电阻R7、第八电阻R8、第二电容C2和第三电容C3；
第六电阻R6与第七电阻R7串联，该串联支路的一端连接第二p型功率MOS管pM2的漏极，该串联支路的另一端接地；第二p型功率MOS管pM2的源极连接第二输入电源91，第二p型功率MOS管pM2的栅极连接第四误差放大器EA4的输出端；其中，第二输入电源91为该片上电压调整器的前一级片上电压调整器中与该片上电压调整器相连的片上电压调整器的输出；
第二p型功率MOS管pM2的漏极连接第二电容C2的一端，第二电容C2的另一端接地；
第四误差放大器EA4的反相输入端接收第二参考信号Vref2，第四误差放大器EA4的同相输入端连接第六电阻R6与第七电阻R7相连的连接点；
第三n型功率MOS管nM3的栅极连接第四误差放大器EA4的输出端，第三n型功率MOS管nM3的源极通过第八电阻R8和第三电容C3并联后的并联支路接地，第三n型功率MOS管nM3的漏极与第二p型功率MOS管pM2的漏极相连，第二p型功率MOS管pM2的漏极为该片上电压调整器的输出端OUT。
可选地，除第一级片上电压调整器以外的每一级片上电压调整器中的一个片上电压调整器如图10所示，包括第九电阻R9、第十电阻R10、第十一电阻R11、第四电容C4、第五电容C5、第四n型功率MOS管nM4、数字控制器92、第三脉冲宽度调制比较器PWMC3和至少一个第三p型功率MOS管pM3；
所述至少一个第三p型功率MOS管pM3的源极均连接第三输入电源111，所述至少一个第三p型功率MOS管pM3的漏极相连，作为该片上电压调整器的输出端OUT，所述至少一个第三p型功率MOS管的栅极分别接收数字控制器92输出的控制信号；其中，第三输入电源111为该片上电压调整器的前一级片上电压调整器中与该片上电压调整器相连的片上电压调整器的输出；
第九电阻R9与第十电阻R10串联，该串联支路的一端连接该片上电压调整器的输出端OUT，该串联支路的另一端接地；
第四电容C4的一端连接该片上电压调整器的输出端OUT，第四电容C4的另一端接地；
数字控制器92，用于根据第三脉冲宽度调制比较器PWMC3输出的信号，输出控制信号，从而控制所述至少一个第三p型功率MOS管pM3中的MOS管在导通与关断之间切换；
第三脉冲宽度调制比较器PWMC3的同相输入端接收第三参考信号Vref3，第三脉冲宽度调制比较器PWMC3的反相输入端连接第九电阻R9与第十电阻R10相连的连接点；
第四n型功率MOS管nM4的漏极连接该片上电压调整器的输出端 OUT，第四n型功率MOS管nM4的源极通过第十一电阻R11和第五电容C5并联后的并联支路接地，第四n型功率MOS管nM4的栅极连接第三脉冲宽度调制比较器PWMC3的输出端。
本领域技术人员可以理解附图只是一个优选实施例的示意图，附图中的模块或流程并不一定是实施本发明所必须的。
本领域技术人员可以理解实施例中的装置中的模块可以按照实施例描述进行分布于实施例的装置中，也可以进行相应变化位于不同于本实施例的一个或多个装置中。上述实施例的模块可以合并为一个模块，也可以进一步拆分成多个子模块。
上述本发明实施例序号仅仅为了描述，不代表实施例的优劣。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。
Figure PCTCN2015080990-appb-000001

Claims (7)

  1. 之间切换；
    其中，当片上电压调整器为第一级片上电压调整器、且该片上电压调整器接收所述供电电源输出的电压时，所述第一输入电源为所述供电电源；当片上电压调整器为第一级片上电压调整器、且该片上电压调整器接收所述片外电压调整器输出的电压时，所述第一输入电源为所述片外电压调整器的输出；当片上电压调整器为除第一级片上电压调整器以外的片上电压调整器时，所述第一输入电源为该片上电压调整器的前一级片上电压调整器中与该片上电压调整器相连的片上电压调整器的输出。
  2. 如权利要求3所述的片上供电网络，其特征在于，所述开关电路包括第一p型功率MOS管和第一n型功率MOS管；
    所述第一p型功率MOS管的栅极和所述第一n型功率MOS管的栅极分别接收所述驱动电路输出的信号；所述第一p型功率MOS管的源极与所述第一n型功率MOS管的源极分别连接所述第一输入电源；所述第一p型功率MOS管的漏极与所述第一n型功率MOS管的漏极相连，作为所述开关电路的输出端。
  3. 如权利要求3所述的片上供电网络，其特征在于，当所述反馈环用于根据第一参考电压和所述储能电路输出的电压生成所述驱动信号时，所述反馈环包括第一电阻、第二电阻、第三电阻、第一电容、用于输出第一载波的第一振荡器、第一误差放大器和第一脉冲宽度调制比较器；
    所述第一电阻与所述第二电阻串联，该串联支路的一端接收所述储能电路输出的电压，该串联支路的另一端接地；
    所述第一电容连接在所述第一误差放大器的反相输入端与所述第一误差放大器的输出端之间；
    所述第一误差放大器的反相输入端通过所述第三电阻连接所述第一电阻和所述第二电阻相连的连接点；所述第一误差放大器的同相输入端接收所述第一参考电压；所述第一误差放大器的输出端连接所述第一脉冲宽度调制比较器的反相输入端；所述第一脉冲宽度调制比较器的同相输入端接收所述第一振荡器输出的第一载波；所述第一脉冲宽度调制比较器通过其输出端向所述驱动电路输出所述驱动信号。
  4. 如权利要求3所述的片上供电网络，其特征在于，当所述反馈环用于根据第一参考电压和所述储能电路流过的电流生成所述驱动信号时，所述 反馈环包括第四电阻、第五电阻、第二误差放大器、补偿器、第一比较器、加法器、第一电压电流转换器、第二电压电流转换器、输出第二载波的第二振荡器和第二脉冲宽度调制比较器；
    所述第一电压电流转换器，用于接收所述开关电路输出给所述储能电路的电压，并将接收到的电压转换为电流输出；
    所述第二电压电流转换器，用于接收第三载波的电压，并将接收到的电压转换为电流输出；
    所述加法器，用于确定所述第一电压电流转换器输出的电流与所述第二电压电流转换器输出的电流之和，并根据确定的电流之和输出电压；
    所述第四电阻与所述第五电阻串联，该串联支路的一端接收所述储能电路输出的电压，该串联支路的另一端接地；
    所述第二误差放大器的反相输入端连接所述第四电阻和所述第五电阻相连的连接点；所述第二误差放大器的同相输入端接收所述第一参考电压；所述第二误差放大器的输出端连接所述第一比较器的反相输入端；
    所述补偿器连接在所述第二误差放大器的反相输入端和所述第二误差放大器的输出端之间；所述补偿器用于对所述第二误差放大器输出的电压进行补偿；
    所述第一比较器的同相输入端接收所述加法器输出的电压，所述第一比较器的输出端连接所述第二脉冲宽度调制比较器的反相输出端；所述第二脉冲宽度调制比较器的同相输出端接收所述第二振荡器输出的第二载波；所述第二脉冲宽度调制比较器通过其输出端向所述驱动电路输出所述驱动信号。
  5. 如权利要求3所述的片上供电网络，其特征在于，所述片上电压调整器还包括第二滤波电路；所述第二滤波电路包括第二n型功率MOS管和第三误差放大器；
    所述第二n型功率MOS管的源极接收所述储能电路输出的电压，所述第二n型功率MOS管的漏极接地，所述第二n型功率MOS管的栅极连接所述第三误差放大器的输出端，所述第三误差放大器的反相输入端接收与所述储能电路输出的电压成正比的电压，所述第三误差放大器的同相输入端接收所述第一参考电压。
  6. 如权利要求1或2所述的片上供电网络，其特征在于，除第一级片上电压调整器以外的每一级片上电压调整器中的一个片上电压调整器包括 第二p型功率MOS管、第三n型功率MOS管、第四误差放大器、第六电阻、第七电阻、第八电阻、第二电容和第三电容；
    所述第六电阻与所述第七电阻串联，该串联支路的一端连接所述第二p型功率MOS管的漏极，该串联支路的另一端接地；所述第二p型功率MOS管的源极连接第二输入电源，所述第二p型功率MOS管的栅极连接所述第四误差放大器的输出端；其中，所述第二输入电源为该片上电压调整器的前一级片上电压调整器中与该片上电压调整器相连的片上电压调整器的输出；
    所述第二p型功率MOS管的漏极连接所述第二电容的一端，所述第二电容的另一端接地；
    所述第四误差放大器的反相输入端接收第二参考信号，所述第四误差放大器的同相输入端连接所述第六电阻与所述第七电阻相连的连接点；
    所述第三n型功率MOS管的栅极连接所述第四误差放大器的输出端，所述第三n型功率MOS管的源极通过所述第八电阻和所述第三电容并联后的并联支路接地，所述第三n型功率MOS管的漏极与所述第二p型功率MOS管的漏极相连，所述第二p型功率MOS管的漏极为该片上电压调整器的输出端。
  7. 如权利要求1或2所述的片上供电网络，其特征在于，除第一级片上电压调整器以外的每一级片上电压调整器中的一个片上电压调整器包括第九电阻、第十电阻、第十一电阻、第四电容、第五电容、第四n型功率MOS管、数字控制器、第三脉冲宽度调制比较器和至少一个第三p型功率MOS管；
    所述至少一个第三p型功率MOS管的源极均连接第三输入电源，所述至少一个第三p型功率MOS管的漏极相连，作为该片上电压调整器的输出端，所述至少一个第三p型功率MOS管的栅极分别接收所述数字控制器输出的控制信号；其中，所述第三输入电源为该片上电压调整器的前一级片上电压调整器中与该片上电压调整器相连的片上电压调整器的输出；
    所述第九电阻与所述第十电阻串联，该串联支路的一端连接该片上电压调整器的输出端，该串联支路的另一端接地；
    所述第四电容的一端连接该片上电压调整器的输出端，所述第四电容的另一端接地；
    所述数字控制器，用于根据所述第三脉冲宽度调制比较器输出的信号， 输出控制信号；
    所述第三脉冲宽度调制比较器的同相输入端接收第三参考信号，所述第三脉冲宽度调制比较器的反相输入端连接所述第九电阻与所述第十电阻相连的连接点；
    所述第四n型功率MOS管的漏极连接该片上电压调整器的输出端，所述第四n型功率MOS管的源极通过所述第十一电阻和所述第五电容并联后的并联支路接地，所述第四n型功率MOS管的栅极连接所述第三脉冲宽度调制比较器的输出端。
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CN102970008A (zh) * 2012-11-21 2013-03-13 东南大学 一种快速瞬态响应脉冲宽度调制电路
CN103227566A (zh) * 2013-04-22 2013-07-31 华为技术有限公司 一种dc-dc变换器
CN104065268A (zh) * 2014-06-17 2014-09-24 华为技术有限公司 一种片上供电网络

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110120746A (zh) * 2017-02-15 2019-08-13 华为技术有限公司 一种多相并联dcdc电路及其芯片结构
CN110120746B (zh) * 2017-02-15 2023-09-22 华为技术有限公司 一种多相并联dcdc电路及其芯片结构

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