WO2015187810A1 - An input/output virtualization (iov) host controller (hc) (iov-hc) of a flash-memory-based storage device - Google Patents

An input/output virtualization (iov) host controller (hc) (iov-hc) of a flash-memory-based storage device Download PDF

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Publication number
WO2015187810A1
WO2015187810A1 PCT/US2015/033953 US2015033953W WO2015187810A1 WO 2015187810 A1 WO2015187810 A1 WO 2015187810A1 US 2015033953 W US2015033953 W US 2015033953W WO 2015187810 A1 WO2015187810 A1 WO 2015187810A1
Authority
WO
WIPO (PCT)
Prior art keywords
slot
trl
iov
cri
tmrl
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2015/033953
Other languages
English (en)
French (fr)
Inventor
Assaf Shacham
Dolev Raviv
David Teb
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Priority to KR1020167033830A priority Critical patent/KR20170013270A/ko
Priority to CN201580029245.XA priority patent/CN106462522B/zh
Priority to EP15729697.1A priority patent/EP3152667A1/en
Priority to JP2016569591A priority patent/JP2017522645A/ja
Publication of WO2015187810A1 publication Critical patent/WO2015187810A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0662—Virtualisation aspects
    • G06F3/0664—Virtualisation aspects at device level, e.g. emulation of a storage device or system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays

Definitions

  • UFS Universal Flash Storage
  • JEDEC Joint Electron Device Engineering Council
  • SCSI Small Computer System Interface
  • eMMC Embedded MultiMediaCard
  • each of the TRL slot count register values 310(0)-310(4) is aligned to the corresponding TRL slot offset register values 308(0)-308(4), and the settings for a particular CRI 202(0)-202(3) must be configured before the corresponding I/O client 104(0)404(3) is enabled and should not be changed as long as the CRI 202(0)-202(3) is active. These requirements are also optional.
  • FIG. 4 A the IOV-HC 102 receives a TR 400 from the CRI 202(3).
  • the TR 400 includes a slot identifier 402, which in this example has a value of one (1) and represents an index to the second slot in the virtual TRL 320 of Figure 3 allocated to the CRI 202(3).
  • FIGs 7A and 7B are provided to illustrate exemplary operations of the IOV-HC 102 of Figure 1 for allocating slots of the shared TRL 256 using the virtual TRL registers 254 of Figure 2. Elements of Figures 1-6 are referenced in describing Figures 7A and 7B for the sake of clarity.
  • operations according to some aspects may begin with the IOV-HC 102 receiving, from the VMM 108, a TRL slot offset register value (such as the TRL slot offset register value 308(1)) and a TRL slot count register value (such as the TRL slot count register value 310(1)) for each CRI 202(1) of the plurality of CRIs 202(0)-202(N), responsive to initialization of the IOV- HC 102 (block 700).

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
PCT/US2015/033953 2014-06-03 2015-06-03 An input/output virtualization (iov) host controller (hc) (iov-hc) of a flash-memory-based storage device Ceased WO2015187810A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020167033830A KR20170013270A (ko) 2014-06-03 2015-06-03 플래시 메모리 기반 저장 디바이스의 입력/출력 가상화 (iov) 호스트 제어기 (hc) (iov-hc)
CN201580029245.XA CN106462522B (zh) 2014-06-03 2015-06-03 基于闪存的存储设备的输入/输出虚拟化(iov)主机控制器(hc)(iov-hc)
EP15729697.1A EP3152667A1 (en) 2014-06-03 2015-06-03 An input/output virtualization (iov) host controller (hc) (iov-hc) of a flash-memory-based storage device
JP2016569591A JP2017522645A (ja) 2014-06-03 2015-06-03 フラッシュメモリベースのストレージデバイスの入力／出力仮想化（ｉｏｖ）ホストコントローラ（ｈｃ）（ｉｏｖ−ｈｃ）

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201462007136P 2014-06-03 2014-06-03
US62/007,136 2014-06-03
US14/728,343 2015-06-02
US14/728,343 US9632953B2 (en) 2014-06-03 2015-06-02 Providing input/output virtualization (IOV) by mapping transfer requests to shared transfer requests lists by IOV host controllers

Publications (1)

Publication Number Publication Date
WO2015187810A1 true WO2015187810A1 (en) 2015-12-10

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PCT/US2015/033953 Ceased WO2015187810A1 (en) 2014-06-03 2015-06-03 An input/output virtualization (iov) host controller (hc) (iov-hc) of a flash-memory-based storage device

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Country Link
US (1) US9632953B2 (enExample)
EP (1) EP3152667A1 (enExample)
JP (1) JP2017522645A (enExample)
KR (1) KR20170013270A (enExample)
CN (1) CN106462522B (enExample)
WO (1) WO2015187810A1 (enExample)

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US9690720B2 (en) * 2014-06-03 2017-06-27 Qualcomm Incorporated Providing command trapping using a request filter circuit in an input/output virtualization (IOV) host controller (HC) (IOV-HC) of a flash-memory-based storage device
US9881680B2 (en) 2014-06-03 2018-01-30 Qualcomm Incorporated Multi-host power controller (MHPC) of a flash-memory-based storage device
CN105307102A (zh) * 2014-07-18 2016-02-03 光宝电子(广州)有限公司 蓝牙无线音频传输器
US9891945B2 (en) 2016-03-21 2018-02-13 Qualcomm Incorporated Storage resource management in virtualized environments
KR102498319B1 (ko) 2018-06-04 2023-02-08 삼성전자주식회사 반도체 장치
KR102643803B1 (ko) * 2018-11-15 2024-03-05 삼성전자주식회사 멀티 호스트 컨트롤러와 이를 포함하는 반도체 장치
KR20220048303A (ko) 2020-10-12 2022-04-19 삼성전자주식회사 크레딧을 이용하는 호스트 장치와 스토리지 장치의 동작 방법

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Also Published As

Publication number Publication date
CN106462522B (zh) 2019-10-18
JP2017522645A (ja) 2017-08-10
EP3152667A1 (en) 2017-04-12
US20150347016A1 (en) 2015-12-03
US9632953B2 (en) 2017-04-25
KR20170013270A (ko) 2017-02-06
CN106462522A (zh) 2017-02-22

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