WO2015180359A1 - 阵列基板及其制作方法、以及显示装置 - Google Patents

阵列基板及其制作方法、以及显示装置 Download PDF

Info

Publication number
WO2015180359A1
WO2015180359A1 PCT/CN2014/088083 CN2014088083W WO2015180359A1 WO 2015180359 A1 WO2015180359 A1 WO 2015180359A1 CN 2014088083 W CN2014088083 W CN 2014088083W WO 2015180359 A1 WO2015180359 A1 WO 2015180359A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
film layer
array substrate
wire
common electrode
Prior art date
Application number
PCT/CN2014/088083
Other languages
English (en)
French (fr)
Inventor
杨盛际
董学
王海生
薛海林
刘英明
赵卫杰
刘红娟
丁小梁
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP14861115.5A priority Critical patent/EP3151278B1/en
Priority to US14/443,280 priority patent/US9559690B2/en
Publication of WO2015180359A1 publication Critical patent/WO2015180359A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated
    • H03K17/96—Touch switches
    • H03K17/962—Capacitive touch switches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/94—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00 characterised by the way in which the control signal is generated
    • H03K2217/96—Touch switches
    • H03K2217/9607—Capacitive touch switches
    • H03K2217/960755—Constructional details of capacitive touch and proximity switches

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device.
  • the Touch Screen Panel has gradually spread throughout people's lives.
  • the touch structure included in the touch screen can be divided into: a mutual capacitance touch structure and a self capacitance contact structure.
  • self-capacitance touch structures due to the accuracy of their touch sensing and high signal-to-noise ratio, they are favored by major panel manufacturers.
  • the self-capacitance touch structure utilizes the principle of self-capacitance to realize the detection of the finger touch position.
  • a plurality of self-capacitance electrodes arranged in the same layer and independent of each other are disposed in the touch structure, and when the human body does not touch the screen, the respective capacitor electrodes are The capacitive capacity is a fixed value.
  • the capacitance of the self-capacitance electrode corresponding to the touch position is a fixed value superimposed on the human body capacitance, and the touch detection chip passes the detection of the respective capacitor electrode during the touch time period.
  • the change in capacitance value can determine the touch position.
  • each self-capacitance electrode needs to be connected to the touch detection chip through a separate lead line.
  • each lead line specifically includes: connecting the self-capacitance electrode 1 to the border of the touch screen.
  • each self-capacitance electrode since the number of self-capacitance electrodes is very large, the corresponding lead-out lines are also very large. For example, the area occupied by each self-capacitance electrode is 5 mm*5 mm, and the 5-inch liquid crystal display requires 264 pieces. Self-capacitance electrodes, if each self-capacitance electrode is designed to be smaller, there will be more self-capacitance electrodes, then more lead wires need to be set.
  • the wires 2 and the self-capacitance electrodes 1 in the lead wires are generally disposed in the same layer, and more wires 2 cause the touch dead zone to be large, wherein
  • the touch blind zone refers to the area where the traces are concentrated in the touch screen.
  • the signal in the touch blind zone is relatively turbulent, so it is called a touch dead zone, that is, the touch performance in the touch area cannot be guaranteed.
  • the touch blind area in the current self-capacitance touch structure is too large, and the touch performance of the touch screen including the self-capacitance touch structure is relatively poor.
  • the embodiment of the invention provides an array substrate, a manufacturing method thereof, and a display device, which are used to solve the problem that the touch blind area is too large in the self-capacitance touch structure existing in the prior art.
  • an array substrate includes: a substrate, a gate and a gate line on the substrate, and an active layer on a film layer where the gate and the gate line are located, a drain, a source, and a data line on the active layer, a pixel electrode on the film layer on which the drain, the source, and the data line are located and electrically connected to the drain through the first via, And a common electrode layer on the film layer where the pixel electrode is located and electrically insulated from the pixel electrode;
  • the common electrode layer includes a plurality of self-capacitance electrodes disposed in the same layer and insulated from each other;
  • the array substrate further includes:
  • each of the wires is electrically connected to the corresponding self-capacitance electrode through the second via.
  • the film layer in which the wire is located is located between the film layer where the drain, source, and data lines are located and the common electrode layer.
  • the film layer in which the wire is located is located between the film layer where the drain, source, and data lines are located and the film layer where the pixel electrode is located.
  • a first passivation layer is disposed between the film layer where the drain, the source, and the data line are located and the film layer where the pixel electrode is located, and the first via penetrates through the first passivation Floor;
  • a film layer of the wire is located between the first passivation layer and the film layer where the pixel electrode is located;
  • the array substrate further includes:
  • first insulating layer between the film layer where the wire is located and the film layer where the pixel electrode is located, and the first via hole and the second via hole both penetrate the first insulating layer;
  • the pixel electrode is electrically connected to the drain through the first via.
  • the film layer where the wire is located is located between the film layer where the pixel electrode is located and the common electrode layer.
  • a second passivation layer is disposed between the film layer where the pixel electrode is located and the common electrode layer;
  • a film layer of the wire is located between the second passivation layer and the common electrode layer;
  • the array substrate further includes:
  • a second insulating layer is located between the film layer where the wire is located and the common electrode layer, and the second via hole penetrates the second insulating layer.
  • the film layer on which the wire is located is above the common electrode layer.
  • the array substrate further includes:
  • a third insulating layer is located between the film layer where the wire is located and the common electrode layer, and the second via hole penetrates through the third insulating layer.
  • an orthographic projection of the wire on the substrate substrate is within an orthographic projection of the data line on the substrate substrate;
  • An orthographic projection of the wire on the base substrate is located within an orthographic projection of the gate line on the substrate.
  • the wire is used as a common electrode line that supplies power to the common electrode layer during a display scan time.
  • a display device comprising the array substrate of any of the embodiments described above.
  • a method for fabricating an array substrate includes:
  • the pixel electrode electrically connected to the drain through the first via, and located on the film layer where the pixel electrode is located and the pixel electrode Electrically insulated common electrode layer, and a plurality of wires;
  • the common electrode layer includes a plurality of self-capacitance electrodes disposed in the same layer and insulated from each other; the wires are electrically insulated from the drain, the source, the data lines, and the pixel electrodes, and the common electrode layer is different from the layer The wires are electrically connected to the corresponding self-capacitance electrodes through the second via holes.
  • the common electrode layer included in the array substrate includes a plurality of self-capacitance electrodes disposed in the same layer and insulated from each other, and the array substrate further includes: a plurality of wires electrically connected to the corresponding self-capacitance electrodes; Therefore, the touch electrodes (ie, self-capacitance electrodes) and the wires in the self-capacitance touch structure can be embedded into the array substrate, so as to implement the in-cell touch screen;
  • the touch dead zone in the self-capacitance touch structure can be eliminated to improve the touch performance of the touch screen including the self-capacitance touch structure;
  • the common electrode layer included in the array substrate includes a plurality of layers disposed in the same layer and insulated from each other
  • the self-capacitance electrode can be used as a touch electrode in the self-capacitance touch structure, so as to avoid separately setting the film layer of the touch electrode to simplify the number of layers.
  • FIG. 1 is a schematic top plan view of a capacitive touch structure in the prior art
  • FIG. 2 is a schematic side view showing the structure of an array substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram showing a positional relationship between a wire and a data line in an embodiment of the present invention
  • FIG. 4 is a schematic top plan view of a capacitive touch structure according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram showing driving timings of a display device according to an embodiment of the present invention.
  • an array substrate provided by an embodiment of the present invention includes: a substrate 00, a gate 11 and a gate line 12 on the substrate 00, where the gate 11 and the gate line 12 are located.
  • the active layer 20 on the film layer, the drain 31, the source 32 and the data line 33 on the active layer 20 are located on the film layer where the drain 31, the source 32 and the data line 33 are located and pass the first a pixel electrode 40 electrically connected to the drain 31 and a common electrode layer 50 located on the film layer of the pixel electrode 40 and electrically insulated from the pixel electrode 40;
  • the common electrode layer 50 includes a plurality of self-capacitance electrodes 51 disposed in the same layer and insulated from each other;
  • the array substrate further includes:
  • a plurality of wires 60 are disposed on the film layer of the drain 31, the source 32 and the data line 33, and are electrically insulated from the drain 31, the source 32, the data line 33 and the pixel electrode 40;
  • the common electrode layer 50 is disposed in a different layer, and each of the wires 60 is electrically connected to the corresponding self-capacitance electrode 51 through the second via hole 200.
  • a film layer in which an element is located refers to a general term of elements including the same layer as the element.
  • the film layer located on a certain component is not limited to being directly above the component, and may be obliquely above the component.
  • the portion between the film layer where the component is located and the film layer where the other component is located is not limited to the portion directly above (lower) of the component and directly below (upper) the component, and may also include the portion An extension on the surface of the substrate.
  • the common electrode layer included in the array substrate includes a plurality of self-capacitance electrodes disposed in the same layer and insulated from each other, and the array substrate further includes: a plurality of wires electrically connected to the capacitor electrode; thereby, the touch electrodes (ie, self-capacitance electrodes) and the wires in the self-capacitance touch structure are embedded in the array substrate, so as to implement the in-cell touch screen;
  • the touch dead zone in the self-capacitance touch structure can be eliminated to improve the touch performance of the touch screen including the self-capacitance touch structure;
  • the common electrode layer included in the array substrate includes a plurality of self-capacitance electrodes disposed in the same layer and insulated from each other, the common electrode layer can be used as a touch electrode in the self-capacitance touch structure, thereby avoiding separately setting the touch electrodes. Located in the film layer to simplify the number of layers.
  • the implementation of the self-capacitance electrode included in the common electrode layer is similar to the implementation of the self-capacitance electrode included in the prior art self-capacitance touch structure, and details are not described herein again.
  • the positional connection relationship of the wires in the embodiment of the present invention may be as follows: the drain, the source, and the data line are located above the film layer, and the drain, the source, the data line, and the pixel.
  • the electrodes are electrically insulated; and are disposed in a different layer from the common electrode layer, and each of the wires is electrically connected to the corresponding self-capacitance electrode through the second via.
  • the film layer where the wire is located is located between the film layer where the drain, the source and the data line are located, and the common electrode layer.
  • the film layer of the wire is located between the film layer where the drain, the source and the data line are located, and the common electrode layer, which can reduce the interference of the human body capacitance on the signal transmitted on the wire.
  • the film layer where the wire is located when the film layer where the wire is located is located between the film layer where the drain, the source and the data line are located and the common electrode layer, the film layer where the wire is located may be located at the drain and the source.
  • the film layer between the pole and the data line and the film layer where the pixel electrode is located may also be located between the film layer where the pixel electrode is located and the common electrode layer, which will be separately described below.
  • the film layer of the wire is located between the film layer where the drain, the source and the data line are located, and the film layer where the pixel electrode is located.
  • the film layer where the wire is located is located between the film layer where the drain, the source and the data line are located, and the film layer where the pixel electrode is located, which can ensure the distance between the film layer where the pixel electrode is located and the common electrode layer. Small, so that the electric field formed between the pixel electrode and the common electrode layer is sufficiently strong to improve the display effect.
  • a first passivation layer including the first via is disposed between the film layer where the drain, the source and the data line are located and the film layer where the pixel electrode is located;
  • the film layer of the wire may be located between the film layer where the drain, the source and the data line are located, and the film layer where the first passivation layer is located, or may be located at the film layer and the layer where the first passivation layer is located. Between the layers of the film where the pixel electrodes are located.
  • a first passivation including the first via 100 is disposed between the film layer where the drain 31, the source 32 and the data line 33 are located, and the film layer where the pixel electrode 40 is located.
  • the film layer of the wire 60 is located between the first passivation layer 70 and the film layer where the pixel electrode 40 is located;
  • the array substrate further includes:
  • the first insulating layer 80 is located between the film layer where the wire 60 is located and the film layer where the pixel electrode 40 is located, and includes the first via hole 100 and the second via hole 200;
  • the pixel electrode 40 is electrically connected to the drain 31 through the first via 100 included in the first insulating layer 80 and the first via 100 included in the first passivation layer 70;
  • the wire 60 is electrically connected to the self-capacitance electrode 51 through the second via hole 200 included in the first insulating layer 80.
  • the film layer of the wire is located between the film layer where the first passivation layer is located and the film layer where the pixel electrode is located, which can reduce the number of second via holes, thereby simplifying the fabrication of the array substrate The complexity of art.
  • the film layer where the wire is located is located between the film layer where the drain, the source and the data line are located, and the film layer where the first passivation layer is located, and is located at the film layer where the wire is located.
  • the embodiment between the film layer where the first passivation layer is located and the film layer where the pixel electrode is located is similar; however, the film layer where the wire is located is located at the film layer where the drain, the source and the data line are located and When the first passivation layer is between the film layers, the first insulating layer needs to be located between the film layer where the drain, the source and the data line are located, and the film layer where the wire is located, and the first In addition to the first via, the passivation layer also needs to include a second via.
  • the film layer of the wire 60 is located between the film layer where the drain 31, the source 32 and the data line 33 are located, and the film layer where the pixel electrode 40 is located;
  • the array substrate further includes:
  • the second passivation layer 90 is located between the film layer where the pixel electrode 40 is located and the common electrode layer 50.
  • the second passivation layer is located between the film layer where the pixel electrode is located and the common electrode layer, so that the pixel electrode and the common electrode layer are electrically insulated.
  • the array substrate further includes:
  • the gate insulating layer 110 is located between the film layer where the gate electrode 11 and the gate line 12 are located and the active layer 20.
  • the implementation of the gate insulating layer in the embodiment of the present invention is similar to the implementation of the gate insulating layer in the prior art, and details are not described herein again.
  • the film layer where the wire is located is located between the film layer where the pixel electrode is located and the common electrode layer.
  • the film layer where the wire is located is located between the film layer where the pixel electrode is located and the common electrode layer, and the number of the second via hole and the first via hole can be reduced to simplify the process of fabricating the array substrate.
  • a second passivation layer is disposed between the film layer where the pixel electrode is located and the common electrode layer;
  • the film layer where the wire is located may be located between the film layer where the pixel electrode is located and the second passivation layer, or may be located between the second passivation layer and the common electrode layer.
  • a second passivation layer is disposed between the film layer where the pixel electrode is located and the common electrode layer;
  • a film layer of the wire is located between the second passivation layer and the common electrode layer;
  • the array substrate further includes:
  • the wire is electrically connected to the self-capacitance electrode through a second via included in the second insulating layer.
  • only the second via hole is disposed in the second insulating layer, which can achieve the solution in the embodiment of the present invention, thereby simplifying the complexity of the process for fabricating the array substrate.
  • the film layer where the wire is located is located between the film layer where the pixel electrode is located and the second passivation layer, and the film layer where the wire is located is located at the second passivation layer and the The embodiment between the common electrode layers is similar; however, when the film layer where the wire is located is located between the film layer where the pixel electrode is located and the second passivation layer, the second insulating layer needs to be located.
  • the film layer where the pixel electrode is located and the film layer where the wire is located does not include a via hole, and the second passivation layer needs to include a second via hole.
  • the film layer where the wire is located is located above the common electrode layer.
  • the film layer on which the wire is located is located above the common electrode layer. It can be ensured that the connection relationship between the respective film layers included in the existing array substrate is not changed.
  • the array substrate further includes:
  • the wire is electrically connected to the self-capacitance electrode through a second via included in the third insulating layer.
  • an orthographic projection of the wire on the substrate substrate is within an orthographic projection of the data line on the substrate;
  • An orthographic projection of the wire on the base substrate is located within an orthographic projection of the gate line on the substrate.
  • the orthographic projection of the wire 60 electrically connected to the corresponding self-capacitance electrode 51 through the second via 200 on the substrate substrate (the substrate substrate not shown in FIG. 3) Located within the orthographic projection of the data line 33 on the substrate.
  • an orthographic projection of the wire on the substrate is located within an orthographic projection of the data line on the substrate; and/or an orthographic projection of the wire on the substrate
  • the orthographic projection of the gate line on the substrate substrate can ensure that the electric field generated by the wire does not affect the electric field of the pixel opening region, and therefore does not affect the normal display.
  • an orthographic projection of the wire on the substrate is located within an orthographic projection of the data line on the substrate; and/or an orthographic projection of the wire on the substrate.
  • the orthographic projection of the wire on the substrate is located in an orthographic projection of the data line on the substrate, and the extending direction of each wire is consistent with the extending direction of the data line. Conducive to narrow border design.
  • the embodiment of the positional relationship between the wire and the gate line and the data line in the embodiment of the present invention may also be other embodiments, for example, the data line and/or the gate line are in the lining.
  • An orthographic projection on the base substrate is located within an orthographic projection of the wire on the substrate; or an orthographic projection of the wire on the substrate is associated with the data line and/or gate line.
  • the orthographic projections on the substrate substrate overlap; or the orthographic projection of the wires on the substrate substrate does not overlap with the orthographic projection of the data lines and/or gate lines on the substrate substrate, etc. , will not repeat them here.
  • a self-capacitance electrode can be electrically connected to at least one wire, and the wires of the respective capacitor electrodes are electrically connected differently.
  • the common electrode layer 50 includes a plurality of self-capacitance electrodes 51 arranged in a matrix and insulated from each other in a matrix arrangement;
  • a wire 60 is electrically connected to a self-capacitance electrode 51, and the wires 60 electrically connected to the respective capacitor electrodes 51 are different;
  • the wires 60 are disposed in different layers from the common electrode layer 50, and each of the wires 60 is electrically connected to the corresponding self-capacitance electrode 51 through the second via 200.
  • the wire is used as a common electrode line that supplies power to the common electrode layer during the display scan time.
  • the wire is used as a power supply to the common electrode layer during the display scan time.
  • the use of the common electrode line can save the number of traces included in the array substrate, thereby reducing the complexity of fabricating the array substrate.
  • the common electrode line is a gate Vcom line disposed in the same layer as the gate and the gate line, and disposed in a different layer from the common electrode layer and electrically connected to the common electrode layer through the via hole
  • the use of the wire as a common electrode line for supplying power to the common electrode layer during a display scan time can also avoid via etching of each film layer between the film layer and the common electrode layer where the gate and the gate line are located.
  • the gate Vcom line and the common electrode layer are electrically connected to reduce the mask used for fabricating the array substrate, thereby reducing the cost and complexity of fabricating the array substrate.
  • the embodiment of the present invention further provides a display device, including: the array substrate described in the embodiment of the present invention;
  • the display device can be: a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc., any product or component having a display function;
  • the array substrate described in the embodiment of the present invention has a touch electrode (ie, a self-capacitance electrode) and a wire in the self-capacitance touch structure, and thus includes the array substrate according to the embodiment of the present invention.
  • the display device has both a display function and a touch function.
  • the display device including the array substrate described in the embodiment of the present invention can also eliminate the touch dead zone and improve Touch performance;
  • the display device including the array substrate described in the embodiments of the present invention can also simplify the number of layers.
  • the display device further includes: a color filter substrate disposed opposite to the array substrate; wherein the color filter substrate comprises sequentially stacked: a base substrate, a black matrix layer, a color film layer, a planarization layer, and a PS (separator layer).
  • a color filter substrate disposed opposite to the array substrate; wherein the color filter substrate comprises sequentially stacked: a base substrate, a black matrix layer, a color film layer, a planarization layer, and a PS (separator layer).
  • the embodiment of the present invention further provides a scanning method for the display device, including:
  • the driving signals are applied to the respective capacitor electrodes in a time-sharing manner through the wires connected to the respective capacitor electrodes; the feedback signals of the respective capacitor electrodes are received, and the touch position is determined according to the feedback signals.
  • time-division touch scanning and display scanning can reduce display signals and touch signals Mutual interference between each other to improve picture quality and touch accuracy.
  • the touch detection chip can apply a driving signal to the respective capacitor electrodes in a time-sharing manner through the wires connected to the respective capacitor electrodes; receive the feedback signals of the respective capacitor electrodes, and determine the touch position according to the feedback signals.
  • the touch detection chip is disposed on the circuit board, and may be disposed on a circuit board located at the back of the display device, and may be disposed on a circuit board located in a frame area of the display device, or may be disposed on the array substrate.
  • the flexible circuit board On the flexible circuit board.
  • the display driver chip and the touch detection chip can be integrated into one chip to reduce the production cost.
  • a scanning method of the display device in the embodiment of the present invention will be described in detail below with reference to FIG.
  • the time at which the display device displays each frame is divided into a display scan period (Display) and a touch scan period (Touch), for example, the display device displays a frame time of 16.7 ms. 5 ms is selected as the touch scan time period, and the other 11.7 ms is used as the display scan time period.
  • the duration of the two chips can be appropriately adjusted according to the processing capability of the IC chip, and is not specifically limited herein;
  • a gate scan signal is sequentially applied to each of the gate signal lines Gate1, Gate2, ..., Gate n in the display device, and a gray scale signal is applied to the data signal line Data to realize a display function;
  • the touch detection chip applies a driving signal to the respective capacitor electrodes Cx1 . . . Cxn in a time division manner; at the same time, receives the feedback signals of the respective capacitor electrodes Cx1 . . . Cxn, and passes through the respective capacitor electrodes Cx1...
  • the analysis of the feedback signal of Cxn determines the touch position to implement the touch function.
  • the implementation of the touch detection chip to determine the touch position by the analysis of the feedback signals of the respective capacitor electrodes Cx1 . . . Cxn is similar to the prior art embodiment, and details are not described herein again.
  • a Vcom voltage is applied to each of the capacitor electrodes during the display scanning period (Display).
  • the display device can be normally displayed.
  • a GND signal is applied to the touch signal period (Touch), the data signal line, and each gate signal line.
  • the respective capacitor electrodes may be scanned one by one in the lateral direction, and the driving signals may be applied to the respective capacitor electrodes in a time-sharing manner; the respective capacitor electrodes may be scanned one by one in the vertical direction to be applied to the respective capacitor electrodes in a time-sharing manner.
  • Drive signal when the driving signals are applied to the respective capacitor electrodes in a time division manner, the respective capacitor electrodes may be scanned one by one in the lateral direction, and the driving signals may be applied to the respective capacitor electrodes in a time-sharing manner; the respective capacitor electrodes may be scanned one by one in the vertical direction to be applied to the respective capacitor electrodes in a time-sharing manner.
  • Drive signal when the driving signals are applied to the respective capacitor electrodes in a time division manner, the respective capacitor electrodes may be scanned one by one in the lateral direction, and the driving signals may be applied to the respective capacitor electrodes in a time-sharing manner; the respective capacitor electrodes may be scanned one by one in the vertical direction to be applied to the respective capacitor electrodes
  • the driving signal is applied to the respective capacitor electrodes in an all-drive manner.
  • the specific implementation is similar to the implementation in the prior art, and details are not described herein again.
  • an embodiment of the present invention also provides a method for fabricating an array substrate, including:
  • Step 601 sequentially forming a film layer of the gate and the gate line on the base substrate, an active layer, and a film layer of the drain, the source and the data line;
  • Step 602 forming, on the film layer where the drain, the source and the data line are located, the pixel electrode electrically connected to the drain through the first via hole, located on the film layer where the pixel electrode is located and a common electrode layer electrically insulated from the pixel electrode, and a plurality of wires;
  • the common electrode layer includes a plurality of self-capacitance electrodes disposed in the same layer and insulated from each other; the wires are electrically insulated from the drain, the source, the data lines, and the pixel electrodes, and the common electrode layer is different from the layer The wires are electrically connected to the corresponding self-capacitance electrodes through the second via holes.
  • the method for fabricating the array substrate of the embodiment of the invention includes:
  • Step 1 as shown in Figure 2, forming a gate 11 and a gate line 12 on the substrate 00;
  • electrically connected gates and gate lines are formed on the base substrate by a single Gate Mask process.
  • a gate Vcom line is also formed on the substrate substrate in the same layer as the gate and gate lines and electrically insulated;
  • the gate Vcom line may be created, or the gate Vcom line may not be created.
  • Step 2 as shown in FIG. 2, a gate insulating layer 110 is formed on the film layer where the gate electrode 11 and the gate line 12 are located;
  • Step 3 as shown in FIG. 2, forming an active layer 20 on the gate insulating layer 110;
  • an active layer is formed on the gate insulating layer 11 by an active mask (active layer etching) process.
  • a GI Mask (gate insulating layer etching) process is also required to form a via hole exposing the gate Vcom line in the gate insulating layer;
  • the GI Mask process step is not required when the gate Vcom line is not created.
  • Step 4 as shown in FIG. 2, forming a drain 31, a source 32 and a data line 33 on the active layer 20;
  • the drain, the source and the data line are formed on the active layer by a single SD Mask process.
  • Step 5 as shown in FIG. 2, a first passivation layer 70 including a first via 100 exposing the drain 31 is formed on the film layer on which the drain 31, the source 32 and the data line 33 are located;
  • the first passivation layer including the first via hole exposing the drain is formed by one PVX1 Mask process.
  • the gate Vcom line when the gate Vcom line is not fabricated, it is not necessary to form a via hole exposing the gate Vcom line in the first passivation layer.
  • Step 6 as shown in Figure 2, forming a wire 60 on the first passivation layer 70;
  • the wire is formed by a single Metal Mask process.
  • Step 7 as shown in FIG. 2, a first insulating layer 80 is formed on the film layer where the wire 60 is located, the first insulating layer 80 includes a first via 100 exposing the drain 31, and a second pass exposing the wire 60. Hole 200;
  • the first insulating layer including the first via hole and the second via hole is formed by an I Mask (Insulation Layer Etching) process.
  • a via hole exposing the gate Vcom line needs to be formed in the first insulating layer.
  • Step 8 as shown in FIG. 2, a pixel electrode 40 is formed on the first insulating layer 80, and the pixel electrode 40 passes through the first via hole 100 and the first passivation layer 70 included in the first insulating layer 80.
  • the first via hole 100 is electrically connected to the drain 31;
  • the pixel electricity is formed by a 1st ITO Mask process pole.
  • Step 9 as shown in FIG. 2, a second passivation layer 90 including a second via hole 200 is formed on the film layer where the pixel electrode 40 is located;
  • the second passivation layer including the second via hole is formed by a PVX2 Mask process.
  • the gate Vcom line when the gate Vcom line is not fabricated, it is not necessary to form a via hole exposing the gate Vcom line in the second passivation layer.
  • Step 10 as shown in FIG. 2, forming a common electrode layer 50 including a plurality of self-capacitance electrodes 51 disposed in the same layer and insulated from each other on the second passivation layer; the wires 60 are included by the first insulating layer 80
  • the second via 200 and the second via 200 included in the second passivation layer are electrically connected to the corresponding self-capacitance electrode 51.
  • the common electrode layer is formed by a 2nd ITO Mask process.
  • Step 1 Form a black matrix layer on the base substrate
  • a black matrix layer is formed on the base substrate by a BM Mask (black matrix layer etching) process.
  • Step 2 forming an RGB (red, green, blue) color film layer on the black matrix layer;
  • the RGB is formed on the black matrix layer by an R Mask (red sub-pixel unit etching) process, a G Mask (green sub-pixel unit etching) process, and a Mask (blue sub-pixel unit etching) process, respectively.
  • R Mask red sub-pixel unit etching
  • G Mask green sub-pixel unit etching
  • Mask blue sub-pixel unit etching
  • Step 3 forming a planarization layer on the RGB color film layer
  • Step 4 Form a PS on the planarization layer.
  • the PS is formed by a PS Mask process.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Human Computer Interaction (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板及其制作方法、以及显示装置。该阵列基板包括：位于衬底基板（00）上的栅极（11）和栅线（12），位于栅极（11）和栅线（12）所在膜层上的有源层（20），位于有源层（20）上的漏极（31）、源极（32）和数据线（33），位于漏极（31）、源极（32）和数据线（33）所在膜层上且通过第一过孔（100）与漏极（31）连接的像素电极（40），以及位于像素电极（40）所在膜层上且与像素电极（40）绝缘的公共电极层（50）；其中：公共电极层（50）包括多个同层设置且相互绝缘的自电容电极（51）；所述阵列基板还包括：多条导线（60），位于漏极（31）、源极（32）和数据线（33）所在膜层之上，与漏极（31）、源极（32）、数据线（33）和像素电极（40）绝缘；以及与公共电极层（50）异层设置，且每条导线（60）通过第二过孔（200）与对应的自电容电极（51）电性连接。

Description

阵列基板及其制作方法、以及显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制作方法、以及显示装置。
背景技术
随着显示技术的飞速发展，触摸屏(Touch Screen Panel)已经逐渐遍及人们的生活中。目前，触摸屏包括的触摸结构可以分为：互电容触摸结构和自电容触摸结构。对于自电容触摸结构，由于其触控感应的准确度和信噪比比较高，因而受到了各大面板厂家青睐。
目前，自电容触摸结构利用自电容的原理实现检测手指触摸位置，具体为：在触摸结构中设置多个同层设置且相互独立的自电容电极，当人体未触碰屏幕时，各自电容电极所承受的电容为一固定值，当人体触碰屏幕时，触碰位置对应的自电容电极所承受的电容为固定值叠加人体电容，触控侦测芯片在触控时间段通过检测各自电容电极的电容值变化可以判断出触控位置。
在自电容触摸结构中，每一个自电容电极需要通过单独的引出线与触控侦测芯片连接，如图1所示，每条引出线具体包括：将自电容电极1连接至触摸屏的边框处的导线2，以及设置在边框处用于将自电容电极1导通至触控侦测芯片的接线端子3的周边走线4。
在具体实施时，由于自电容电极的数量非常多，对应的引出线也会非常多，以每个自电容电极的所占面积为5mm*5mm为例，5寸的液晶显示屏就需要264个自电容电极，若将每个自电容电极设计的更小一些，则会有更多的自电容电极，那么需要设置更多的引出线。
而且，在设计时，由于为了简化膜层数量，如图1所示，一般将引出线中的导线2和自电容电极1同层设置，较多的导线2会造成触控盲区偏大，其中触控盲区是指触控屏中走线集中的区域，在这个触控盲区内的信号相对比较紊乱，故此称为触控盲区，即在该区域内的触控性能无法保证。
综上所述，目前的自电容触摸结构中的触控盲区偏大，造成包含所述自电容触摸结构的触摸屏的触控性能比较差。
发明内容
本发明实施例提供了一种阵列基板及其制作方法、以及显示装置，用以解决现有技术中存在的自电容触摸结构中的触控盲区偏大的问题。
根据本发明的一个实施例提供一种阵列基板，包括：衬底基板，位于所述衬底基板上的栅极和栅线，位于所述栅极和栅线所在膜层上的有源层，位于所述有源层上的漏极、源极和数据线，位于所述漏极、源极和数据线所在膜层上且通过第一过孔与所述漏极电性连接的像素电极，以及位于所述像素电极所在膜层上且与所述像素电极电性绝缘的公共电极层；其中，
所述公共电极层包括多个同层设置且相互绝缘的自电容电极；
所述阵列基板还包括：
多条导线，位于所述漏极、源极和数据线所在膜层之上，与所述漏极、源极、数据线和像素电极电性绝缘；以及，与所述公共电极层异层设置，且每条所述导线通过第二过孔与对应的自电容电极电性连接。
在一个示例中，所述导线所在膜层位于所述漏极、源极和数据线所在膜层和所述公共电极层之间。
在一个示例中，所述导线所在膜层位于所述漏极、源极和数据线所在膜层和所述像素电极所在膜层之间。
在一个示例中，所述漏极、源极和数据线所在膜层和所述像素电极所在膜层之间设置有第一钝化层，且所述第一过孔贯穿所述第一钝化层；
所述导线所在膜层位于所述第一钝化层和所述像素电极所在膜层之间；
所述阵列基板还包括：
第一绝缘层，位于所述导线所在膜层和所述像素电极所在膜层之间，且所述第一过孔和所述第二过孔均贯穿所述第一绝缘层；
其中，所述像素电极通过所述第一过孔与所述漏极电性连接。
在一个示例中，所述导线所在膜层位于所述像素电极所在膜层和所述公共电极层之间。
在一个示例中，所述像素电极所在膜层和所述公共电极层之间设置有第二钝化层；
所述导线所在膜层位于所述第二钝化层和所述公共电极层之间；
所述阵列基板还包括：
第二绝缘层，位于所述导线所在膜层和所述公共电极层之间，且所述第二过孔贯穿所述第二绝缘层。
在一个示例中，所述导线所在膜层位于所述公共电极层之上。
在一个示例中，所述阵列基板还包括：
第三绝缘层，位于所述导线所在膜层和所述公共电极层之间，且所述第二过孔贯穿所述第三绝缘层。
在一个示例中，所述导线在所述衬底基板上的正投影位于所述数据线在所述衬底基板上的正投影内；和/或
所述导线在所述衬底基板上的正投影位于所述栅线在所述衬底基板上的正投影内。
在一个示例中，将所述导线作为在显示扫描时间内向所述公共电极层供电的公共电极线使用。
根据本发明的另一个实施例提供一种显示装置，包括如上所述任一实施例所述的阵列基板。
根据本发明的再一个实施例提供一种阵列基板的制作方法，包括：
在衬底基板上依次形成所述栅极和栅线所在膜层，有源层，以及所述漏极、源极和数据线所在膜层；
在所述漏极、源极和数据线所在膜层上形成所述通过第一过孔与所述漏极电性连接的像素电极，位于所述像素电极所在膜层上且与所述像素电极电性绝缘的公共电极层，以及多条导线；
其中，所述公共电极层包括多个同层设置且相互绝缘的自电容电极；所述导线与所述漏极、源极、数据线和像素电极电性绝缘，与所述公共电极层异层设置，且每条所述导线通过第二过孔与对应的自电容电极电性连接。
在本发明实施例中，阵列基板包含的公共电极层包括多个同层设置且相互绝缘的自电容电极，且所述阵列基板还包括：与对应的自电容电极电性连接的多条导线；从而可以实现将自电容触摸结构中的触控电极(即，自电容电极)和导线内嵌到阵列基板中，以便于实现内嵌式触摸屏；
由于导线和公共电极层异层设置，从而可以消除自电容触摸结构中的触控盲区，以提高包含所述自电容触摸结构的触摸屏的触控性能；
另外，由于阵列基板包含的公共电极层包括多个同层设置且相互绝缘的 自电容电极，从而可以将公共电极层作为自电容触摸结构中的触控电极使用，避免单独设置所述触控电极所在膜层，以简化膜层数量。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为现有技术中的电容式触摸结构的俯视结构示意图；
图2为本发明实施例中的阵列基板的侧视结构示意图；
图3为本发明实施例中的导线和数据线的位置关系示意图；
图4为本发明实施例中的电容式触摸结构的俯视结构示意图；
图5为本发明实施例中的显示装置的驱动时序示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
需要说明的是，本发明所提到的方向用语，如表示方向的“上”、“下”，仅是参考附图的方向以说明及理解本发明，而不用于限制本发明实施例；而且，附图中各层膜层的厚度和形状不反映真实比例，目的只是示意说明本发明内容。
如图2所示，本发明实施例提供的一种阵列基板，包括：衬底基板00，位于衬底基板00上的栅极11和栅线12，位于所述栅极11和栅线12所在膜层上的有源层20，位于有源层20上的漏极31、源极32和数据线33，位于所述漏极31、源极32和数据线33所在膜层上且通过第一过孔100与漏极31电性连接的像素电极40，以及位于所述像素电极40所在膜层上且与像素电极40电性绝缘的公共电极层50；其中：
所述公共电极层50包括多个同层设置且相互绝缘的自电容电极51；
所述阵列基板还包括：
多条导线60，位于所述漏极31、源极32和数据线33所在膜层之上，与所述漏极31、源极32、数据线33和像素电极40电性绝缘；以及，与公共电极层50异层设置，且每条导线60通过第二过孔200与对应的自电容电极51电性连接。
在本说明书中，某元件所在膜层例如是指包含与该元件位于同一层的元件的总称。位于某元件所在膜层上并不限定于在该元件的正上方，也可以在该元件的斜上方。位于某元件所在膜层与另一元件所在膜层之间也不限定于在该元件的正上(下)方且在该另一元件正下(上)方的部分，也可以包括该部分在基板表面上的延伸部分。
实施中，与现有技术相比，在本发明实施例中，阵列基板包含的公共电极层包括多个同层设置且相互绝缘的自电容电极，且所述阵列基板还包括：与对应的自电容电极电性连接的多条导线；从而可以实现将自电容触摸结构中的触控电极(即，自电容电极)和导线内嵌到阵列基板中，以便于实现内嵌式触摸屏；
由于导线和公共电极层异层设置，从而可以消除自电容触摸结构中的触控盲区，以提高包含所述自电容触摸结构的触摸屏的触控性能；
另外，由于阵列基板包含的公共电极层包括多个同层设置且相互绝缘的自电容电极，从而可以将公共电极层作为自电容触摸结构中的触控电极使用，避免单独设置所述触控电极所在膜层，以简化膜层数量。
例如，所述公共电极层包括的自电容电极的实施方式与现有技术中自电容触摸结构包括的自电容电极的实施方式类似，在此不再赘述。
例如，本发明实施例中的导线的位置连接关系只要满足如下条件即可：位于所述漏极、源极和数据线所在膜层之上，与所述漏极、源极、数据线和像素电极电性绝缘；以及，与所述公共电极层异层设置，且每条所述导线通过第二过孔与对应的自电容电极电性连接。
下面将对本发明实施例中的导线与阵列基板包含的多个膜层之间的位置连接关系的实施方式进行介绍。
一、所述导线所在膜层位于所述漏极、源极和数据线所在膜层和所述公共电极层之间。
实施中，所述导线所在膜层位于所述漏极、源极和数据线所在膜层和所述公共电极层之间，可以减少人体电容对在导线上传输的信号的干扰。
需要说明的是，在所述导线所在膜层位于所述漏极、源极和数据线所在膜层和所述公共电极层之间时，所述导线所在膜层可以位于所述漏极、源极和数据线所在膜层和像素电极所在膜层之间；也可以位于所述像素电极所在膜层和所述公共电极层之间，下面将分别进行介绍。
1、所述导线所在膜层位于所述漏极、源极和数据线所在膜层和所述像素电极所在膜层之间。
实施中，所述导线所在膜层位于所述漏极、源极和数据线所在膜层和所述像素电极所在膜层之间，可以保证像素电极所在膜层和公共电极层之间的距离比较小，从而可以保证像素电极和公共电极层之间形成的电场足够强，以提高显示效果。
例如，所述漏极、源极和数据线所在膜层和所述像素电极所在膜层之间设置有包含所述第一过孔的第一钝化层；
所述导线所在膜层可以位于所述漏极、源极和数据线所在膜层和所述第一钝化层所在膜层之间，也可以位于所述第一钝化层所在膜层和所述像素电极所在膜层之间。
例如，如图2所示，所述漏极31、源极32和数据线33所在膜层和所述像素电极40所在膜层之间设置有包含所述第一过孔100的第一钝化层70；
所述导线60所在膜层位于所述第一钝化层70和所述像素电极40所在膜层之间；
所述阵列基板还包括：
第一绝缘层80，位于所述导线60所在膜层和所述像素电极40所在膜层之间，且包含所述第一过孔100和第二过孔200；
其中，所述像素电极40通过所述第一绝缘层80包含的第一过孔100和所述第一钝化层70包含的第一过孔100，与所述漏极31电性连接；所述导线60通过所述第一绝缘层80包含的第二过孔200，与所述自电容电极51电性连接。
实施中，所述导线所在膜层位于所述第一钝化层所在膜层和所述像素电极所在膜层之间，可以减少第二过孔的数量，从而可以简化制作阵列基板工 艺的复杂度。
需要说明的是，所述导线所在膜层位于所述漏极、源极和数据线所在膜层和所述第一钝化层所在膜层之间的实施方式，与所述导线所在膜层位于所述第一钝化层所在膜层和所述像素电极所在膜层之间的实施方式类似；只不过，在所述导线所在膜层位于所述漏极、源极和数据线所在膜层和所述第一钝化层所在膜层之间时，所述第一绝缘层需要位于所述漏极、源极和数据线所在膜层和所述导线所在膜层之间，且所述第一钝化层除了包含第一过孔，还需要包含第二过孔。
例如，如图2所示，所述导线60所在膜层位于所述漏极31、源极32和数据线33所在膜层和所述像素电极40所在膜层之间；
所述阵列基板还包括：
第二钝化层90，位于所述像素电极40所在膜层和所述公共电极层50之间。
实施中，第二钝化层位于所述像素电极所在膜层和所述公共电极层之间，可以保证像素电极和公共电极层电性绝缘。
例如，如图2所示，所述阵列基板还包括：
栅绝缘层110，位于所述栅极11和栅线12所在膜层和所述有源层20之间。
具体实施中，本发明实施例中的栅绝缘层的实施方式与现有技术中栅绝缘层的实施方式类似，在此不再赘述。
2、所述导线所在膜层位于所述像素电极所在膜层和所述公共电极层之间。
实施中，所述导线所在膜层位于所述像素电极所在膜层和所述公共电极层之间，可以减少第二过孔和第一过孔的数量，以简化制作阵列基板工艺的复杂度。
例如，所述像素电极所在膜层和所述公共电极层之间设置有第二钝化层；
所述导线所在膜层可以位于所述像素电极所在膜层和所述第二钝化层之间，也可以位于所述第二钝化层和所述公共电极层之间。
例如，所述像素电极所在膜层和所述公共电极层之间设置有第二钝化层；
所述导线所在膜层位于所述第二钝化层和所述公共电极层之间；
所述阵列基板还包括：
第二绝缘层，位于所述导线所在膜层和所述公共电极层之间，且包含所述第二过孔；
其中，所述导线通过所述第二绝缘层包含的第二过孔，与所述自电容电极电性连接。
实施中，只需要在第二绝缘层中设置第二过孔，既可以实现本发明实施例中的方案，从而可以简化制作阵列基板工艺的复杂度。
需要说明的是，所述导线所在膜层位于所述像素电极所在膜层和所述第二钝化层之间的实施方式，与所述导线所在膜层位于所述第二钝化层和所述公共电极层之间的实施方式类似；只不过，在所述导线所在膜层位于所述像素电极所在膜层和所述第二钝化层之间时，所述第二绝缘层需要位于所述像素电极所在膜层和所述导线所在膜层之间且不包含过孔，且所述第二钝化层需要包含第二过孔。
二、所述导线所在膜层位于所述公共电极层之上。
实施中，所述导线所在膜层位于所述公共电极层之上。可以保证不改变现有阵列基板包含的各膜层之间的连接关系。
例如，所述阵列基板还包括：
第三绝缘层，位于所述导线所在膜层和所述公共电极层之间，且包含所述第二过孔；
其中，所述导线通过所述第三绝缘层包含的第二过孔，与所述自电容电极电性连接。
下面将以所述导线的位置与栅线和/或数据线的位置之间的关系为分类依据，对本发明实施例的所述导线的位置的实施方式进行介绍。
例如，所述导线在所述衬底基板上的正投影位于所述数据线在所述衬底基板上的正投影内；和/或
所述导线在所述衬底基板上的正投影位于所述栅线在所述衬底基板上的正投影内。
比如，如图3所示，通过第二过孔200与对应的自电容电极51电性连接的所述导线60在所述衬底基板(图3中未示出衬底基板)上的正投影位于所述数据线33在所述衬底基板上的正投影内。
实施中，所述导线在所述衬底基板上的正投影位于所述数据线在所述衬底基板上的正投影内；和/或所述导线在所述衬底基板上的正投影位于所述栅线在所述衬底基板上的正投影内，可以保证所述导线产生的电场不会影响像素开口区域的电场，因此，不会影响正常显示。
实施中，所述导线在所述衬底基板上的正投影位于所述数据线在所述衬底基板上的正投影内；和/或所述导线在所述衬底基板上的正投影位于所述栅线在所述衬底基板上的正投影内，可以避免影响透过率。
实施中，所述导线在所述衬底基板上的正投影位于所述数据线在所述衬底基板上的正投影内，可以保证各导线的延伸方向与所述数据线的延伸方向一致，有利于窄边框设计。
需要说明的是，本发明实施例中的所述导线与所述栅线和数据线的位置关系的实施方式也可以为其他实施方式，比如，所述数据线和/或栅线在所述衬底基板上的正投影位于所述导线在所述衬底基板上的正投影内；或者，所述导线在所述衬底基板上的正投影与所述数据线和/或栅线在所述衬底基板上的正投影部分交叠；或者，所述导线在所述衬底基板上的正投影与所述数据线和/或栅线在所述衬底基板上的正投影无交叠等，在此不再赘述。
例如，与现有技术中导线与自电容电极的对应关系的实施方式类似，在本发明实施例中，一个自电容电极可以与至少一条导线电性连接，且各自电容电极电性连接的导线不同。
下面以图4为例，对本发明实施例中的导线和公共电极层的位置连接关系进行介绍。
如图4所示，公共电极层50包括多个同层设置且相互绝缘的呈矩阵式排布的自电容电极51；
一条导线60电性连接一个自电容电极51，各自电容电极51电性连接的导线60不同；
导线60与公共电极层50异层设置，且每条导线60通过第二过孔200与对应的自电容电极51电性连接。
例如，将所述导线作为在显示扫描时间内向所述公共电极层供电的公共电极线使用。
实施中，将所述导线作为在显示扫描时间内向所述公共电极层供电的公 共电极线使用，可以节省阵列基板包含的走线数量，以降低制作阵列基板的复杂度。
实施中，在公共电极线为与栅极和栅线所在膜层同层设置、与所述公共电极层异层设置、且通过过孔与所述公共电极层电性连接的gate Vcom line时，将所述导线作为在显示扫描时间内向所述公共电极层供电的公共电极线使用，还可以避免对位于栅极和栅线所在膜层和公共电极层之间的各膜层进行过孔刻蚀以电性连接gate Vcom line和公共电极层，以减少制作阵列基板所采用的掩膜版，降低制作阵列基板的成本和复杂度。
基于同一发明构思，本发明实施例同时还提供了一种显示装置，包括：本发明实施例中所述的阵列基板；
该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件；
该显示装置的实施可以参见上述实施例，重复之处不再赘述。
实施中，由于本发明实施例中所述的阵列基板内嵌有自电容触摸结构中的触控电极(即，自电容电极)和导线，因此，包含本发明实施例中所述的阵列基板的显示装置同时具有显示功能和触控功能。
实施中，由于本发明实施例中所述的阵列基板可以消除自电容触摸结构中的触控盲区，因此，包含本发明实施例中所述的阵列基板的显示装置也可以消除触控盲区，提高触控性能；
实施中，由于本发明实施例中所述的阵列基板可以简化膜层数量，因此，包含本发明实施例中所述的阵列基板的显示装置也可以简化膜层数量。
例如，所述显示装置还包括：与所述阵列基板相对设置的彩膜基板；其中，所述彩膜基板包括依次层叠的：衬底基板、黑矩阵层、彩膜层、平坦化层和PS(隔垫物层)。
例如，本发明实施例还提供了一种对所述显示装置的扫描方法，包括：
在一帧时间内，分时进行触摸扫描和显示扫描；其中：
在触摸扫描时间内，通过与各自电容电极相连的导线，分时向各自电容电极施加驱动信号；接收各自电容电极的反馈信号，并根据反馈信号判断触控位置。
实施中，分时进行触摸扫描和显示扫描，可以降低显示信号和触控信号 之间的相互干扰，提高画面品质和触控准确性。
例如，可以由触控侦测芯片通过与各自电容电极相连的导线，分时向各自电容电极施加驱动信号；接收各自电容电极的反馈信号，并根据反馈信号判断触控位置。
例如，触控侦测芯片设置于电路板上，具体可以设置于位于显示装置背部的电路板上，可以设置于位于显示装置的边框区域的电路板上，也可以设置于所述阵列基板包含的柔性电路板上。
例如，在具体实施中，可以将显示驱动芯片和触控侦测芯片整合为一个芯片，以降低生产成本。
下面将结合图5，对本发明实施例中对所述显示装置的扫描方法进行详细介绍。
如图5所示，将显示装置显示每一帧(V-sync)的时间分成显示扫描时间段(Display)和触摸扫描时间段(Touch)，比如，显示装置的显示一帧的时间为16.7ms，选取其中5ms作为触摸扫描时间段，其他的11.7ms作为显示扫描时间段，当然也可以根据IC芯片的处理能力适当的调整两者的时长，在此不做具体限定；
在显示扫描时间段(Display)，对显示装置中的每条栅极信号线Gate1，Gate2……Gate n依次施加栅扫描信号，对数据信号线Data施加灰阶信号，实现显示功能；
在触控时间段(Touch)，触控侦测芯片分时向各自电容电极Cx1……Cxn施加驱动信号；同时，接收各自电容电极Cx1……Cxn的反馈信号，通过对各自电容电极Cx1……Cxn的反馈信号的分析，判断出触控位置，以实现触控功能。
例如，触控侦测芯片通过对各自电容电极Cx1……Cxn的反馈信号的分析以判断出触控位置的实施方式与现有技术中实施方式类似，在此不再赘述。
例如，如图5所示，在显示扫描时间段(Display)，各自电容电极上施加Vcom电压。
实施中，可以保证显示装置正常进行显示。
例如，如图5所示，在触控时间段(Touch)，数据信号线和各栅极信号线上施加GND信号。
例如，可以减少数据信号线和各栅极信号线上的信号对导线上传输的信号的干扰。
例如，在分时向各自电容电极施加驱动信号时，可以横向逐个扫描各自电容电极，以分时向各自电容电极施加驱动信号；可以竖向逐个扫描各自电容电极，以分时向各自电容电极施加驱动信号。
具体实施中，也可以采用全驱(all driving)的方式，向各自电容电极施加驱动信号；具体实施方式与现有技术中的实施方式类似，在此不再赘述。
基于同一发明构思，本发明实施例同时还提供了一种制作阵列基板的方法，包括：
步骤601、在衬底基板上依次形成所述栅极和栅线所在膜层，有源层，以及所述漏极、源极和数据线所在膜层；
步骤602、在所述漏极、源极和数据线所在膜层上形成所述通过第一过孔与所述漏极电性连接的像素电极，位于所述像素电极所在膜层上且与所述像素电极电性绝缘的公共电极层，以及多条导线；
其中，所述公共电极层包括多个同层设置且相互绝缘的自电容电极；所述导线与所述漏极、源极、数据线和像素电极电性绝缘，与所述公共电极层异层设置，且每条所述导线通过第二过孔与对应的自电容电极电性连接。
实施例一
在本发明实施例一中，将对制作如图2所示的阵列基板的方法进行详细介绍。
较佳地，本发明实施例的阵列基板的制作方法，包括：
步骤1、如图2所示，在衬底基板00上形成栅极11和栅线12；
其中，通过一次Gate Mask(栅刻蚀)工艺，在衬底基板上形成电性连接的栅极和栅线。
其中，在现有技术中，通过一次Gate Mask工艺，在衬底基板上还形成有与栅极和栅线同层设置且电性绝缘的gate Vcom line；
而在本发明实施例中，可以制作该gate Vcom line，也可以不制作该gate Vcom line。
步骤2、如图2所示，在栅极11和栅线12所在膜层上形成栅绝缘层110；
步骤3、如图2所示，在栅绝缘层110上形成有源层20；
其中，通过一次Active Mask(有源层刻蚀)工艺，在栅绝缘层11上形成有源层。
其中，在现有技术中，在Active Mask工艺后，还需要进行一次GI Mask(栅绝缘层刻蚀)工艺，以在栅绝缘层中形成露出gate Vcom line的过孔；
而在本发明实施例中，在不制作该gate Vcom line时，无需进行该GI Mask工艺步骤。
步骤4、如图2所示，在有源层20上形成漏极31、源极32和数据线33；
其中，通过一次SD Mask(源漏刻蚀)工艺，在有源层上形成漏极、源极和数据线。
步骤5、如图2所示，在所述漏极31、源极32和数据线33所在膜层上形成包含露出漏极31的第一过孔100的第一钝化层70；
其中，通过一次PVX1 Mask(第一钝化层刻蚀)工艺，形成包含露出漏极的第一过孔的第一钝化层。
其中，在现有技术中，在PVX1 Mask工艺中，还需要在第一钝化层中形成露出gate Vcom line的过孔；
而在本发明实施例中，在不制作该gate Vcom line时，无需在第一钝化层中形成露出gate Vcom line的过孔。
步骤6、如图2所示，在第一钝化层70上形成导线60；
其中，通过一次Metal Mask(导线刻蚀)工艺，形成所述导线。
步骤7、如图2所示，在导线60所在膜层上形成第一绝缘层80，所述第一绝缘层80包含露出漏极31的第一过孔100、以及露出导线60的第二过孔200；
其中，通过一次I Mask(绝缘层刻蚀)工艺，形成包含第一过孔和第二过孔的第一绝缘层。
其中，在本发明实施例中，在制作该gate Vcom line时，需要在第一绝缘层中形成露出gate Vcom line的过孔。
步骤8、如图2所示，在第一绝缘层80上形成像素电极40，所述像素电极40通过所述第一绝缘层80包含的第一过孔100和所述第一钝化层70包含的第一过孔100，与所述漏极31电性连接；
其中，通过一次1st ITO Mask(像素电极刻蚀)工艺，形成所述像素电 极。
步骤9、如图2所示，在所述像素电极40所在膜层上形成包含第二过孔200的第二钝化层90；
其中，通过一次PVX2 Mask(第二钝化层刻蚀)工艺，形成包含第二过孔的所述第二钝化层。
其中，在现有技术中，在PVX2 Mask工艺中，还需要在第二钝化层中形成露出gate Vcom line的过孔；
而在本发明实施例中，在不制作该gate Vcom line时，无需在第二钝化层中形成露出gate Vcom line的过孔。
步骤10、如图2所示，在第二钝化层上形成包括多个同层设置且相互绝缘的自电容电极51的公共电极层50；所述导线60通过所述第一绝缘层80包含的第二过孔200和第二钝化层90包含的第二过孔200，与对应的自电容电极51电性连接。
其中，通过一次2nd ITO Mask(公共电极层刻蚀)工艺，形成所述公共电极层。
实施例二
在本发明实施例二中，将对制作与阵列基板相对设置的彩膜基板的方法进行详细介绍。
本发明实施例的彩膜基板的制作方法，包括：
步骤1、在衬底基板上形成黑矩阵层；
其中，通过一次BM Mask(黑矩阵层刻蚀)工艺，在衬底基板上形成黑矩阵层。
步骤2、在黑矩阵层上形成RGB(红绿蓝)彩膜层；
其中，分别通过R Mask(红色亚像素单元刻蚀)工艺、G Mask(绿色亚像素单元刻蚀)工艺、以及Mask(蓝色亚像素单元刻蚀)工艺，在黑矩阵层上形成所述RGB彩膜层。
步骤3、在RGB彩膜层上形成平坦化层；
步骤4、在平坦化层上形成PS。
其中，通过一次PS Mask(隔垫物层刻蚀)工艺，形成所述PS。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了 基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。本申请要求于2014年5月30日递交的中国专利申请第201410239888.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (12)

  1. 一种阵列基板，包括：衬底基板，位于所述衬底基板上的栅极和栅线，位于所述栅极和栅线所在膜层上的有源层，位于所述有源层上的漏极、源极和数据线，位于所述漏极、源极和数据线所在膜层上且通过第一过孔与所述漏极电性连接的像素电极，以及位于所述像素电极所在膜层上且与所述像素电极电性绝缘的公共电极层；其中，
    所述公共电极层包括多个同层设置且相互绝缘的自电容电极；
    所述阵列基板还包括：
    多条导线，位于所述漏极、源极和数据线所在膜层之上，与所述漏极、源极、数据线和像素电极电性绝缘；以及，与所述公共电极层异层设置，且每条所述导线通过第二过孔与对应的自电容电极电性连接。
  2. 如权利要求1所述的阵列基板，其中，所述导线所在膜层位于所述漏极、源极和数据线所在膜层和所述公共电极层之间。
  3. 如权利要求2所述的阵列基板，其中，所述导线所在膜层位于所述漏极、源极和数据线所在膜层和所述像素电极所在膜层之间。
  4. 如权利要求3所述的阵列基板，其中，所述漏极、源极和数据线所在膜层和所述像素电极所在膜层之间设置有第一钝化层，且所述第一过孔贯穿所述第一钝化层；
    所述导线所在膜层位于所述第一钝化层和所述像素电极所在膜层之间；
    所述阵列基板还包括：
    第一绝缘层，位于所述导线所在膜层和所述像素电极所在膜层之间，且所述第一过孔和所述第二过孔均贯穿所述第一绝缘层；
    其中，所述像素电极通过所述第一过孔与所述漏极电性连接。
  5. 如权利要求2所述的阵列基板，其中，所述导线所在膜层位于所述像素电极所在膜层和所述公共电极层之间。
  6. 如权利要求5所述的阵列基板，其中，所述像素电极所在膜层和所述公共电极层之间设置有第二钝化层；
    所述导线所在膜层位于所述第二钝化层和所述公共电极层之间；
    所述阵列基板还包括：
    第二绝缘层，位于所述导线所在膜层和所述公共电极层之间，且所述第二过孔贯穿所述第二绝缘层。
  7. 如权利要求1所述的阵列基板，其中，所述导线所在膜层位于所述公共电极层之上。
  8. 如权利要求7所述的阵列基板，还包括：
    第三绝缘层，位于所述导线所在膜层和所述公共电极层之间，且所述第二过孔贯穿所述第三绝缘层。
  9. 如权利要求1～8任一所述的阵列基板，其中，所述导线在所述衬底基板上的正投影位于所述数据线在所述衬底基板上的正投影内；和/或
    所述导线在所述衬底基板上的正投影位于所述栅线在所述衬底基板上的正投影内。
  10. 如权利要求1～8任一所述的阵列基板，其中，将所述导线作为在显示扫描时间内向所述公共电极层供电的公共电极线使用。
  11. 一种显示装置，包括如权利要求1～10任一项所述的阵列基板。
  12. 一种阵列基板的制作方法，包括：
    在衬底基板上依次形成所述栅极和栅线所在膜层，有源层，以及所述漏极、源极和数据线所在膜层；
    在所述漏极、源极和数据线所在膜层上形成所述通过第一过孔与所述漏极电性连接的像素电极，位于所述像素电极所在膜层上且与所述像素电极电性绝缘的公共电极层，以及多条导线；
    其中，所述公共电极层包括多个同层设置且相互绝缘的自电容电极；所述导线与所述漏极、源极、数据线和像素电极电性绝缘，与所述公共电极层异层设置，且每条所述导线通过第二过孔与对应的自电容电极电性连接。
PCT/CN2014/088083 2014-05-30 2014-10-01 阵列基板及其制作方法、以及显示装置 WO2015180359A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP14861115.5A EP3151278B1 (en) 2014-05-30 2014-10-01 Array substrate and manufacturing method therefor, and display device
US14/443,280 US9559690B2 (en) 2014-05-30 2014-10-01 Array substrate and manufacturing method thereof, and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410239888.4A CN104022127B (zh) 2014-05-30 2014-05-30 一种阵列基板及其制作方法、以及显示装置
CN201410239888.4 2014-05-30

Publications (1)

Publication Number Publication Date
WO2015180359A1 true WO2015180359A1 (zh) 2015-12-03

Family

ID=51438797

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/088083 WO2015180359A1 (zh) 2014-05-30 2014-10-01 阵列基板及其制作方法、以及显示装置

Country Status (4)

Country Link
US (1) US9559690B2 (zh)
EP (1) EP3151278B1 (zh)
CN (1) CN104022127B (zh)
WO (1) WO2015180359A1 (zh)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104022128B (zh) * 2014-05-30 2017-02-15 京东方科技集团股份有限公司 一种阵列基板及其制作方法、以及显示装置
CN104022127B (zh) 2014-05-30 2016-10-05 京东方科技集团股份有限公司 一种阵列基板及其制作方法、以及显示装置
KR102169034B1 (ko) * 2014-07-25 2020-10-23 엘지디스플레이 주식회사 표시장치 및 그 제조방법
CN104460080A (zh) * 2014-12-04 2015-03-25 深圳市华星光电技术有限公司 触控显示装置
CN104407757A (zh) 2014-12-04 2015-03-11 深圳市华星光电技术有限公司 触控显示装置
KR101712246B1 (ko) * 2014-12-05 2017-03-06 엘지디스플레이 주식회사 자기 정전용량식 터치 센서 일체형 표시장치
CN104536603B (zh) * 2014-12-18 2018-01-09 深圳市华星光电技术有限公司 显示器及具有触控功能的面板
CN104503619B (zh) * 2014-12-31 2017-09-05 深圳市华星光电技术有限公司 一种阵列基板的制造方法及触摸屏
CN104503648B (zh) 2015-01-09 2017-06-09 京东方科技集团股份有限公司 一种内嵌式触摸屏及显示装置
CN104571768B (zh) * 2015-01-30 2018-03-20 京东方科技集团股份有限公司 一种阵列基板、内嵌式触摸屏和显示装置
CN104731405B (zh) * 2015-03-09 2018-01-19 上海天马微电子有限公司 一种触控显示装置及其制造方法
CN104793820A (zh) * 2015-03-31 2015-07-22 深圳市华星光电技术有限公司 自电容式触摸屏结构、内嵌式触摸屏以及液晶显示器
CN104733477B (zh) * 2015-04-01 2018-04-13 上海天马微电子有限公司 阵列基板及其制作方法、显示面板、显示装置
CN104699357B (zh) * 2015-04-01 2018-01-09 上海天马微电子有限公司 一种电子设备、触摸显示面板以及触控显示基板
CN104699321B (zh) * 2015-04-01 2018-03-23 上海天马微电子有限公司 触控显示基板和触控显示装置
CN104777933B (zh) 2015-04-09 2018-02-06 上海天马微电子有限公司 一种阵列基板、触控显示面板及显示装置
KR102263876B1 (ko) * 2015-05-29 2021-06-14 엘지디스플레이 주식회사 인셀 터치 액정 디스플레이 장치와 그 제조방법
CN104866153B (zh) * 2015-05-29 2018-01-16 武汉华星光电技术有限公司 自电容式内嵌触摸屏及其制备方法、液晶显示器
CN104865726B (zh) 2015-06-04 2018-08-14 上海天马微电子有限公司 一种阵列基板、显示面板、显示装置以及制备方法
CN105159486A (zh) 2015-07-14 2015-12-16 京东方科技集团股份有限公司 Ads阵列基板及其制作方法、显示器件
US20170017338A1 (en) * 2015-07-17 2017-01-19 Innolux Corporation Touch display device
TW201704958A (zh) * 2015-07-17 2017-02-01 群創光電股份有限公司 觸控顯示面板及觸控模式的驅動方法
CN105867686A (zh) * 2016-03-28 2016-08-17 南京中电熊猫液晶显示科技有限公司 一种In-Cell触控显示面板
CN105717690A (zh) * 2016-04-27 2016-06-29 武汉华星光电技术有限公司 内嵌触摸屏及其制备方法、液晶显示器
CN105808014B (zh) 2016-05-19 2019-07-02 京东方科技集团股份有限公司 一种阵列基板及其制作方法、触控显示装置
CN106353937B (zh) * 2016-11-28 2020-11-24 京东方科技集团股份有限公司 阵列基板、阵列基板的制造方法和显示装置
CN106896602B (zh) * 2017-03-14 2020-02-07 上海中航光电子有限公司 阵列基板、显示面板、显示装置及制作方法
CN108364931B (zh) * 2018-02-28 2020-01-03 武汉华星光电技术有限公司 阵列基板、显示面板和移动终端
US10551705B2 (en) * 2018-02-28 2020-02-04 Wuhan China Star Optoelectronics Technology Co., Ltd. Array substrate, display panel and mobile terminal
US10825838B2 (en) 2018-03-29 2020-11-03 Wuhan China Star Optoelectronics Technology Co., Ltd. Array substrate and its manufacturing method and display device
CN108461507A (zh) * 2018-03-29 2018-08-28 武汉华星光电技术有限公司 一种阵列基板及其制备方法、显示器
US11086461B2 (en) 2019-01-02 2021-08-10 Boe Technology Group Co., Ltd. Array substrate, embedded touch screen, and display device
CN113360013B (zh) * 2020-03-05 2023-10-31 北京京东方显示技术有限公司 阵列基板、显示装置及阵列基板的制作方法
CN115145418A (zh) * 2021-03-31 2022-10-04 京东方科技集团股份有限公司 一种显示基板和显示装置
US20240155889A1 (en) * 2021-05-26 2024-05-09 Hefei Boe Joint Technology Co., Ltd. Display panel and display device
CN114489382A (zh) * 2022-01-27 2022-05-13 上海天马微电子有限公司 触控面板和触控装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130135247A1 (en) * 2011-11-24 2013-05-30 Samsung Electro-Mechanics Co., Ltd. Touch sensing apparatus
CN103279244A (zh) * 2013-06-06 2013-09-04 敦泰科技有限公司 一种电容式触摸屏
CN103353819A (zh) * 2013-07-05 2013-10-16 浙江大学 具有高精度手写笔输入功能的自电容多点触摸屏
CN103793120A (zh) * 2014-01-28 2014-05-14 北京京东方光电科技有限公司 一种内嵌式触摸屏及显示装置
CN103809807A (zh) * 2012-11-12 2014-05-21 乐金显示有限公司 显示装置及其驱动方法
CN104022127A (zh) * 2014-05-30 2014-09-03 京东方科技集团股份有限公司 一种阵列基板及其制作方法、以及显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG136795A1 (en) 2000-09-14 2007-11-29 Semiconductor Energy Lab Semiconductor device and manufacturing method thereof
US8994673B2 (en) * 2011-12-09 2015-03-31 Lg Display Co., Ltd. Display device with integrated touch screen having electrical connections provided in inactive regions of display panel
KR101295536B1 (ko) * 2012-03-26 2013-08-12 엘지디스플레이 주식회사 터치 스크린 일체형 표시장치 및 그 제조 방법
KR101466556B1 (ko) 2012-03-29 2014-11-28 엘지디스플레이 주식회사 액정표시장치 및 그 제조방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130135247A1 (en) * 2011-11-24 2013-05-30 Samsung Electro-Mechanics Co., Ltd. Touch sensing apparatus
CN103809807A (zh) * 2012-11-12 2014-05-21 乐金显示有限公司 显示装置及其驱动方法
CN103279244A (zh) * 2013-06-06 2013-09-04 敦泰科技有限公司 一种电容式触摸屏
CN103353819A (zh) * 2013-07-05 2013-10-16 浙江大学 具有高精度手写笔输入功能的自电容多点触摸屏
CN103793120A (zh) * 2014-01-28 2014-05-14 北京京东方光电科技有限公司 一种内嵌式触摸屏及显示装置
CN104022127A (zh) * 2014-05-30 2014-09-03 京东方科技集团股份有限公司 一种阵列基板及其制作方法、以及显示装置

Also Published As

Publication number Publication date
EP3151278A4 (en) 2018-01-17
EP3151278A1 (en) 2017-04-05
CN104022127B (zh) 2016-10-05
CN104022127A (zh) 2014-09-03
US20160294386A1 (en) 2016-10-06
US9559690B2 (en) 2017-01-31
EP3151278B1 (en) 2020-04-29

Similar Documents

Publication Publication Date Title
WO2015180359A1 (zh) 阵列基板及其制作方法、以及显示装置
WO2015180358A1 (zh) 阵列基板及其制作方法和显示装置
WO2015180356A1 (zh) 电容式触摸结构、内嵌式触摸屏、显示装置及其扫描方法
WO2015180322A1 (zh) 内嵌式触摸屏以及显示装置
WO2015180312A1 (zh) 内嵌式触摸屏及显示装置
WO2016112693A1 (zh) 内嵌式触摸屏及显示装置
WO2015180311A1 (zh) 内嵌式触摸屏及显示装置
WO2015180316A1 (zh) 内嵌式触摸屏及显示装置
WO2016119445A1 (zh) 内嵌式触摸屏及显示装置
WO2015180303A1 (zh) 内嵌式触摸屏及显示装置
WO2015158083A1 (zh) 触摸屏及显示装置
WO2015180321A1 (zh) 内嵌式触摸屏及显示装置
US10013121B2 (en) In-cell touch panel and display device with self-capacitance electrodes
WO2015180318A1 (zh) 内嵌式触摸屏及显示装置
WO2015180315A1 (zh) 电容式触摸结构、内嵌式触摸屏、显示装置及其扫描方法
WO2015180313A1 (zh) 内嵌式触摸屏及显示装置
WO2016123985A1 (zh) 阵列基板及其制作方法和驱动方法、显示装置
WO2015180314A1 (zh) 内嵌式触摸屏及显示装置
WO2016110016A1 (zh) 一种内嵌式触摸屏及显示装置
US9830028B2 (en) In-cell touch panel with self-capacitive electrodes and display device
WO2017024716A1 (zh) 触控显示面板及其驱动方法、显示装置
WO2014139229A1 (zh) 电容式内嵌触摸屏及显示装置
WO2019000531A1 (zh) 触控显示面板及触控显示装置
WO2014183375A1 (zh) 电容式触摸屏、电容式触摸屏制备方法及显示装置
WO2015180274A1 (zh) 内嵌式触摸屏及显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14443280

Country of ref document: US

REEP Request for entry into the european phase

Ref document number: 2014861115

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2014861115

Country of ref document: EP

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14861115

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE