WO2015180321A1 - 内嵌式触摸屏及显示装置 - Google Patents

内嵌式触摸屏及显示装置 Download PDF

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Publication number
WO2015180321A1
WO2015180321A1 PCT/CN2014/087155 CN2014087155W WO2015180321A1 WO 2015180321 A1 WO2015180321 A1 WO 2015180321A1 CN 2014087155 W CN2014087155 W CN 2014087155W WO 2015180321 A1 WO2015180321 A1 WO 2015180321A1
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Prior art keywords
layer
self
electrode
capacitance
disposed
Prior art date
Application number
PCT/CN2014/087155
Other languages
English (en)
French (fr)
Inventor
刘英明
董学
薛海林
王海生
赵卫杰
杨盛际
丁小梁
刘红娟
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/650,708 priority Critical patent/US10409425B2/en
Priority to EP14866805.6A priority patent/EP3153955B1/en
Publication of WO2015180321A1 publication Critical patent/WO2015180321A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04107—Shielding in digitiser, i.e. guard or shielding arrangements, mostly for capacitive touchscreens, e.g. driven shields, driven grounds
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04112—Electrode mesh in capacitive digitiser: electrode for touch sensing is formed of a mesh of very fine, normally metallic, interconnected lines that are almost invisible to see. This provides a quite large but transparent electrode surface, without need for ITO or similar transparent conductive material

Definitions

  • At least one embodiment of the present invention is directed to an in-cell touch screen and display device.
  • the Touch Screen Panel With the rapid development of display technology, the Touch Screen Panel has gradually spread throughout people's lives.
  • the touch screen can be divided into an add-on touch panel, an on-cell touch panel, and an in-cell touch panel according to the composition structure.
  • the external touch screen is a touch-sensitive liquid crystal display formed by separately separating the touch screen from the liquid crystal display (LCD), and the external touch screen has high production cost and low light transmittance. Shortcomings such as thicker modules.
  • the in-cell touch screen embeds the touch electrode of the touch screen inside the liquid crystal display, which can reduce the thickness of the whole module, and can greatly reduce the manufacturing cost of the touch screen, and is favored by the major panel manufacturers.
  • the in-cell touch panel utilizes the principle of mutual capacitance or self-capacitance to detect the touch position of the finger.
  • a plurality of self-capacitance electrodes arranged in the same layer and insulated from each other can be disposed in the touch screen.
  • the capacitance of the respective capacitor electrodes is a fixed value
  • the touch detection chip can determine the touch position by detecting the change of the capacitance value of each capacitor electrode during the touch time period.
  • the touch capacitance caused by the human body touching the screen is larger than the touch screen produced by the mutual capacitance principle, so that the human body capacitance can only act on the projection capacitance in the mutual capacitance.
  • the self-capacitance touch screen can effectively improve the signal-to-noise ratio of the touch relative to the mutual-capacitance touch screen, thereby improving the accuracy of the touch sensing.
  • At least one embodiment of the present invention provides an in-cell touch panel and a display device for reducing mutual interference between a display signal and a touch signal, and improving picture quality and touch accuracy.
  • At least one embodiment of the present invention provides an in-cell touch panel including an upper substrate and a lower substrate disposed opposite to each other; and a side of the upper substrate facing the lower substrate or the lower substrate facing a plurality of self-capacitance electrodes disposed on one side of the upper substrate and insulated from each other; a shield electrode on a side of each of the self-capacitance electrodes facing the lower substrate, each of the self-capacitance electrodes and the shield electrode Insulating each other; and an insulating layer between each of the self-capacitance electrodes and the shield electrode.
  • a display device includes the above-described in-cell touch panel provided by the embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of an in-cell touch panel according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a self-capacitance electrode in an in-cell touch panel according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a wire and a self-capacitance electrode disposed in the same layer in an in-cell touch panel according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of a self-capacitance electrode partition of a display area in an in-cell touch panel according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of connection between a self-capacitance electrode and a conductive connection point disposed in the same layer in each area of the in-cell touch panel according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of a wire and a shield electrode disposed in the same layer in an in-cell touch panel according to an embodiment of the present invention
  • FIG. 7 is a schematic structural diagram of a self-capacitance electrode and a shield electrode simultaneously disposed on an upper substrate in an in-cell touch panel according to an embodiment of the present invention.
  • FIGS. 8a and 8b are schematic diagrams showing timings of touch and display time-sharing driving of an in-cell touch panel according to an embodiment of the present invention
  • FIG. 9 is a schematic diagram of timings of simultaneous driving and display driving of an in-cell touch panel according to an embodiment of the present invention.
  • each film layer in the drawings do not reflect the true scale, and are merely intended to illustrate the present invention.
  • the inventor of the present application has noticed that in the in-cell touch panel, in order to reduce the mutual interference between the display signal and the touch signal, and improve the picture quality and the touch accuracy, it is generally required to drive the touch and display phases in a time-sharing manner. Since the time of one frame is generally a fixed value, the time-division driving causes the touch time period and the display time period to have less time respectively, which may result in insufficient charging during the display time period and affect the normal display. The time period may detect the signal for too short a time and affect the touch effect.
  • the following in-cell touch panel provided by the embodiments of the present invention is applicable to both a twisted nematic (TN) liquid crystal display and an advanced Dimension Switch (ADS) type liquid crystal display and a plane.
  • TN twisted nematic
  • ADS advanced Dimension Switch
  • IPS In-Plane Switch
  • An in-cell touch panel provided by at least one embodiment of the present invention, as shown in FIG. 1 , includes an upper substrate 01 and a lower substrate 02 disposed opposite to each other; and a side or lower substrate 02 disposed on the upper substrate 01 facing the lower substrate 02 a plurality of self-capacitance electrodes 03 disposed on one side of the upper substrate 01 and insulated from each other (the structure in which the self-capacitance electrode is located on the side of the upper substrate 01 facing the lower substrate 02); at the respective capacitor electrodes 03
  • the shield electrode 05 facing one side of the lower substrate 02, the respective capacitor electrode 03 and the shield electrode 05 are insulated from each other; and the insulating layer 06 between the respective capacitor electrode 03 and the shield electrode 05.
  • the in-cell touch panel may further include a touch detection chip 04 that determines a touch position by detecting a change in a capacitance value of the respective capacitor electrode 03.
  • a plurality of self-capacitance electrodes 03 disposed in the same layer and insulated from each other are disposed in the touch screen by using the principle of self-capacitance, and are disposed on one side of the respective capacitor electrode faces 03 on the lower substrate 02.
  • the shielding electrode 05 is provided with an insulating layer 06 between the respective capacitor electrodes 03 and the shield electrodes 05; and the touch detection signal loaded from the capacitor electrode 03 is isolated from the display signal by the shield electrode 05 insulated from the self-capacitance electrode 03. Avoid mutual interference between the two, realize the synchronous execution of touch detection and display driver, and ensure better display and touch effects.
  • the in-cell touch panel provided by the different embodiments of the present invention may further include: disposed on a side of the upper substrate 01 facing the lower substrate 02, or disposed on a side of the lower substrate 02 facing the upper substrate 01, as shown in FIG.
  • the black matrix layer 07; the pattern of the respective capacitor electrodes 03 and the orthographic projection of the pattern of the shield electrode 05 on the lower substrate 02 may be located in the region of the pattern of the black matrix layer 07.
  • the shield electrode 05 and the self-capacitance electrode 03 can be made of metal; the shield electrode 05 and the self-capacitance electrode 03 can also be made of a transparent conductive material, for example, indium tin oxide (ITO) or indium zinc oxide (IZO) can be used. ) Transparent conductive materials such as materials, carbon nanotubes, and graphene.
  • the shield electrode 05 and the self-capacitance electrode 03 are generally made of metal, because the resistance of the metal is smaller than that of the ITO, which is advantageous for reducing the resistance of the shield electrode 05 and the self-capacitance electrode 03, improving the touch sensitivity and shielding electrodes. 05 shielding effect.
  • the density of the touch screen is usually on the order of millimeters. Therefore, in a specific implementation, the density and the occupied area of the respective capacitor electrodes 03 can be selected according to the required touch density to ensure the required touch density.
  • the respective capacitor electrodes 03 are designed as square electrodes of about 5 mm * 5 mm.
  • the density of the display screen is usually on the order of micrometers. Therefore, generally one self-capacitance electrode 03 corresponds to a plurality of pixel units in the display screen. In order to ensure that the pattern of the respective capacitor electrodes 03 does not occupy the opening area of the pixel unit, as shown in FIG.
  • the pattern of the position corresponding to the opening area of the pixel unit in the pattern of the respective capacitor electrodes 03 can be dug, that is, the respective capacitors can be
  • the pattern of the electrode 03 is designed such that the orthographic projection on the lower substrate 02 is in a lattice-like structure in the region where the pattern of the black matrix layer 07 is located.
  • a pattern of self-capacitance electrodes 03 may be disposed at a gap of each sub-pixel unit in each pixel unit, and each group of RGB sub-pixel units in FIG. 2 constitutes one pixel unit.
  • the density referred to in the embodiment of the present invention refers to the pitch of the self-capacitance electrodes of the touch screen or the pitch of the pixel units of the display screen.
  • the pattern of the shield electrode 05 can cover the pattern of the self-capacitance electrode 03, that is, Since the pattern of the self-capacitance electrode 03 can be a grid-like structure in which the orthographic projection of the lower substrate 02 is located in the region of the pattern of the black matrix layer 07, the pattern of the shield electrode can also be located at the black matrix layer on the orthographic projection of the lower substrate 02. The grid structure in the area where the pattern of 07 is located.
  • the in-cell touch panel provided by the embodiment of the present invention, as shown in FIG. 3, may further include: a corresponding wire 08, and a conduction connection point 09 corresponding to the self-capacitance electrode 03; each of the conduction connection points 09 is generally disposed in the area of the frame glue of the in-cell touch screen, and in order not to affect the normal display function,
  • the orthographic projection of each of the wires 08 on the lower substrate 02 is also located in the region of the pattern of the black matrix layer 07; the respective capacitor electrodes 03 are connected to the conduction connection point 09 through the wires 08, and are passed through the traces 10 and the contacts located in the region where the frame glue is located.
  • connection terminal 11 of the control detection chip is electrically connected.
  • FIG. 3 the case of eight self-capacitance electrodes 03 in a row is shown, and the number of the wires 08 and the conduction connection points 09 corresponding to the respective capacitance electrodes 03 may be one or more, and may be plural. Not limited.
  • the wire 08 and the conductive connection point 09 are generally disposed on the same substrate as the self-capacitance electrode 03, that is, may be disposed on the upper substrate 01 at the same time, or may be simultaneously disposed on the lower substrate 02; the trace 10 and the touch
  • the connection terminal 11 of the detecting chip is generally disposed on the lower substrate 02.
  • the conduction connection point 09 can pass through the upper and lower conduction of the conductive particles (such as a gold ball) in the sealant and the lower substrate 02
  • the trace 10 of the area where the border glue is located is electrically connected, and then led to the connection terminal 11 of the corresponding touch detection chip through the trace 10.
  • the conduction connection point 09 can be directly electrically connected to the trace 10 located in the region where the frame glue of the lower substrate 02 is located, and then through the trace 10 Lead to the connection terminal 11 of the corresponding touch detection chip.
  • each of the wires 08 may be disposed in the same layer as the respective capacitor electrodes 03.
  • the pattern of the shield electrode 05 on the lower substrate 02 covers the pattern of each of the wires 08 and the respective capacitor electrodes 03.
  • each of the wires 08 is disposed in the same layer as the respective capacitor electrodes 03, a pattern of the self-capacitance electrodes 03 and the wires 08 is designed by using a metal layer.
  • the wires 08 connecting the respective capacitor electrodes 03 are connected. It is necessary to do not cross each other. Therefore, when the wires are designed by the wiring method as shown in FIG. 3, the wires 08 connected to all the self-capacitance electrodes 03 are extended in one direction and connected to the same side region.
  • the corresponding wiring mode on the connection point 09 is turned on, a large number of touch dead zones may appear in the touch screen.
  • FIG. 3 shows a touch dead zone formed by eight self-capacitance electrodes 03 in a row, and only the pattern of the self-capacitance electrode 03 is illustrated in FIG. And the pattern of the wires 08 connected to the respective capacitor electrodes 03, the pattern of each sub-pixel unit is not shown; and, for convenience of viewing, the regions occupied by the respective capacitor electrodes 03 are shown in different filling patterns in FIG.
  • the wires 08 connecting the plurality of self-capacitance electrodes in the touch dead zone pass through the touch dead zone. Therefore, the signal in the touch blind zone is relatively disordered, so it is called a touch dead zone, that is, the touch in the area. Control performance is not guaranteed.
  • the conductive connection point 09 may be distributed on the four sides of the area where the frame glue of the in-cell touch screen is located, that is, the conductive connection point 09 is on the four sides of the area where the frame glue is located.
  • the sides are distributed such that the respective capacitive electrodes 03 are respectively connected to the corresponding conductive connection points 09 disposed around the display area by the wires 08, and the area of the touch dead zones can be reduced as a whole.
  • the design of the above-mentioned reduced touch dead zone provided by the embodiment of the present invention is illustrated by taking a 5-inch touch screen as an example.
  • all the self-capacitance electrodes 03 can be divided into 8 regions. : PartA to PartH, in each area, the self-capacitance electrodes 03 in the area need to be connected one by one to the FPC Bonding Pad of the touch detection chip below the display area.
  • FIG. 5 in each area of FIG.
  • three self-capacitance electrodes 03 are shown, and the respective capacitor electrodes of the Part A region are taken out from the upper left area of the display area, and are introduced to the touch detection through the left border of the display area.
  • the connection terminals of the test chip; the respective capacitive electrodes of the Part B region are drawn from above the display area, and then introduced from the left frame of the display area to the connection terminal of the touch detection chip; the respective capacitive electrodes of the Part C area are from the display area After the upper lead is taken out, the right border of the display area is introduced to the connection terminal of the touch detection chip; the respective capacitive electrodes of the Part D area are drawn from the upper right of the display area and then introduced to the touch detection chip through the right border of the display area.
  • the respective capacitor electrodes of the Part E region are led out from the lower left of the display area, and are introduced to the connection terminals of the touch detection chip through the left border of the display area; the respective capacitive electrodes of the Part F region are from the display area. Connected directly to the connection terminal of the touch detection chip; the respective capacitor electrodes of the Part G area are taken out from the lower side of the display area Connected to the connection terminal connected to a touch-sensing chip; Part H respective capacitor electrode from the lower right area of the display region extraction, is introduced to the connection terminal via a touch-sensing chip display area on the right frame.
  • FIG. 5 only shows the connection of the partial self-capacitance electrode 03 and the conduction connection point 09. relationship.
  • the size of the touch dead zone in Part A, Part D, Part E, and Part H on both sides of the display area is about 3 sub-pixel units, which is represented by h in FIG. 5, and is 5
  • the size of the corresponding pixel unit in the inch touch screen is estimated, and the touch dead zone is about 260 ⁇ m; the size of the touch dead zone in Part B, Part C, Part F, and Part G in the middle of the display area is about 10 sub-pixel units.
  • connection relationship between the self-capacitance electrode 03 and the conduction connection point 09 is merely an example, and can be designed according to the specific size of the touch screen in actual design.
  • the conductive connection point 09 corresponding to the respective capacitor electrode 03 can be distributed at the side of the region where the frame glue is closest to the self-capacitance electrode 03, so as to be shortened as much as possible.
  • the length of the wire 08 between the self-capacitance electrode 03 and the conduction connection point 09 is connected to minimize the area of the touch dead zone.
  • the self-capacitance electrode 03 and the wire 08 may be disposed in different layers.
  • the wire 08 and the shield electrode 05 may be disposed in the same layer, and the respective capacitor electrodes 03 and the corresponding wires 08 are electrically connected through the via holes in the insulating layer 06, so that the touch dead zone can be avoided.
  • Out of the line it can also be achieved without increasing the production process.
  • a wiring manner as shown in FIG. 6 may be adopted, that is, the wires 08 connected to all the self-capacitance electrodes 03 extend in one direction and are connected to the same region disposed in the region of the frame glue.
  • a corresponding conductive connection point 09 in one of the side regions.
  • Fig. 6 shows a pattern in which the wires and the shield electrode 05 are disposed in the same layer. It can be seen from Fig. 6 that the shield electrode 05 and the wires are insulated from each other.
  • the self-capacitance electrode 03 and the shield electrode 05 may be disposed on the upper substrate 01, and the existing film layer in the upper substrate 01 is used as the insulating layer 06.
  • the metal layer for fabricating the self-capacitance electrode 03 and the shield electrode 05 in the fabrication process of the upper substrate 01. For example, as shown in FIG.
  • the black matrix layer 07 may be located on a side of the upper substrate 01 facing the lower substrate 02, and a color filter layer 12 is generally disposed on the black matrix layer 07, and generally disposed on the color filter layer 12
  • the flat layer 13 and the flat layer 13 are generally provided A spacer layer 14 is placed.
  • a first possible implementation manner is as follows: As shown in FIG. 7, the color filter layer 12 is used as the insulating layer 06 between the self-capacitance electrode 03 and the shield electrode 05.
  • the respective capacitor electrodes 03 are located between the black matrix layer 07 and the color filter layer 12, and the respective wires 08 and shield electrodes 05 are located between the color filter layer 12 and the flat layer 13.
  • a second possible implementation is to use the flat layer 13 as the insulating layer 06 between the self-capacitance electrode 03 and the shield electrode 05.
  • the respective capacitor electrodes 03 are located between the color filter layer 12 and the flat layer 13, and the respective wires 08 and shield electrodes 05 are located between the flat layer 13 and the spacer layer 14.
  • a third possible implementation is to use the spacer layer 14 as an insulating layer 06 between the self-capacitance electrode 03 and the shield electrode 05.
  • the respective capacitor electrodes 03 are located between the flat layer 13 and the spacer layer 14, and the respective wires 08 and shield electrodes 05 are located above the spacer layer 14.
  • the wire 08 and the shield electrode 05 are disposed in the same metal layer, and the color filter layer 12 or the spacer layer 14 is used as the insulating layer 06, since both layers are The patterning process is required. Therefore, it is only necessary to change the mask pattern in the patterning process to increase the via pattern of the connecting line 08 and the self-capacitance electrode 03 without increasing the fabrication process; and using the flat layer 13 as the insulating layer 06 At this time, since the planarization layer 13 does not need to perform the patterning process, it is necessary to increase the mask of the corresponding flat layer 13, which increases a manufacturing process. Therefore, the position of the film layer of the self-capacitance electrode 03 and the shield electrode 05 may be required according to actual needs, which is not limited herein.
  • the self-capacitance electrode 03 and the shield electrode 05 may be disposed on the lower substrate 02, and the existing film layer in the lower substrate 02 is used as the insulating layer. 06, in this way, it is only necessary to increase the manufacturing process of the metal layer for fabricating the self-capacitance electrode 03 and the shield electrode 05 in the fabrication process of the lower substrate 02.
  • a common electrode layer is generally disposed on the lower substrate 02
  • a passivation layer is generally disposed on the common electrode layer
  • a pixel electrode layer is generally disposed on the passivation layer.
  • the passivation layer as the insulating layer 06 between the self-capacitance electrode 03 and the shield electrode 05.
  • the respective capacitor electrodes 03 may be located above the passivation layer, and each of the wires 08 and the shield electrode 05 are located between the common electrode layer and the passivation layer.
  • the self-capacitance electrode 03 is generally made of metal, it cannot be fabricated simultaneously with the pixel electrode layer made of ITO, and the pattern of the pixel electrode has a pattern only in the opening area of each pixel unit, and there is no picture in the pattern area of the black matrix layer. The pattern and the pattern of the self-capacitance electrode do not overlap, and therefore, the pattern of the self-capacitance electrode 03 can be formed before or after the pixel electrode layer is formed.
  • the shielding electrode is disposed under the self-capacitance electrode, the mutual interference between the touch detection signal and the display signal can be isolated, and thus the touch and display in the touch screen
  • the method of simultaneous driving may be adopted, or the method of time-division driving may be adopted, that is, the touch detection chip works in the display time period and the touch time period of each frame, or only in the touch time period of each frame.
  • the display driving chip and the touch detection chip can also be integrated into one chip to further reduce the production cost.
  • the time at which the touch screen displays each frame is divided into a display period and a touch period.
  • the time of displaying one frame of the touch screen is 16.7 ms, and 5 ms is selected as the touch time period, and the other 11.7 ms is used as the display time period.
  • the duration of the two chips can be appropriately adjusted according to the processing capability of the IC chip, and is not specifically limited herein.
  • a gate scan signal is sequentially applied to each of the gate signal lines Gate1, Gate2, ..., Gate n in the touch screen, and a gray scale signal is applied to the data signal line Data to realize a liquid crystal display function.
  • the touch detection chip connected to the respective capacitance electrodes Cx1 . . . Cx n can simultaneously apply driving signals to the respective capacitance electrodes Cx1 . . . Cx n while receiving the respective capacitance electrodes Cx1... a feedback signal of Cx n; or as shown in FIG. 8b, the touch detection chip connected to the respective capacitance electrodes Cx1 . . .
  • Cx n sequentially applies driving signals to the respective capacitance electrodes Cx1 . . . Cx n to respectively receive the respective capacitance electrodes
  • the feedback signals of Cx1...Cx n are not limited herein.
  • the touch function is implemented by analyzing the feedback signal to determine whether a touch occurs.
  • each gate signal line Gate1, Gate2, ... in the touch screen is gated. n sequentially applying a gate scan signal, applying a gray scale signal to the data signal line Data to realize a liquid crystal display function; meanwhile, the touch detection chip connected to the respective capacitor electrodes Cx1 . . . Cx n is directed to the respective capacitor electrodes Cx1 . . . Cx n
  • the driving signal is applied, and the feedback signals of the respective capacitive electrodes Cx1 . . . Cx n are received, and the touch signal is realized by analyzing the feedback signal to determine whether a touch occurs.
  • At least one embodiment of the present invention further provides a display device including the above-described in-cell touch panel provided by the embodiment of the present invention.
  • the display device can be: mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc. A product or part that exhibits functionality.
  • the in-cell touch panel and the display device provided by the embodiments of the present invention provide a plurality of self-capacitance electrodes disposed in the same layer and insulated from each other in the touch screen by using the principle of self-capacitance, and shielding is disposed on a side of the respective capacitor electrodes facing the lower substrate.
  • the electrode is provided with an insulating layer between the respective capacitor electrode and the shielding electrode; the touch detection signal loaded by the self-capacitance electrode is separated from the display signal by a shielding electrode insulated from the self-capacitance electrode to avoid mutual interference between the electrodes. Realize the synchronous execution of touch detection and display driver, while ensuring better display and touch effects.

Abstract

一种内嵌式触摸屏及显示装置，该内嵌式触摸屏包括：相对而置的上基板（01）和下基板（02）；设置于所述上基板（01）面向所述下基板（02）的一侧或所述下基板（02）面向所述上基板（01）的一侧的多个同层设置且相互绝缘的自电容电极（03）；位于各所述自电容电极（03）面向所述下基板（02）的一侧的屏蔽电极（05），各所述自电容电极（03）与所述屏蔽电极（05）相互绝缘；以及位于各所述自电容电极（03）和所述屏蔽电极（05）之间的绝缘层。该内嵌式触摸屏可以将自电容电极（03）加载的触控侦测信号与显示用信号隔离，避免两者之间相互干扰。

Description

内嵌式触摸屏及显示装置 技术领域
本发明的至少一个实施例涉及一种内嵌式触摸屏及显示装置。
背景技术
随着显示技术的飞速发展，触摸屏(Touch Screen Panel)已经逐渐遍及人们的生活中。目前，触摸屏按照组成结构可以分为：外挂式触摸屏(Add on Mode Touch Panel)、覆盖表面式触摸屏(On Cell Touch Panel)以及内嵌式触摸屏(In Cell Touch Panel)。外挂式触摸屏是将触摸屏与液晶显示屏(Liquid Crystal Display，LCD)分开生产，然后贴合到一起形成的具有触摸功能的液晶显示屏，外挂式触摸屏存在制作成本较高、光透过率较低、模组较厚等缺点。内嵌式触摸屏将触摸屏的触控电极内嵌在液晶显示屏内部，可以减薄模组整体的厚度，又可以大大降低触摸屏的制作成本，受到各大面板厂家青睐。
目前，内嵌式触摸屏是利用互电容或自电容的原理实现检测手指触摸位置。利用自电容的原理可以在触摸屏中设置多个同层设置且相互绝缘的自电容电极，当人体未触碰屏幕时，各自电容电极所承受的电容为一固定值，当人体触碰屏幕时，对应的自电容电极所承受的电容为固定值叠加人体电容，触控侦测芯片在触控时间段通过检测各自电容电极的电容值变化可以判断出触控位置。由于人体电容可以作用于全部自电容，相对于人体电容仅能作用于互电容中的投射电容的方式，由人体碰触屏幕所引起的触控变化量大于利用互电容原理制作出的触摸屏，因此自电容的触摸屏相对于互电容的触摸屏能有效提高触控的信噪比，从而提高触控感应的准确性。
发明内容
本发明的至少一个实施例提供了一种内嵌式触摸屏及显示装置，用以降低显示信号和触控信号之间的相互干扰，提高画面品质和触控准确性。
本发明的至少一个实施例提供的一种内嵌式触摸屏，包括相对而置的上基板和下基板；设置于所述上基板面向所述下基板的一侧或所述下基板面向 所述上基板的一侧的多个同层设置且相互绝缘的自电容电极；位于各所述自电容电极面向所述下基板一侧的屏蔽电极，各所述自电容电极与所述屏蔽电极相互绝缘；以及，位于各所述自电容电极和所述屏蔽电极之间的绝缘层。
本发明的至少一个实施例提供的一种显示装置，包括本发明实施例提供的上述内嵌式触摸屏。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本发明实施例提供的内嵌式触摸屏的结构示意图；
图2为本发明实施例提供的内嵌式触摸屏中一个自电容电极的结构示意图；
图3为本发明实施例提供的内嵌式触摸屏中同层设置的导线和自电容电极的示意图；
图4为本发明实施例提供的内嵌式触摸屏中显示区域的自电容电极分区示意图；
图5为本发明实施例提供的内嵌式触摸屏中各区域内同层设置的自电容电极与导通连接点的连接示意图；
图6为本发明实施例提供的内嵌式触摸屏中导线与屏蔽电极同层设置的结构示意图；
图7为本发明实施例提供的内嵌式触摸屏中自电容电极与屏蔽电极同时设置在上基板的结构示意图；
图8a和图8b分别为本发明实施例提供的内嵌式触摸屏的触控和显示分时驱动时序示意图；
图9为本发明实施例提供的内嵌式触摸屏的触控和显示同时驱动时序示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
附图中各膜层的厚度和形状不反映真实比例，目的只是示意说明本发明内容。
本申请的发明人注意到，在内嵌式触摸屏中，为了降低显示信号和触控信号之间的相互干扰，提高画面品质和触控准确性，一般需要将触控和显示阶段进行分时驱动，由于一帧的时间一般为固定值，这样分时驱动会致使触控时间段和显示时间段各自所享有的时间较少，导致在显示时间段可能充电不充分而影响正常显示，在触控时间段可能侦测信号的时间过短而影响触控效果等问题。
本发明实施例提供的下述内嵌式触摸屏既适用于扭转向列(Twisted Nematic,TN)型液晶显示屏，也适用于高级超维场开关(Advanced Dimension Switch,ADS)型液晶显示屏和平面内开关(In-Plane Switch,IPS)型液晶显示屏。
本发明的至少一个实施例提供的一种内嵌式触摸屏，如图1所示，包括相对设置的上基板01和下基板02；设置于上基板01面向下基板02的一侧或下基板02面向上基板01的一侧的多个同层设置且相互绝缘的自电容电极03(图1中示出了自电容电极位于上基板01面向下基板02一侧的结构)；位于各自电容电极03面向下基板02的一侧的屏蔽电极05，各自电容电极03与屏蔽电极05相互绝缘；以及，位于各自电容电极03和屏蔽电极05之间的绝缘层06。在一个实施例中，所述内嵌式触摸屏还可以包括通过检测各自电容电极03的电容值变化以判断触控位置的触控侦测芯片04。
本发明实施例提供的上述内嵌式触摸屏，利用自电容的原理在触摸屏内设置多个同层设置且相互绝缘的自电容电极03，并且在各自电容电极面03向下基板02的一侧设置屏蔽电极05，在各自电容电极03和屏蔽电极05之间设置绝缘层06；利用与自电容电极03绝缘的屏蔽电极05将自电容电极03加载的触控侦测信号与显示用信号隔离，以避免两者之间相互干扰，实现触控侦测和显示驱动的同步执行，同时保证较好的显示和触控效果。
本发明的不同实施例提供的上述内嵌式触摸屏还可以包括：如图1所示，设置于上基板01面向下基板02的一侧，或设置于下基板02面向上基板01的一侧的黑矩阵层07；各自电容电极03的图形以及屏蔽电极05的图形在下基板02上的正投影可以位于黑矩阵层07的图形所在区域内。
由于将各自电容电极03和屏蔽电极05的图形均设置在黑矩阵层07的图形所在的区域，因此，可以避免自电容电极03和屏蔽电极05影响触摸屏的透过率。在此基础上，可以采用金属制作屏蔽电极05和自电容电极03；还可以采用透明导电材料制作屏蔽电极05和自电容电极03，例如，可以采用氧化铟锡(ITO)或氧化铟锌(IZO)材料、碳纳米管、石墨烯等透明导电材料。在具体实施时，一般采用金属制作屏蔽电极05和自电容电极03，这是由于金属的电阻比ITO小，有利于减小屏蔽电极05和自电容电极03的电阻，提高触控灵敏度和屏蔽电极05的屏蔽效果。
触摸屏的密度通常在毫米级，因此，在具体实施时，可以根据所需的触控密度选择各自电容电极03的密度和所占面积以保证所需的触控密度。例如，通常各自电容电极03设计为5mm*5mm左右的方形电极。显示屏的密度通常在微米级，因此，一般一个自电容电极03会对应显示屏中的多个像素单元。为了保证各自电容电极03的图形不占用像素单元的开口区域，如图2所示，可以将各自电容电极03的图形中与像素单元的开口区域对应的位置的图形挖去，即可以将各自电容电极03的图形设计为在下基板02上的正投影位于黑矩阵层07的图形所在区域内的网格状结构。并且，为了确保显示的均匀性，可以在各像素单元中的每个亚像素单元的间隙处均设置有自电容电极03的图形，图2中每一组RGB亚像素单元组成一个像素单元。本发明实施例中所指的密度是指的触摸屏的自电容电极的间距或者显示屏的像素单元的间距(Pitch)。
基于此，由于屏蔽电极05的作用是隔离自电容电极03加载的触控侦测信号与显示用信号，因此，在一个实施例中，屏蔽电极05的图形可以覆盖自电容电极03的图形，即由于自电容电极03的图形可以为在下基板02的正投影位于黑矩阵层07的图形所在区域内的网格状结构，因此屏蔽电极的图形同样也可以为在下基板02的正投影位于黑矩阵层07的图形所在区域内的网格状结构。
在一个实施例中，为了便于触控侦测芯片检测各自电容电极的电容值变化，本发明实施例提供的上述内嵌式触摸屏，如图3所示，还可以包括：与各自电容电极03一一对应的导线08，以及与自电容电极03一一对应的导通连接点09；各导通连接点09一般设置在内嵌式触摸屏的边框胶所在区域，且为了不影响正常的显示功能，各导线08在下基板02上的正投影也位于黑矩阵层07的图形所在区域内；各自电容电极03通过导线08连接至导通连接点09后，通过位于边框胶所在区域的走线10与触控侦测芯片的连接端子11电性连接。在图3中示出了一行中8个自电容电极03的情况，与各自电容电极03一一对应的导线08以及导通连接点09的个数可以为一个，也可以为多个，在此不做限定。
在具体实施时，导线08和导通连接点09一般与自电容电极03设置在同一基板上，即可以同时设置在上基板01上，也可以同时设置在下基板02上；走线10和触控侦测芯片的连接端子11一般设置在下基板02上。当导线08和导通连接点09与自电容电极03设置在上基板01时，导通连接点09可通过封框胶中的导电粒子(例如金球)的上下导通作用与位于下基板02的边框胶所在区域的走线10电性连接，然后通过走线10引至相应的触控侦测芯片的连接端子11处。当导线08和导通连接点09与自电容电极03设置在下基板02时，导通连接点09可直接与位于下基板02的边框胶所在区域的走线10电性连接，然后通过走线10引至相应的触控侦测芯片的连接端子11处。
在一个实施例中，如图3所示，可以将各导线08与各自电容电极03同层设置。为了保证屏蔽电极05能隔离自电容电极加载的触控侦测信号和显示用信号，屏蔽电极05的图形在下基板02的正投影覆盖各导线08和各自电容电极03的图形。
由于各导线08与各自电容电极03同层设置时采用一层金属层设计自电容电极03和导线08的图形，为了避免各自电容电极03之间发生短路的现象，连接各自电容电极03的导线08需要互不交叉，因此，采用如图3所示的布线方式设计导线时，即采用与所有自电容电极03连接的导线08都沿着一个方向延伸，且连接至设置在同一个侧边区域内的对应的导通连接点09上的布线方式时，在触摸屏中可出现大量的触控盲区。图3示出了在一行中8个自电容电极03形成的触控盲区，在图3中仅示意出了自电容电极03的图形以 及与各自电容电极03连接的导线08的图案，未示出各亚像素单元的图形；并且，为了方便观看，在图3中采用不同填充图案示出了各自电容电极03所占区域。在触控盲区内连接多个自电容电极的导线08均经过该触控盲区，因此，在这个触控盲区内的信号相对比较紊乱，故此称为触控盲区，也就是在该区域内的触控性能无法保证。
为了尽量减小触控盲区的面积，可以在内嵌式触摸屏的边框胶所在区域具有的四个侧边均分布导通连接点09，即导通连接点09在边框胶所在区域的四个侧边均有分布，这样，通过导线08将各自电容电极03分别连接至设置在显示区域四周的对应的导通连接点09，可以从总体上减小了触控盲区的面积。
以一个5寸触摸屏为例说明本发明实施例提供的上述减少触控盲区的设计。在5寸触摸屏中需要的自电容电极03的数量约为22*12＝264个。如图4所示，为了将每个自电容电极03都引入至对应的导通连接点09处，且尽可能降低触控盲区的面积，可以将所有的自电容电极03共分为8个区域:PartA～PartH，在每个区域都需要将区域内的自电容电极03逐个连接至显示区域(Panel)下方的触控侦测芯片的连接端子11(FPC Bonding Pad)处。如图5所示，在图5中每个区域均示出了3个自电容电极03，Part A区域的各自电容电极从显示区域的左上方区域引出，经过显示区域左边框引入至触控侦测芯片的连接端子；Part B区域的各自电容电极从显示区域的上方引出后，再从显示区域的左边框引入至触控侦测芯片的连接端子；Part C区域的各自电容电极从显示区域的上方引出后，再从显示区域的右边框引入至触控侦测芯片的连接端子；Part D区域的各自电容电极从显示区域的右上方引出后经过显示区域的右边框引入至触控侦测芯片的连接端子；同理，Part E区域的各自电容电极从显示区域的左下方引出后，经过显示区域的左边框引入至触控侦测芯片的连接端子；Part F区域的各自电容电极从显示区域的下方引出后直接连接至触控侦测芯片的连接端子；Part G区域的各自电容电极从显示区域的下方引出后直接连接至触控侦测芯片的连接端子；Part H区域的各自电容电极从显示区域的右下方引出，经过显示区域右边框引入至触控侦测芯片的连接端子。
为了便于观看图5仅示出了部分自电容电极03与导通连接点09的连接 关系。从图5可以看出，位于显示区域两侧的Part A、Part D、Part E和Part H中触控盲区的大小约为3个亚像素单元的高度，在图5中用h表示，以5寸触摸屏中对应的像素单元的大小进行估算，触控盲区约为260μm；位于显示区域中部的Part B、Part C、Part F和Part G中触控盲区的大小约为10个亚像素单元的宽度，在图5中用w表示，以5寸触摸屏中对应的像素单元的大小进行估算，触控盲区约为290μm。
上述自电容电极03与导通连接点09的连接关系仅是举例说明，在实际设计时可以根据触摸屏的具体尺寸进行设计。为了尽可能地减少触控盲区的面积，可以将与各自电容电极03对应的导通连接点09分布在离自电容电极03距离最近的边框胶所在区域的侧边处，这样可以尽可能的缩短连接自电容电极03与导通连接点09之间的导线08的长度，以便尽可能的减少触控盲区的面积。
在一个实施例中，为了消除触摸屏中出现的触控盲区，可以将自电容电极03与导线08异层设置。例如，如图6所示，可以将导线08与屏蔽电极05同层设置，且各自电容电极03与对应的导线08通过绝缘层06中的过孔电性相连，这样既可以避免触控盲区的出线，也可以实现不增加制作工艺。例如，在设计导线08的连接关系时可以采用如图6所示的布线方式，即与所有自电容电极03连接的导线08都沿着一个方向延伸，且连接至设置在边框胶所在区域的同一个侧边区域内的对应的导通连接点09上。
在一个实施例中，为了保证屏蔽电极05能隔离自电容电极03加载的触控侦测信号和显示用信号，在导线08与屏蔽电极05同层设置时，屏蔽电极05和导线08的图形在下基板02的正投影可以覆盖各自电容电极03的图形。图6示出了导线和屏蔽电极05同层设置的图案，从图6可以看出屏蔽电极05和导线之间相互绝缘。
在具体实施时，本发明实施例提供的上述内嵌式触摸屏中，自电容电极03和屏蔽电极05可以均设置在上基板01上，利用上基板01中已有的膜层作为绝缘层06，这样仅需在上基板01的制作工艺中增加制作自电容电极03和屏蔽电极05的金属层的制作工艺。例如，如图7所示，黑矩阵层07可以位于上基板01面向下基板02的一侧，在黑矩阵层07上一般设置有彩色滤光层12，在彩色滤光层12上一般设置有平坦层13，以及在平坦层13上一般设 置有隔垫物层14。
第一种可能的实施方式为：如图7所示，将彩色滤光层12作为位于自电容电极03和屏蔽电极05之间的绝缘层06。例如，各自电容电极03位于黑矩阵层07与彩色滤光层12之间，各导线08和屏蔽电极05位于彩色滤光层12与平坦层13之间。
第二种可能的实施方式为：将平坦层13作为位于自电容电极03和屏蔽电极05之间的绝缘层06。例如，各自电容电极03位于彩色滤光层12与平坦层13之间，各导线08和屏蔽电极05位于平坦层13与隔垫物层14之间。
第三种可能的实施方式为：将隔垫物层14作为位于自电容电极03和屏蔽电极05之间的绝缘层06。例如，各自电容电极03位于平坦层13与隔垫物层14之间，各导线08和屏蔽电极05位于隔垫物层14之上。
在上述三种可能的实施方式中，若将导线08与屏蔽电极05设置在同一金属层中，采用彩色滤光层12或隔垫物层14作为绝缘层06时，由于这两个膜层均需要进行构图工艺，因此，仅需对构图工艺中的掩膜板图形进行变更以增加连接导线08和自电容电极03的过孔图形，不会增加制作工艺；而采用平坦层13作为绝缘层06时，由于平坦层13原本不需要进行构图工艺，因此，需要增加对应的平坦层13的掩膜板，会增加一道制作工艺。因此，可以需要根据实际需要设置自电容电极03和屏蔽电极05的膜层位置，在此不做限定。
同理，在具体实施时，本发明实施例提供的上述内嵌式触摸屏中，自电容电极03和屏蔽电极05可以均设置在下基板02上，利用下基板02中已有的膜层作为绝缘层06，这样仅需在下基板02的制作工艺中增加制作自电容电极03和屏蔽电极05的金属层的制作工艺。例如，在下基板02上一般设置有公共电极层，在公共电极层上一般设置有钝化层，在钝化层上一般设置有像素电极层。
一种可能的实施方式为：将钝化层作为位于自电容电极03和屏蔽电极05之间的绝缘层06。例如，各自电容电极03可以位于钝化层之上，各导线08和屏蔽电极05位于公共电极层与钝化层之间。并且，由于自电容电极03一般采用金属制作，不能与采用ITO制作的像素电极层同时制作，且像素电极的图形仅在每个像素单元的开口区域有图形，在黑矩阵层的图形区域无图 案，和自电容电极的图案不会重合，因此，可以在制作像素电极层之前或者之后制作自电容电极03的图形。
在本发明的一个实施例提供的上述触摸屏中，由于在自电容电极的下方设置了屏蔽电极可以隔离触控侦测信号和显示用信号之间的相互干扰，因此，触摸屏中的触控和显示可以采用同时驱动的方式，也可以采用分时驱动的方式，即触控侦测芯片在每帧的显示时间段和触控时间段均工作，或者仅在每帧的触控时间段工作。并且，在一个实施例中，还可以将显示驱动芯片和触控侦测芯片整合为一个芯片，以进一步降低生产成本。
例如，在采用分时驱动的方式时，如图8a和图8b所示的驱动时序图中，将触摸屏显示每一帧(V-sync)的时间分成显示时间段和触控时间段。例如，图8a和图8b所示的驱动时序图中触摸屏的显示一帧的时间为16.7ms，选取其中5ms作为触控时间段，其他的11.7ms作为显示时间段。当然也可以根据IC芯片的处理能力适当的调整两者的时长，在此不做具体限定。在显示时间段，对触摸屏中的每条栅极信号线Gate1，Gate2……Gate n依次施加栅扫描信号，对数据信号线Data施加灰阶信号，以实现液晶显示功能。在触控时间段，如图8a所示，与各自电容电极Cx1……Cx n连接的触控侦测芯片可以向各自电容电极Cx1……Cx n同时施加驱动信号，同时接收各自电容电极Cx1……Cx n的反馈信号；也可以如图8b所示，与各自电容电极Cx1……Cx n连接的触控侦测芯片向各自电容电极Cx1……Cx n依次施加驱动信号，分别接收各自电容电极Cx1……Cx n的反馈信号，在此不做限定。通过对反馈信号的分析判断是否发生触控，以实现触控功能。
例如，在采用同时驱动的方式时，如图9所示的驱动时序图中，在每一帧(V-sync)的时间内，对触摸屏中的每条栅极信号线Gate1，Gate2……Gate n依次施加栅扫描信号，对数据信号线Data施加灰阶信号，以实现液晶显示功能；同时，与各自电容电极Cx1……Cx n连接的触控侦测芯片向各自电容电极Cx1……Cx n同时施加驱动信号，接收各自电容电极Cx1……Cx n的反馈信号，通过对反馈信号的分析判断是否发生触控，以实现触控功能。
基于同一发明构思，本发明的至少一个实施例还提供了一种显示装置，其包括本发明实施例提供的上述内嵌式触摸屏。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显 示功能的产品或部件。该显示装置的实施可以参见上述内嵌式触摸屏的实施例，重复之处不再赘述。
本发明实施例提供的上述内嵌式触摸屏及显示装置，利用自电容的原理在触摸屏内设置多个同层设置且相互绝缘的自电容电极，并且在各自电容电极面向下基板的一侧设置屏蔽电极，在各自电容电极和屏蔽电极之间设置绝缘层；利用与自电容电极绝缘的屏蔽电极将自电容电极加载的触控侦测信号与显示用信号隔离，以避免两者之间相互干扰，实现触控侦测和显示驱动的同步执行，同时保证较好的显示和触控效果。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。
本申请要求于2014年5月30日递交的中国专利申请第201410241051.3号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (11)

  1. 一种内嵌式触摸屏，包括：
    相对而置的上基板和下基板；
    设置于所述上基板面向所述下基板的一侧或所述下基板面向所述上基板的一侧的多个同层设置且相互绝缘的自电容电极；
    位于各所述自电容电极面向所述下基板的一侧的屏蔽电极，其中，各所述自电容电极与所述屏蔽电极相互绝缘；以及，
    位于各所述自电容电极和所述屏蔽电极之间的绝缘层。
  2. 如权利要求1所述的内嵌式触摸屏，还包括：通过检测各所述自电容电极的电容值变化以判断触控位置的触控侦测芯片。
  3. 如权利要求1或2所述的内嵌式触摸屏，还包括：设置于所述上基板面向所述下基板的一侧，或设置于所述下基板面向所述上基板的一侧的黑矩阵层；
    其中，各所述自电容电极的图形以及所述屏蔽电极的图形在所述下基板的正投影位于所述黑矩阵层的图形所在区域内。
  4. 如权利要求3所述的内嵌式触摸屏，其中，各所述自电容电极的图形和所述屏蔽电极的图形分别为在所述下基板上的正投影位于所述黑矩阵层的图形所在区域内的网格状结构。
  5. 如权利要求3或4所述的内嵌式触摸屏，还包括：与各所述自电容电极电性连接的一一对应的至少一条导线，以及与所述自电容电极一一对应的至少一个导通连接点；其中，
    各所述导线在所述下基板上的正投影位于所述黑矩阵层的图形所在区域内，各所述导通连接点设置在所述内嵌式触摸屏的边框胶所在区域；
    各所述自电容电极通过所述导线连接至所述导通连接点后，通过位于所述边框胶所在区域的走线与所述触控侦测芯片的连接端子电性连接。
  6. 如权利要求5所述的内嵌式触摸屏，其中，各所述导线与各所述自电容电极同层设置；
    所述屏蔽电极的图形在所述下基板的正投影覆盖各所述导线和各所述自电容电极的图形。
  7. 如权利要求5所述的内嵌式触摸屏，其中，各所述导线与所述屏蔽电极同层设置，各所述自电容电极与对应的导线通过所述绝缘层中的过孔电性相连；
    所述屏蔽电极和各所述导线的图形在所述下基板的正投影覆盖各所述自电容电极的图形。
  8. 如权利要求3-7任一所述的内嵌式触摸屏，其中，所述黑矩阵层位于所述上基板面向所述下基板的一侧，在所述黑矩阵层上设置有彩色滤光层，在所述彩色滤光层上设置有平坦层，以及在所述平坦层上设置有隔垫物层；
    各所述自电容电极位于所述黑矩阵层与所述彩色滤光层之间，各所述导线和所述屏蔽电极位于所述彩色滤光层与所述平坦层之间，所述彩色滤光层作为位于所述自电容电极和所述屏蔽电极之间的绝缘层；或，
    各所述自电容电极位于所述彩色滤光层与所述平坦层之间，各所述导线和所述屏蔽电极位于所述平坦层与所述隔垫物层之间，所述平坦层作为位于所述自电容电极和所述屏蔽电极之间的绝缘层；或，
    各所述自电容电极位于所述平坦层与所述隔垫物层之间，各所述导线和所述屏蔽电极位于所述隔垫物层之上，所述隔垫物层作为位于所述自电容电极和所述屏蔽电极之间的绝缘层。
  9. 如权利要求2-7任一所述的内嵌式触摸屏，在所述下基板上设置有公共电极层，在所述公共电极层上设置有钝化层，在所述钝化层上设置有像素电极层；
    各所述自电容电极位于所述钝化层之上，各所述导线和所述屏蔽电极位于所述公共电极层与所述钝化层之间，所述钝化层作为位于所述自电容电极和所述屏蔽电极之间的绝缘层。
  10. 如权利要求2-9任一所述的内嵌式触摸屏，其中，所述触控侦测芯片在每帧的显示时间段和触控时间段均工作，或仅在每帧的触控时间段工作。
  11. 一种显示装置，包括如权利要求1-10任一项所述的内嵌式触摸屏。
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