WO2015169038A1 - 集成电路总线系统及其数据操作和传输方法 - Google Patents

集成电路总线系统及其数据操作和传输方法 Download PDF

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Publication number
WO2015169038A1
WO2015169038A1 PCT/CN2014/087476 CN2014087476W WO2015169038A1 WO 2015169038 A1 WO2015169038 A1 WO 2015169038A1 CN 2014087476 W CN2014087476 W CN 2014087476W WO 2015169038 A1 WO2015169038 A1 WO 2015169038A1
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fpga
iic
level
cpu
operation instruction
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PCT/CN2014/087476
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English (en)
French (fr)
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郦会
杨利君
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中兴通讯股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure

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  • the present invention relates to the field of general-purpose integrated circuit bus technology, and in particular to an integrated circuit bus system and a data operation and transmission method thereof.
  • the Inter-Integrated Circuit (IIC) specification as a two-wire serial bus - a bus with only one data line and one clock line - has become an international standard in more than 100 different integrated circuits (integrated circuits) , IC) is implemented and licensed by more than 50 companies.
  • ICs that conform to the IIC bus standard must have a 7-bit device address as the address identifier when they are accessed.
  • the device and device addresses must be one-to-one.
  • Many IC manufacturers' devices only support 2-3bits of custom addresses. In this case, if the number of identical devices on the same bus is greater than the maximum number of addresses supported by the custom address, the same device address will be mapped to multiple devices. For example, a temperature sensor chip has only 2bits custom address. If a hardware system is designed with 6 temperature senses, there must be two temperature sensor chips and other temperature sensor chip addresses overlapping.
  • the commonly used method is to make a gate switch through the logic chip, and then access the corresponding optical module.
  • the optical module is strobed to the IIC bus and then accesses the device address of the optical module.
  • this method requires a LocalBus bus or General-Purpose Input/Output Ports (GPIO) to handle the gating switch function, that is, another bus other than the IIC bus is required to cooperate, and is not universally applicable. Resolution of various address overlap problems.
  • GPIO General-Purpose Input/Output Ports
  • the present invention provides an IIC bus system and a data operation and transmission method thereof to at least solve the above problems.
  • an integrated circuit bus IIC system including a central processing unit CPU and an IIC device, a field programmable logic gate array FPGA connected between the CPU and an IIC device, wherein the CPU Connected to the FPGA through a first IIC bus; between the FPGA and the IIC device Connected by the second IIC bus, the first IIC bus and the second IIC bus are independent of each other; the CPU is configured to access the FPGA through the first IIC bus, and to the IIC device through the FPGA Transmitting an operation instruction; the FPGA is configured to interact with the IIC device as a master device through the second IIC bus, execute the operation instruction, and transparently transmit read data transmitted between the CPU and the IIC device Or write data.
  • the FPGA includes multiple, and the plurality of the FPGAs are connected by a third independent IIC bus.
  • a data operation method of an integrated circuit bus IIC which is applied to the above system, the method comprising: a central processing unit CPU establishes a next level with the CPU through a first IIC bus a connection of the field programmable gate array FPGA; the CPU will sequentially send the next instruction from the next level device of the next level FPGA to the address of each device of the IIC device to be operated and an operation instruction to be executed Level FPGA, indicating that each FPGA in the upper-level FPGA from the next-level FPGA to the IIC device to be operated is respectively connected as a master device and a next-level device, and executes the operation instruction, wherein
  • the first level device includes: an FPGA or the IIC device; the CPU passes from the next-stage FPGA to each FPGA in the upper-level FPGA of the IIC device to be operated from the IIC device to be operated Read or write data.
  • the CPU establishes a connection with the next-stage field programmable gate array FPGA of the CPU through the first IIC bus, including: the CPU sends the next-level FPGA by using the first IIC bus Address and write operation instruction; the CPU receives the acknowledgement information ACK sent by the next-stage FPGA through the first IIC bus.
  • the CPU sequentially sends an address of the next-level device of the next-level FPGA to each device of the IIC device to be operated and an operation instruction to be executed.
  • the method further includes: the CPU transmitting an internal register address of the IIC device to be operated through the first IIC bus; and after receiving the ACK, the CPU passes the An IIC bus sends 1 byte of data to be written, and after receiving the ACK, sends the next byte of data to be written until all data to be written is sent, and the CPU sends the data through the first IIC bus. Stop the instruction.
  • the CPU sends, by using the first IIC bus, the address of the IIC device to be operated after the operation address of the upper-level FPGA and an operation instruction to be executed.
  • the method further includes: the CPU transmitting a stop instruction through the first IIC bus; the CPU reestablishing a connection with the next-level FPGA of the CPU through the first IIC bus;
  • the first IIC bus transmits a register address and a read operation instruction that need to read data;
  • the CPU receives an ACK And transmitting, by the first IIC bus, an address and a read operation instruction of the next-stage FPGA of the CPU; the CPU receiving a read from the IIC device of a next-stage FPGA transmission of the CPU 1 byte of read data; the CPU sends an ACK to the next-stage FPGA, and receives the next byte data read from the IIC device transmitted by the next-stage FPGA until all the readings need to be read The data.
  • a data transmission method for an integrated circuit bus IIC including: a first field programmable logic gate array FPGA passes through a first IIC bus with a higher level controller, and The upper level controller establishes a connection, wherein the upper level controller includes: a central processing unit CPU or an FPGA; and the first FPGA receives the upper level controller by using the first IIC bus for the first An operation instruction of the next-level device of the FPGA, where the next-level device includes: a next-level FPGA or an IIC device to be operated, the operation instruction includes: a write operation instruction or a read operation instruction; Executing, by the FPGA as a master device, the operation instruction transmitted through the second IIC bus between the next-level device and transparently transmitting the write data transmitted between the upper-level controller and the next-level device or Read the data.
  • the first FPGA establishes a connection with the upper-level controller by using a first IIC bus between the first-level controller, and the first FPGA receives the sending by the upper-level controller.
  • a first address information bit and a write operation instruction wherein the first address information bit indicates address information of the first FPGA under the upper level controller; the first FPGA passes the first IIC bus And returning an acknowledgement message ACK to the upper level controller.
  • the operation instruction is a write operation instruction
  • the write data or the read data transmitted between the first-level devices includes: the first FPGA as a master device, according to the second address information bit sent by the upper-level controller and the write operation command, by using the first a second IIC bus, establishing a connection with the next-level device, wherein the second address information bit indicates an address of the next-level device; the first FPGA transparently transmits the first FPGA and the A data frame transmitted by the first IIC bus between the next level of devices.
  • the operation instruction is a read operation instruction
  • the read data or the data to be written transmitted between the first-level devices includes: the first FPGA as a master device, and the second address information bit sent by the upper-level controller passes the second IIC a bus, establishing a connection with the next-level device, wherein the second address information bit indicates an address of the next-level device; if the next-level device is the IIC device to be operated, The first FPGA reads data from the next-level device through the second IIC bus according to the internal register address of the IIC device to be operated, according to the data to be read sent by the upper-level controller, and Transmitting the read data to the upper level controller through the first IIC bus; or, if the next level device is a next level FPGA, the first FPGA passes the second IIC bus Xiangshou The next level FPGA sends a third address information bit
  • the method further includes: the first FPGA saves the The second address information bit and the third address information bit sent by the upper controller; the first FPGA sends the confirmation information to the upper controller; the first FPGA passes the first An IIC bus, establishing a connection with the upper controller again; the first FPGA receives and saves an internal register address of the IIC device to be read sent by the upper controller; The first FPGA receives a first address information bit and a read operation instruction sent by the upper-level controller through the first IIC bus; the first FPGA establishes a connection with the next-level FPGA, and the The internal register address is sent to the next level FPGA; the first FPGA sends the second address information bit and a read operation instruction to the next level FPGA.
  • a field programmable logic gate array is added between the CPU and the IIC device, and the IIC bus between the CPU and the FPGA is independent of the IIC bus between the FPGA and the IIC device, and the CPU can be connected to multiple FPGAs.
  • An FPGA can be divided into multiple zones, and each zone can be connected to multiple IIC devices, thereby solving the problem of address overlap of multiple IIC devices, and does not depend on additional buses, and does not increase the interface load on the CPU side. .
  • FIG. 1 is a schematic structural diagram of an IIC bus system according to an embodiment of the present invention.
  • FIG. 2 is a diagram showing an example of a design of a secondary IIC bus system according to an embodiment of the present invention
  • FIG. 3 is a flow chart of a data operation method of IIC according to an embodiment of the present invention.
  • FIG. 4 is a flowchart of a data transmission method of IIC according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a timing of a standard IIC bus write operation in the related art
  • FIG. 7 is a schematic diagram of a timing of a standard IIC bus read operation in the related art.
  • Figure 8 is a flow chart of a standard IIC read operation in the related art
  • FIG. 9 is a schematic diagram of a timing of a write operation of a secondary IIC in an embodiment of the present invention.
  • FIG. 10 is a flow chart of a write operation of a secondary IIC in an embodiment of the present invention.
  • FIG. 11 is a schematic diagram of a timing of a read operation of a secondary IIC in an embodiment of the present invention.
  • FIG. 12 is a flow chart of a read operation of a secondary IIC in an embodiment of the present invention.
  • FIG. 13 is a schematic diagram showing the timing of the read operation of the three-stage IIC in the embodiment of the present invention.
  • the IIC system in the embodiment of the present invention includes: a CPU 1, an FPGA 2, and an IIC device.
  • the CPU 1 and the FPGA 2 are connected by a first IIC bus 10;
  • the FPGA 2 and the IIC device 3 are connected by a second IIC bus 20, and the first IIC bus 10 and the The second IIC bus 20 is independent of each other;
  • the CPU 1 is configured to access the FPGA 2 through the first IIC bus 10, and send an operation instruction to the IIC device 3 through the FPGA 2;
  • the FPGA 2 setting In order to interact with the IIC device 3 through the second IIC bus 20 as a master device, the operation instruction is executed, and read data or write data transmitted between the CPU 1 and the IIC device 3 is transparently transmitted.
  • FPGAs 2 connected between the CPU 1 and the IIC device 3, and a plurality of the FPGAs are connected by mutually independent third IIC buses. That is, there are multiple levels (greater than 2) IIC bus between the CPU 1 and the IIC device 3, so that more IIC devices with non-overlapping addresses can be laid out.
  • an FPGA device is added between the CPU and the IIC device as a secondary master device.
  • the operation timing of the primary CPU to the IIC device can be referred to as one frame.
  • the CPU accesses the IIC device by means of indirect addressing, that is, the CPU first accesses the FPGA through the IIC bus.
  • the CPU is the master device
  • the FPGA is the slave device
  • the FPGA transmits the data frame transmitted by the CPU locally. Strip the content that is relevant to you, and then use it as the master device to transparently pass the data frame to the specified IIC device.
  • the IIC bus between the CPU and the FPGA and the IIC bus between the FPGA and the device are independent of each other.
  • FIG. 2 is a diagram showing an example of design of a secondary IIC bus system in an embodiment of the present invention.
  • the CPU is connected to the FPGA through the first IIC bus, and the FPGA is divided into two areas, and the addresses of the two areas are address A1 and address A2, respectively.
  • the 1st region of the FPGA is connected to three IIC devices through the second IIC bus, namely, IIC device 1 (address B1), IIC device 2 (address B2), and IIC device 3 (address B3).
  • the 2 regions of the FPGA are connected to the three IIC devices through the second IIC bus, namely, IIC device 4 (address B4), IIC device 5 (address B5), and IIC device 6 (address B6).
  • the FPGA since the FPGA has the functions of buffering data, forwarding, and independently sending packets, it can respond to and isolate multiple IIC addresses, and has the functions of the IIC master-slave device, so that multiple IIC device addresses can be overlapped. .
  • the embodiment of the present invention further provides an IIC data operation method by which the CPU can read or write data from the IIC device.
  • FIG. 3 is a flowchart of a data operation method of an IIC according to an embodiment of the present invention. As shown in FIG. 3, the method mainly includes the following steps:
  • Step S302 the CPU establishes a connection with the next-level FPGA of the CPU through the first IIC bus;
  • step S302 may include: step 1, the CPU sends an address of the next-level FPGA and a write operation instruction through the first IIC bus; and the CPU receives the acknowledgement sent by the next-level FPGA through the first IIC bus.
  • Information ACK may include: step 1, the CPU sends an address of the next-level FPGA and a write operation instruction through the first IIC bus; and the CPU receives the acknowledgement sent by the next-level FPGA through the first IIC bus.
  • Information ACK may include: step 1, the CPU sends an address of the next-level FPGA and a write operation instruction through the first IIC bus; and the CPU receives the acknowledgement sent by the next-level FPGA through the first IIC bus.
  • Step S304 the CPU sequentially sends the address of each device of the next-level FPGA from the next-level device to the IIC device to be operated and the operation instruction to be executed to the next-level FPGA, indicating from the next Each of the FPGAs in the upper-level FPGA of the first-level FPGA to the IIC device to be operated establishes a connection with the next-level device as a master device, and executes the operation instruction, wherein the next-level device includes: an FPGA Or the IIC device;
  • Step S306 the CPU reads or writes data from the IIC device to be operated from each FPGA in the upper-level FPGA of the next-stage FPGA to the IIC device to be operated.
  • the CPU will execute an address from a next-level device of the next-level FPGA to each device of the IIC device to be operated and needs to be executed.
  • the method further includes: the CPU transmitting an internal register address of the IIC device to be operated through the first IIC bus; after receiving the ACK, the CPU Pass Transmitting, by the first IIC bus, 1 byte of data to be written, and after receiving the ACK, transmitting the next byte of data to be written until all data to be written is sent, the CPU passes the An IIC bus sends a stop command.
  • the CPU sends, by using the first IIC bus, the address of the IIC device to be operated after the operation address of the upper-level FPGA and an operation instruction to be executed.
  • the method further includes: the CPU transmitting a stop instruction through the first IIC bus; the CPU reestablishing a connection with the next-level FPGA of the CPU through the first IIC bus;
  • the first IIC bus sends a register address and a read operation instruction that need to read data; after receiving the ACK, the CPU sends an address and a read operation of the next-stage FPGA of the CPU through the first IIC bus.
  • the CPU receives 1 byte of read data read from the IIC device transmitted by the next-stage FPGA of the CPU; the CPU sends an ACK to the next-stage FPGA, and receives the next The next byte of data read from the IIC device transmitted by the stage FPGA until all data that needs to be read is received.
  • an embodiment of the present invention further provides an IIC data transmission method, by which the FPGA can be used as an intermediate device to implement indirect reading or writing of data from the IIC device by the CPU. .
  • FIG. 4 is a flowchart of a data transmission method of an IIC bus according to an embodiment of the present invention. As shown in FIG. 4, the method mainly includes the following steps:
  • Step S402 the first FPGA establishes a connection with the upper-level controller through a first IIC bus between the upper-level controller, wherein the upper-level controller includes: a central processing unit CPU or an FPGA;
  • step S402 when the connection between the first FPGA and the upper-level controller is established, the address information bit of the first FPGA and the write operation instruction are sent by the upper-level controller, so, optionally, step S402 may be performed.
  • the method includes: Step 1, the first FPGA receives a first address information bit and a write operation instruction sent by the upper-level controller, where the first address information bit indicates that the first FPGA is in the previous The address information under the level controller; in step 2, the first FPGA returns an acknowledgement information ACK to the upper-level controller through the first IIC bus.
  • Step S404 the first FPGA receives an operation instruction of the upper-level controller for the next-level device of the first FPGA by using the first IIC bus, where the next-level device includes: a next-level FPGA Or an IIC device to be operated, the operation instruction includes: a write operation instruction or a read operation instruction;
  • Step S406 the first FPGA is used as a master device, and the operation instruction is executed by using a second IIC bus between the first FPGA and the next-level device, and transparently transmitting between the upper-level controller and the next-level device. Transmitted write data or read data.
  • the step S406 may include: the first FPGA as a master device, according to the second address information bit sent by the upper level controller and the write operation instruction Establishing a connection with the next-level device by using the second IIC bus, wherein the second address information bit indicates an address of the next-level device; the first FPGA transparently transmits the A data frame transmitted by the first IIC bus between an FPGA and the next-level device.
  • the step S406 may include: the first FPGA as a master device, and the second address information bit sent by the upper-level controller passes the second IIC. a bus, establishing a connection with the next-level device, wherein the second address information bit indicates an address of the next-level device; if the next-level device is the IIC device to be operated, The first FPGA reads data from the next-level device through the second IIC bus according to the internal register address of the IIC device to be operated, according to the data to be read sent by the upper-level controller, and Transmitting the read data to the upper level controller through the first IIC bus; or, if the next level device is a next level FPGA, the first FPGA passes the second IIC bus Transmitting, to the next-stage FPGA, a third address information bit and a read operation instruction, wherein the third address information bit indicates a next step from the CPU to the next-level FPGA between the IIC devices to be operated Level device address information.
  • the method may further include: the first FPGA saver The second address information bit and the third address information bit sent by the first level controller; the first FPGA sends the confirmation information to the upper level controller; the first FPGA passes the An IIC bus, establishing a connection with the upper controller again; the first FPGA receives and saves the data to be read sent by the upper controller in an internal register address of the IIC device to be operated.
  • the first FPGA receives the first address information bit and the read operation instruction sent by the upper-level controller through the first IIC bus; the first FPGA establishes a connection with the next-level FPGA, and the The internal register address is sent to the next-level FPGA; the first FPGA sends the second address information bit and a read operation instruction to the next-stage FPGA.
  • the data frame sent by the CPU can be reasonably designed, so that the data frames transmitted in each stage conform to the IIC bus protocol standard.
  • the write timing of the IIC is as shown in FIG. 5, and the flow of the main device writing data to the slave device is as shown in FIG. 6.
  • the read timing is as shown in Fig. 7, and the flow of the master device reading data from the slave device is as shown in Fig. 8.
  • S denotes Start
  • A denotes ACK
  • N denotes NACK
  • P denotes Stop.
  • the white part and the "N" are the data sent by the master device
  • the padding part is the data sent by the slave device.
  • the Slave Address in the standard sequence is modified to the SecondMaster Address
  • the Register Address is modified to the Slave Address (7bit)-WR/RD (1 bit). ), and increase the Register Address to the front of DATA, so that the total number of bytes of DATA becomes N+1.
  • the write timing issued by the modified CPU is as shown in FIG. 9, and the flow of the main device writing data to the slave device is as shown in FIG.
  • the read timing is divided into two operations.
  • the first operation is a write operation.
  • the purpose is to let the SecondMaster obtain the read operation instruction and the slave device address.
  • the second operation starts to read the data from the slave device.
  • the timing is as shown in FIG. Figure 12 shows.
  • the SecondMaster Address is the address of the FPGA
  • the Slave Address is the address of the device (slave) that is ultimately accessed
  • the Register Address is the internal offset of the slave. This increases the encapsulation of the primary address. It can be seen that for the CPU and FPGA, the operation of the two still meets the standard protocol of the IIC bus. If the Slave Address (7 bit) - WR / RD (1 bit) is treated as a byte, the CPU write operation to the FPGA is consistent with the standard timing, and the CPU can read the FPGA as a write operation + a read operation.
  • S denotes Start
  • A denotes ACK
  • N denotes NACK
  • P denotes Stop
  • SM denotes SecondMaster.
  • the white portion and "N" are sent as the master device, and the padding portion is sent from the slave device.
  • the FPGA side when receiving a read/write request from the CPU, it is necessary to determine whether the 1-bit read/write flag bit following the Slave Address (7bit) is read or write. If it is a write operation, the write timing is sent directly to the device (slave) that is ultimately accessed:
  • the timing between the FPGA and the slave is the same as the standard IIC bus timing, ie, Figures 5 and 7.
  • the cooperation of the two buses is realized by the transmission of the ACK signal.
  • the ACK signal sent from the device is sent to the FPGA, and the FPGA sends an ACK signal to the CPU to complete the entire timing requirement.
  • the following describes the write operation and read operation of the CPU to the finally accessed device (slave device) by taking the secondary IIC bus as an example.
  • FIG. 10 is a flowchart of a CPU performing a write operation on a finally accessed device (slave device) according to an embodiment of the present invention.
  • the CPU performs a write operation on the IIC device, which mainly includes the following process:
  • the CPU sends a Start signal.
  • the CPU sends a 7-bit (bit) FPGA address and a 1-bit write signal.
  • the FPGA receives the connection request from the CPU and returns an ACK signal.
  • the CPU establishes communication with the slave device.
  • the CPU sends a 7-bit slave address and a 1-bit write signal.
  • the FPGA receives the slave address and the write signal, and determines that the operation on the slave device is a write operation.
  • the FPGA converts the role to the master device and sends a Start signal to the finally accessed device.
  • the FPGA sends a 7-bit slave address and a 1-bit write signal.
  • the slave device receives the connection request of the FPGA and returns an ACK signal.
  • the FPGA After receiving the ACK signal, the FPGA returns an ACK signal to the CPU.
  • the CPU tells the slave device to access the register address
  • the CPU sends a 1 byte slave internal register address to the FPGA.
  • the FPGA After receiving the register address, the FPGA sends it to the slave device.
  • the ACK signal is returned after receiving the register address from the device.
  • the FPGA After receiving the ACK signal, the FPGA returns an ACK signal to the CPU.
  • the CPU sends 1 byte of data.
  • the FPGA After the FPGA receives the data, it sends it to the slave device.
  • the third step is to perform a write operation after receiving the data from the device and return an ACK signal.
  • the FPGA After receiving the ACK signal, the FPGA returns an ACK signal to the CPU.
  • the first to fourth steps are repeated until the data is completely transmitted.
  • the CPU sends a Stop signal.
  • the FPGA After receiving the Stop signal, the FPGA sends Stop to the slave device. The operation is completed.
  • FIG. 12 is a flowchart of a CPU performing a read operation on a finally accessed device (slave device) according to an embodiment of the present invention.
  • the CPU performs a read operation on the IIC device, which mainly includes the following. process:
  • the CPU sends a Start signal.
  • the CPU sends a 7-bit FPGA address and a 1-bit write signal.
  • the FPGA receives the connection request from the CPU and returns an ACK signal.
  • the CPU tells the FPGA that the operation is a read operation
  • the CPU sends a 7-bit slave address and a 1-bit read signal.
  • the FPGA receives the slave address and the read signal, and determines that the operation on the slave device is a read operation.
  • the slave device address is saved locally and the ACK signal is returned to the CPU.
  • the CPU sends a Stop signal.
  • the CPU sends a Start signal.
  • the CPU sends a 7-bit FPGA address and a 1-bit write signal.
  • the FPGA receives the connection request from the CPU and returns an ACK signal.
  • the CPU sends a 1-byte slave internal device address.
  • the FPGA saves the register address locally and returns an ACK signal to the CPU.
  • the CPU sends a 7-bit FPGA address and a 1-bit read signal.
  • the FPGA receives the FPGA address and the read signal, and determines that the operation on the slave device is a read operation.
  • the FPGA converts the role to the master device and sends a Start signal to the finally accessed device.
  • the FPGA sends a 7-bit slave address and a 1-bit write signal.
  • the slave device receives the connection request of the FPGA and returns an ACK signal.
  • FPGA reads data from the slave device and returns to the CPU
  • the FPGA sends a 1-byte slave device's internal register address.
  • the ACK signal is returned after the device receives the register address.
  • the FPGA After receiving the ACK signal, the FPGA sends a Start signal.
  • the FPGA sends a 7-bit slave address and a 1-bit read signal.
  • the slave device receives the connection request of the FPGA and returns an ACK signal.
  • the FPGA After receiving the data, the FPGA returns an ACK signal to the CPU and sends the data to the CPU.
  • the CPU returns an ACK signal after receiving the data.
  • the FPGA After receiving the ACK signal, the FPGA returns an ACK signal to the slave device.
  • the sixth to ninth steps are repeated (the seventh step no longer returns the ACK signal to the CPU) until the last data is received.
  • the last 1 byte of data is sent from the device.
  • the FPGA After the FPGA receives the data, it sends the data to the CPU.
  • the CPU determines that it is the last data and returns a NACK signal.
  • the FPGA After receiving the NACK signal, the FPGA returns a NACK signal to the slave device.
  • the control of the data line is discarded.
  • the FPGA sends a Stop signal on the IIC bus connected to the slave device, and gives up control of the data line connected to the bus.
  • the CPU sends a Stop signal. The operation is completed.
  • the operation sequence of the two IIC buses on the FPGA may be adjusted as long as the design timings of both sides are satisfied. Repeating the first five steps of the read operation and the first ten steps of the write operation can increase the number of IIC levels to three or more. For example, if the IIC is three-level, the read operation timing between the CPU and each FPGA (FPGA1 and FPGA2) is as shown in FIG.
  • a field programmable logic gate array is added between the CPU and the IIC device, and between the IIC bus between the CPU and the FPGA and between the FPGA and the IIC device.
  • the IIC bus is independent of each other, the CPU can be connected to multiple FPGAs, and one FPGA can be divided into multiple zones, each zone can be connected to multiple IIC devices, thereby solving the problem of address overlap of multiple IIC devices, and does not depend on Additional additional buses do not increase the interface burden on the CPU side.
  • modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein.
  • the steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module.
  • the invention is not limited to any specific combination of hardware and software.
  • the problem of address overlap of a plurality of IIC devices is solved, and it is not dependent on an additional other bus, and the interface negative on the CPU side is not increased.

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Abstract

本发明公开一种集成电路总线系统及其数据操作和传输方法。其中，该集成电路总线系统包括：CPU和IIC器件，连接在CPU与IIC器件之间的现场可编程逻辑门阵列FPGA，其中，CPU与FPGA之间通过第一IIC总线连接；FPGA与IIC器件之间通过第二IIC总线连接，第一IIC总线与第二IIC总线相互独立；CPU设置为通过第一IIC总线访问FPGA，并通过FPGA向IIC器件发送操作指令；FPGA设置为作为主设备通过第二IIC总线与IIC器件进行交互，执行操作指令，以及透传CPU与IIC器件之间传输的读数据或写数据。

Description

集成电路总线系统及其数据操作和传输方法 技术领域
本发明涉及通用集成电路总线技术领域，具体而言，涉及一种集成电路总线系统及其数据操作和传输方法。
背景技术
集成电路总线(Inter-Integrated Circuit，IIC)规范作为一种两线式串行总线-只有一条数据线和一条时钟线的总线-已经成为一个国际标准，在超过100种不同的集成电路(integrated circuit，IC)上实现并得到超过50家公司的许可。符合IIC总线标准的IC都必须有一个7bits的器件地址，作为自己被访问时的地址标识。此外，在同一条总线上，器件和器件地址必须是一一对应的。很多IC厂家的器件只支持2-3bits的自定义地址。在这种情况下，如果同一条总线上相同器件的数量大于自定义地址支持的最大地址数，则将导致同一器件地址对应多个器件。比如某温度传感芯片，只有2bits自定义地址，如果一个硬件系统设计有6个温感，则必然有2个温度传感芯片和其他温度传感芯片的地址重叠。
针对有固定器件地址的IC，比如光模块器件(相同型号的光模块，器件地址全部相同)相关技术中通常采用的方式是通过逻辑芯片做一个选通开关，在访问指定光模块前先将对应的光模块选通到IIC总线上，然后访问光模块的器件地址。但是这种方法需要LocalBus总线或通用I/O端口(General-Purpose Input/Output Ports，GPIO)来处理选通开关功能，即需要除IIC总线之外的另一条总线做配合，并不能普遍适用于各种地址重叠问题的解决。
针对相关技术中多个器件的地址重叠问题，目前尚未提出有效的解决方案。
发明内容
针对相关技术中存在的多个器件的地址重叠的问题，本发明提供了一种IIC总线系统及其数据操作和传输方法，以至少解决上述问题。
根据本发明的一个方面，提供了一种集成电路总线IIC系统，包括中央处理器CPU和IIC器件，连接在所述CPU与IIC器件之间的现场可编程逻辑门阵列FPGA，其中，所述CPU与所述FPGA之间通过第一IIC总线连接；所述FPGA与所述IIC器件之间 通过第二IIC总线连接，所述第一IIC总线与所述第二IIC总线相互独立；所述CPU设置为通过所述第一IIC总线访问所述FPGA，并通过所述FPGA向所述IIC器件发送操作指令；所述FPGA设置为作为主设备通过所述第二IIC总线与所述IIC器件进行交互，执行所述操作指令，以及透传所述CPU与所述IIC器件之间传输的读数据或写数据。
可选地，所述FPGA包括多个，多个所述FPGA之间通过相互独立的第三IIC总线连接。
根据本发明的另一个方面，提供了一种集成电路总线IIC的数据操作方法，应用于上述的系统，所述方法包括：中央处理器CPU通过第一IIC总线建立与所述CPU的下一级现场可编程逻辑门阵列FPGA的连接；所述CPU将从所述下一级FPGA的下一级设备到待操作的IIC器件的各个设备的地址及需要执行的操作指令，依次发送所述下一级FPGA，指示从所述下一级FPGA到所述待操作的IIC器件的上一级FPGA中的各个FPGA分别作为主设备与下一级设备建立连接，并执行所述操作指令，其中，所述下一级设备包括：FPGA或所述IIC器件；所述CPU通过从所述下一级FPGA到所述待操作的IIC器件的上一级FPGA中的各个FPGA从所述待操作的IIC器件读取或写入数据。
可选地，所述CPU通过第一IIC总线建立与所述CPU的下一级现场可编程逻辑门阵列FPGA的连接，包括：所述CPU通过所述第一IIC总线发送所述下一级FPGA的地址及写操作指令；所述CPU接收所述下一级FPGA通过所述第一IIC总线发送的确认信息ACK。
可选地，如果所述操作指令为写操作指令，则所述CPU将从所述下一级FPGA的下一级设备到待操作的IIC器件的各个设备的地址及需要执行的操作指令依次发送所述下一级FPGA之后，所述方法还包括：所述CPU通过所述第一IIC总线发送待操作的所述IIC器件的内部寄存器地址；所述CPU在接收到ACK后，通过所述第一IIC总线发送需要写入的1字节数据，在接收到ACK后，发送需要写入的下一字节数据，直至发送完所有需要写的数据，所述CPU通过所述第一IIC总线发送停止指令。
可选地，如果所述操作指令为读操作指令，则所述CPU通过所述第一IIC总线发送所述待操作的IIC器件在所述上一级FPGA下地址及需要执行的操作指令之后，所述方法还包括：所述CPU通过所述第一IIC总线发送停止指令；所述CPU通过所述第一IIC总线再次建立与所述CPU的所述下一级FPGA的连接；所述CPU通过所述第一IIC总线发送需要读取数据的寄存器地址及读操作指令；所述CPU接收到ACK 后，通过所述第一IIC总线发送所述CPU的所述下一级FPGA的地址及读操作指令；所述CPU接收所述CPU的下一级FPGA传输的从所述IIC器件中读取的1字节的读数据；所述CPU向所述下一级FPGA发送ACK，接收所述下一级FPGA传输的从所述IIC器件中读取的下一字节数据，直至接收完所有需要读的数据。
根据本发明的又一个方面，提供了一种集成电路总线IIC的数据传输方法，包括：第一现场可编程逻辑门阵列FPGA通过与上一级控制器之间的第一IIC总线，与所述上一级控制器建立连接，其中，所述上一级控制器包括：中央处理器CPU或FPGA；所述第一FPGA接收所述上一级控制器通过所述第一IIC总线针对所述第一FPGA的下一级设备的操作指令，其中，所述下一级设备包括：下一级FPGA或待操作的IIC器件，所述操作指令包括：写操作指令或读操作指令；所述第一FPGA作为主设备，通过与所述下一级设备之间的第二IIC总线，执行所述操作指令，透传所述上一级控制器与所述下一级设备之间传输的写数据或读数据。
可选地，第一FPGA通过与上一级控制器之间的第一IIC总线，与所述上一级控制器建立连接，包括：所述第一FPGA接收所述上一级控制器发送的第一地址信息比特及写操作指令，其中，所述第一地址信息比特指示所述第一FPGA在所述上一级控制器下的地址信息；所述第一FPGA通过所述第一IIC总线，向所述上一级控制器返回确认信息ACK。
可选地，如果所述操作指令为写操作指令，则通过与所述下一级设备之间的第二IIC总线，执行所述操作指令，透传所述上一级控制器与所述下一级设备之间传输的写数据或读数据，包括：所述第一FPGA作为主设备，根据所述上一级控制器发送的第二地址信息比特及所述写操作指令，通过所述第二IIC总线，与所述下一级设备之间建立连接，其中，所述第二地址信息比特指示所述下一级设备的地址；所述第一FPGA透传所述第一FPGA与所述下一级设备之间所述第一IIC总线发送的数据帧。
可选地，如果所述操作指令为读操作指令，则通过与所述下一级设备之间的第二IIC总线，执行所述操作指令，透传所述上一级控制器与所述下一级设备之间传输的读取的数据或待写入的数据，包括：所述第一FPGA作为主设备，根据所述上一级控制器发送的第二地址信息比特通过所述第二IIC总线，与所述下一级设备建立连接，其中，所述第二地址信息比特指示所述下一级设备的地址；如果所述下一级设备为所述待操作的IIC器件，则所述第一FPGA根据所述上一级控制器发送的待读取的数据在所述待操作的IIC器件的内部寄存器地址，通过所述第二IIC总线从所述下一级设备读取数据，并将读取的数据通过所述第一IIC总线传输给所述上一级控制器；或者，如果所述下一级设备为下一级FPGA，则所述第一FPGA通过所述第二IIC总线向所 述下一级FPGA发送第三地址信息比特及读操作指令，其中，所述第三地址信息比特指示从CPU到所述待操作的IIC器件之间的所述下一级FPGA的下一级设备地址信息。
可选地，在所述第一FPGA通过所述第二IIC总线向所述下一级FPGA发送第三地址信息比特及读操作指令之后，所述方法还包括：所述第一FPGA保存所述上一级控制器发送的所述第二地址信息比特及所述第三地址信息比特；所述第一FPGA向所述上一级控制器发送确认信息；所述第一FPGA通过所述第一IIC总线，再次与所述上一级控制器建立连接；所述第一FPGA接收并保存所述上一级控制器发送的待读取的数据在所述待操作的IIC器件的内部寄存器地址；所述第一FPGA接收所述上一级控制器通过所述第一IIC总线发送的第一地址信息比特和读操作指令；所述第一FPGA与所述下一级FPGA建立连接，将所述内部寄存器地址发送给所述下一级FPGA；所述第一FPGA向所述下一级FPGA发送所述第二地址信息比特和读操作指令。
通过本发明，在CPU和IIC器件之间增加现场可编程逻辑门阵列(FPGA)，CPU与FPGA之间的IIC总线与FPGA与IIC器件之间的IIC总线相互独立，CPU可以连接多个FPGA，而一个FPGA可以分为多个区，每个区可以连接多个IIC器件，从而解决了多个IIC器件的地址重叠的问题，并且不依赖于额外的其他总线，不会增加CPU侧的接口负担。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本申请的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1是根据本发明实施例的IIC总线系统的结构示意图；
图2是根据本发明实施例的二级IIC总线系统设计示例图；
图3是根据本发明实施例的IIC的数据操作方法的流程图；
图4是根据本发明实施例的IIC的数据传输方法的流程图；
图5是相关技术中标准IIC总线写操作时序的示意图；
图6是相关技术中标准IIC写操作流程图；
图7是相关技术中标准IIC总线读操作时序的示意图；
图8是相关技术中标准IIC读操作流程图；
图9是本发明实施例中二级IIC的写操作时序的示意图；
图10是本发明实施例中二级IIC的写操作流程图；
图11是本发明实施例中二级IIC的读操作时序的示意图；
图12是本发明实施例中二级IIC的读操作流程图；
图13是本发明实施例中三级IIC的读操作时序的示意图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本发明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
图1是根据本发明实施例的集成电路总线(IIC)系统的结构示意图，如图1所示，本发明实施例中的IIC系统包括：CPU 1、FPGA 2和IIC器件。其中，所述CPU 1与所述FPGA 2之间通过第一IIC总线10连接；所述FPGA 2与所述IIC器件3之间通过第二IIC总线20连接，所述第一IIC总线10与所述第二IIC总线20相互独立；所述CPU 1设置为通过所述第一IIC总线10访问所述FPGA 2，并通过所述FPGA 2向所述IIC器件3发送操作指令；所述FPGA 2设置为作为主设备通过所述第二IIC总线20与所述IIC器件3进行交互，执行所述操作指令，以及透传所述CPU 1与所述IIC器件3之间传输的读数据或写数据。
可选地，连接在CPU 1与所述IIC器件3之间的FPGA 2可以有多个，多个所述FPGA之间通过相互独立的第三IIC总线连接。即在CPU 1与所述IIC器件3之间有多级(大于2)IIC总线，从而可以布局更多的地址不重叠的IIC器件。
例如，以二级寻址为例，在CPU与IIC器件之间增加一个FPGA器件作为二级主设备。在本实施例中，可以将一次CPU对IIC器件的操作时序称为一帧。本发明实施例中，CPU通过间接寻址的方式访问IIC器件，即首先CPU通过IIC总线访问FPGA，此时CPU是主设备，FPGA是从设备，然后FPGA将CPU传来的数据帧存在本地，剥离与自己有关的内容，而后自己作为主设备，将数据帧透传到指定的IIC器件。CPU到FPGA间的IIC总线和FPGA到器件间的IIC总线相互独立。
图2是本发明实施例中，二级IIC总线系统的设计示例图。如图2所示，在本实施例中，CPU通过第一IIC总线连接FPGA，FPGA分为两个区，两个区的地址分别为地址A1和地址A2。FPGA的1区通过第二IIC总线连接三个IIC器件，即IIC器件1(地址为B1)、IIC器件2(地址为B2)及IIC器件3(地址为B3)。而FPGA的2区通过第二IIC总线连接三个IIC器件，即IIC器件4(地址为B4)、IIC器件5(地址为B5)及IIC器件6(地址为B6)。
通过本发明实施例提供的技术方案，由于FPGA其具有缓存数据、转发、独立发包等功能，能够响应并隔离多个IIC地址，兼备IIC主从设备功能，从而可以实现多个IIC器件地址不重叠。
基于本发明实施例提供的上述IIC总线系统，本发明实施例还提供了一种IIC的数据操作方法，通过该方法，CPU可以从IIC器件中读取或写入数据。
图3为根据本发明实施例的IIC的数据操作方法的流程图，如图3所示，该方法主要包括以下步骤：
步骤S302，CPU通过第一IIC总线建立与CPU的下一级FPGA的连接；
在本发明实施例中，CPU可以通过向下一级FPGA发送该FPGA的地址及写操作指令，与下一级FPGA建立连接。因此，可选地，步骤S302可以包括：步骤1，CPU通过第一IIC总线发送下一级FPGA的地址及写操作指令；CPU接收所述下一级FPGA通过所述第一IIC总线发送的确认信息ACK。
步骤S304，CPU将从所述下一级FPGA的下一级设备到待操作的IIC器件的各个设备的地址及需要执行的操作指令，依次发送至所述下一级FPGA，指示从所述下一级FPGA到所述待操作的IIC器件的上一级FPGA中的各个FPGA分别作为主设备与下一级设备建立连接，并执行所述操作指令，其中，所述下一级设备包括：FPGA或所述IIC器件；
步骤S306，CPU通过从所述下一级FPGA到所述待操作的IIC器件的上一级FPGA中的各个FPGA从所述待操作的IIC器件读取或写入数据。
在一个可选实施方式中，如果所述操作指令为写操作指令，则所述CPU将从所述下一级FPGA的下一级设备到待操作的IIC器件的各个设备的地址及需要执行的操作指令依次发送所述下一级FPGA之后，所述方法还包括：所述CPU通过所述第一IIC总线发送待操作的所述IIC器件的内部寄存器地址；所述CPU在接收到ACK后，通 过所述第一IIC总线发送需要写入的1字节数据，在接收到ACK后，发送需要写入的下一字节数据，直至发送完所有需要写的数据，所述CPU通过所述第一IIC总线发送停止指令。
可选地，如果所述操作指令为读操作指令，则所述CPU通过所述第一IIC总线发送所述待操作的IIC器件在所述上一级FPGA下地址及需要执行的操作指令之后，所述方法还包括：所述CPU通过所述第一IIC总线发送停止指令；所述CPU通过所述第一IIC总线再次建立与所述CPU的所述下一级FPGA的连接；所述CPU通过所述第一IIC总线发送需要读取数据的寄存器地址及读操作指令；所述CPU接收到ACK后，通过所述第一IIC总线发送所述CPU的所述下一级FPGA的地址及读操作指令；所述CPU接收所述CPU的下一级FPGA传输的从所述IIC器件中读取的1字节的读数据；所述CPU向所述下一级FPGA发送ACK，接收所述下一级FPGA传输的从所述IIC器件中读取的下一字节数据，直至接收完所有需要读的数据。
基于本发明实施例提供的上述IIC总线系统，本发明实施例还提供了一种IIC的数据传输方法，通过该方法，FPGA可以作为中间设备，实现CPU间接从IIC器件中读取或写入数据。
图4为根据本发明实施例的提供的IIC总线的数据传输方法的流程图，如图4所示，该方法主要包括以下步骤：
步骤S402，第一FPGA通过与上一级控制器之间的第一IIC总线，与所述上一级控制器建立连接，其中，所述上一级控制器包括：中央处理器CPU或FPGA；
可选地，第一FPGA与上一级控制器之间建立连接时，可以通过上一级控制器发送第一FPGA的地址信息比特及写操作指令来实现，因此，可选地，步骤S402可以包括：步骤1，所述第一FPGA接收所述上一级控制器发送的第一地址信息比特及写操作指令，其中，所述第一地址信息比特指示所述第一FPGA在所述上一级控制器下的地址信息；步骤2，所述第一FPGA通过所述第一IIC总线，向所述上一级控制器返回确认信息ACK。
步骤S404，第一FPGA接收所述上一级控制器通过所述第一IIC总线针对所述第一FPGA的下一级设备的操作指令，其中，所述下一级设备包括：下一级FPGA或待操作的IIC器件，所述操作指令包括：写操作指令或读操作指令；
步骤S406，第一FPGA作为主设备，通过与所述下一级设备之间的第二IIC总线，执行所述操作指令，透传所述上一级控制器与所述下一级设备之间传输的写数据或读数据。
如果所述操作指令为写操作指令，则可选地，步骤S406可以包括：所述第一FPGA作为主设备，根据所述上一级控制器发送的第二地址信息比特及所述写操作指令，通过所述第二IIC总线，与所述下一级设备之间建立连接，其中，所述第二地址信息比特指示所述下一级设备的地址；所述第一FPGA透传所述第一FPGA与所述下一级设备之间所述第一IIC总线发送的数据帧。
如果所述操作指令为读操作指令，则可选地，步骤S406可以包括：所述第一FPGA作为主设备，根据所述上一级控制器发送的第二地址信息比特通过所述第二IIC总线，与所述下一级设备建立连接，其中，所述第二地址信息比特指示所述下一级设备的地址；如果所述下一级设备为所述待操作的IIC器件，则所述第一FPGA根据所述上一级控制器发送的待读取的数据在所述待操作的IIC器件的内部寄存器地址，通过所述第二IIC总线从所述下一级设备读取数据，并将读取的数据通过所述第一IIC总线传输给所述上一级控制器；或者，如果所述下一级设备为下一级FPGA，则所述第一FPGA通过所述第二IIC总线向所述下一级FPGA发送第三地址信息比特及读操作指令，其中，所述第三地址信息比特指示从CPU到所述待操作的IIC器件之间的所述下一级FPGA的下一级设备地址信息。
可选地，在所述第一FPGA通过所述第二IIC总线向所述下一级FPGA发送第三地址信息比特及读操作指令之后，所述方法还可以包括：所述第一FPGA保存所述上一级控制器发送的所述第二地址信息比特及所述第三地址信息比特；所述第一FPGA向所述上一级控制器发送确认信息；所述第一FPGA通过所述第一IIC总线，再次与所述上一级控制器建立连接；所述第一FPGA接收并保存所述上一级控制器发送的待读取的数据在所述待操作的IIC器件的内部寄存器地址；所述第一FPGA接收所述上一级控制器通过所述第一IIC总线发送的第一地址信息比特和读操作指令；所述第一FPGA与所述下一级FPGA建立连接，将所述内部寄存器地址发送给所述下一级FPGA；所述第一FPGA向所述下一级FPGA发送所述第二地址信息比特和读操作指令。
本发明实施例中，可以通过合理设计CPU发出的数据帧，使得每一级传递中数据帧都符合IIC总线协议标准。
在标准IIC总线协议中，IIC的写时序如图5所示，主设备向从设备写入数据的流程如图6所示。读时序如图7所示，主设备由从设备读出数据的流程如图8所示。图5和图7中S表示Start(开始)，A表示ACK，N表示NACK，P表示Stop(结束)。白色部分及“N”为主设备发送的数据，填充部分为从设备发送的数据。
本发明实施例，以二级IIC总线为例，将标准时序中的Slave Address(从设备地址)修改为SecondMaster Address，将Register Address(注册地址)修改为Slave Address(7bit)—WR/RD(1bit)，并将Register Address增加到DATA前面，使得DATA的总字节数变为N+1。
修改后的CPU发出的写时序如图9所示，主设备向从设备写入数据的流程如图10所示。读时序分为两次操作，第一次操作为写操作，目的是让SecondMaster获得读操作指令和从设备地址，第二次操作开始由从设备读出数据，时序如图11所示，流程如图12所示。
其中SecondMaster Address为FPGA的地址，Slave Address为最终被访问的器件(从设备)地址，Register Address为从设备的内部偏移地址。由此增加了一级地址的封装。可以看出，对于CPU和FPGA来说，二者这间的操作依然满足IIC总线的标准协议。如果把Slave Address(7 bit)—WR/RD(1bit)当做一个byte来看，CPU对FPGA的写操作与标准时序一致，CPU对FPGA的读操作可以看做一次写操作+一次读操作。
在图9和图11中S表示Start，A表示ACK，N表示NACK，P表示Stop，SM表示SecondMaster。白色部分和“N”为主设备发送，填充部分为从设备发送。在FPGA侧，收到CPU的读写请求，需要判断Slave Address(7bit)后面的1bit读写标识位是读还是写。如果是写操作，则直接向最终被访问的器件(从设备)发送写时序：
Start—Slave Address(7bit)—WR(1bit)—ACK—Register Address—ACK—DATA(N byte)—ACK—STOP；
如果是读操作，需要先缓存Slave Address，然后向CPU发送应答信号，等待CPU的第二次操作。当再次收到相同的Slave Address并且后面的1bit读写标识位是读操作后，发送读时序：
Start—Slave Address(7bit)—WR(1bit)—ACK—Register Address—ACK—Start—Slave Address—RD(1bit)—ACK—DATA(N byte)—NACK—STOP。
可以看到，FPGA和从设备间的时序与标准IIC总线时序，即图5和7相同。两条总线的配合是通过ACK信号的传递实现的。从设备发出的ACK信号发送到FPGA，FPGA再发ACK信号给CPU，完成整个时序要求。
为进一步理解本发明，下面以二级IIC总线为例，分别对CPU对最终被访问器件(从设备)执行写操作和读操作进行描述。
图10为本发明实施例中，CPU对最终被访问器件(从设备)执行写操作的流程图，如图10所示，在二级IIC总线中，CPU对IIC器件执行写操作主要包括以下的过程：
1、CPU与FPGA建立通信
第一步，CPU发送Start信号。
第二步，CPU发送7bits(比特)的FPGA地址和1bit写信号。
第三步，FPGA收到CPU的连接请求，回复ACK信号。
2、CPU与从设备建立通信
第一步，CPU发送7bits从设备地址和1bit写信号。
第二步，FPGA收到从设备地址和写信号，判断对从设备的操作为写操作。
第三步，FPGA转换角色为主设备，向最终被访问器件发送Start信号。
第四步，FPGA发送7bits从设备地址和1bit写信号。
第五步，从设备收到FPGA的连接请求，回复ACK信号。
第六步，FPGA收到ACK信号后，返回ACK信号给CPU。
3、CPU告知从设备访问寄存器地址
第一步，CPU发送1byte的从设备内部寄存器地址给FPGA。
第二步，FPGA收到寄存器地址后，将其发送给从设备。
第三步，从设备收到寄存器地址后返回ACK信号。
第四步，FPGA收到ACK信号后，返回ACK信号给CPU。
4、CPU向从设备写入数据
第一步，CPU发送1byte的数据。
第二步，FPGA收到数据后，将其发送给从设备。
第三步，从设备收到数据后执行写操作，并返回ACK信号。
第四步，FPGA收到ACK信号后，返回ACK信号给CPU。
第五步，重复第一到第四步，直到数据全部发送完成。
5、通信结束
第一步，CPU发送Stop信号。
第二步，FPGA收到Stop信号后，发送Stop给从设备。操作完毕。
图12为本发明实施例中，CPU对最终被访问器件(从设备)执行读操作的流程图，如图12所示，在二级IIC总线中，CPU对IIC器件执行读操作主要包括以下的过程：
1、CPU与FPGA建立通信
第一步，CPU发送Start信号。
第二步，CPU发送7bits的FPGA地址和1bit写信号。
第三步，FPGA收到CPU的连接请求，回复ACK信号。
2、CPU告知FPGA此次操作为读操作
第一步，CPU发送7bits从设备地址和1bit读信号。
第二步，FPGA收到从设备地址和读信号，判断对从设备的操作为读操作。将从设备地址保存在本地，回复ACK信号给CPU。
第三步，CPU发送Stop信号。
3、CPU与FPGA重新建立通信
第一步，CPU发送Start信号。
第二步，CPU发送7bits的FPGA地址和1bit写信号。
第三步，FPGA收到CPU的连接请求，回复ACK信号。
第四步，CPU发送1byte的从设备内部寄存器地址。
第五步，FPGA将寄存器地址保存在本地，回复ACK信号给CPU。
4、CPU与从设备建立通信
第一步，CPU发送7bits的FPGA地址和1bit读信号。
第二步，FPGA收到FPGA地址和读信号，判断对从设备的操作为读操作。
第三步，FPGA转换角色为主设备，向最终被访问器件发送Start信号。
第四步，FPGA发送7bits从设备地址和1bit写信号。
第五步，从设备收到FPGA的连接请求，回复ACK信号。
5、FPGA由从设备读出数据并返回给CPU
第一步，FPGA发送1byte的从设备的内部寄存器地址。
第二步，从设备收到寄存器地址后返回ACK信号。
第三步，FPGA收到ACK信号后，发送Start信号。
第四步，FPGA发送7bits从设备地址和1bit读信号。
第五步，从设备收到FPGA的连接请求，回复ACK信号。
第六步，从设备发送1byte的数据。
第七步，FPGA收到数据后，返回ACK信号给CPU，并将数据发送给CPU。
第八步，CPU收到数据后返回ACK信号。
第九步，FPGA收到ACK信号后，返回ACK信号给从设备。
第十步，重复第六到第九步(第七步不再返回ACK信号给CPU)，直到接收最后一个数据。
6、通信结束
第一步，从设备发送最后1byte的数据。
第二步，FPGA收到数据后，将数据发送给CPU。
第三步，CPU收到数据后，判断其为最后一个数据，返回NACK信号。
第四步，FPGA收到NACK信号后，返回NACK信号给从设备。
第五步，从设备收到NACK信号后，放弃数据线的控制权。
第六步，FPGA在与从设备相连的IIC总线上发送Stop信号，并放弃与CPU相连总线的数据线控制权。
第七步，CPU发送Stop信号。操作完毕。
对于本发明实施例中FPGA上两条IIC总线的操作顺序可以有调整，只要满足两侧的设计时序即可。对读操作的前五步和写操作的前十步进行重复，可以将IIC级数增加到三级或以上。例如，如果IIC为三级时，CPU和各个FPGA(FPGA1和FPGA2)间读操作时序如图13所示。
从以上的描述中，可以看出，在本发明实施例中，在CPU和IIC器件之间增加现场可编程逻辑门阵列(FPGA)，CPU与FPGA之间的IIC总线与FPGA与IIC器件之间的IIC总线相互独立，CPU可以连接多个FPGA，而一个FPGA可以分为多个区，每个区可以连接多个IIC器件，从而解决了多个IIC器件的地址重叠的问题，并且不依赖于额外的其他总线，不会增加CPU侧的接口负担。
显然，本领域的技术人员应该明白，上述的本发明的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本发明不限制于任何特定的硬件和软件结合。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
工业实用性
如上所述，通过上述实施例及优选实施方式,解决了多个IIC器件的地址重叠的问题，并且不依赖于额外的其他总线，不会增加CPU侧的接口负。

Claims (11)

  1. 一种集成电路总线IIC系统，包括中央处理器CPU和IIC器件，还包括：连接在所述CPU与IIC器件之间的现场可编程逻辑门阵列FPGA，其中，
    所述CPU与所述FPGA之间通过第一IIC总线连接；
    所述FPGA与所述IIC器件之间通过第二IIC总线连接，所述第一IIC总线与所述第二IIC总线相互独立；
    所述CPU设置为通过所述第一IIC总线访问所述FPGA，并通过所述FPGA向所述IIC器件发送操作指令；
    所述FPGA设置为作为主设备通过所述第二IIC总线与所述IIC器件进行交互，执行所述操作指令，以及透传所述CPU与所述IIC器件之间传输的读数据或写数据。
  2. 根据权利要求1所述的系统，其中，所述FPGA包括多个，多个所述FPGA之间通过相互独立的第三IIC总线连接。
  3. 一种集成电路总线IIC的数据操作方法，应用于权利要求1或2所述的系统，所述方法包括：
    中央处理器CPU通过第一IIC总线建立与所述CPU的下一级现场可编程逻辑门阵列FPGA的连接；
    所述CPU将从所述下一级FPGA的下一级设备到待操作的IIC器件的各个设备的地址及需要执行的操作指令，依次发送所述下一级FPGA，指示从所述下一级FPGA到所述待操作的IIC器件的上一级FPGA中的各个FPGA分别作为主设备与下一级设备建立连接，并执行所述操作指令，其中，所述下一级设备包括：FPGA或所述IIC器件；
    所述CPU通过从所述下一级FPGA到所述待操作的IIC器件的上一级FPGA中的各个FPGA从所述待操作的IIC器件读取或写入数据。
  4. 根据权利要求3所述的方法，其中，所述CPU通过第一IIC总线建立与所述CPU的下一级现场可编程逻辑门阵列FPGA的连接，包括：
    所述CPU通过所述第一IIC总线发送所述下一级FPGA的地址及写操作指令；
    所述CPU接收所述下一级FPGA通过所述第一IIC总线发送的确认信息ACK。
  5. 根据权利要求3或4所述的方法，其中，如果所述操作指令为写操作指令，则所述CPU将从所述下一级FPGA的下一级设备到待操作的IIC器件的各个设备的地址及需要执行的操作指令依次发送所述下一级FPGA之后，所述方法还包括：
    所述CPU通过所述第一IIC总线发送待操作的所述IIC器件的内部寄存器地址；
    所述CPU在接收到ACK后，通过所述第一IIC总线发送需要写入的1字节数据，在接收到ACK后，发送需要写入的下一字节数据，直至发送完所有需要写的数据，所述CPU通过所述第一IIC总线发送停止指令。
  6. 根据权利要求3或4所述的方法，其中，如果所述操作指令为读操作指令，则所述CPU通过所述第一IIC总线发送所述待操作的IIC器件在所述上一级FPGA下地址及需要执行的操作指令之后，所述方法还包括：
    所述CPU通过所述第一IIC总线发送停止指令；
    所述CPU通过所述第一IIC总线再次建立与所述CPU的所述下一级FPGA的连接；
    所述CPU通过所述第一IIC总线发送需要读取数据的寄存器地址及读操作指令；
    所述CPU接收到ACK后，通过所述第一IIC总线发送所述CPU的所述下一级FPGA的地址及读操作指令；
    所述CPU接收所述CPU的下一级FPGA传输的从所述IIC器件中读取的1字节的读数据；
    所述CPU向所述下一级FPGA发送ACK，接收所述下一级FPGA传输的从所述IIC器件中读取的下一字节数据，直至接收完所有需要读的数据。
  7. 一种集成电路总线IIC的数据传输方法，包括：
    第一现场可编程逻辑门阵列FPGA通过与上一级控制器之间的第一IIC总线，与所述上一级控制器建立连接，其中，所述上一级控制器包括：中央处理器CPU或FPGA；
    所述第一FPGA接收所述上一级控制器通过所述第一IIC总线针对所述第一FPGA的下一级设备的操作指令，其中，所述下一级设备包括：下一级FPGA或待操作的IIC器件，所述操作指令包括：写操作指令或读操作指令；
    所述第一FPGA作为主设备，通过与所述下一级设备之间的第二IIC总线，执行所述操作指令，透传所述上一级控制器与所述下一级设备之间传输的写数据或读数据。
  8. 根据权利要求7所述的方法，其中，第一FPGA通过与上一级控制器之间的第一IIC总线，与所述上一级控制器建立连接，包括：
    所述第一FPGA接收所述上一级控制器发送的第一地址信息比特及写操作指令，其中，所述第一地址信息比特指示所述第一FPGA在所述上一级控制器下的地址信息；
    所述第一FPGA通过所述第一IIC总线，向所述上一级控制器返回确认信息ACK。
  9. 根据权利要求7所述的方法，其中，如果所述操作指令为写操作指令，则通过与所述下一级设备之间的第二IIC总线，执行所述操作指令，透传所述上一级控制器与所述下一级设备之间传输的写数据或读数据，包括：
    所述第一FPGA作为主设备，根据所述上一级控制器发送的第二地址信息比特及所述写操作指令，通过所述第二IIC总线，与所述下一级设备之间建立连接，其中，所述第二地址信息比特指示所述下一级设备的地址；
    所述第一FPGA透传所述第一FPGA与所述下一级设备之间所述第一IIC总线发送的数据帧。
  10. 根据权利要求7所述的方法，其中，如果所述操作指令为读操作指令，则通过与所述下一级设备之间的第二IIC总线，执行所述操作指令，透传所述上一级控制器与所述下一级设备之间传输的读取的数据或待写入的数据，包括：
    所述第一FPGA作为主设备，根据所述上一级控制器发送的第二地址信息比特通过所述第二IIC总线，与所述下一级设备建立连接，其中，所述第二地址信息比特指示所述下一级设备的地址；
    如果所述下一级设备为所述待操作的IIC器件，则所述第一FPGA根据所述上一级控制器发送的待读取的数据在所述待操作的IIC器件的内部寄存器地 址，通过所述第二IIC总线从所述下一级设备读取数据，并将读取的数据通过所述第一IIC总线传输给所述上一级控制器；或者，
    如果所述下一级设备为下一级FPGA，则所述第一FPGA通过所述第二IIC总线向所述下一级FPGA发送第三地址信息比特及读操作指令，其中，所述第三地址信息比特指示从CPU到所述待操作的IIC器件之间的所述下一级FPGA的下一级设备地址信息。
  11. 根据权利要求10所述的方法，其中，在所述第一FPGA通过所述第二IIC总线向所述下一级FPGA发送第三地址信息比特及读操作指令之后，所述方法还包括：
    所述第一FPGA保存所述上一级控制器发送的所述第二地址信息比特及所述第三地址信息比特；
    所述第一FPGA向所述上一级控制器发送确认信息；
    所述第一FPGA通过所述第一IIC总线，再次与所述上一级控制器建立连接；
    所述第一FPGA接收并保存所述上一级控制器发送的待读取的数据在所述待操作的IIC器件的内部寄存器地址；
    所述第一FPGA接收所述上一级控制器通过所述第一IIC总线发送的第一地址信息比特和读操作指令；
    所述第一FPGA与所述下一级FPGA建立连接，将所述内部寄存器地址发送给所述下一级FPGA；
    所述第一FPGA向所述下一级FPGA发送所述第二地址信息比特和读操作指令。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117407343A (zh) * 2023-12-13 2024-01-16 苏州元脑智能科技有限公司 集成电路总线透传模式下时钟延展的处理方法及装置

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI557577B (zh) * 2016-01-12 2016-11-11 英業達股份有限公司 用於防止地址衝突之系統及其方法
CN106681220A (zh) * 2017-01-13 2017-05-17 上海蔚来汽车有限公司 基于中央处理器和可编程逻辑器件的换电动作控制系统
CN106921547B (zh) * 2017-01-25 2020-05-08 华为技术有限公司 管理设备的装置和方法
CN107870885A (zh) * 2017-11-28 2018-04-03 国网技术学院 通信系统、装置及方法
CN108108316B (zh) * 2017-12-14 2023-08-11 珠海西格电力科技有限公司 一种基于现场可编程门阵列的接口扩展方法及系统
CN109446154A (zh) * 2018-10-30 2019-03-08 广州开信通讯系统有限公司 光模块监控系统和方法
CN109614351B (zh) * 2018-11-30 2022-05-24 中国人民解放军陆军工程大学 带有纠错和自动应答机制的并行总线串行互联扩展方法
CN109992552A (zh) * 2019-04-10 2019-07-09 苏州浪潮智能科技有限公司 一种iic的管理装置及管理方法
CN110109857A (zh) * 2019-04-29 2019-08-09 杭州迪普科技股份有限公司 一种数据传输方法及装置
CN111400230A (zh) * 2020-03-10 2020-07-10 昆山丘钛微电子科技有限公司 数据传输方法、系统、控制设备及存储介质
WO2021203227A1 (zh) * 2020-04-07 2021-10-14 华为技术有限公司 基于内部集成电路协议的数据传输方法和传输装置
CN114398304A (zh) * 2022-03-01 2022-04-26 山西银河电子设备厂 一种解决srio接口阻塞的方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201374060Y (zh) * 2008-12-16 2009-12-30 康佳集团股份有限公司 一种iic总线扩展系统结构
CN103123615A (zh) * 2011-11-18 2013-05-29 快捷半导体(苏州)有限公司 管脚可选的i2c从机地址
CN103577356A (zh) * 2013-11-06 2014-02-12 杭州华三通信技术有限公司 实现iic接口地址扩展的设备及方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040255070A1 (en) * 2003-06-12 2004-12-16 Larson Thane M. Inter-integrated circuit router for supporting independent transmission rates
CN101324875B (zh) * 2007-06-11 2011-06-01 大唐移动通信设备有限公司 一种扩展i2c总线的方法及i2c总线扩展装置
CN102169463B (zh) * 2011-04-28 2013-10-23 杭州华三通信技术有限公司 一种基于iic总线的制造信息的获取方法和设备
CN103067179B (zh) * 2012-07-19 2016-08-10 曙光信息产业(北京)有限公司 一种利用双层连接器实现的24千兆以太网后插卡

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201374060Y (zh) * 2008-12-16 2009-12-30 康佳集团股份有限公司 一种iic总线扩展系统结构
CN103123615A (zh) * 2011-11-18 2013-05-29 快捷半导体(苏州)有限公司 管脚可选的i2c从机地址
CN103577356A (zh) * 2013-11-06 2014-02-12 杭州华三通信技术有限公司 实现iic接口地址扩展的设备及方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117407343A (zh) * 2023-12-13 2024-01-16 苏州元脑智能科技有限公司 集成电路总线透传模式下时钟延展的处理方法及装置
CN117407343B (zh) * 2023-12-13 2024-02-23 苏州元脑智能科技有限公司 集成电路总线透传模式下时钟延展的处理方法及装置

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