WO2015163603A1 - Dispositif électronique reconfigurable et son procédé d'exploitation - Google Patents

Dispositif électronique reconfigurable et son procédé d'exploitation Download PDF

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Publication number
WO2015163603A1
WO2015163603A1 PCT/KR2015/003420 KR2015003420W WO2015163603A1 WO 2015163603 A1 WO2015163603 A1 WO 2015163603A1 KR 2015003420 W KR2015003420 W KR 2015003420W WO 2015163603 A1 WO2015163603 A1 WO 2015163603A1
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electrode
electronic device
reconfigurable
electrodes
gate insulating
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PCT/KR2015/003420
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English (en)
Korean (ko)
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이종호
진성훈
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서울대학교 산학협력단
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a reconfigurable electronic device, and more particularly, to implement an independent bottom electrode array structure having a nonvolatile memory function, and to be deformable by electrically adjusting a channel layer based on ID, 2D material, or a thin semiconductor thin film.
  • a reconfigurable electronic device having a nonvolatile memory function is described in detail below.
  • Si-based sub-nm 3D devices are expected to be around 2020, the structural, material and performance limitations of Si-based devices are increasing the need for new next-generation semiconductor materials and new devices.
  • 1D semiconductor materials of Si nanowires (Si nanowi re) or i CNT-based attention due to the characteristics of quas i-bal li st ic transport, steep subthreshold swing, the ideal electrostat ic coupl ing I am getting it.
  • the ability to independently control the threshold voltage and the polarity of the FET (n-type or p-type) in the FET using the 1D material is known as a core technology of the reconfigurable circuit technology.
  • the polarity change (n-type or p-type) of the device using a gate electrode capable of applying voltage independently to the SWNT device [Non-Patent Document 1] published in 2005.
  • Non-Patent Documents 2 to 5 Ni S 2 is formed on both sides of a low concentration doped Si nanowire to form a Schottky junction, a gate insulating film is formed, By controlling the resistance of the Schot tky junction using two gate electrodes formed in isolation from each other near the two Schot tky junctions, or by simultaneously supplying electrons or holes selectively, the pMOSFETs can be changed to nMOSFETs and vice versa. In other words, the device that can change the type is being studied.
  • Non-Patent Document 5 The current level is merely a simulation showing the operation of the logic gate [Non-Patent Document 5]. Therefore, the reconstruction circuit published so far shows that the concept of the research is excellent, but the fundamental limitations of the device itself are as follows. First, in realizing the device through the junction of Si nanowires and NiS2, the precise position control of the junction becomes a fundamental problem in the manufacturing process, and when the two top-gates are implemented, the junction and the self-alignment do not become parasitic resistance. However, the dose component is greatly increased. Second, when switching device types (eg nMOSFET-> pMOSFET), one must always apply voltage to either of the two top-gates, resulting in increased wiring and parasitics.
  • switching device types eg nMOSFET-> pMOSFET
  • the gate insulating film can be applied to a nonvolatile memory function, but increases the E ot (eqmvalent thi ckness of oxide) is significantly reduced by the current driving capacity, it is impossible to further reduction in size channel length.
  • E ot eqmvalent thi ckness of oxide
  • the source or the drain must have a Schott tky junction, so essentially the large low-frequency noise generated by the Schottky junction greatly limits the usability of these devices.
  • the junction electrically formed is a drain junction, and the Schot tky junction is a source junction, so that the f of the current is small, but in the circuit, the position of the source / drain is arbitrarily changed so that of the f current.
  • the first prior art referred to herein is a technique disclosed in the following non-patent documents 2, 4, and 5, and the second prior art is a technique disclosed in the non-patent document 3, and the third prior art is a technique disclosed in the patent document 2.
  • the fourth prior art is a technique disclosed in Patent Document 1.
  • Patent Document 1 US Patent US 8,350,602 B2
  • Non-Patent Document 1 Y. -M. Lin, J. Appenzeller, J. Knoch, and P. AVour i s, "High-Performance Carbon Nanotube Field-Effect Transistor ith Tunable Polarities", IEEE Trns. Natotech. , vol. 4, no. 5, p. 481 ⁇ 488, 2005.
  • Non-Patent Document 2 A. Heingzig, S. Slesazeck, F. Kreu, T. Mikolaj ick, and W. M. Weber, "Reconf igurable Silicon Nanowire Transistors", Nano Lett. vol. 12, pp. 119-124, 2012.
  • Non-Patent Document 3 M. Mongillo, P. Spathis, G. Katsaros, P.
  • Non-Patent Document 4 A. Heingzig, T. Mikolaj ick, J. Trommer, D.
  • Non-Patent Document 5 J. Trommer, A. Heinzig, S. Slesazeck, T.
  • the present invention is reconfigurable based on Si nanowire (NW) devices implemented in a conventional top-down or bottom-down method.
  • NW Si nanowire
  • TMDC ranc it ion metal di chalcogenides
  • phosphorene thin semiconductor films
  • thin semiconductor films such as Si thin films or Metal Oxide semiconductor thin films
  • SWNTs Single-walled carbon nanotubes (unless otherwise mentioned in the present specification, which are referred to as carbon nanotubes) are implemented based on single-walled carbon nanotubes (Singl e Wa l led Carbon Nanotubes; SWNTs).
  • the position of the gate electrode is disposed below to freely adjust the resistance of the Schott tky junction of the device, and to precisely control the position of the gate electrode, the S / D electrode, and the channel part in the device.
  • the conventional reconfigurable device is voltage-coupled with other wires because a voltage must always be applied to one of the two top-gates when changing the device type (e.g. nMOSFET-> pMOSFET).
  • leakage current may occur and the degree of freedom of wiring is greatly reduced.
  • the conventional reconfigurable devices can be applied to non-volatile memory function for the gate insulation film, but E ot (equivalent thi ckness of oxide) is increased by a current drive capability is greatly decreased, and even very small channel length field (L ⁇ lOnoi) becomes difficult to shrink.
  • the present invention constructs a lower gate insulating film including a lower electrode array and a nonvolatile memory function to which voltage is independently applied, and introduces a channel layer based on ID, 2D material, or thin semiconductor thin film thereon. Subsequently, the S / D electrode based on the photo process is implemented. Accordingly, the present invention provides a channel threshold voltage control and a Schott tky barrier between the source and drain electrodes and the channel layer. In addition, the gate control of the channel is implemented through the upper electrode to solve the limitation of the gate insulating layer thickened to include the memory function. Third, even though conventional devices operate with any type of M0SFET, either source or drain amplifiers must have SchoUky junctions.
  • an electrically formed junction becomes a drain junction, and when the SchoUky junction between the source electrode and the channel layer is controlled by the gate electrode, the f of the current can be reduced, but in the circuit, the source / drain positions are arbitrarily selected. This can be a major drawback in terms of current.
  • an upper gate electrode surrounding the junction located near the source and drain is configured. . Therefore, it should be designed and implemented in consideration of the width of the upper gate electrode and the process separation minimum distance or line width (F) between the gate electrode and the electrode.
  • the minimum feasible channel length is increased by that amount.
  • FIG. As shown in (b), the lower electrode for adjusting the threshold voltage of the SchoUky barrier and the channel is disposed under the channel layer, thereby substantially reducing the area required for the independent lower electrode while maintaining the role of the independent lower electrode. Can be. This can lead to an improvement in the density.
  • the conventional reconfigurable device in order to implement a plurality of independent gate electrodes on the channel sublayer, the minimum distance between the gate insulating film and the gate metal is minimized, and the limit of the minimum area that can maintain the adhesive force between the metal and the gate insulating film is achieved.
  • the process difficulty increases in implementing multiple independent gate interconnections. Because of this, the conventional reconfigurable The devices have various process problems, such as a short circuit between the metal lines and a break of the fine independent gate lines.
  • the conventional reconfigurable devices have a problem in that the channel length increases with the number of independent gates.
  • the reconfigurable electronic device uses a process of deposition, etching, and chemical mechanical polishing (chemi cal mechani cal pol i shing), which is highly consistent with the latest semiconductor standard process. It is a structure that can increase process reproducibility and process margin.
  • the reconfigurable electronic device according to the present invention functions to easily control the work function of the lower electrode and minimize the distance between the electrodes by doping a semiconductor material such as Si or realizing the lower electrode with a metal having various work functions. It is a structure that provides an advantage that can maximize the degree of integration.
  • the reconfigurable electronic device preferably further includes a first insulating film formed between the substrate and the lower electrodes to electrically isolate the substrate and the lower electrodes.
  • the lower gate insulating layer may be made of a ferroelectric material, and may be programmed or erased according to voltages applied to the lower electrodes.
  • the lower gate insulating film is formed of at least two insulating films, and adjacent layers are formed of a material having a different energy bandgap or dielectric constant. It is preferable that at least one of the insulating films constituting the insulating film can store electric charges.
  • the substrate is composed of a semiconductor material or a conductive material
  • the electronic device further comprises a second insulating film formed between the substrate and the lower electrode to electrically lower the lower electrodes from the substrate It is preferable to separate.
  • the distance between the two lower electrodes is equal to the distance between the source and drain electrodes, and the opposite edges of the lower electrodes are formed to be aligned with the edges of the source and drain electrodes.
  • the distance between the lower electrodes may be shorter than the distance between the source and drain electrodes, or the distance between the two lower electrodes may be wider than the distance between the source and drain electrodes.
  • the reconfigurable electronic device may further include a buffer layer for improving their interface characteristics between the channel layer and the upper gate insulating layer, or the surface of the channel layer may be chemically or physically treated.
  • the channel layer is a one-dimensional nanomaterial, two-dimensional nanomaterials, metal oxide thin film, silicon It is preferred to consist of one of the thin films.
  • the lower gate insulating layer may be programmed or erased by applying a voltage to the lower electrodes. It is desirable to be determined by the magnitude or time of the voltage applied to the lower electrodes.
  • the voltage applied to the lower electrodes is adjusted so that the lower gate insulating layer positioned below the source electrode and the lower gate insulating layer positioned below the drain electrode are differently programmed or erased.
  • one of the lower gate insulating layer positioned below the source electrode and the lower gate insulating layer positioned below the drain electrode may be programmed and the other may be erased.
  • the same voltage (including 0V) may be applied to the source electrode and the drain electrode in the program or erasure by applying the voltage of the lower electrode.
  • a voltage is applied to the source electrode and the lower electrode positioned below the source electrode to induce holes in the channel layer positioned below the source electrode, and drain and drain electrodes.
  • the voltage applied to the lower electrode positioned below is controlled to induce electrons in the channel layer positioned below the drain electrode to operate as a pn diode or to be applied to the lower electrodes positioned below the source and drain electrodes.
  • the electron layer or the hole layer may be induced in the channel layer to operate as an n-type M0SFET or a p-type M0SFET.
  • the reconfigurable electronic device according to the present invention is characterized by being equipped with a nonvolatile memory function and independently configuring lower electrodes. Due to this feature, the electronic device according to the present invention can be applied to a conventional reconfigurable device. Compared to this, there is a high degree of freedom of wiring for circuit operation, simplification of driving, and even if the applied voltage is cut off from the outside after changing the polarity of the device by utilizing the nonvolatile memory function, the changed polarity can be maintained as it is. And the electrical coupling between wires can be significantly reduced.
  • the lower electrode may be electrically floated, and in this case, parasitics seen in the upper gate electrode or the source or drain electrode. Dose components can be reduced.
  • the reconfigurable electronic device adopts a structure in which an upper gate structure is used when driving a circuit and a lower electrode is used to control device polarity, thereby reducing the polarity (eg, n-type or p-type) of the device.
  • the lower electrode having the nonvolatile memory effect to convert and the upper gate electrode used when operating the actual device as a circuit are characterized by being positioned differently from each other independently. Due to this feature, the reconfigurable electronic device according to the present invention can effectively incorporate a nonvolatile memory function while lowering a driving voltage during circuit operation.
  • the reconfigurable electronic device can freely scale the upper gate insulating film, thereby reducing the operation driving operation and having the advantage of driving the device up to the minimum channel region.
  • the process of silicide formation between Si and transition metal which is recognized as a problem of the conventional reconfigurable element, it is difficult to control the exact position of the junction (for example, the junction of Si and Ni silicide) in the process, so that the generation of parasitic capacitance To regulate the channel part and junction area of the wire. It is difficult to accurately adjust the position of the gate electrode, which makes it difficult to accurately adjust the threshold voltage in the channel.
  • the lower electrode since the lower electrode is first formed, the subsequent insulating layer and the channel layer are formed, and then the source and drain electrodes are aligned based on the lower electrode, precise position control is possible, and thus the area of the device is improved. You can optimize performance as well as minimize it.
  • the reconfigurable electronic device places the lower electrode serving as an independent gate under the source electrode and the drain electrode, thereby reducing the length of the device and improving the degree of integration.
  • a conventional reconfigurable device there may be a limit in increasing the number or implementing a fine process by placing the independent gate electrodes on the upper portion, and thus, the number of independent gate electrodes is usually three or less.
  • the conventional reconfigurable device lacks a function of locally adjusting the threshold voltage of the channel layer, and thus, locally doping is limited. Therefore, the conventional reconfigurable device is limited in its ability to implement n-p-n or p-n-p junctions through local electrical doping in a channel, and as a result, there is a difficulty in implementing various multifunctional devices.
  • the reconfigurable electronic device according to the present invention has an advantage of implementing a plurality of lower electrodes under the channel layer. There is a lower gate insulating layer capable of storing charge between each lower electrode and the channel layer. Due to these advantages, the reconfigurable electronic device according to the present invention enables local electrical doping as mentioned above, resulting in a change in device type (ie pn ⁇ np diode, n type p type), channel length modulation, diode Various multifunctional devices such as logic can be realized. In addition, the reconfigurable electronic device according to the present invention may improve the variety of functions, the degree of freedom in driving the device, and the degree of integration when the reconfigurable circuit is implemented.
  • FIG. 10 is a cross-sectional view of each device described to compare the degree of integration of a reconfigurable device according to the prior art and a reconfigurable electronic device according to the present invention. 10, it can be easily seen that the reconfigurable electronic device according to the present invention has a very high degree of integration as compared to conventional devices.
  • the reconfigurable electronic device according to the present invention is characterized in that the parasitic resistance component, power consumption, and the wiring diversity required for implementing the reconfigurable circuit operation, the functional diversity of the multifunctional device, the process alignment, and the adjustment of the Schot tky contact resistance.
  • the performance of the reconfigurable electronic device according to the present invention has a great advantage in terms of all characteristics compared to other conventional technologies.
  • FIG. 1A is a perspective view of a reconfigurable electronic device according to a first embodiment of the present invention
  • FIG. 1B is a cross-sectional view taken along the direction A-B of FIG.
  • FIG. 2 is a perspective view and a cross-sectional view of a reconfigurable electronic device according to a second embodiment of the present invention.
  • FIG 3 is a perspective view and a cross-sectional view showing the reconfigurable electronic device according to the third embodiment of the present invention.
  • FIG. 4 is a perspective view and a cross-sectional view of a reconfigurable electronic device according to a fourth embodiment of the present invention.
  • FIG. 5A is a perspective view illustrating a reconfigurable electronic device according to a fifth embodiment of the present invention
  • FIG. 5B is a perspective view illustrating a reconfigurable electronic device according to a sixth embodiment of the present invention. to be.
  • FIG. 6 is a cross-sectional view illustrating the expandability of the lower electrode in the reconfigurable device according to the fifth to eighth embodiments of the present invention.
  • FIG. 7 (a) and 7 (b) illustrate the overlapping according to the position of the lower electrodes GK20 and GN 22 in the reconfigurable elements according to the present invention. It is a cross section.
  • FIG. 8 is a schematic view showing the configuration of a lower gate insulating film causing a nonvolatile memory function in the reconfigurable devices according to the present invention.
  • 9 is a representative perspective view and a cross-sectional view showing the configuration of the channel layer in the reconfigurable device according to the present invention.
  • FIG. 10 is a cross-sectional view of each device described to compare the degree of integration of a reconfigurable device according to the prior art and a reconfigurable electronic device according to the present invention.
  • FIG. 11 is a chart in which the characteristics of each item are compared and analyzed for reconfigurable electronic devices according to the related art and reconfigurable electronic devices according to the present invention. It is a schematic diagram which shows the implementation form of the deformable element in the reconfigurable electronic element which concerns on this invention.
  • FIGS. 13A and 13B are perspective views illustrating a conventional representative reconfigurable device and a reconfigurable electronic device according to the present invention, respectively.
  • FIG. 1A is a perspective view of a reconfigurable electronic device according to a first embodiment of the present invention
  • FIG. 1B is a cross-sectional view taken along the direction A-B of FIG.
  • the reconfigurable electronic device is a lower electrode-based deformable device having a nonvolatile memory function, and includes a substrate 1, lower electrodes 20 and 22, and a first insulating film ( 10), an inter-electrode insulating film 11, a lower gate insulating film 30, a channel layer 40, a source electrode 50, a drain electrode 51, an upper gate insulating film 60, an upper gate electrode 80 do.
  • the upper gate insulating layer 60 is configured to overlap some or all of the source and drain electrodes when they are formed first.
  • the reconfigurable electronic device according to the present embodiment is characterized in that it has two lower electrodes, and the upper gate electrode 80 is configured to be aligned with the source electrode and the drain electrode 50, 51.
  • each component of the reconfigurable electronic device according to the present embodiment will be described in detail.
  • the substrate 1 may be made of an insulating material or a semiconductor material such as Si.
  • the lower electrodes 20 and 22 are formed on the substrate, and are formed of two lower electrodes spaced apart by a predetermined distance by the inter-electrode insulating film 11.
  • the lower electrodes are also electrically connected to the substrate.
  • the electronic device further comprises a first insulating film 10 formed between the substrate and the lower electrode to electrically separate the lower electrodes from the mold. desirable.
  • an insulating film is deposited on a substrate (1) made of Si semiconductor or the like, or a thermal oxide film is formed on the substrate through oxi dat ion, and then doped silicon on the insulating film.
  • a metal material and patterning by a photolithography process it is possible to form electrically separated bottom electrodes.
  • a metal selected in consideration of process convenience and electrical operation characteristics of the device on a photosensitive photosensitive film patterned by a photolithography process in addition to a method of forming by a deposition and a subsequent etching process. After the deposition, it may be configured through a lift off process.
  • the lower gate insulating layer 30 is formed on the lower electrodes and the inter-electrode insulating layer 11, and is configured to be programmable or erased according to the polarity of the voltage applied to the lower electrodes.
  • the lower gate insulating film 30 may be composed of a single ferroelectric film or at least two insulating films.
  • the lower gate insulating film is formed of two or more insulating films
  • adjacent layers may be formed with different energy band gaps or dielectric constants, and at least one of insulating films constituting the lower gate insulating film may be It is preferable to constitute a charge storage layer capable of storing charges.
  • FIG. 8 is a schematic view illustrating various configurations of a lower gate insulating layer inducing a nonvolatile memory function in reconfigurable devices according to the present invention.
  • the lower gate insulating layer is nonvolatile using a polarization phenomenon of a single thin film layer composed of an organic material (eg, PVDF) or an inorganic material (eg, PZT) based ferroelectric material, as shown in FIG. 8A.
  • Memory functions can be inherent.
  • the lower electrode is made of a semiconductor material.
  • the lower gate insulating film may form a blocking insulating film based on a thermal oxide film or an insulating film having various dielectric constants deposited thereon.
  • various high dielectric insulating films may be used as the blocking insulating film.
  • the lower gate insulating layer may have a blocking insulating layer formed on the lower electrode, and a charge storage layer may be formed on the formed blocking insulating layer to have a two-layer structure.
  • the lower gate insulating film may be implemented in a three-layer structure by forming a tunneling insulating film on the two-layer structure. The tunneling insulating layer allows electrons or holes to be injected into the charge storage layer by tunneling between the lower gate insulating layer and the channel layer.
  • the above-described three-layer structure may be composed of a tunneling insulating film, a charge storage layer, and a blocking insulating film (for example, oxide / silicon nitride / oxide, oide / Hf0 2 / Al 2 O 3, etc.).
  • a tunneling insulating film for example, oxide / silicon nitride / oxide, oide / Hf0 2 / Al 2 O 3, etc.
  • the channel layer 40 is formed on the lower gate insulating film, and includes one of a one-dimensional nanomaterial, a two-dimensional nanomaterial, a metal oxide thin film, a silicon thin film, a mv group compound semiconductor thin film, and a ⁇ - ⁇ group compound semiconductor thin film.
  • the one-dimensional nanomaterials include Si nanowires, carbon nanotubes, graphene nanoribbons (NR), the two-dimensional nanomaterials include TMDC, phospherene, etc., and the metal oxide thin film is Indium-gallium-zinc-oxide.
  • the silicon thin film may include a thin film of a single crystal, polycrystalline, or amorphous based silicon material.
  • the m-v compound semiconductor thin film and the ⁇ - ⁇ compound semiconductor thin film may include GaAs, InAs, or the like.
  • FIG. 9 is a representative perspective view and a cross-sectional view showing the configuration of the channel layer in the reconfigurable device according to the present invention.
  • Si nanowires, carbon nanotubes, and graphene nanoribbon may be utilized by using a bottom-up or top-down process technology.
  • FIG. 9A illustrates an example of a reconfigurable device to which a semiconducting carbon nanotubes (s-SWNTs), which is a representative 1D channel layer, is applied as an example for implementing a channel layer.
  • s-SWNTs semiconducting carbon nanotubes
  • FIG. 9 (b) is an example of introducing a single layer of graphene, a 2D material, into a channel layer using nanopatterning technology or using another method of implementing graphene nanoribbons.
  • FIG. 9C illustrates a device in which 2D material is applied as a channel layer, and the 2D channel layer may be implemented using a material having an energy band gap.
  • it may be TMDC (trans it ionmetal di chacogenides; MoS 2 , WSe 2 , WS 2 ), phosphorene, or the like.
  • Some or all of the source electrode 50 and the drain electrode 51 are formed on the channel layer.
  • the edges of the source electrode and the drain electrode may be formed to be aligned with the opposite edges of the lower electrodes so as to be aligned with the lower electrodes, or some or all of the source electrode and the drain electrode may be aligned with the lower electrodes. Or formed with of fest.
  • the upper gate insulating layer 60 is formed on the channel layer and overlaps some or all of the source electrode and the drain electrode.
  • the upper gate insulating layer 60 on the channel layer to prevent deterioration of device characteristics due to an interfacial charge tram that may exist between the 1D or 2D nanomaterial-based semiconductor layer constituting the channel layer and the upper gate insulating layer.
  • the chemical or physical surface treatment process such as 0 2 , N 2 , Ar plasma treatment on the upper surface of the channel layer, it is preferable to form the upper gate insulating film on the channel layer.
  • the upper gate insulating layer 60 may be formed of a single layer composed of a conventional high dielectric material or two or more layers having different dielectric constants for low voltage driving. Formed by the upper gate insulating film is then formed in consideration of the factors that may affect the threshold voltage of the i-channel layer, select the type of the metal, deposited without the source electrode and the drain electrode and overlapping so as to their minimum over the parasitic capacitance ol It is desirable to. In some cases, the upper gate insulating layer may be interposed to partially overlap the source and drain electrodes as well as the channel charge.
  • the transparent or opaque metal material may be implemented by various processes, for example, by using an electron beam evaporat ion and a li ft of f process, or after forming a metal using a vacuum evaporation or sputtering process. It can be implemented through the existing patterning process.
  • the upper gate electrode is used as an application terminal of the driving gate voltage to control the main operation of the circuit, the lower electrode independently configured to adjust the potential barrier or threshold voltage of Schot tky barr i er, or It can be used as a main gate electrode device for determining the operation of unit devices and circuits.
  • the upper gate electrode 80 is formed on the upper gate insulating film.
  • the upper gate electrode 80 may be formed with a gate insulating layer interposed between the source electrode 50 and the drain electrode 51 facing each other.
  • FIG. 2 is a perspective view and a cross-sectional view of a reconfigurable electronic device according to a second embodiment of the present invention.
  • the reconfigurable electronic device is a lower electrode array-based deformable device having a nonvolatile memory function.
  • the substrate 1, the lower electrodes 20 and 22, and the first insulating film are the same as the first embodiment. 10, the inter-electrode insulating film 11, the lower gate insulating film 30, the channel layer 40, the source electrode 50, the drain electrode 51, the upper gate insulating film 60, the upper gate electrode 80 Equipped.
  • the reconfigurable electronic device is characterized by having two lower electrodes.
  • the upper gate insulating layer 60 is configured to overlap a part or the entire area of the source electrode and the drain electrode.
  • the upper gate electrode 80 is formed on the upper gate insulating film, so that the upper gate electrode 80 is overlapped with a portion of the source electrode and the drain electrode 50, 51 via the upper gate insulating film. do.
  • the components except for the upper gate insulating film 60 and the upper gate electrode 80 of the reconfigurable electronic device according to this embodiment have the same configuration as those of the first embodiment. ⁇ Crab 3 Example>
  • FIG. 3 is a perspective view and a cross-sectional view of a reconfigurable electronic device according to a third embodiment of the present invention.
  • the reconfigurable electronic device is a lower electrode array-based deformable device having a nonvolatile memory function, and includes a substrate 1, lower electrodes 20 and 22, a first insulating film 10, and an electrode between electrodes.
  • the reconfigurable electronic device according to the present embodiment is characterized by having two lower electrode structures 20 and 22.
  • the reconfigurable electronic device according to the present exemplary embodiment includes a buffer layer 70 between the channel layer 40 and the upper gate insulating layer 60, and the upper gate electrode 80 includes the source electrode 50 and the drain electrode. It is characterized in that it is aligned with (51) without overlap.
  • the components except for the buffer layer 70 have the same configuration as those of the first embodiment.
  • the buffer layer 70 is formed between the channel layer and the upper gate insulating film in order to improve the interface characteristics of the channel layer 40 and the upper gate insulating film 60.
  • the buffer layer may be composed of an organic material or an inorganic material (e.g., spin on glass as SOG, epoxy-based negative photoresi st), Octadecyl tr i chloros il ane (OTS), and octadecanethi ol (0DT). have.
  • the upper gate insulating layer 60 on the channel layer prevents deterioration of device characteristics due to an interface charge trap that may exist between the 1D or 2D nanomaterial-based semiconductor layer constituting the channel layer and the upper gate insulating layer.
  • the upper gate insulating layer 60 may be implemented using atomi c layer depos it on (ALD) or a sputtering process on the buffer layer, for example, a high dielectric material having a high dielectric constant, which is conventional for low voltage driving.
  • FIG. 4 is a perspective view and a cross-sectional view of a reconfigurable electronic device according to a fourth embodiment of the present invention.
  • the reconfigurable electronic device is a lower electrode array-based deformable device having a nonvolatile memory function, and includes a substrate 1, lower electrodes 20 and 22, a first insulating film 10, and an electrode between electrodes.
  • the reconfigurable electronic device according to the present embodiment is characterized by having two lower electrodes 20 and 22.
  • the reconfigurable electronic device according to the present embodiment is characterized by including a buffer layer 70 between the channel layer 40 and the upper gate insulating film 60.
  • the upper gate insulating layer 60 is configured to overlap some regions of the source electrode and the drain electrode.
  • the upper gate electrode 80 is formed on the upper gate insulating film so that the upper gate electrode 80 is upper. It is characterized in that it is comprised so that it may overlap with the some area
  • the components except for the buffer layer 70 have the same configuration as those of the second embodiment, and the buffer layer 70 has the same configuration as the buffer layer of the third embodiment.
  • FIG. 5A is a perspective view showing a reconfigurable electronic device according to a fifth embodiment of the present invention
  • FIG. 5B is a perspective view showing a reconfigurable electronic device according to a sixth embodiment of the present invention. to be.
  • the reconfigurable electronic device according to the above 15 to 8 embodiments is characterized in that the lower electrodes of the electronic devices according to the first to fourth embodiments are configured in the form of a lower electrode array.
  • Reconfigurable electronic devices unlike the first to fourth embodiments, have a lower electrode array composed of at least three lower electrodes 20, 21, 22. It is done. That is, the reconfigurable electronic devices according to the present exemplary embodiments include a lower electrode array having at least three lower electrodes, a source electrode disposed on an upper portion of the lower electrode positioned at one end of the lower electrode array, and a lower portion positioned at the other end. A drain electrode is disposed above the electrode.
  • the remaining lower electrodes except for the lower electrodes respectively positioned at both ends of the lower electrode array may adjust the threshold voltage of the channel. To be used.
  • FIG. 6 is a cross-sectional view illustrating the expandability of the lower electrode array in the reconfigurable device according to the fifth to eighth embodiments.
  • an electrode located below the source electrode 50 may be referred to as GK20 in order to sequentially include G2 (21), G3 (23), G4 (24), G5 (25), and the like.
  • the structure of the device expandable to the GN 22 is shown. At this time, the separation distance between independent lower electrodes is defined as Ls, and Ls is fairly spaced apart.
  • FIG. 7 (a) and 7 (b) illustrate the overlapping according to the position of the lower electrodes GK20 and GN 22 in the reconfigurable elements according to the present invention. It is a cross section.
  • the positions of the lower electrodes G1 and GN overlap the source electrode and the drain electrode, and also overlap the channel layer.
  • the point A is defined as the right edge position in the configuration of Gl 20, the lower electrode under the source electrode, and the point B is defined as the right edge position of the source electrode 50.
  • the lower electrode GK20 is formed to extend further to the right than the source electrode, whereby A is formed longer than B in the direction so that AB> 0.
  • the upper gate electrode The parasitic capacitance component between the source and drain electrodes and the gate electrode may be enjoyed by partially overlapping the lower electrode G1 without overlapping the source electrode in an alignment viewpoint.
  • the left edge of the lower electrode GN extends to the left more than the left edge of the drain electrode.
  • FIG. 7B is a cross-sectional view illustrating the overlap depending on the positions of the GU20 and the GN 22 in the reconfigurable elements (including the types 1, 2, 3, 4, 5, and 6).
  • the source electrode is formed to extend to the right side than the lower electrode G1, so that the source electrode is formed longer than A in the + direction, whereby A-B ⁇ 0.
  • the lower electrode does not affect the channel layer formed by overlapping the upper gate electrode and the upper gate insulating layer. That is, the influence of program and eraser operation of the lower electrode affects only the channel layer under the source electrode in terms of alignment.
  • the left edge of the drain electrode extends to the left more than the left edge of the lower electrode GN.
  • the description about the source vicinity can be applied as it is.
  • the distance between two lower electrodes respectively formed under the source electrode and the drain electrode is shorter than the distance between the source electrode and the drain electrode to reduce the effective channel length.
  • the effective channel length can be increased by forming longer than the distance between the source electrode and the drain electrode. Therefore, the distance between the two lower electrodes may be set according to the effective channel length of the electronic device.
  • the reconfigurable electronic device having the above-described structure has two or more independently configured lower electrode structures based on a metal or a heavily doped Si material, and between the two lower electrodes formed below each other.
  • some photos can be overlapped Form based on alignment by process.
  • a lower gate insulating film is formed on the lower electrode to induce a nonvolatile memory function.
  • the lower gate insulating film may be formed of a single layer based on an organic material or an inorganic material, or may be formed of two or more insulating films. When the lower gate insulating layer is formed of two or more insulating layers, adjacent charges may have different energy band gaps and dielectric constants.
  • One-dimensional (1 dimens ional; ID) structured channel material Si, ⁇ -VNW, SWNTs,-graphene nanor ibbon, etc.
  • 2D two-dimensional channel material formed on the lower gate insulating layer using a top-down or bottom-up process platform.
  • a channel layer is formed by placing a semiconductor material with an energy bandgap (TMDC: ⁇ 3 ⁇ 4, WSe 2 , W3 ⁇ 4, phosphor ene, etc.).
  • TMDC energy bandgap
  • TMDC ⁇ 3 ⁇ 4, WSe 2 , W3 ⁇ 4, phosphor ene, etc.
  • a metal oxide thin film or a semiconductor thin film can be used as the channel layer.
  • a source / drain electrode is formed on the channel layer by aligning the lower electrode with a photographic process, wherein the source electrode and the drain electrode are made of a metal selected in consideration of the material constituting the channel layer and the consistency of the work function. It is preferable.
  • An upper gate insulating layer is formed on the formed channel layer and the source / drain electrode structure to be compatible with the upper channel material.
  • An upper gate insulating layer having a high dielectric constant eg, Hf0 2 , AI 2 O 3 , ⁇ 0 2
  • Zr0 2 1 SiN x, etc. is formed on the channel layer.
  • An upper gate electrode is formed on the formed upper gate insulating layer.
  • the upper gate electrode is made of a transparent or opaque organic and inorganic material having high work function, and is formed in consideration of the overlap between the source electrode and the drain electrode.
  • the upper gate electrode may be embodied in a structure that is completely aligned with a channel layer that is a distance between the source electrode and the drain electrode in consideration of parasitic components and device operating environments, or includes both the channel layer region and the source electrode. It can be implemented in a structure that can overlap a portion of the drain electrode at the same time.
  • the reconfigurable element is a source / drain electrode through a voltage applied independently to the lower electrode gate array capable of applying a voltage independently
  • the following Schot tky barrier is adjusted to implement the characteristics of the reconfigurable device.
  • the potential barrier is formed by injecting charge into the charge storage layer of the lower gate insulating film having the nonvolatile memory function through a program / eraser operation applied to the source electrode / drain electrode and the selected lower electrode. Adjust
  • a lower electrode capable of applying an independent voltage is provided, and a program or eraser is performed on the charge storage layer to enable the nonvolatile memory function, thereby controlling the Schot tky potential barrier.
  • the potential barrier is adjusted, so that the wiring can be effectively implemented in driving the reconfigurable element and the circuit.
  • the conventional reconfigurable device disclosed in Patent Document 1 has a nonvolatile memory function based on an upper gate electrode structure, and controls the electrical operation of the device by using the same gate insulating film.
  • the charge storage layer is in the upper gate insulating film, and electrons or holes are injected therein, and these charges may be undesired or come out undesirably under normal operating conditions, resulting in a problem of reliability.
  • a lower electrode is prepared for a program and an eraser, and under normal operating conditions, the upper gate is in charge to solve the above problem.
  • Patent Document 1 has a common feature of utilizing a nonvolatile memory function, the density of the structure according to the present invention is 5F, and the degree of integration of the structure according to Patent Document 1 is 17.5 F, so that the degree of integration is significantly lower than that of the present invention. There are disadvantages.
  • the first to fourth prior arts do not have a non-volatile function, and if this function is added, a thick gate insulating film is required for the operation of the memory device, and thus, the operation of the microchannel cannot be realized.
  • the first to fourth prior arts are significantly inferior to the present invention (5F) in that the length of the device is 10F to 12F.
  • the present invention since the upper gate insulating film can be made thin, there is no problem in miniaturization of the device.
  • the reconfigurable electronic device uses a lower electrode structure as a Sdiot tky barrier for the contact area between the channel layer and the source electrode / drain electrode.
  • the upper gate electrode mainly positioned at the upper side is mainly used, and in some cases, the lower electrode positioned at the lower side of the channel may be adjusted by applying a voltage.
  • FIG. 12 is a schematic diagram showing an implementation of a deformable device of a reconfigurable electronic device according to the present invention.
  • the reconfigurable electronic device may electrically implement a p-n diode.
  • a positive program voltage is applied to the lower electrode positioned below the source electrode, and electrons are injected into the lower gate insulating layer having the charge storage layer to electrically hole the channel layer positioned below the source electrode.
  • Organic is applied to the lower electrode array positioned below and around the drain electrode to inject holes into the lower gate insulating film having the charge storage layer, thereby channel layers positioned below and around the drain electrode. Induces electrons in In this way, the p-n diode can be realized by electrically inducing the p region and the n region to the channel layer.
  • the reconfigurable electronic device according to the present invention may electrically implement an np diode.
  • the method for implementing this is similar to the description of FIG. 12A, but has the following differences.
  • the bottom electrode below the source electrode in the above description By injecting holes into the charge storage layer and injecting electrons into the charge storage layer using the drain electrode and the lower electrode below, an electrical np diode can be realized.
  • the reconfigurable electronic device according to the present invention may be driven by an n-type transistor having an ideal ohmi c characteristic as shown in FIG. 12 (b), or ideal ohmi as shown in FIG. 12 (c). It can be driven by a p-type transistor having a c characteristic.
  • holes are injected into the lower gate insulating layer having the charge storage layer located under the source electrode and the drain electrode by using the lower electrode, and between the source and drain electrodes and the channel layer. It is possible to drive the n-type M0SFET by lowering the potential barrier of and allowing the organic layer to function like the doped source / drain regions of the existing n-type M0SFET. In this case, the junction between the source drain electrode and the channel layer may be controlled to be close to the Ohmi c junction.
  • the reconfigurable electronic device according to the present invention is p It can be driven by a type transistor.
  • the reconfigurable electronic device has an n-type transistor and p having ohmi c contact characteristics through externally applied program / erase voltage control.
  • Type transistors can be implemented independently in the same device structure without additional process or structural change.
  • Conventional reconfigurable devices can be freely changed into transistors and diodes in the same device structure. Due to the limitation of the number of independent gate electrodes required for the type change, it is difficult to implement locally electrical doping in the form of n-pn or pnp in the nano-sized channel due to the characteristics of the device structure. There is this.
  • the reconfigurable electronic device according to the present invention can be locally doped by using a structure based on a plurality of independent lower electrode arrays as shown in FIG.
  • the reconfigurable electronic device according to the present invention may have a lower gate insulating layer and a lower gate insulating layer having a single layer or multilayer based memory characteristics as shown in FIG. 8.
  • the electrodes can be used to implement nonvolatile memory functions. Therefore, the characteristics distinguishing the existing technology and the present invention are summarized through the comparison table of FIG. 11.
  • FIG. 11 is a chart in which the characteristics of each item are compared and analyzed with respect to the conventional reconfigurable electronic devices and the reconfigurable electronic devices according to the present invention.
  • the crab 1 is disclosed in Nam LAB (Germany), and the reconfigurable device is implemented as shown in FIG. 13 (a).
  • the technique forms a junction of Si nanowires with Ni silicides, resulting in band alignment near the mid-gap within the band gap of the Si nanowires, resulting in almost similar size in terms of electrons and holes. It is a device having a potential barrier.
  • two independent upper electrodes positioned immediately adjacent to the source electrode and the drain electrode are implemented.
  • the two upper electrodes are formed over the Si and Ni silicide junctions.
  • Two independent upper electrodes formed around the source and drain regions independently control the type (n-type or p-type) of the device and implement a reconfigurable device.
  • the device is nonvolatile.
  • the number of independent nodes required to implement a reconfigurable device should be at least four, and the simple device type (n-type or p-type) can be changed, but there are limitations in various reconfigurable functions such as channel length modulation. Schot tky barriers can be controlled and bonded to bottom-up and top-down processes. However, fair matching with ID and 2D materials is limited.
  • the second prior art is a multifunction based reconfigurable device proposed for Joseph Four ier University in France, employing a device structure similar to the concept of the first prior art, the difference is only Schottky barrier
  • the two upper independent gate electrodes that can control the structure has a separate upper independent gate electrode for adjusting the channel characteristics of the device in the center of the channel.
  • This technology is also a non-volatile memory device technology is applied, the parasitic capacitance is the same as the first conventional technology, the minimum implementation area of the device is as large as 20F2 (assuming 2F device width).
  • the third prior art is a device presented by Swiss ijk Polytechnic, which combines two independent upper electrodes for adjusting the Schot tky barrier in the first prior art, and also, as in the second prior art, It is an element structure having a gate electrode. Therefore, the minimum area required for device implementation is 20F2, as in the conventional art. Since the two independent upper electrodes are tied together, the structure of the reconfigurable circuit cannot be used while exchanging the source and the drain. As a result, there are disadvantages in that there is a variety of reconfigurable circuit implementations and limitations in driving methods. It is described in Patent Document 2 that the prior art also does not have a nonvolatile memory function and is only implemented in a top-down process to implement a channel layer.
  • the prior art is Seoul National University Prof.
  • a technique introduced by the Hong Group a method of implementing a reconfigurable device by introducing two channel layers and a nonvolatile memory function is proposed.
  • the parasitic capacitance is large due to the use of two channel layers ;
  • the minimum implementation area is about 35F2.
  • There is no function to change the shape of the device (n-type or p-type) in the same channel and the implementation of the reconfigurable device also has a limitation in implementing multi-function because it uses a device having two independent channels.
  • the gate electrode is formed to cover the entire region of the channel layer, the Schott tky barrier cannot be changed locally between the channel layer, the source and the drain electrode.
  • the reconfigurable device can be implemented, it is a device structure that has great weakness in terms of functionality, density, and dynamic power consumption.
  • the present invention is the first place where a nonvolatile memory structure is used to implement a reconfigurable device.
  • a nonvolatile memory structure is used to implement a reconfigurable device.
  • the reconfigurable device disclosed in Patent Document 1 can have a characteristic for nonvolatile memory, it is not a single channel structure due to the device structure, and thus the parasitic resistance and capacity of the device are not only large, but also the integration is greatly reduced. Can be.
  • the integration degree is very low, as shown in Figure 11, the unit device area of 35F2.
  • the minimum device length occupied by the unit reconfigurable device becomes 4F, considering the separation between one upper gate electrode, three lower electrodes, and a lower electrode in the process (see FIG. 10 (d): 0.5F).
  • the multifunction based reconfigurable device according to the prior art 2 has a device length of 11F. Assuming the same device width, this results in an approximately double density increase.
  • the performance of the reconfigurable electronic device according to the present invention has a great advantage in terms of various characteristics in terms of various device characteristics including ID and matching with 2D materials. Shows.
  • the reconfigurable electronic device according to the present invention may show various deformable device characteristics as shown in FIG. 12, and are summarized as follows.
  • the contact resistance between the source and drain electrodes and the channel layer is controlled through the program / erase characteristics of the lower electrodes under the source and drain electrodes, and the electrical n-type and p-type regions are implemented to implement the device.
  • the lower electrode positioned below the channel layer can be used to adjust the device threshold voltage in the channel, and devices of different threshold voltages, such as devices of the same type, can be implemented in a circuit.
  • the structure can be operated as a Schot tky diode by modulating the potential barrier between the channel layer and the source and drain electrodes by adjusting the program / erase characteristics using the bottom electrodes located below the source and drain electrodes.
  • the potential barrier of the diode can be varied through the program and eraser.
  • the device according to the present invention can be widely used in the semiconductor field.

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Abstract

La présente invention, en ce qui concerne la réalisation d'un dispositif reconfigurable, a permis d'augmenter significativement le degré d'intégration par rapport à des dispositifs existants reconfigurables et possédant les mêmes fonctions du fait de la configuration d'une porte supérieure et d'une porte inférieure distinctes, et permet de réduire des composantes parasites dynamiques lors d'opérations de circuits reconfigurables et de réduire la complexité de câblage, sur la base d'un réseau d'électrodes inférieures distinct à l'intérieur du dispositif et possédant une fonction de mémoire non volatile intégrée, de façon à finalement constituer une configuration qui permet une baisse de consommation d'énergie. En outre, l'invention concerne un dispositif qui présente une supériorité par rapport à des dispositifs existants reconfigurables en termes de diverses caractéristiques telles qu'une diversité de fonctions dans un dispositif multifonctionnel, des tolérances d'alignement au cours de processus de fabrication, une capacité de formation de dopage électronique minimale à l'intérieur de canaux, une compatibilité avec des procédés de traitement de fabrication amont et aval et une compatibilité avec des matériaux 1D et 2D.
PCT/KR2015/003420 2014-04-22 2015-04-06 Dispositif électronique reconfigurable et son procédé d'exploitation WO2015163603A1 (fr)

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KR102577815B1 (ko) * 2022-04-15 2023-09-11 연세대학교 산학협력단 재구성 가능한 트랜지스터
KR102666169B1 (ko) * 2022-07-25 2024-05-13 연세대학교 산학협력단 재구성 가능한 양극성 트랜지스터

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