WO2015158264A1 - 控制内存芯片的方法、芯片控制器和内存控制器 - Google Patents

控制内存芯片的方法、芯片控制器和内存控制器 Download PDF

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Publication number
WO2015158264A1
WO2015158264A1 PCT/CN2015/076668 CN2015076668W WO2015158264A1 WO 2015158264 A1 WO2015158264 A1 WO 2015158264A1 CN 2015076668 W CN2015076668 W CN 2015076668W WO 2015158264 A1 WO2015158264 A1 WO 2015158264A1
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Prior art keywords
chip
signal
individual
chip select
information
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PCT/CN2015/076668
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English (en)
French (fr)
Inventor
肖世海
杨伟
赵俊峰
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华为技术有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Definitions

  • Embodiments of the present invention relate to the field of computers, and in particular, to a method, a chip controller, and a memory controller for controlling a memory chip.
  • the computer architecture has a memory system, and the most commonly used storage medium for a memory system is a Dynamic Random Access Memory (DRAM).
  • Computer memory is often in the form of Dual Inline Memory Modules (DIMMs). Registered DIMMs (RDIMMs) and Load-Reduced DIMMs (LRDIMMs) are commonly used. DIMM form.
  • the RDIMM and LRDIMM receive the address signal, the chip select signal, and the clock enable signal from the memory controller, and are registered by the register module and then output to the DRAM chips on the DIMM.
  • a typical RDIMM works as follows: Multiple narrow-width DRAM chips form a wide-width DIMM.
  • RDIMM has a register function circuit or chip on the DIMM strip. The circuit or chip registers the chip select signal, clock enable signal and address signal sent by the memory controller to the DRAM, and is re-driven and output to each DRAM chip. .
  • Each DRAM chip of one RDIMM memory operates in synchronization.
  • DRAM system similar to a conventional RDIMM in the prior art.
  • DIMM register between the memory controller and the DRAM chip of the DRAM system, and the register is used to temporarily store the chip select signal, the clock enable signal and the address signal sent by the memory controller to the DIMM, and re-drive the signals and send them to DRAM chip.
  • the DRAM system also has a decoder for decoding the chip select signal and clock enable signal issued by the memory controller for a RANK in the entire DIMM into a chip select and clock enable signal for each DRAM chip.
  • the DRAM system transmits the individual chip select information corresponding to the DRAM command in the previous cycle of the current DRAM command, the chip select signal and the separate After the chip select information is decoded, it becomes a plurality of independent chip select signals, and respectively controls a plurality of corresponding DRAM chips in the DIMM.
  • each DRAM command of the memory controller needs to send separate chip select information in the previous cycle of the DRAM command, which seriously occupies the transmission bandwidth of the DRAM system.
  • Embodiments of the present invention provide a method of controlling a memory chip, a chip controller, and a memory controller, which can effectively reduce the occupation of a transmission bandwidth of a DRAM system.
  • a chip controller including: a registration module for registering individual chip selection information; and a control module, configured to: receive a first chip selection signal output by the memory controller; and according to the first chip selection signal and The individual chip select information registered by the output register module generates a plurality of individual chip select signals, wherein the plurality of individual chip select signals are in one-to-one correspondence with the plurality of memory chips, and the first chip select signal is used to indicate that multiple memory chips are selected, and the individual chip selects are selected.
  • the information is used to indicate that at least one of the plurality of memory chips is separately selected; and the plurality of individual chip chips are respectively outputted to the plurality of memory chips, so that at least one of the plurality of memory chips outputs a control command according to the memory controller.
  • the signal performs an operation corresponding to the control command signal.
  • the registering module is further configured to: generate, by the control module, a plurality of individual chip select signals according to the first chip select signal and the individual chip select information registered by the register module Previously, receiving a first address signal output by the memory controller, the first address signal carries address information of the individual chip select information and the individual chip select information, and registers the individual chip select information according to the first address signal.
  • the first address signal further carries the chip selection policy information
  • the chip selection policy information is registered in the registration module and is separate
  • the chip selection information is used to indicate whether the individual chip selection information is valid for the control command signal
  • the control module is further configured to receive the control command signal output by the memory controller, where the control module is used to indicate the individual in the chip selection policy information.
  • control module is further configured to: in the chip select policy information, indicate that the individual chip select information is for the control command signal When invalid, generate multiple individual chip selection messages according to the first chip selection signal and the predetermined chip selection information.
  • the predetermined chip selection information indicates that the generated plurality of individual chip select signals select a corresponding plurality of memory chips.
  • the registration module is further configured to receive the second separate output of the memory controller The chip select indication signal and the second chip select signal, wherein the second individual chip select indication signal and the second chip select signal jointly instruct the registration module to register the individual chip select information according to the first address signal.
  • control module is further configured to receive the memory controller output a first individual chip select indication signal, wherein the first individual chip select indication signal and the first chip select signal joint indication control module generate a plurality of individual chip select signals according to the first chip select signal and the individual chip select information registered in the register module .
  • control module is further configured to receive the memory controller output a first clock enable signal, generating a plurality of individual clock enable signals according to the first clock enable signal and the individual clock enable information registered in the register module, and outputting a plurality of individual clock enable signals to the plurality of memory chips, wherein, the plurality of individual clock enable signals are in one-to-one correspondence with the plurality of memory chips, the first clock enable signal is used for controlling clock signals of the plurality of memory chips, and the plurality of individual clock enable signals are respectively used for separately controlling the plurality of memories A clock signal of at least one chip in the chip.
  • the register module is further configured to register in the chip controller according to the first clock enable signal and the chip controller Before the individual clock enable information generates the plurality of individual clock enable signals, receiving the second address signal output by the memory controller, and registering the individual clock enable information according to the second address signal, wherein the address signal carries the individual clock enable information and The address information of the individual clock enable information, and the second address signal carries the address information of the individual clock enable information and the individual clock enable information.
  • the second address signal further carries clock enable policy information
  • the clock enable policy information is registered in the chip controller.
  • the clock enable policy information is used to indicate whether the individual clock enable information is valid for the control command signal
  • the control module is further configured to receive the control command signal output by the memory controller, and the control module is used to When the clock enable policy information indicates that the individual clock enable information is valid, a plurality of individual clock enable signals are generated according to the first clock enable signal and the individual clock enable information.
  • control module is further configured to: when the clock enable policy information indicates that the individual clock enable information is invalid for the control command signal And generating, by the first clock enable signal and the predetermined clock enable information, a plurality of individual clock enable signals, the predetermined clock enable information indicating the generated plurality of individual clock enable signals to select the corresponding plurality of memory chips.
  • the register module is further configured to receive the second separate output of the memory controller The clock enable indication signal and the second clock enable signal, wherein the second individual clock enable indication signal and the second clock enable signal jointly indicate that the control module registers the individual clock enable information according to the second address signal.
  • control module is further configured to receive the first output of the memory controller a clock enable indication signal, wherein the first clock enable indication signal and the first clock enable signal jointly instruct the chip controller to generate a plurality of individual clocks based on the first clock enable signal and the individual clock enable information registered in the registration module Can signal.
  • a memory comprising: a plurality of memory chips and a chip controller as claimed in any one of claims 1 to 12.
  • a third aspect provides a memory controller, including: a generating module, configured to generate a first chip select signal, a first individual chip select indication signal, and a control command signal; and an output module, configured to output the first slice to the chip controller And a first individual chip select indication signal, wherein the first individual chip select indication signal and the first chip select signal jointly indicate that the chip controller generates the plurality of pieces according to the first chip select signal and the individual chip select information registered in the chip controller
  • a separate chip select signal the individual chip select information is used to generate a plurality of individual chip select signals, and the plurality of individual chip select signals are in one-to-one correspondence with the plurality of memory chips, and the first chip select signal is used to select multiple memories in the finger
  • the individual chip selection information is used to indicate that the plurality of memory chips are separately selected from one memory chip
  • the output module is further configured to output a control command signal to the plurality of memory chips, so that at least one of the plurality of memory chips is according to the chip.
  • the output module is further configured to output a first address signal to the chip controller, where the address signal carries address information of the individual chip selection information and the individual chip selection information.
  • the address signal further carries the chip selection policy information, where the chip selection policy information is used to indicate whether the individual chip selection information is valid for the control command signal, wherein the output module is further configured to output a control command signal to the chip controller.
  • the output module is further configured to output, to the chip controller, a second individual chip selection indication signal and a The two chip select signals, wherein the second individual chip select indication signal and the second chip select signal jointly instruct the chip controller to register the individual chip select information according to the address information.
  • the output module is further configured to output to the chip controller a first clock enable signal and a first individual clock enable indication signal, wherein the first clock enable indication signal and the first clock enable signal jointly indicate that the chip controller is registered according to the first clock enable signal and the chip controller
  • the individual clock enable information generates a plurality of individual clock enable signals, and the individual clock enable information is used to generate a plurality of individual clock enable signals, and the plurality of individual clock enable signals are in one-to-one correspondence with the plurality of memory chips, the first clock enables
  • the energy signal is used to control clock signals of a plurality of memory chips, and the plurality of individual clock enable signals are respectively used to individually control clock signals of at least one of the plurality of memory chips.
  • the output module is further configured to output a second address signal to the chip controller, where the second address signal carries a separate clock Address information for information and individual clock enable information.
  • the address signal further carries clock enable policy information, where the clock enable policy information is used to indicate individual clock enable information Whether the control command signal is valid.
  • the output module is further configured to output a second separate clock to the chip controller The enable indication signal and the second clock enable signal, wherein the second individual clock enable indication signal and the second clock enable signal jointly instruct the chip controller to register the individual clock enable information according to the second address signal
  • a fourth aspect provides a method for controlling a memory, comprising: a chip controller receiving a first chip select signal output by a memory controller; and a chip controller according to the first chip select signal and a separate chip select information registered in the chip controller Generating a plurality of individual chip select signals, wherein the plurality of individual chip select signals are in one-to-one correspondence with the plurality of memory chips, the first chip select signal is used to indicate that a plurality of memory chips are selected, and the individual chip select information is used to indicate that multiple memories are individually selected.
  • At least one memory chip in the chip the chip controller separately to the plurality of memory cores
  • the slice outputs a plurality of individual chip select signals such that at least one of the plurality of memory chips performs an operation corresponding to the control command signal according to a control command signal output by the memory controller.
  • the method further includes: receiving, by the chip controller, a first address signal output by the memory controller, where the first address signal carries address information of the individual chip selection information and the individual chip selection information; and the chip controller registers the individual chip selection information according to the first address signal.
  • the first address signal further carries the chip selection policy information
  • the chip selection policy information is registered in the chip controller and The chip selection policy information is used to indicate whether the individual chip selection information is valid for the control command signal
  • the method further includes: the chip controller receiving the control command signal output by the memory controller, wherein the chip controller Generating a plurality of individual chip select signals according to the first chip select signal and the individual chip select information registered in the chip controller, including: if the chip select policy information indicates that the individual chip select information is valid for the control command signal, the chip controller is according to the first The chip select signal and the individual chip select information generate a plurality of individual chip select signals.
  • the method further includes: if the chip selection policy information indicates the individual chip selection information When the control command signal is invalid, the chip controller generates a plurality of individual chip select signals according to the first chip select signal and the predetermined chip select information, and the predetermined chip select information indicates that the generated plurality of individual chip select signals select the corresponding multiple memories. chip.
  • the method further includes: receiving, by the chip controller, a memory controller output And a second chip select indication signal and a second chip select signal, wherein the second individual chip select indication signal and the second chip select signal jointly instruct the chip controller to register the individual chip select information according to the first address signal.
  • the method further includes: receiving, by the chip controller, a memory controller output a single chip select indication signal, wherein the first individual chip select indication signal and the first chip select signal jointly instruct the chip controller to generate a plurality of individual chip select signals according to the first chip select signal and the individual chip select information registered in the chip controller .
  • the method further includes: receiving, by the chip controller, a first clock enable signal output by the memory controller; the chip controller is configured according to the first clock enable signal and the register in the chip controller
  • the clock enable information generates a plurality of individual clock enable signals, and the plurality of individual clock enable signals are in one-to-one correspondence with the plurality of memory chips, and the first clock enable signal is used to control clock signals of the plurality of memory chips, and the plurality of separate clocks
  • the enable signals are respectively used to individually control clock signals of at least one of the plurality of memory chips; the chip controller outputs a plurality of individual clock enable signals to the plurality of memory chips, respectively.
  • the chip controller is configured to enable the individual clock enable information according to the first clock enable signal and the chip controller Before generating the plurality of individual clock enable signals, the method further includes: the chip controller receiving the second address signal output by the memory controller, the address signal carrying the individual clock enable information and the address information of the individual clock enable information, and the second address signal carrying The individual clock enable information and the address information of the individual clock enable information; the chip controller registers the individual clock enable information according to the second address signal.
  • the second address signal further carries clock enable policy information
  • the clock enable policy information is registered in the chip controller.
  • the clock enable policy information is used to indicate whether the individual clock enable information is valid for the control command signal
  • the method further includes: the chip controller receiving the control command signal output by the memory controller, The chip controller generates a plurality of individual clock enable signals according to the first clock enable signal and the individual clock enable information registered in the chip controller, including:
  • the chip controller If the clock enable policy information indicates that the individual clock enable information is valid, the chip controller generates a plurality of individual clock enable signals based on the first clock enable signal and the individual clock enable information.
  • the method further includes: if the clock enable policy information indicates that the individual clock enable information is invalid for the control command signal, Then, the chip controller generates a plurality of individual clock enable signals according to the first clock enable signal and the predetermined clock enable information, and the generated plurality of individual clock enable signals select the corresponding plurality of memory chips.
  • the method further includes: receiving, by the chip controller, the output of the memory controller And a second individual clock enable indication signal and a second clock enable signal, wherein the second individual clock enable indication signal and the second clock enable signal jointly instruct the chip controller to register the individual clock enable information in accordance with the second address signal.
  • the method further includes: the chip controller receiving the memory controller output a first clock enable indication signal, wherein the first clock enable indication signal and the first clock enable signal jointly instruct the chip controller to generate more based on the first clock enable signal and the individual clock enable information registered in the chip controller A separate clock enable signal.
  • a fifth aspect provides a method for controlling a memory chip, the method comprising: the memory controller outputting a first chip select signal and a first individual chip select indication signal to a chip controller, wherein the first individual chip select indication signal and the first A piece of signal selection instruction chip controller generates a plurality of individual chip selection signals according to the first chip selection signal and the individual chip selection information registered in the chip controller, and the individual chip selection information is used to generate a plurality of individual chip selection signals, and multiple The single chip select signal is in one-to-one correspondence with the plurality of memory chips, the first chip select signal is used to indicate that a plurality of memory chips are selected, and the individual chip select information is used to indicate that at least one of the plurality of memory chips is individually selected; the memory controller The control command signal is output to the plurality of memory chips such that at least one of the plurality of memory chips performs an operation corresponding to the control command signal according to the plurality of individual chip select signals output by the chip control.
  • the method further includes: the memory controller outputting a first address signal to the chip controller, where the address signal carries the individual chip selection information and the individual chip selection information Address information.
  • the address signal further carries the chip selection policy information, where the chip selection policy information is used to indicate that the individual chip selection information is for the control command. Whether the signal is valid, wherein the method further comprises: the memory controller outputs a control command signal to the chip controller.
  • the method further includes: the memory controller outputting a second individual chip selection indication to the chip controller And a second chip select signal, wherein the second individual chip select indication signal and the second chip select signal jointly instruct the chip controller to register the individual chip select information based on the address information.
  • the method further includes: controlling the memory controller to the chip And outputting a first clock enable signal and a first individual clock enable indication signal, wherein the first clock enable indication signal and the first clock enable signal jointly indicate that the chip controller is configured according to the first clock enable signal and the chip controller Registered individual clock enable information to generate multiple individual clock enable signals, separate clock
  • the enable information is used to generate a plurality of individual clock enable signals, and the plurality of individual clock enable signals are in one-to-one correspondence with the plurality of memory chips, and the first clock enable signal is used to control clock signals of the plurality of memory chips, and the plurality of separate signals
  • the clock enable signals are respectively used to individually control clock signals of at least one of the plurality of memory chips.
  • the method further includes: the memory controller outputs a second address signal to the chip controller, where the second address signal carries Individual clock enable information and address information for individual clock enable information.
  • the address signal further carries clock enable policy information, where the clock enable policy information is used to indicate individual clock enable information Whether the control command signal is valid.
  • the method further includes: the memory controller outputs the first to the chip controller Two separate clock enable indicator signals and a second clock enable signal, wherein the second individual clock enable indication signal and the second clock enable signal jointly instruct the chip controller to register individual clock enable information in accordance with the second address signal.
  • the technical solution of the present invention generates a plurality of individual chip select signals according to the chip select signal received from the memory controller and the registered individual chip select information by registering the individual chip select information in the chip controller, and respectively A plurality of memory chips output the plurality of individual chip select signals. Since the individual chip select information is registered in the chip controller, the memory controller is not required to send separate chip select information for each command, thereby reducing the occupation of the transmission bandwidth.
  • FIG. 1 is a schematic structural diagram of a memory system in accordance with an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a chip controller in accordance with an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a memory controller in accordance with an embodiment of the present invention.
  • FIG. 4 is a schematic flow chart of a method of controlling a memory chip according to an embodiment of the present invention.
  • 5A is a schematic diagram of signal flow of a memory system in accordance with an embodiment of the present invention.
  • 5B is a schematic diagram of signal flow of a chip controller in accordance with an embodiment of the present invention.
  • FIG. 6 is a schematic flow chart of a control method of a chip controller according to an embodiment of the present invention.
  • FIG. 7 is a schematic flow chart of a method of controlling a memory chip according to another embodiment of the present invention.
  • FIG. 8 is a schematic flow chart of a method of controlling a memory chip according to still another embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of a chip controller in accordance with an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a memory according to an embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram of a memory controller in accordance with an embodiment of the present invention.
  • the memory system 100 includes a memory controller 110 and a memory 120.
  • the memory controller 110 is used to control data exchange between the memory 120 and a central processing unit (CPU).
  • the memory 120 includes a chip controller 121 and a plurality of memory chips 122.
  • the chip controller 121 is located between the memory controller 110 and the memory chip 122 for controlling the operation of the memory chip 110 by the memory controller 110.
  • the memory controller 110 communicates with the memory 120 via a communication bus. It should be understood that the chip controller 121 may also be located outside of the memory, in other words, the chip controller 121 and the memory chip 122 may be separate.
  • the memory controller 110 and the central processing unit (CPU) may be separate or integrated into the CPU.
  • the memory 120 may be in the form of a dual in-line memory module (DIMM), or may take other forms, for example, It can be that the chip controller and the processor are on a single board. Or the chip controller acts as a daughter card or daughter board of other forms.
  • DIMM dual in-line memory module
  • the chip controller 121 is connected to the memory chip 122.
  • the control command signal and the address signal can be input from one side of the DIMM into the chip, and the individual chip select signals and/or individual clocks can be made.
  • the energy signal is input from the other side of the DIMM into the chip.
  • embodiments of the invention are not limited in this manner.
  • the interface between the chip controller 121 and the memory controller 110 can transmit an address (ADDRESS) signal, a control command (CMD) signal, a chip select (CS) signal, and a clock in a double rate synchronous random access memory (DDR) transmission standard.
  • ADRESS address
  • CMD control command
  • CS chip select
  • DDR double rate synchronous random access memory
  • the interface between the chip controller 121 and the memory controller 110 can also transmit an indication signal, for example, such an indication signal can be used by the registration module to determine the registration of individual chip selection information and Separate clock enable information, which can also be used by the control module to determine the processing of the chip select signal and the clock enable signal.
  • the memory controller 110 is coupled to a central processing unit (CPU) and is controlled by a central processing unit.
  • CPU central processing unit
  • FIG. 2 is a schematic structural diagram of a chip controller 200 according to an embodiment of the present invention.
  • the chip controller 200 is an example of the chip controller 121 of FIG.
  • the chip controller 200 includes a registration module 210 and a control module 220.
  • the control module 220 is configured to: receive a first chip select signal output by the memory controller; generate a plurality of individual chip select signals according to the first chip select signal and the individual chip select information registered by the register module 210, wherein the plurality of individual chip select signals are The plurality of memory chips are in one-to-one correspondence, the first chip selection signal is used to indicate that a plurality of memory chips are selected, and the individual chip selection information is used to indicate that at least one of the plurality of memory chips is individually selected; and the plurality of memory chips are respectively outputted
  • the individual chip select signals are such that at least one of the plurality of memory chips performs an operation corresponding to the control command signal according to a control command signal output by the memory controller.
  • the technical solution of the present invention generates a plurality of individual chip select signals according to the chip select signal and the registered individual chip select information by registering individual chip select information in the chip controller, and respectively outputting the plurality of chip select signals to the plurality of memory chips Multiple separate chip select signals. Since the individual chip select information is registered in the chip controller, the memory controller is not required to send separate chip select information for each command, thereby reducing the occupation of the transmission bandwidth.
  • the chip controller 200 may further include another registration module, wherein the signal output by the control module 220 is sent to another registration module.
  • This registration module is used to buffer and redrive the signal. In the case of good signal quality and sufficient timing margin, the registration module can be omitted.
  • the input signal of the chip controller 200 may be a CMD, ADDRESS, CS, CKE signal and an indication signal output by the memory controller, and the output signal may be a separate chip select signal and a separate clock enable signal corresponding to each chip.
  • Each individual chip select signal is used to control a chip corresponding to the individual chip select signal to execute a specific operational command.
  • Each individual clock enable signal is used to control the individual clock enable signal corresponding The chip is in sleep mode.
  • the chip controller can receive the first chip select signal output by the memory controller through the communication bus.
  • the first chip select signal indicates that all the memory chips in the memory stick are selected for operation, for example, a write operation or a read operation, and embodiments of the present invention are not limited thereto, and for example, the operation may further include activation, Precharge or refresh operations.
  • each of the memory chips receives the first chip select signal to perform the operation indicated by the control command signal.
  • the individual chip select signals are in one-to-one correspondence with the memory chips, and the individual chip select signals indicate that the corresponding memory chips are selected for the operation indicated by the control command signals.
  • the individual chip select signals when the individual chip select signals are selected and the corresponding memory chips are used for the operation, the individual chip select signals may be set to be high level or low level, which is not limited by the embodiment of the present invention.
  • the registering module is further configured to: receive the first address signal output by the memory controller before the control module generates the plurality of individual chip select signals according to the first chip select signal and the individual chip select information registered by the register module
  • the first address signal carries address information of the individual chip select information and the individual chip select information; and the individual chip select information is registered according to the first address signal.
  • the address signal instructs the registration module to register individual chip select information.
  • the registration module registers the individual chip selection information in accordance with the control command signal and the address signal indicating the registration operation. It is also possible that the registration module registers the individual chip selection information according to the address signal. It should also be understood that it can be sent only once during each complete operation of the memory chip, or it can be sent multiple times.
  • the memory controller sends a signal carrying the individual chip selection information only before the first control command signal in the process of a complete write, read or refresh operation of the data, and the control module controls the memory chip in the operation.
  • the command signal calls the individual chip select information registered by the registration module.
  • the chip controller can acquire the individual chip selection information when needed, so that the chip controller does not need to receive individual chip selection information for each control command signal, thereby saving bandwidth and improving the control chip. flexibility.
  • the first address signal further carries chip selection policy information
  • the chip selection policy information is registered in the registration module and corresponds to the individual chip selection information
  • the chip selection policy information is used to indicate the individual chip selection information for the control command.
  • the control module is further configured to receive a control command signal output by the memory controller, wherein the control module is configured to: when the chip select policy information indicates that the individual chip select information is valid for the control command signal, according to the first chip select signal and the separate The chip select information generates a plurality of individual chip select signals.
  • the control module If the chip selection policy information indicates that the individual chip selection information is invalid for the control command signal, the control module generates a plurality of individual chip selection signals according to the first chip selection signal and the predetermined chip selection information, and the predetermined chip selection information indication The generated plurality of individual chip select signals select a corresponding plurality of memory chips.
  • the corresponding chip selection policy information can be set for the individual chip selection information.
  • the chip select policy information has a mapping relationship with the individual chip select information and the predetermined control command signal. In this case, when the control module registers the information registered in the registration module, the control module does not choose to invoke the individual chip selection information, but only the corresponding chip selection policy information.
  • the policy information indicates that the individual chip select information is valid for the refresh command, and the chip controller outputs a separate chip select signal according to the individual chip select information in the case of receiving the refresh command.
  • the control command signal may also be any one of a write operation command signal, a read operation command signal, or an Activate (ACT) command signal.
  • the policy information indicates that the individual chip select signal is invalid for the read command signal
  • the chip controller generates and outputs a plurality of individual chip select signals according to the predetermined chip select information. For example, if the policy information indicates that the individual chip select information is invalid for the read command, the chip controller does not output a separate chip select signal but receives the first chip select signal in the case of receiving the read command.
  • the control command signal may also be any one of an ACT command signal, a refresh command signal, and a write operation signal.
  • the predetermined chip selection information can be set to default, in particular, the chip controller can be instructed to select all of the memory chips.
  • control command for outputting the separate chip select signal only outputs one chip select signal, and does not output multiple separate chip select signals, thereby reducing The transmission of unnecessary information improves the utilization of bandwidth.
  • the registration module is further configured to receive a second individual chip select indication signal and a second chip select signal output by the memory controller, wherein the second individual chip select indication signal and the second chip select signal jointly indicate the registration module
  • the individual chip selection information is registered according to the first address signal.
  • first chip select signal and the second chip select signal carry the same chip select command.
  • the second chip select signal indicates registration of individual chip select information
  • the first chip select signal indicates that a separate chip select signal is output according to the registered individual chip select information.
  • the second individual chip select indication signal and the second chip select signal are used to instruct the chip controller to register the individual chip select information according to the first address signal, for example, the chip controller can be in the second individual chip select indication signal and the second chip select signal When it is valid at the same time, the individual chip selection information carried in the first address signal is registered.
  • the second individual chip select signal may be determined to be active when the second chip select signal is at a high level, and the second chip select signal may be determined to be active when the second chip select signal is at a low level. It should be understood that the second chip select signal may be determined to be active when the second individual chip select indication signal is low, and the second chip select signal is determined to be valid when the second chip select signal is high.
  • the chip controller can determine whether to register the individual chip selection information by using the second individual chip selection indication signal and the second chip selection signal, the chip controller does not perform the registration operation, but only forwards and receives when the individual chip selection information is not required to be registered.
  • the signal enhances the flexibility of the memory controller to control the chip controller while increasing bandwidth utilization.
  • control module is further configured to receive a first individual chip select indication signal output by the memory controller, where the first individual chip select indication signal and the first chip select signal jointly indicate that the control module is configured according to the first chip select signal Separate chip select information registered in the registration module generates a plurality of individual chip select signals.
  • the first individual chip select indication signal and the first chip select signal jointly instruct the chip controller to generate a plurality of individual chip select signals based on the first chip select signal and the individual chip select information registered in the chip controller. Similar to the second individual chip select indication signal and the second chip select signal, for example, the chip controller may process the individual chip select information when the first individual chip select indication signal and the first chip select signal are simultaneously active, and according to the individual slices The selection information generates a separate chip select signal. Specifically, similar to the second individual chip select indication signal, the first individual chip select indication signal may be determined to be active at a high level or at a low level. Similar to the second chip select signal, the first chip select signal can be asserted to be active at a high level or at a low level.
  • the chip controller can determine whether to generate a separate chip select signal according to the first individual chip select indication signal and the first chip select signal, so that the chip controller does not perform corresponding operations when the separate chip select signal is not required to be output, thereby enhancing the memory.
  • the flexibility of the controller to control the chip controller further enhances the flexibility of the memory controller for memory chip control.
  • the control module is further configured to receive a first clock enable indication signal, a first clock enable signal, a first clock enable indication signal, and a first clock enable signal joint indication chip output by the memory controller.
  • the controller generates a plurality of individual clock enable signals according to the first clock enable signal and the individual clock enable information registered in the chip controller
  • the register module is further configured to receive the second individual clock enable indication signal output by the memory controller, a second clock enable signal and a second address signal, the second individual clock enable indication signal and the second clock enable signal jointly instruct the chip controller to register individual clock enable information according to the second address signal, the second address signal carrying a separate Clock enable information, address information of individual clock enable information.
  • the clock enable signal is similar to the chip select signal, and the clock enable signal indicates the operation of selecting a plurality of memory chips to perform the control command signal indication.
  • the individual chip select signals are similar to the individual clock enable signals, for example, can be set to be active when the individual clock enable signals are high or low.
  • the address signal indicates that the registration module registers individual clock enable information.
  • the memory module registers the individual clock enable information in accordance with the control command signal and the address signal indicating the registration operation. It is also possible that the registration module registers the individual clock enable information according to the address signal.
  • the signal carrying the individual clock enable information may be sent only once during each complete operation of the memory chip or multiple times.
  • the memory controller sends a signal carrying the individual clock enable information only before the first control command signal in the process of a complete write, read or refresh operation of the data, and the control module is directed to the memory chip in the operation.
  • the control command signal calls the individual clock enable information registered by the registration module.
  • the corresponding clock enablement policy information can be set for the individual clock enable information.
  • the clock enable policy information is mapped to both the individual clock enable information and the predetermined control command signal.
  • the control module when the control module registers the information registered in the registration module, the control module does not choose to invoke the individual clock enable information, but only the corresponding clock enable strategy information.
  • the policy information indicates that the individual clock enable information is valid for the ACT command, and the chip controller outputs a separate clock enable signal according to the individual clock enable information in the case of the ACT command.
  • the control command signal may also be any one of a write operation command signal, a read operation command signal, or a refresh command signal.
  • the first clock enable signal and the second clock enable signal carry the same clock enable command.
  • the second clock enable signal indicates registration of individual clock enable information
  • the first clock enable signal indicates that a separate clock enable signal is output based on the registered individual clock enable information.
  • the second individual clock enable indication signal and the second clock enable signal are used to instruct the chip controller to register the individual clock enable information according to the first address signal, for example, the chip controller can enable the indication signal and the second individual clock
  • the individual clock enable information is registered.
  • the second individual clock enable indication signal may be determined to be active when the second individual clock enable indication signal is at a high level
  • the second clock enable signal may be determined to be active when the second clock enable signal is at a low level.
  • the second clock enable signal may be determined to be active when the second individual clock enable indication signal is low, and the second clock enable signal is determined to be active when the second clock enable signal is high.
  • the first individual clock enable indication signal and the first clock enable signal jointly instruct the chip controller to generate a plurality of individual clock enable signals based on the first clock enable signal and the individual clock enable information registered in the chip controller.
  • the chip controller can process the individual clocks when the first individual clock enable indication signal and the first clock enable signal are simultaneously active.
  • Information, and enable information generation sheet based on individual clocks A unique clock enable signal.
  • the first individual clock enable indication signal can be determined to be active at a high level or at a low level.
  • the first clock enable signal can be asserted to be active at a high level or at a low level.
  • the memory chip Since a separate clock enable signal is output for each memory chip, the memory chip does not accept the command of the clock signal without requiring a clock signal. Since a separate clock enable signal is generated, the chip controller can individually control the chip, for example, to put a specific chip in a sleep mode, thereby reducing the power consumption of the chip.
  • the memory controller 300 includes: a generating module 310, configured to generate a first chip select signal, a first individual chip select indication signal, and a control command signal; and an output module 320, configured to output a first chip select signal and a chip to the chip controller a single chip select indication signal, wherein the first individual chip select indication signal and the first chip select signal jointly instruct the chip controller to generate a plurality of individual chip select signals according to the first chip select signal and the individual chip select information registered in the chip controller
  • the individual chip select information is used to generate a plurality of individual chip select signals, and the plurality of individual chip select signals are in one-to-one correspondence with the plurality of memory chips, and the first chip select signal is used to select a plurality of memory chips, and the individual slices are selected
  • the selection information is used to indicate that a plurality of memory chips are separately selected and one memory chip is used; the output module is further configured to output a control command signal to the plurality of
  • the technical solution of the present invention generates a plurality of individual chip select signals according to the chip select signal and the registered individual chip select information by registering individual chip select information in the chip controller, and respectively outputting the plurality of chip select signals to the plurality of memory chips Multiple separate chip select signals. Since the individual chip select information is registered in the chip controller, the memory controller is not required to send separate chip select information for each command, thereby reducing the occupation of the transmission bandwidth.
  • the output module is further configured to output a first address signal to the chip controller, the address signal carrying address information of the individual chip selection information and the individual chip selection information.
  • the address signal further carries the chip selection policy information, where the chip selection policy information is used to indicate whether the individual chip selection information is valid for the control command signal, wherein the output module is further configured to output the control command signal to the chip controller.
  • the output module is further configured to output a second individual chip select indication signal and a second chip select signal to the chip controller, wherein the second individual chip select indication signal and the second chip select signal jointly indicate the chip controller
  • the individual chip selection information is registered based on the address information.
  • FIG. 4 is a schematic flow chart of a method of controlling a memory chip according to an embodiment of the present invention.
  • 5A is a schematic diagram of signal flow of a memory system in accordance with an embodiment of the present invention.
  • 5B is a schematic diagram of signal flow of a chip controller in accordance with an embodiment of the present invention.
  • FIG. 5A illustrates a method of signal transmission between a memory controller, a chip controller, and a memory chip.
  • Figure 5B specifically illustrates the operations performed by the control module in the chip controller for a plurality of signals.
  • the first individual chip select indication signal, the second individual chip select indication signal, the first individual clock enable indication signal, and the second individual clock enable indication signal are collectively referred to as an indication signal
  • first The address signal and the second address signal are collectively referred to as an address signal
  • the first chip select signal and the second chip select signal are collectively referred to as a chip select signal
  • the first clock enable signal and the second clock enable signal are collectively referred to as a clock enable signal.
  • this embodiment uses a DIMM memory chip composed of a DRAM chip.
  • the registration module receives a bus command signal output by the memory controller.
  • the bus command signals include an address signal, a control command signal, a chip select signal, a clock enable signal, and an indication signal.
  • the registration module determines to register the individual chip select information according to the second chip select signal and the second individual chip select indication signal, and the register module determines to register the individual clock enable information according to the second clock enable signal and the second individual clock enable indication signal.
  • the second chip select signal and the second individual chip select indication signal when the second chip select signal and the second individual chip select indication signal are simultaneously active, it indicates that the registration module determines to register the individual chip select information.
  • the second clock enable signal and the second individual clock enable indication signal are simultaneously active, it indicates that the registration module determines to register the individual clock enable information.
  • the second chip select signal may be made active when the second chip select signal and the second individual chip enable signal are predetermined to be low, and the second clock enable signal is predetermined to be Valid when high.
  • the registration module registers separate chip selection information and individual clock enable information.
  • the address signal carries separate chip select information, separate clock enable information, and address information of individual chip select information and address information of individual clock enable information.
  • the memory controller writes individual chip select information and individual clock enable information into the register module through address signals and control command signals in the bus.
  • the register module is further divided into a chip select register module and a clock enable register module for registering individual chip select information and individual clock enable information, respectively.
  • Table 1 shows individual chip select information and a separate clock registered by the register module.
  • the enable information has specific addresses a0 and a1, respectively.
  • the registration module registers chip selection policy information for the individual chip selection information, where the chip selection policy information is used to indicate an application policy of the individual chip selection information.
  • the registration module registers clock enablement policy information also for individual clock enable information, the clock enable policy information being used to indicate an application strategy for individual clock enable information.
  • the chip select policy information indicates whether the individual chip select information is valid for the ACT command signal.
  • the clock policy information indicates whether the individual clock enable information is valid for the ACT command signal.
  • the chip selection policy information may be defined as policy information for the ACT command, that is, when the control module receives the signal of the ACT command, it is determined according to the policy information whether to output a separate chip selection signal according to the individual chip selection information. If the policy information still indicates that a separate chip select signal is output according to the individual chip select information, the control module outputs a separate chip select signal according to the individual chip select information. If the policy information indicates that the chip select signal is output according to the predetermined default information, the control module outputs the chip select signal according to the predetermined default information. For example, the control module sets the default information to indicate that all the individual chip select signals are valid, and ignores the individual slices. Select information. In other words, similar to the chip select signal, all individual chip select signals are instructed to execute the ACT command by the corresponding memory chip. Other control commands, such as the read command or the refresh command, are similar to the ACT command, and are not described here.
  • the clock enable policy information may be defined as policy information for the ACT command, that is, when the control module receives the signal of the ACT command, it is determined according to the policy information whether to output a separate chip select signal according to the individual chip select information. It should be understood that in the embodiment, similar operations are performed on the chip select signal and the clock enable signal, for example, the policy information of the individual chip select signal and the individual clock enable signal is defined as being for the same control command, however, It is defined as policy information for different control commands.
  • the control module receives a control command signal, a chip select signal, a clock enable signal, and an indication signal in the bus command signal.
  • the control module determines to process the chip select signal according to the chip select signal and the indication signal, and determines to process the clock enable signal according to the clock enable signal and the indication signal.
  • the control module is configured to generate and output each DIMM in the memory module according to the information registered by the registration module.
  • the control module 220 includes a chip select control module 221 and a clock enable control module 222.
  • the registration module 210 includes a chip select registration module 211 and a clock enable registration module 212.
  • the registration module 210 includes a chip select register module 211 and a clock enable register module 212 for registering chip select related information and clock enable related information, respectively.
  • the chip select control module 221 generates and outputs a separate chip select signal corresponding to each DRAM chip
  • the clock enable control module 222 generates and outputs a separate clock enable signal corresponding to each DRAM chip.
  • the control module determines that presence policy information exists.
  • the policy information exists in the registration module, so the control module judges according to the policy information, and it should be understood that if there is no policy information, it is judged according to the individual chip selection information.
  • the control module determines, according to the received control command signal, strategy information that is used for the control command signal.
  • the control module since the ACT command has corresponding policy information, and the policy information indicates that the signal is output according to the individual chip selection information and the individual enable information, the control module does not output according to the predetermined chip selection information and the predetermined clock enable information.
  • the individual chip select signals and the individual clock enable signals are output according to the individual chip select information and the individual clock enable information.
  • the control module outputs a separate chip select signal and a separate clock enable signal to the memory chip.
  • Each memory chip receives a corresponding individual chip select signal and a separate clock enable signal.
  • a separate chip select signal corresponding to the memory chip indicates that the chip is in an unselected state in the case of a write operation command, and the memory chip does not perform a write operation after receiving the signal.
  • the registration module may also not register individual clock enable information. Accordingly, the control module may also not process the clock enable signal, ie, generate a separate clock enable signal without using the clock enable signal.
  • FIG. 6 is a flow chart of a method of controlling a chip controller in accordance with an embodiment of the present invention.
  • the chip select signal is taken as an example.
  • the control module is similar to the clock enable signal and the judgment and operation of the chip select signal, and details are not described herein again. It should also be understood that this embodiment employs a DRAM chip in the form of a DIMM, but embodiments of the present invention are not limited thereto.
  • 610 Receive a signal of the bus from the memory controller, including an address signal, an indication signal, a chip select signal, and a control command signal.
  • the chip controller processes the chip select signal.
  • the chip select signal is a command for the DRAM chip within the DIMM controlled by the chip controller.
  • the chip select signal and the indication signal are different, it indicates that the chip controller does not perform any processing on the chip select signal. If the result of the determination is yes, execute 640, and if the result of the determination is no, execute 630.
  • the chip controller outputs the chip select signal to the memory chip without generating and outputting a separate chip select signal, that is, the individual chip select signals are unselected.
  • the chip controller selects to process the chip select signal. Further, the control module determines, by the register module, whether the control command has corresponding policy information. If the result of the determination is yes, that is, there is predetermined policy information, execute 660. If the result of the determination is no, that is, there is no predetermined policy information, execute 650.
  • the control module generates and outputs a separate chip select signal according to the individual chip selection information.
  • the control module outputs, according to the policy information, the output according to the individual chip selection information or according to the predetermined chip selection information.
  • the predetermined chip selection information may be default information.
  • the control module If the policy information indication is output according to the predetermined chip selection information, for example, according to the default information, the control module generates and outputs a corresponding signal according to the default information.
  • the default information can be set to indicate that all individual chip select signals are active, while individual chip select information is ignored. In other words, since the plurality of individual chip select information are all valid, the case where the plurality of memory chips receive the plurality of individual chip select signals is similar to the case where the chip select signals are received, and all the individual chip select signals indicate the corresponding memory chips. Perform operations such as activation or refresh.
  • the control module executes 650, ie, the control module generates and outputs a separate chip select signal based on the individual chip select information.
  • FIG. 7 is a schematic flow chart of a method of controlling a memory chip in accordance with one embodiment of the present invention.
  • the method of Figure 7 is performed by a chip controller, including the following.
  • the chip controller receives a first chip select signal output by the memory controller.
  • the chip controller generates a plurality of individual chip select signals according to the first chip select signal and the individual chip select information registered in the chip controller, wherein the plurality of individual chip select signals are in one-to-one correspondence with the plurality of memory chips, and the first chip selects
  • the signal is used to indicate that a plurality of memory chips are selected
  • the individual chip selection information is used to indicate that at least one of the plurality of memory chips is individually selected.
  • the chip controller outputs a plurality of individual chip select signals to the plurality of memory chips, respectively, for multiple At least one of the memory chips performs an operation corresponding to the control command signal according to a control command signal output from the memory controller.
  • the technical solution of the present invention generates a plurality of individual chip select signals according to the chip select signal received from the memory controller and the registered individual chip select information by registering the individual chip select information in the chip controller, and respectively respectively
  • the memory chip outputs a plurality of individual chip select signals. Since the individual chip select information is registered in the chip controller, the memory controller is not required to send separate chip select information for each command, thereby reducing the occupation of the transmission bandwidth.
  • the method of FIG. 7 further includes: a chip controller Receiving a first address signal output by the memory controller, the first address signal carries address information of the individual chip select information and the individual chip select information; the chip controller registers the individual chip select information according to the first address signal.
  • the first address signal further carries chip selection policy information
  • the chip selection policy information is registered in the chip controller and corresponds to the individual chip selection information
  • the chip selection policy information is used to indicate that the individual chip selection information is for control Whether the command signal is valid
  • the method further comprises: the chip controller receiving the control command signal output by the memory controller, wherein the chip controller generates the plurality of separate signals according to the first chip selection signal and the individual chip selection information registered in the chip controller
  • the chip select signal includes: if the chip select policy information indicates that the individual chip select information is valid for the control command signal, the chip controller generates a plurality of individual chip select signals according to the first chip select signal and the individual chip select information.
  • the method of FIG. 7 further includes: if the chip selection policy information indicates that the individual chip selection information is invalid for the control command signal, the chip controller generates the first chip selection signal and the predetermined chip selection information. A plurality of individual chip select signals, the predetermined chip select information indicating that the generated plurality of individual chip select signals select a corresponding plurality of memory chips.
  • the method of FIG. 7 further includes: the chip controller receiving the second individual chip select indication signal and the second chip select signal output by the memory controller, wherein the second individual chip select indication signal and the second The two chip select signals jointly instruct the chip controller to register individual chip select information based on the first address signal.
  • the method of FIG. 7 further includes: receiving, by the chip controller, a first individual chip select indication signal output by the memory controller, where the first individual chip select indication signal and the first chip select signal are combined
  • the chip controller generates a plurality of individual chip select signals based on the first chip select signal and the individual chip select information registered in the chip controller.
  • the method of FIG. 7 further includes: the chip controller receives a first clock enable signal output by the memory controller; and the chip controller is configured according to the first clock enable signal and the chip controller
  • the individual clock enable information generates a plurality of individual clock enable signals, and the plurality of individual clock enable signals are in one-to-one correspondence with the plurality of memory chips, and the first clock enable signal is used to control clock signals of the plurality of memory chips, and the plurality of separate signals
  • the clock enable signals are respectively used to individually control clock signals of at least one of the plurality of memory chips; the chip controller outputs a plurality of individual clock enable signals to the plurality of memory chips, respectively.
  • the method of FIG. 7 further includes: The chip controller receives the second address signal output by the memory controller, the address signal carries the address information of the individual clock enable information and the individual clock enable information, and the second address signal carries the address of the individual clock enable information and the individual clock enable information. Information; the chip controller registers the individual clock enable information according to the second address signal.
  • the second address signal also carries clock enable strategy information
  • the clock enable policy information is registered in the chip controller and corresponds to individual clock enable information
  • the clock enable policy information is used to indicate a separate clock
  • the enabling information is valid for the control command signal
  • the method further comprises: the chip controller receiving the control command signal output by the memory controller, wherein the chip controller is configured according to the first clock enable signal and a separate clock registered in the chip controller
  • the information can generate a plurality of individual clock enable signals, including: if the clock enable policy information indicates that the individual clock enable information is valid, the chip controller generates a plurality of separate clocks based on the first clock enable signal and the individual clock enable information. Can signal.
  • the method of FIG. 7 further includes: if the clock enable policy information indicates that the individual clock enable information is invalid for the control command signal, the chip controller according to the first clock enable signal and the predetermined clock The enable information generates a plurality of individual clock enable signals, and the generated plurality of individual clock enable signals select a corresponding plurality of memory chips.
  • the method of FIG. 7 further includes: the chip controller receiving the second individual clock enable indication signal and the second clock enable signal output by the memory controller, wherein the second individual clock enable indication The signal and the second clock enable signal in conjunction indicate that the chip controller registers the individual clock enable information in accordance with the second address signal.
  • the method of FIG. 7 further includes: the chip controller receiving a first clock enable indication signal output by the memory controller, wherein the first clock enable indication signal and the first clock enable The signal joint instructs the chip controller to generate a plurality of individual clock enable signals based on the first clock enable signal and the individual clock enable information registered in the chip controller.
  • FIG. 8 is a schematic flowchart of a method of controlling a memory chip according to another embodiment of the present invention.
  • the method of Figure 8 is performed by a memory controller, including the following.
  • the memory controller outputs a first chip select signal and a first individual chip select indication signal to the chip controller, where the first individual chip select indication signal and the first chip select signal jointly indicate that the chip controller is configured according to the first chip select signal and
  • the individual chip select information registered in the chip controller generates a plurality of individual chip select signals, and the individual chip select information is used to generate a plurality of individual chip select signals, and the plurality of individual chip select signals are in one-to-one correspondence with the plurality of memory chips, the first slice
  • the selection signal is used to indicate that a plurality of memory chips are selected, and the individual chip selection information is used to indicate that at least one of the plurality of memory chips is individually selected.
  • the memory controller outputs a control command signal to the plurality of memory chips, so that at least one of the plurality of memory chips performs an operation corresponding to the control command signal according to the plurality of individual chip select signals output by the chip control.
  • the technical solution of the present invention generates a plurality of individual chip select signals according to the chip select signal received from the memory controller and the registered individual chip select information by registering the individual chip select information in the chip controller, and respectively respectively
  • the memory chip outputs a plurality of individual chip select signals. Since the individual chip select information is registered in the chip controller, the memory controller is not required to send separate chip select information for each command, thereby reducing the occupation of the transmission bandwidth.
  • the method of FIG. 8 further includes: the memory controller outputting a first address signal to the chip controller, where the address signal carries address information of the individual chip selection information and the individual chip selection information.
  • the address signal further carries the chip selection policy information, where the chip selection policy information is used to indicate whether the individual chip selection information is valid for the control command signal, wherein the method further includes: the memory controller outputs the control command to the chip controller. signal.
  • the method of FIG. 8 further includes: the memory controller outputting a second individual chip select indication signal and a second chip select signal to the chip controller, wherein the second individual chip select indication signal and the second The chip select signal instructs the chip controller to register individual chip select information based on the address information.
  • the method of FIG. 8 further includes: the memory controller outputs a first clock enable signal and a first individual clock enable indication signal to the chip controller, wherein the first clock enable indication signal and The first clock enable signal joint instructs the chip controller to generate a plurality of individual clock enable signals according to the first clock enable signal and the individual clock enable information registered in the chip controller, and the individual clock enable The information is used to generate a plurality of individual clock enable signals, and the plurality of individual clock enable signals are in one-to-one correspondence with the plurality of memory chips, and the first clock enable signal is used to control clock signals of the plurality of memory chips, and the plurality of separate clocks enable The energy signals are respectively used to individually control clock signals of at least one of the plurality of memory chips.
  • the method of FIG. 8 further includes: the memory controller outputting a second address signal to the chip controller, where the second address signal carries address information of the individual clock enable information and the individual clock enable information.
  • the address signal also carries clock enable policy information, the clock enable policy information being used to indicate whether the individual clock enable information is valid for the control command signal.
  • the method of FIG. 8 further includes: the memory controller outputs a second individual clock enable indication signal and a second clock enable signal to the chip controller, wherein the second individual clock enable indication signal And the second clock enable signal jointly instructs the chip controller to register the individual clock enable information according to the second address signal.
  • FIG. 9 is a schematic block diagram of a chip controller in accordance with one embodiment of the present invention.
  • the chip controller 900 includes a register 910 and a controller 920.
  • the register 910 is connected to the controller 920, wherein the register 910 is used to register the individual chip select information.
  • the controller 920 is configured to: receive the first chip select signal output by the memory controller.
  • the technical solution of the present invention generates a plurality of individual chip select signals according to the chip select signal received from the memory controller and the registered individual chip select information by registering the individual chip select information in the chip controller, and respectively respectively
  • the memory chip outputs a plurality of individual chip select signals. Since the individual chip select information is registered in the chip controller, the memory controller is not required to send separate chip select information for each command, thereby reducing the occupation of the transmission bandwidth.
  • the register is further configured to: before the controller generates the plurality of individual chip select signals according to the first chip select signal and the individual chip select information registered by the register, receive the first address signal output by the memory controller, An address signal carries address information of the individual chip select information and the individual chip select information; the individual chip select information is registered according to the first address signal.
  • the first address signal further carries chip selection policy information
  • the chip selection policy information is registered in the chip controller and corresponds to the individual chip selection information
  • the chip selection policy information is used to indicate that the individual chip selection information is for control Whether the command signal is valid
  • the controller is further configured to receive a control command signal output by the memory controller, and generate a plurality of individual chip select signals according to the first chip select signal and the individual chip select information registered in the chip controller, including: if the chip select The policy information indicates that the individual chip selection information is valid for the control command signal, and then generating a plurality of individual chip selection signals according to the first chip selection signal and the individual chip selection information; if the chip selection policy information indicates that the individual chip selection information is invalid for the control command signal, And generating a plurality of individual chip select signals according to the first chip select signal and the predetermined chip select information, wherein the predetermined chip select information indicates that the generated plurality of individual chip select signals select the corresponding plurality of memory chips.
  • the register is further configured to receive a second individual chip select indication signal and a second chip select signal output by the memory controller, wherein the second individual chip select indication signal and the second chip select signal jointly indicate the chip controller
  • the individual chip selection information is registered according to the first address signal.
  • the controller is further configured to receive a first individual chip select indication signal output by the memory controller, wherein the first individual chip select indication signal and the first chip select signal jointly indicate that the chip controller is configured according to the first chip
  • the individual chip select information registered in the signal and chip controller generates a plurality of individual chip select signals.
  • the controller is further configured to receive a first clock enable indication signal, a first clock enable signal, a first clock enable indication signal, and a first clock enable signal joint indication chip output by the memory controller.
  • the controller generates a plurality of individual clock enable signals according to the first clock enable signal and the individual clock enable information registered in the chip controller, and the register is further configured to receive a second individual clock enable indication signal output by the memory controller, a second clock enable signal and a second address signal, the second individual clock enable indication signal and the second clock enable signal jointly instruct the chip controller to register individual clock enable information according to the second address signal, the second address signal carrying a separate clock Enable information, address information of individual clock enable information.
  • FIG. 10 is a schematic block diagram of a memory in accordance with one embodiment of the present invention.
  • the memory 1000 includes a plurality of memory chips 1010 and a chip controller 900 as shown in FIG.
  • the technical solution of the present invention generates a plurality of individual chip select signals according to the chip select signal received from the memory controller and the registered individual chip select information by registering the individual chip select information in the chip controller, and respectively respectively
  • the memory chip outputs a plurality of individual chip select signals. Since the individual chip select information is registered in the chip controller, the memory controller is not required to send separate chip select information for each command, thereby reducing the occupation of the transmission bandwidth.
  • FIG. 11 is a schematic block diagram of a memory controller in accordance with one embodiment of the present invention.
  • the memory controller 1100 includes: a processor 1110 and a transmitter 1120, wherein the processor 1110 is connected to the transmitter 1120, and the processor 1110 is configured to generate a first chip selection signal, a first individual chip selection indication signal, and a control command signal;
  • the transmitter 1120 is configured to output a first chip select signal and a first individual chip select indication signal to the chip controller, where the first individual chip select indication signal and the first chip select signal jointly indicate that the chip controller is configured according to the first chip select signal
  • Separate chip selection information registered in the chip controller generates a plurality of individual chip selection signals, and the individual chip selection information is used to generate a plurality of individual chip selection signals, and the plurality of individual chip selection signals are in one-to-one correspondence with the plurality of memory chips, first The chip select signal is used to select a plurality of memory chips, and the individual chip select information is used to indicate that a plurality of memory
  • the technical solution of the present invention generates a plurality of individual chip select signals according to the chip select signal received from the memory controller and the registered individual chip select information by registering the individual chip select information in the chip controller, and respectively respectively
  • the memory chip outputs a plurality of individual chip select signals. Since the individual chip select information is registered in the chip controller, the memory controller is not required to send separate chip select information for each command, thereby reducing the occupation of the transmission bandwidth.
  • the transmitter is further configured to output a first address signal to the chip controller, the address signal carrying address information of the individual chip selection information and the individual chip selection information.
  • the address signal further carries chip selection policy information, where the chip selection policy information is used to indicate whether the individual chip selection information is valid for the control command signal, wherein the transmitter is further configured to output a control command signal to the chip controller.
  • the transmitter is further configured to output a second individual chip select indication signal and a second chip select signal to the chip controller, wherein the second individual chip select indication signal and the second chip select signal jointly indicate the chip controller
  • the individual chip selection information is registered based on the address information.
  • the transmitter is further configured to output a second individual chip select indication signal and a second chip select signal to the chip controller, the second individual chip select indication signal and the second chip select signal jointly instruct the chip controller to The address information is sent to the individual chip selection information.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, or an electrical, mechanical or other form of connection.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present invention.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • Computer readable media includes computer storage media and communication media Quality, wherein the communication medium includes any medium that facilitates the transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a computer.
  • computer readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage media or other magnetic storage device, or can be used for carrying or storing in the form of an instruction or data structure.
  • the desired program code and any other medium that can be accessed by the computer may suitably be a computer readable medium.
  • the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable , fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, wireless, and microwave are included in the fixing of the associated media.
  • coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, wireless, and microwave are included in the fixing of the associated media.
  • a disk and a disc include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.

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Abstract

一种控制内存芯片的方法、芯片控制器和内存控制器。该芯片控制器（200）包括：寄存模块（210），用于寄存单独片选信息；控制模块（220），用于：接收内存控制器（110）输出的第一片选信号；根据第一片选信号和寄存模块（210）寄存的单独片选信息生成多个单独片选信号，其中多个单独片选信号与多个内存芯片（122）一一对应，第一片选信号用于指示选择多个内存芯片，单独片选信息用于指示单独选择多个内存芯片中的至少一个内存芯片；分别向多个内存芯片输出多个单独片选信号，以便多个内存芯片中的至少一个内存芯片根据内存控制器输出的控制命令信号执行与控制命令信号对应的操作。能够有效地减少对DRAM系统的传输带宽的占用。

Description

控制内存芯片的方法、芯片控制器和内存控制器
本申请要求于2014年4月17日提交中国专利局、申请号为201410154996.1、发明名称为“控制内存芯片的方法、芯片控制器和内存控制器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明的实施例涉及计算机领域，尤其涉及一种控制内存芯片的方法、芯片控制器和内存控制器。
背景技术
计算机体系结构具有内存系统，内存系统最常用的存储介质是动态随机存取存储器(Dynamic Random Access Memory，DRAM)。计算机的内存常采用双列直插式存储模块(Dual Inline Memory Modules，DIMM)的形式，可寄存的DIMM(Registered DIMM，RDIMM)和低负载DIMM(Load-Reduced DIMM，LRDIMM)是两种常用的DIMM形式。RDIMM和LRDIMM从内存控制器接收地址信号、片选信号和时钟使能信号，并且经过寄存模块寄存后再输出到DIMM上的各DRAM芯片。
通常的RDIMM的工作原理为：多片窄位宽的DRAM芯片构成宽位宽的DIMM。RDIMM在DIMM条上具有一个寄存功能的电路或者芯片，该电路或者芯片寄存内存控制器发送给DRAM的片选信号、时钟使能信号和地址信号等信号，并且进行重新驱动后输出到各个DRAM芯片。一个RDIMM内存的各个DRAM芯片同步地进行操作。
现有技术中有一种与普通RDIMM类似的DRAM系统。该DRAM系统的内存控制器和DRAM芯片之间有一个DIMM寄存器，该寄存器用于暂存内存控制器发送给DIMM的片选信号、时钟使能信号和地址信号，并且重新驱动这些信号后发送给DRAM芯片。该DRAM系统内还有一个解码器，用于将内存控制器发出的针对整个DIMM内一个RANK的片选信号和时钟使能信号解码为针对各个DRAM芯片的片选和时钟使能信号。DRAM系统在当前DRAM命令的前一个周期发送该DRAM命令对应的单独片选信息，片选信号和单独 片选信息经过解码后变为多个独立的片选信号，分别控制DIMM中对应的多个DRAM芯片。
然而，内存控制器每个DRAM命令都需要在该DRAM命令的前一个周期发送单独片选信息，严重占用了DRAM系统的传输带宽。
发明内容
本发明的实施例提供了一种控制内存芯片的方法、芯片控制器和内存控制器，能够有效地减少对DRAM系统的传输带宽的占用。
第一方面，提供了一种芯片控制器，包括：寄存模块，用于寄存单独片选信息；控制模块，用于：接收内存控制器输出的第一片选信号；根据第一片选信号和输出寄存模块寄存的单独片选信息生成多个单独片选信号，其中多个单独片选信号与多个内存芯片一一对应，第一片选信号用于指示选择多个内存芯片，单独片选信息用于指示单独选择多个内存芯片中的至少一个内存芯片；分别向多个内存芯片输出多个单独片选信号，以便多个内存芯片中的至少一个内存芯片根据内存控制器输出的控制命令信号执行与控制命令信号对应的操作。
结合第一方面，在第一方面的第一种可能的实现方式中，寄存模块还用于：在控制模块根据第一片选信号和寄存模块寄存的单独片选信息生成多个单独片选信号之前，接收内存控制器输出的第一地址信号，第一地址信号携带单独片选信息和单独片选信息的地址信息，并且根据第一地址信号寄存单独片选信息。
结合第一方面的第一种可能的实现方式，在第一方面的第二种可能的实现方式中，第一地址信号还携带片选策略信息，片选策略信息寄存在寄存模块中并且与单独片选信息相对应，片选策略信息用于指示单独片选信息针对控制命令信号是否有效，控制模块还用于接收内存控制器输出的控制命令信号，控制模块用于在片选策略信息指示单独片选信息针对控制命令信号有效时，根据第一片选信号和单独片选信息生成多个单独片选信号。
结合第一方面的第一种或第二种可能的实现方式，在第一方面的第三种可能的实现方式中，控制模块还用于在片选策略信息指示单独片选信息针对控制命令信号无效时，根据第一片选信号和预定的片选信息生成多个单独片选信 号，预定的片选信息指示生成的多个单独片选信号选择对应的多个内存芯片。
结合第一方面的第一种至第三种中的任一种可能的实现方式，在第一方面的第四种可能的实现方式中，寄存模块还用于接收内存控制器输出的第二单独片选指示信号和第二片选信号，其中第二单独片选指示信号和第二片选信号联合指示寄存模块根据第一地址信号寄存单独片选信息。
结合第一方面以及第一方面的第一种至第四种中的任一种可能的实现方式，在第一方面的第五种可能的实现方式中，控制模块还用于接收内存控制器输出的第一单独片选指示信号，其中第一单独片选指示信号和第一片选信号联合指示控制模块根据第一片选信号和寄存模块中寄存的单独片选信息生成多个单独片选信号。
结合第一方面以及第一方面的第一种至第五种中的任一种可能的实现方式，在第一方面的第六种可能的实现方式中，控制模块还用于接收内存控制器输出的第一时钟使能信号，根据第一时钟使能信号和寄存模块中寄存的单独时钟使能信息生成多个单独时钟使能信号，并且向多个内存芯片输出多个单独时钟使能信号，其中，多个单独时钟使能信号与多个内存芯片一一对应，第一时钟使能信号用于控制多个内存芯片的时钟信号，多个单独时钟使能信号分别用于单独控制多个内存芯片中的至少一个芯片的时钟信号。
结合第一方面的第六种可能的实现方式，在第一方面的第七种可能的实现方式中，寄存模块还用于在芯片控制器根据第一时钟使能信号和芯片控制器中寄存的单独时钟使能信息生成多个单独时钟使能信号之前，接收内存控制器输出的第二地址信号，并且根据第二地址信号寄存单独时钟使能信息，其中，地址信号携带单独时钟使能信息和单独时钟使能信息的地址信息，第二地址信号携带单独时钟使能信息和单独时钟使能信息的地址信息。
结合第一方面的第七种可能的实现方式，在第一方面的第八种可能的实现方式中，第二地址信号还携带时钟使能策略信息，时钟使能策略信息寄存在芯片控制器中并且与单独时钟使能信息相对应，时钟使能策略信息用于指示单独时钟使能信息针对控制命令信号是否有效，控制模块还用于接收内存控制器输出的控制命令信号，控制模块用于在时钟使能策略信息指示单独时钟使能信息有效时，根据第一时钟使能信号和单独时钟使能信息生成多个单独时钟使能信号。
结合第一方面的第八种可能的实现方式，在第一方面的第九种可能的实现方式中，控制模块还用于在时钟使能策略信息指示单独时钟使能信息针对控制命令信号无效时，根据第一时钟使能信号和预定的时钟使能信息生成多个单独时钟使能信号，预定的时钟使能信息指示生成的多个单独时钟使能信号选择对应的多个内存芯片。
结合第一方面的第六种至第九种中的任一种可能的实现方式，在第一方面的第十种可能的实现方式中，寄存模块还用于接收内存控制器输出的第二单独时钟使能指示信号和第二时钟使能信号，其中第二单独时钟使能指示信号和第二时钟使能信号联合指示控制模块根据第二地址信号寄存单独时钟使能信息。
结合第一方面的第六种至第十种中的任一种可能的实现方式，在第一方面的第十一种可能的实现方式中，控制模块还用于接收内存控制器输出的第一时钟使能指示信号，其中第一时钟使能指示信号和第一时钟使能信号联合指示芯片控制器根据第一时钟使能信号和寄存模块中寄存的单独时钟使能信息生成多个单独时钟使能信号。
第二方面，提供了一种内存，包括：多个内存芯片和如权利要求1至12中的任一项的芯片控制器。
第三方面提供了一种内存控制器，包括：生成模块，用于生成第一片选信号、第一单独片选指示信号和控制命令信号；输出模块，用于向芯片控制器输出第一片选信号和第一单独片选指示信号，其中第一单独片选指示信号和第一片选信号联合指示芯片控制器根据第一片选信号和芯片控制器中寄存的单独片选信息生成多个单独片选信号，单独片选信息用于生成多个单独片选信号，多个单独片选信号与多个内存芯片一一对应，第一片选信号用于指中的至示选择多个内存芯片，单独片选信息用于指示单独选择多个内存芯片少一个内存芯片，其中，输出模块还用于向多个内存芯片输出控制命令信号，以便多个内存芯片中的至少一个内存芯片根据芯片控制输出的多个单独片选信号执行与控制命令信号对应的操作。
结合第三方面，在第三方面的第一种可能的实现方式中，输出模块还用于向芯片控制器输出第一地址信号，地址信号携带单独片选信息和单独片选信息的地址信息。
结合第三方面的第一种可能的实现方式，在第三方面的第二种可能的实现 方式中，地址信号还携带片选策略信息，片选策略信息用于指示单独片选信息针对控制命令信号是否有效，其中，输出模块还用于向芯片控制器输出控制命令信号。
结合第三方面的第一种或第二种可能的实现方式，在第三方面的第三种可能的实现方式中，输出模块还用于向芯片控制器输出第二单独片选指示信号和第二片选信号，其中第二单独片选指示信号和第二片选信号联合指示芯片控制器根据地址信息寄存单独片选信息。
结合第三方面以及第三方面的第一种至第三种中的任一种可能的实现方式，在第三方面的第四种可能的实现方式中，输出模块还用于向芯片控制器输出第一时钟使能信号和第一单独时钟使能指示信号，其中第一时钟使能指示信号和第一时钟使能信号联合指示芯片控制器根据第一时钟使能信号和芯片控制器中寄存的单独时钟使能信息生成多个单独时钟使能信号，单独时钟使能信息用于生成多个单独时钟使能信号，多个单独时钟使能信号与多个内存芯片一一对应，第一时钟使能信号用于控制多个内存芯片的时钟信号，多个单独时钟使能信号分别用于单独控制多个内存芯片中的至少一个芯片的时钟信号。
结合第三方面的第四种可能的实现方式，在第三方面的第五种可能的实现方式中，输出模块还用于向芯片控制器输出第二地址信号，第二地址信号携带单独时钟使能信息和单独时钟使能信息的地址信息。
结合第三方面的第五种可能的实现方式，在第三方面的第六种可能的实现方式中，地址信号还携带时钟使能策略信息，时钟使能策略信息用于指示单独时钟使能信息针对控制命令信号是否有效。
结合第三方面的第四种至第六种中的任一种可能的实现方式，在第三方面的第七种可能的实现方式中，输出模块还用于向芯片控制器输出第二单独时钟使能指示信号和第二时钟使能信号，其中第二单独时钟使能指示信号和第二时钟使能信号联合指示芯片控制器根据第二地址信号寄存单独时钟使能信息
第四方面，提供了一种控制内存的方法，包括：芯片控制器接收内存控制器输出的第一片选信号；芯片控制器根据第一片选信号和芯片控制器中寄存的单独片选信息生成多个单独片选信号，其中多个单独片选信号与多个内存芯片一一对应，第一片选信号用于指示选择多个内存芯片，单独片选信息用于指示单独选择多个内存芯片中的至少一个内存芯片；芯片控制器分别向多个内存芯 片输出多个单独片选信号，以便多个内存芯片中的至少一个内存芯片根据内存控制器输出的控制命令信号执行与控制命令信号对应的操作。
结合第四方面，在第四方面的第一种可能的实现方式中，在芯片控制器根据第一片选信号和芯片控制器中寄存的单独片选信息生成多个单独片选信号之前，方法还包括：芯片控制器接收内存控制器输出的第一地址信号，第一地址信号携带单独片选信息和单独片选信息的地址信息；芯片控制器根据第一地址信号寄存单独片选信息。
结合第四方面的第一种可能的实现方式，在第四方面的第二种可能的实现方式中，第一地址信号还携带片选策略信息，片选策略信息寄存在芯片控制器中并且与单独片选信息相对应，片选策略信息用于指示单独片选信息针对控制命令信号是否有效，其中，该方法还包括：芯片控制器接收内存控制器输出的控制命令信号，其中，芯片控制器根据第一片选信号和芯片控制器中寄存的单独片选信息生成多个单独片选信号，包括：如果片选策略信息指示单独片选信息针对控制命令信号有效，则芯片控制器根据第一片选信号和单独片选信息生成多个单独片选信号。
结合第四方面以及第四方面的第一种或第二种可能的实现方式，在第四方面的第三种可能的实现方式中，该方法还包括：如果片选策略信息指示单独片选信息针对控制命令信号无效，则芯片控制器根据第一片选信号和预定的片选信息生成多个单独片选信号，预定的片选信息指示生成的多个单独片选信号选择对应的多个内存芯片。
结合第四方面以及第四方面的第一种或第三种可能的实现方式，在第四方面的第四种可能的实现方式中，该方法还包括：芯片控制器接收内存控制器输出的第二单独片选指示信号和第二片选信号，其中第二单独片选指示信号和第二片选信号联合指示芯片控制器根据第一地址信号寄存单独片选信息。
结合第四方面以及第四方面的第一种或第四种可能的实现方式，在第四方面的第五种可能的实现方式中，该方法还包括：芯片控制器接收内存控制器输出的第一单独片选指示信号，其中第一单独片选指示信号和第一片选信号联合指示芯片控制器根据第一片选信号和芯片控制器中寄存的单独片选信息生成多个单独片选信号。
结合第四方面以及第四方面的第一种或第五种可能的实现方式，在第四方 面的第六种可能的实现方式中，该方法还包括：芯片控制器接收内存控制器输出的第一时钟使能信号；芯片控制器根据第一时钟使能信号和芯片控制器中寄存的单独时钟使能信息生成多个单独时钟使能信号，多个单独时钟使能信号与多个内存芯片一一对应，第一时钟使能信号用于控制多个内存芯片的时钟信号，多个单独时钟使能信号分别用于单独控制多个内存芯片中的至少一个芯片的时钟信号；芯片控制器分别向多个内存芯片输出多个单独时钟使能信号。
结合第四方面的第六种可能的实现方式，在第四方面的第七种可能的实现方式中，在芯片控制器根据第一时钟使能信号和芯片控制器中寄存的单独时钟使能信息生成多个单独时钟使能信号之前，还包括：芯片控制器接收内存控制器输出的第二地址信号，地址信号携带单独时钟使能信息和单独时钟使能信息的地址信息，第二地址信号携带单独时钟使能信息和单独时钟使能信息的地址信息；芯片控制器根据第二地址信号寄存单独时钟使能信息。
结合第四方面的第七种可能的实现方式，在第四方面的第八种可能的实现方式中，第二地址信号还携带时钟使能策略信息，时钟使能策略信息寄存在芯片控制器中并且与单独时钟使能信息相对应，时钟使能策略信息用于指示单独时钟使能信息针对控制命令信号是否有效，其中，该方法还包括：芯片控制器接收内存控制器输出的控制命令信号，其中芯片控制器根据第一时钟使能信号和芯片控制器中寄存的单独时钟使能信息生成多个单独时钟使能信号，包括：
如果时钟使能策略信息指示单独时钟使能信息有效，则芯片控制器根据第一时钟使能信号和单独时钟使能信息生成多个单独时钟使能信号。
结合第四方面的第八种可能的实现方式，在第四方面的第九种可能的实现方式中，该方法还包括：如果时钟使能策略信息指示单独时钟使能信息针对控制命令信号无效，则芯片控制器根据第一时钟使能信号和预定的时钟使能信息生成多个单独时钟使能信号，生成的多个单独时钟使能信号选择对应的多个内存芯片。
结合第四方面的第六种至第九种中的任一种可能的实现方式，在第四方面的第十种可能的实现方式中，该方法还包括：芯片控制器接收内存控制器输出的第二单独时钟使能指示信号和第二时钟使能信号，其中第二单独时钟使能指示信号和第二时钟使能信号联合指示芯片控制器根据第二地址信号寄存单独时钟使能信息。
结合第四方面的第六种至第十种中的任一种可能的实现方式，在第四方面的第十一种可能的实现方式中，该方法还包括：芯片控制器接收内存控制器输出的第一时钟使能指示信号，其中第一时钟使能指示信号和第一时钟使能信号联合指示芯片控制器根据第一时钟使能信号和芯片控制器中寄存的单独时钟使能信息生成多个单独时钟使能信号。
第五方面，提供了一种控制内存芯片的方法，该方法包括：内存控制器向芯片控制器输出第一片选信号和第一单独片选指示信号，其中第一单独片选指示信号和第一片选信号联合指示芯片控制器根据第一片选信号和芯片控制器中寄存的单独片选信息生成多个单独片选信号，单独片选信息用于生成多个单独片选信号，多个单独片选信号与多个内存芯片一一对应，第一片选信号用于指示选择多个内存芯片，单独片选信息用于指示单独选择多个内存芯片中的至少一个内存芯片；内存控制器向多个内存芯片输出控制命令信号，以便多个内存芯片中的至少一个内存芯片根据芯片控制输出的多个单独片选信号执行与控制命令信号对应的操作。
结合第五方面，在第五方面的第一种可能的实现方式中，该方法还包括：内存控制器向芯片控制器输出第一地址信号，地址信号携带单独片选信息和单独片选信息的地址信息。
结合第五方面的第一种可能的实现方式，在第五方面的第二种可能的实现方式中，地址信号还携带片选策略信息，片选策略信息用于指示单独片选信息针对控制命令信号是否有效，其中，该方法还包括：内存控制器向芯片控制器输出控制命令信号。
结合第五方面的第一种和第二种可能的实现方式，在第五方面的第三种可能的实现方式中，该方法还包括：内存控制器向芯片控制器输出第二单独片选指示信号和第二片选信号，其中第二单独片选指示信号和第二片选信号联合指示芯片控制器根据地址信息寄存单独片选信息。
结合第五方面以及第五方面的第一种至第三种的任一种可能的实现方式，在第五方面的第四种可能的实现方式中，该方法还包括：内存控制器向芯片控制器输出第一时钟使能信号和第一单独时钟使能指示信号，其中第一时钟使能指示信号和第一时钟使能信号联合指示芯片控制器根据第一时钟使能信号和芯片控制器中寄存的单独时钟使能信息生成多个单独时钟使能信号，单独时钟 使能信息用于生成多个单独时钟使能信号，多个单独时钟使能信号与多个内存芯片一一对应，第一时钟使能信号用于控制多个内存芯片的时钟信号，多个单独时钟使能信号分别用于单独控制多个内存芯片中的至少一个芯片的时钟信号。
结合第五方面的第四种可能的实现方式，在第五方面的第五种可能的实现方式中，该方法还包括：内存控制器向芯片控制器输出第二地址信号，第二地址信号携带单独时钟使能信息和单独时钟使能信息的地址信息。
结合第五方面的第五种可能的实现方式，在第五方面的第六种可能的实现方式中，地址信号还携带时钟使能策略信息，时钟使能策略信息用于指示单独时钟使能信息针对控制命令信号是否有效。
结合第五方面的第四种至第六种中的任一种可能的实现方式，在第五方面的第七种可能的实现方式中，该方法还包括：内存控制器向芯片控制器输出第二单独时钟使能指示信号和第二时钟使能信号，其中第二单独时钟使能指示信号和第二时钟使能信号联合指示芯片控制器根据第二地址信号寄存单独时钟使能信息。
因此，本发明的技术方案通过在芯片控制器中寄存单独片选信息，根据从内存控制器接收到的片选信号和寄存的单独片选信息生成多个单独片选信号，并且分别向所述多个内存芯片输出所述多个单独片选信号。由于芯片控制器中寄存了单独片选信息，因此无需内存控制器针对每个命令都发送单独片选信息，从而减少了对传输带宽的占用。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对本发明实施例中所需要使用的附图作简单地介绍，显而易见地，下面所描述的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是根据本发明的实施例的内存系统的示意性结构图。
图2是根据本发明的实施例的芯片控制器的示意性结构图。
图3是根据本发明的实施例的内存控制器的示意性结构图。
图4是根据本发明实施例的控制内存芯片的方法的示意性流程图。
图5A是根据本发明的实施例的内存系统的信号流的示意图。
图5B是根据本发明的实施例的芯片控制器的信号流的示意图。
图6是根据本发明的实施例的芯片控制器的控制方法的示意性流程图。
图7是根据本发明的另一实施例的控制内存芯片的方法的示意性流程图。
图8是根据本发明的又一实施例的控制内存芯片的方法的示意性流程图。
图9是根据本发明的实施例的芯片控制器的示意性结构图。
图10是根据本发明的实施例的内存的示意性结构图。
图11是根据本发明的实施例的内存控制器的示意性结构图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图1是根据本发明实施例的内存系统100的示意性结构图。内存系统100包括内存控制器110和内存120。
内存控制器110用于控制内存120与中央处理器(Central Processing Unit，CPU)之间的数据交换。内存120包括芯片控制器121和多个内存芯片122。芯片控制器121位于内存控制器110与内存芯片122之间，用于控制内存控制器110对内存芯片122的操作。内存控制器110与内存120之间通过通信总线进行通信。应理解，芯片控制器121还可以位于内存之外，换句话说，芯片控制器121与内存芯片122可以是分离的。内存控制器110与中央处理器(CPU)可以是分离的，也可以整合到CPU中。
还应理解，本发明的实施例的技术方案可以应用于多种不同的内存组织形式，例如内存120可以采用双列直插式存储模块(DIMM)的形式，也可以采用其他形式，例如，也可以是芯片控制器和处理器在一块单板上。或者芯片控制器作为其他形式的子卡或子板。
芯片控制器121与内存芯片122相连接，例如，可以使控制命令信号和地址信号从DIMM的一侧输入到芯片中，可以使单独片选信号和/或单独时钟使 能信号从DIMM的另一侧输入到芯片中。然而，应理解，本发明的实施例并不限定于这种方式。
芯片控制器121和内存控制器110之间的接口可以传输双倍速率同步随机存储器(DDR)传输标准中的地址(ADDRESS)信号、控制命令(CMD)信号，片选(CS)信号和时钟使能(CKE)信号等等，除此之外，芯片控制器121和内存控制器110之间的接口还可以传输指示信号，例如，这种指示信号可以用于寄存模块确定寄存单独片选信息和单独时钟使能信息，这种指示信号还可以用于控制模块确定对片选信号和时钟使能信号进行处理。
内存控制器110与中央处理器(CPU)相连接并受中央处理器控制。
图2是根据本发明实施例的芯片控制器200的示意性结构图。芯片控制器200是图1的芯片控制器121的例子。芯片控制器200包括：寄存模块210和控制模块220。
控制模块220用于：接收内存控制器输出的第一片选信号；根据第一片选信号和寄存模块210寄存的单独片选信息生成多个单独片选信号，其中多个单独片选信号与多个内存芯片一一对应，第一片选信号用于指示选择多个内存芯片，单独片选信息用于指示单独选择多个内存芯片中的至少一个内存芯片；分别向多个内存芯片输出多个单独片选信号，以便多个内存芯片中的至少一个内存芯片根据内存控制器输出的控制命令信号执行与控制命令信号对应的操作。
因此，本发明的技术方案通过在芯片控制器中寄存单独片选信息，根据片选信号和寄存的单独片选信息生成多个单独片选信号，并且分别向所述多个内存芯片输出所述多个单独片选信号。由于芯片控制器中寄存了单独片选信息，因此无需内存控制器针对每个命令都发送单独片选信息，从而减少了对传输带宽的占用。
可选地，作为另一实施例，芯片控制器200还可以包括另一寄存模块，其中控制模块220输出的信号给另一寄存模块。该寄存模块用于缓存和重新驱动信号。在信号质量良好和时序裕量充足的情况下，可以省略该寄存模块。
芯片控制器200的输入信号可以是内存控制器输出的CMD、ADDRESS、CS、CKE信号和指示信号，输出信号可以是对应各个芯片的单独片选信号和单独时钟使能信号。每个单独片选信号用于控制该单独片选信号对应的芯片执行特定的操作命令。每个单独时钟使能信号用于控制该单独时钟使能信号对应 的芯片处于睡眠模式。
应理解，芯片控制器可以通过通信总线接收内存控制器输出的第一片选信号。具体而言，第一片选信号指示选择内存条中的所有内存芯片以进行操作，例如，写入操作或读取操作，本发明的实施例并不限于此，例如，操作还可以包括激活、预充电或刷新等操作。换句话说，每个内存芯片都接收第一片选信号以执行控制命令信号指示的操作。单独片选信号与内存芯片一一对应，单独片选信号指示选中其对应的内存芯片进行控制命令信号指示的操作。
还应理解，单独片选信号选择与其对应的内存芯片执行操作时，可以设定单独片选信号为高电平时或者低电平时有效，本发明的实施例对此不作限定。
根据本发明的实施例，寄存模块还用于：在控制模块根据第一片选信号和寄存模块寄存的单独片选信息生成多个单独片选信号之前，接收内存控制器输出的第一地址信号，第一地址信号携带单独片选信息和单独片选信息的地址信息；根据第一地址信号寄存单独片选信息。
应理解，地址信号指示寄存模块寄存单独片选信息。例如，可以是寄存模块根据指示寄存操作的控制命令信号和地址信号来寄存单独片选信息。也可以是，寄存模块根据地址信号寄存单独片选信息。还应理解，可以在每次内存芯片的完整操作过程中只发送一次，也可以发送多次。例如内存控制器只在数据的一次完整写入、读取或刷新操作的过程中的第一个控制命令信号之前发送携带单独片选信息的信号，控制模块在该操作中针对内存芯片以后的控制命令信号调用寄存模块寄存的单独片选信息。
由于寄存了单独片选信息，使得芯片控制器可以在需要时获取该单独片选信息，从而芯片控制器不需要针对每个控制命令信号接收单独片选信息，节省了带宽，提高了控制芯片的灵活性。
根据本发明的实施例，第一地址信号还携带片选策略信息，片选策略信息寄存在寄存模块中并且与单独片选信息相对应，片选策略信息用于指示单独片选信息针对控制命令信号是否有效，控制模块还用于接收内存控制器输出的控制命令信号，其中，控制模块用于在片选策略信息指示单独片选信息针对控制命令信号有效时，根据第一片选信号和单独片选信息生成多个单独片选信号。如果片选策略信息指示单独片选信息针对控制命令信号无效，则控制模块根据第一片选信号和预定的片选信息生成多个单独片选信号，预定的片选信息指示 生成的多个单独片选信号选中对应的多个内存芯片。
具体而言，可以针对单独片选信息设定对应的片选策略信息。换句话说，该片选策略信息与单独片选信息和预定的控制命令信号都存在映射关系。在这种情况下，控制模块在调用寄存模块中寄存的信息时，不选择调用单独片选信息，而只调用对应的片选策略信息。
例如，策略信息指示单独片选信息针对刷新命令有效，则芯片控制器在接收到刷新命令的情况下，根据单独片选信息输出单独片选信号。应理解，控制命令信号还可以是诸如写操作命令信号、读操作命令信号或激活(Activate，ACT)命令信号中的任一个。
又例如，策略信息指示单独片选信号针对读取命令信号无效，则芯片控制器根据预定的片选信息生成并输出多个单独片选信号。例如，如果策略信息指示单独片选信息针对读命令无效，则芯片控制器在接收到读命令的情况下，不会输出单独片选信号，而是输出第一片选信号。应理解，控制命令信号还可以是ACT命令信号、刷新命令信号、写操作信号中的任一个。预定的片选信息可以设置为默认，具体而言，可以指示芯片控制器选中所有的内存芯片。
由于采用了策略信息，并针对不同的控制命令定义了不同的策略，使得针对不必要输出单独片选信号的控制命令只输出一个片选信号，而不会输出多个单独片选信号，从而减少了不必要的信息的传输，提高了带宽的利用率。
根据本发明的实施例，寄存模块还用于接收内存控制器输出的第二单独片选指示信号和第二片选信号，其中第二单独片选指示信号和第二片选信号联合指示寄存模块根据第一地址信号寄存单独片选信息。
应理解，第一片选信号与第二片选信号携带相同的片选命令。第二片选信号指示寄存单独片选信息，第一片选信号指示根据所寄存的单独片选信息输出单独片选信号。第二单独片选指示信号和第二片选信号用于指示芯片控制器根据第一地址信号寄存单独片选信息，例如，芯片控制器可以在第二单独片选指示信号和第二片选信号同时有效时，寄存第一地址信号中携带的单独片选信息。具体而言，可以在第二单独片选指示信号为高电平时，将其确定为有效，并且在第二片选信号为低电平时，将第二片选信号确定为有效。应理解，也可以在第二单独片选指示信号为低电平时，确定为有效，并且在第二片选信号为高电平时，将第二片选信号确定为有效。
由于芯片控制器可以第二单独片选指示信号和第二片选信号来判断是否寄存单独片选信息，使得在不需要寄存单独片选信息时，芯片控制器不进行寄存的操作，只是转发接收的信号，从而增强了内存控制器对芯片控制器控制的灵活性，同时提高了带宽的利用率。
根据本发明的实施例，控制模块还用于接收内存控制器输出的第一单独片选指示信号，其中第一单独片选指示信号和第一片选信号联合指示控制模块根据第一片选信号和寄存模块中寄存的单独片选信息生成多个单独片选信号。
应理解，第一单独片选指示信号和第一片选信号联合指示芯片控制器根据第一片选信号和芯片控制器中寄存的单独片选信息生成多个单独片选信号。与第二单独片选指示信号和第二片选信号相似，例如，芯片控制器可以在第一单独片选指示信号和第一片选信号同时有效时，处理单独片选信息，并根据单独片选信息生成单独片选信号。具体而言，与第二单独片选指示信号相似，可以将第一单独片选指示信号在高电平或者在低电平时确定为有效。与第二片选信号相似，可以将第一片选信号在高电平或者在低电平时确定为有效。
由于芯片控制器可以根据第一单独片选指示信号和第一片选信号判断是否生成单独片选信号，使得芯片控制器在不需要输出单独片选信号时不进行相应的操作，从而增强了内存控制器对芯片控制器控制的灵活性，进一步增强了内存控制器对内存芯片控制的灵活性。
根据本发明的实施例，控制模块还用于接收内存控制器输出的第一时钟使能指示信号、第一时钟使能信号，第一时钟使能指示信号和第一时钟使能信号联合指示芯片控制器根据第一时钟使能信号和芯片控制器中寄存的单独时钟使能信息生成多个单独时钟使能信号，寄存模块还用于接收内存控制器输出的第二单独时钟使能指示信号、第二时钟使能信号和第二地址信号，第二单独时钟使能指示信号和第二时钟使能信号联合指示芯片控制器根据第二地址信号寄存单独时钟使能信息，第二地址信号携带单独时钟使能信息、单独时钟使能信息的地址信息。
应理解，时钟使能信号和片选信号相似，时钟使能信号指示选择多个内存芯片执行控制命令信号指示的操作。单独片选信号与单独时钟使能信号相似，例如，可以设定单独时钟使能信号为高电平或者低电平时为有效。
应理解，地址信号指示寄存模块寄存单独时钟使能信息。例如，可以是寄 存模块根据指示寄存操作的控制命令信号和地址信号来寄存单独时钟使能信息。也可以是，寄存模块根据地址信号寄存单独时钟使能信息。
还应理解，携带单独时钟使能信息的信号可以在每次内存芯片的完整操作过程中只发送一次，也可以发送多次。例如内存控制器只在数据的一次完整写入、读取或刷新操作的过程中的第一个控制命令信号之前发送携带单独时钟使能信息的信号，控制模块在该操作中针对内存芯片以后的控制命令信号调用寄存模块寄存的单独时钟使能信息。
具体而言，可以针对单独时钟使能信息设定对应的时钟使能策略信息。换句话说，该时钟使能策略信息与单独时钟使能信息和预定的控制命令信号都存在映射关系。在这种情况下，控制模块在调用寄存模块中寄存的信息时，不选择调用单独时钟使能信息，而只调用对应的时钟使能策略信息。
例如，策略信息指示单独时钟使能信息针对ACT命令有效，则芯片控制器在ACT命令的情况下，根据单独时钟使能信息输出单独时钟使能信号。应理解，控制命令信号还可以是诸如写操作命令信号、读操作命令信号或刷新命令信号中的任一个。
应理解，第一时钟使能信号与第二时钟使能信号携带相同的时钟使能命令。第二时钟使能信号指示寄存单独时钟使能信息，第一时钟使能信号指示根据所寄存的单独时钟使能信息输出单独时钟使能信号。第二单独时钟使能指示信号和第二时钟使能信号用于指示芯片控制器根据第一地址信号寄存单独时钟使能信息，例如，芯片控制器可以在第二单独时钟使能指示信号和第二时钟使能信号同时有效时，寄存单独时钟使能信息。具体而言，可以在第二单独时钟使能指示信号为高电平时，将其确定为有效，并且在第二时钟使能信号为低电平时，将第二时钟使能信号确定为有效。应理解，也可以在第二单独时钟使能指示信号为低电平时，确定为有效，并且在第二时钟使能信号为高电平时，将第二时钟使能信号确定为有效。
应理解，第一单独时钟使能指示信号和第一时钟使能信号联合指示芯片控制器根据第一时钟使能信号和芯片控制器中寄存的单独时钟使能信息生成多个单独时钟使能信号。与第二单独时钟使能指示信号也第二时钟使能信号相似，例如，可以在芯片控制器可以在第一单独时钟使能指示信号和第一时钟使能信号同时有效时，处理单独时钟使能信息，并根据单独时钟使能信息生成单 独时钟使能信号。具体而言，与第二单独时钟使能指示信号相似，可以将第一单独时钟使能指示信号在高电平或者在低电平时确定为有效。与第二时钟使能信号相似，可以将第一时钟使能信号在高电平或者在低电平时确定为有效。
由于针对每个内存芯片输出单独时钟使能信号，使得内存芯片在不需要时钟信号的情况下，不接受时钟信号的命令。由于生成了单独时钟使能信号，从而使芯片控制器可以单独控制芯片，例如使特定的芯片处于睡眠模式，从而降低芯片的功耗。
图3是根据本发明的另一实施例的内存控制器的示意性结构图。该内存控制器300包括：生成模块310，用于生成第一片选信号、第一单独片选指示信号和控制命令信号；输出模块320，用于向芯片控制器输出第一片选信号和第一单独片选指示信号，其中第一单独片选指示信号和第一片选信号联合指示芯片控制器根据第一片选信号和芯片控制器中寄存的单独片选信息生成多个单独片选信号，单独片选信息用于生成多个单独片选信号，多个单独片选信号与多个内存芯片一一对应，第一片选信号用于指中的至示选择多个内存芯片，单独片选信息用于指示单独选择多个内存芯片少一个内存芯片；输出模块还用于向多个内存芯片输出控制命令信号，以便多个内存芯片中的至少一个内存芯片根据芯片控制输出的多个单独片选信号执行与控制命令信号对应的操作。
因此，本发明的技术方案通过在芯片控制器中寄存单独片选信息，根据片选信号和寄存的单独片选信息生成多个单独片选信号，并且分别向所述多个内存芯片输出所述多个单独片选信号。由于芯片控制器中寄存了单独片选信息，因此无需内存控制器针对每个命令都发送单独片选信息，从而减少了对传输带宽的占用。
根据本发明的实施例，输出模块还用于向芯片控制器输出第一地址信号，地址信号携带单独片选信息和单独片选信息的地址信息。
根据本发明的实施例，地址信号还携带片选策略信息，片选策略信息用于指示单独片选信息针对控制命令信号是否有效，其中，输出模块还用于向芯片控制器输出控制命令信号。
根据本发明的实施例，输出模块还用于向芯片控制器输出第二单独片选指示信号和第二片选信号，其中第二单独片选指示信号和第二片选信号联合指示芯片控制器根据地址信息寄存单独片选信息。
图4是本发明的一个实施例的控制内存芯片的方法的示意性流程图。图5A是根据本发明的实施例的内存系统的信号流的示意图。图5B是根据本发明的实施例的芯片控制器的信号流的示意图。
下面结合图5A和图5B来描述图4所描述的方法，其中图5A示出了内存控制器、芯片控制器以及内存芯片之间的信号传输方法。图5B具体地示出了芯片控制器中的控制模块针对多个信号所执行的操作。
在该实施例中，为了方便描述，第一单独片选指示信号、第二单独片选指示信号、第一单独时钟使能指示信号和第二单独时钟使能指示信号统称为指示信号，第一地址信号和第二地址信号统称为地址信号，第一片选信号和第二片选信号统称为片选信号，第一时钟使能信号和第二时钟使能信号统称为时钟使能信号。此外，本实施例采用DRAM芯片构成的DIMM内存条。
410，寄存模块接收内存控制器输出的总线命令信号。
总线命令信号包括地址信号、控制命令信号、片选信号、时钟使能信号以及指示信号。
420，寄存模块根据第二片选信号和第二单独片选指示信号确定寄存单独片选信息，寄存模块根据第二时钟使能信号和第二单独时钟使能指示信号确定寄存单独时钟使能信息。
例如，当第二片选信号和第二单独片选指示信号同时有效时，表示寄存模块确定寄存单独片选信息。当第二时钟使能信号和第二单独时钟使能指示信号同时有效时，表示寄存模块确定寄存单独时钟使能信息。例如，可以使第二片选信号预定为高电平时有效，使第二单独片选指示信号和第二单独时钟使能指示信号预定为低电平时有效，并使第二时钟使能信号预定为高电平时有效。
430，寄存模块寄存单独芯片选择信息以及单独时钟使能信息。
地址信号携带单独片选信息、单独时钟使能信息以及单独片选信息的地址信息和单独时钟使能信息的地址信息。内存控制器通过总线中的地址信号和控制命令信号将单独片选信息以及单独时钟使能信息写入到寄存模块中。寄存模块又分为片选寄存模块和时钟使能寄存模块，分别用于寄存单独片选信息和单独时钟使能信息，例如，表1示出了寄存模块所寄存的单独片选信息和单独时钟使能信息分别具有特定地址a0和a1。
表1
寄存的参数的地址 寄存的参数类型
a0 单独片选信息
a1 单独时钟使能信息
440，寄存模块寄存针对单独片选信息的片选策略信息，该片选策略信息用于指示单独片选信息的应用策略。寄存模块寄存还针对单独时钟使能信息的时钟使能策略信息，该时钟使能策略信息用于指示单独时钟使能信息的应用策略。
例如，该片选策略信息指示针对ACT命令信号单独片选信息是否有效。例如，该时钟策略信息指示针对ACT命令信号单独时钟使能信息是否有效。
例如，可以将片选策略信息定义为针对ACT命令的策略信息，即当控制模块接收ACT命令的信号时，根据该策略信息确定是否根据单独片选信息输出单独片选信号。如果该策略信息仍然指示根据单独片选信息输出单独片选信号，则控制模块根据单独片选信息输出单独片选信号。如果策略信息指示按照预定的默认信息输出片选信号，则控制模块按照预定的默认信息输出片选信号，例如，控制模块将默认信息设置为指示所有单独片选信号都输出有效，而忽略单独片选信息。换句话说，与片选信号相似，使所有单独片选信号都指示对应的内存芯片进行执行ACT命令。其它控制命令如读取命令或刷新命令等操作命令与ACT命令类似，在此不再赘述。
同样，可以将时钟使能策略信息定义为针对ACT命令的策略信息，即当控制模块接收ACT命令的信号时，根据该策略信息确定是否根据单独片选信息输出单独片选信号。应理解，在本实施例中，对片选信号和时钟使能信号采用相似操作，例如，对单独片选信号和单独时钟使能信号的策略信息的定义为针对同一控制命令，然而，也可以将其定义为针对不同控制命令的策略信息。
450，控制模块接收总线命令信号中的控制命令信号、片选信号、时钟使能信号以及指示信号。
460，控制模块根据片选信号和指示信号确定对该片选信号进行处理，并根据时钟使能信号和指示信号确定对时钟使能信号进行处理。
控制模块用于根据寄存模块寄存的信息，生成并输出DIMM内存条内各 个DRAM芯片的单独片选信号和单独时钟使能信号。
如图5所示，控制模块220包括片选控制模块221和时钟使能控制模块222。寄存模块210包括片选寄存模块211和时钟使能寄存模块212。寄存模块210包括片选寄存模块211和时钟使能寄存模块212分别用于寄存片选相关信息和时钟使能相关信息。该片选控制模块221生成并输出对应各个DRAM芯片的单独片选信号，该时钟使能控制模块222生成并输出对应各个DRAM芯片的单独时钟使能信号。
470，控制模块确定存在策略信息。
寄存模块中存在策略信息，因此控制模块按照策略信息来判断，应理解，如果没有策略信息，则根据单独片选信息判断。
480，控制模块根据接收的控制命令信号确定采用针对控制命令信号的策略信息。
例如，由于该ACT命令存在对应的策略信息，而该策略信息指示根据单独片选信息和单独使能信息输出信号，因此控制模块不是根据预定的片选信息以及预定的时钟使能信息输出，而是根据单独片选信息和单独时钟使能信息输出单独片选信号和单独时钟使能信号。
490，控制模块向内存芯片输出单独片选信号和单独时钟使能信号。
每个内存芯片接收对应的单独片选信号以及单独时钟使能信号。例如，对应内存芯片的单独片选信号指示该芯片在写操作命令的情况下处于不选中状态，则内存芯片接收到该信号之后，不进行写操作。
应理解，寄存模块也可以不寄存单独时钟使能信息，相应地，控制模块也可以不对时钟使能信号做处理，即不利用时钟使能信号生成单独时钟使能信号。
图6是根据本发明的实施例的芯片控制器的控制方法的流程图。在本实施例中，为了描述简洁与方便，只以片选信号为例。控制模块对时钟使能信号和对片选信号的判断和操作的相似的，在此不再赘述。还应理解，本实施例采用DIMM形式的DRAM芯片，但本发明的实施例并不限于此。
610，从内存控制器接收总线的信号，包括地址信号、指示信号、片选信号以及控制命令信号。
620，根据片选信号和指示信号判断是否对片选信号进行处理。
具体而言，在片选信号和指示信号都有效时，表示芯片控制器对该片选信号进行处理。换句话说，该片选信号是针对该芯片控制器所控制的DIMM内的DRAM芯片的命令。当片选信号和指示信号不同时有效时，表示该芯片控制器不对片选信号做任何处理。如果判断的结果为是，则执行640，如果判断的结果为否，则执行630。
630，芯片控制器将片选信号输出到内存芯片，而不生成并且不输出单独片选信号，即单独片选信号为非选中状态。
640，芯片控制器选择处理片选信号，进一步地，控制模块通过寄存模块判断此控制命令是否有相应的策略信息。如果判断的结果为是，即存在预定的策略信息，则执行660，如果判断的结果为否，即不存在预定的策略信息，则执行650。
650，控制模块根据单独片选信息生成并输出单独片选信号。
660，控制模块根据策略信息判断按照单独片选信息输出或者按照预定的片选信息输出。例如，预定的片选信息可以是默认信息。
670，如果策略信息指示按照预定的片选信息输出，例如，按照默认信息，则控制模块按照默认信息生成并输出相应的信号。具体而言，可以将默认信息设置为指示所有单独片选信号都指示有效，而忽略单独片选信息。换句话说，由于多个单独片选信息都指示有效，多个内存芯片接收到多个单独片选信号的情况与接收到片选信号的情况相似，所有单独片选信号都指示对应的内存芯片进行操作，例如，进行激活或刷新等操作。如果策略信息指示不按照默认输出，则控制模块执行650，即控制模块根据单独片选信息生成并输出单独片选信号。
图7是根据本发明的一个实施例的控制内存芯片的方法的示意性流程图。图7的方法由芯片控制器来执行，包括以下内容。
710，芯片控制器接收内存控制器输出的第一片选信号。
720，芯片控制器根据第一片选信号和芯片控制器中寄存的单独片选信息生成多个单独片选信号，其中多个单独片选信号与多个内存芯片一一对应，第一片选信号用于指示选择多个内存芯片，单独片选信息用于指示单独选择多个内存芯片中的至少一个内存芯片。
730，芯片控制器分别向多个内存芯片输出多个单独片选信号，以便多个 内存芯片中的至少一个内存芯片根据内存控制器输出的控制命令信号执行与控制命令信号对应的操作。
因此，本发明的技术方案通过在芯片控制器中寄存单独片选信息，根据从内存控制器接收到的片选信号和寄存的单独片选信息生成多个单独片选信号，并且分别向多个内存芯片输出多个单独片选信号。由于芯片控制器中寄存了单独片选信息，因此无需内存控制器针对每个命令都发送单独片选信息，从而减少了对传输带宽的占用。
可选地，作为另一实施例，在芯片控制器根据第一片选信号和芯片控制器中寄存的单独片选信息生成多个单独片选信号之前，图7的方法还包括：芯片控制器接收内存控制器输出的第一地址信号，第一地址信号携带单独片选信息和单独片选信息的地址信息；芯片控制器根据第一地址信号寄存单独片选信息。
根据本发明的实施例，第一地址信号还携带片选策略信息，片选策略信息寄存在芯片控制器中并且与单独片选信息相对应，片选策略信息用于指示单独片选信息针对控制命令信号是否有效，其中，方法还包括：芯片控制器接收内存控制器输出的控制命令信号，其中，芯片控制器根据第一片选信号和芯片控制器中寄存的单独片选信息生成多个单独片选信号，包括：如果片选策略信息指示单独片选信息针对控制命令信号有效，则芯片控制器根据第一片选信号和单独片选信息生成多个单独片选信号。
可选地，作为另一实施例，图7的方法还包括：如果片选策略信息指示单独片选信息针对控制命令信号无效，则芯片控制器根据第一片选信号和预定的片选信息生成多个单独片选信号，预定的片选信息指示生成的多个单独片选信号选择对应的多个内存芯片。
可选地，作为另一实施例，图7的方法还包括：芯片控制器接收内存控制器输出的第二单独片选指示信号和第二片选信号，其中第二单独片选指示信号和第二片选信号联合指示芯片控制器根据第一地址信号寄存单独片选信息。
可选地，作为另一实施例，图7的方法还包括：芯片控制器接收内存控制器输出的第一单独片选指示信号，其中第一单独片选指示信号和第一片选信号联合指示芯片控制器根据第一片选信号和芯片控制器中寄存的单独片选信息生成多个单独片选信号。
可选地，作为另一实施例，图7的方法还包括：芯片控制器接收内存控制器输出的第一时钟使能信号；芯片控制器根据第一时钟使能信号和芯片控制器中寄存的单独时钟使能信息生成多个单独时钟使能信号，多个单独时钟使能信号与多个内存芯片一一对应，第一时钟使能信号用于控制多个内存芯片的时钟信号，多个单独时钟使能信号分别用于单独控制多个内存芯片中的至少一个芯片的时钟信号；芯片控制器分别向多个内存芯片输出多个单独时钟使能信号。
可选地，作为另一实施例，在芯片控制器根据第一时钟使能信号和芯片控制器中寄存的单独时钟使能信息生成多个单独时钟使能信号之前，图7的方法还包括：芯片控制器接收内存控制器输出的第二地址信号，地址信号携带单独时钟使能信息和单独时钟使能信息的地址信息，第二地址信号携带单独时钟使能信息和单独时钟使能信息的地址信息；芯片控制器根据第二地址信号寄存单独时钟使能信息。
根据本发明的实施例，第二地址信号还携带时钟使能策略信息，时钟使能策略信息寄存在芯片控制器中并且与单独时钟使能信息相对应，时钟使能策略信息用于指示单独时钟使能信息针对控制命令信号是否有效，其中，方法还包括：芯片控制器接收内存控制器输出的控制命令信号，其中芯片控制器根据第一时钟使能信号和芯片控制器中寄存的单独时钟使能信息生成多个单独时钟使能信号，包括：如果时钟使能策略信息指示单独时钟使能信息有效，则芯片控制器根据第一时钟使能信号和单独时钟使能信息生成多个单独时钟使能信号。
可选地，作为另一实施例，图7的方法还包括：如果时钟使能策略信息指示单独时钟使能信息针对控制命令信号无效，则芯片控制器根据第一时钟使能信号和预定的时钟使能信息生成多个单独时钟使能信号，生成的多个单独时钟使能信号选择对应的多个内存芯片。
可选地，作为另一实施例，图7的方法还包括：芯片控制器接收内存控制器输出的第二单独时钟使能指示信号和第二时钟使能信号，其中第二单独时钟使能指示信号和第二时钟使能信号联合指示芯片控制器根据第二地址信号寄存单独时钟使能信息。
可选地，作为另一实施例，图7的方法还包括：芯片控制器接收内存控制器输出的第一时钟使能指示信号，其中第一时钟使能指示信号和第一时钟使能 信号联合指示芯片控制器根据第一时钟使能信号和芯片控制器中寄存的单独时钟使能信息生成多个单独时钟使能信号。
图8是根据本发明的另一实施例的控制内存芯片的方法的示意性流程图。图8的方法由内存控制器执行，包括以下内容。
810，内存控制器向芯片控制器输出第一片选信号和第一单独片选指示信号，其中第一单独片选指示信号和第一片选信号联合指示芯片控制器根据第一片选信号和芯片控制器中寄存的单独片选信息生成多个单独片选信号，单独片选信息用于生成多个单独片选信号，多个单独片选信号与多个内存芯片一一对应，第一片选信号用于指示选择多个内存芯片，单独片选信息用于指示单独选择多个内存芯片中的至少一个内存芯片。
820，内存控制器向多个内存芯片输出控制命令信号，以便多个内存芯片中的至少一个内存芯片根据芯片控制输出的多个单独片选信号执行与控制命令信号对应的操作。
因此，本发明的技术方案通过在芯片控制器中寄存单独片选信息，根据从内存控制器接收到的片选信号和寄存的单独片选信息生成多个单独片选信号，并且分别向多个内存芯片输出多个单独片选信号。由于芯片控制器中寄存了单独片选信息，因此无需内存控制器针对每个命令都发送单独片选信息，从而减少了对传输带宽的占用。
可选地，作为另一实施例，图8的方法还包括：内存控制器向芯片控制器输出第一地址信号，地址信号携带单独片选信息和单独片选信息的地址信息。
根据本发明的实施例，地址信号还携带片选策略信息，片选策略信息用于指示单独片选信息针对控制命令信号是否有效，其中，方法还包括：内存控制器向芯片控制器输出控制命令信号。
可选地，作为另一实施例，图8的方法还包括：内存控制器向芯片控制器输出第二单独片选指示信号和第二片选信号，其中第二单独片选指示信号和第二片选信号联合指示芯片控制器根据地址信息寄存单独片选信息。
可选地，作为另一实施例，图8的方法还包括：内存控制器向芯片控制器输出第一时钟使能信号和第一单独时钟使能指示信号，其中第一时钟使能指示信号和第一时钟使能信号联合指示芯片控制器根据第一时钟使能信号和芯片控制器中寄存的单独时钟使能信息生成多个单独时钟使能信号，单独时钟使能 信息用于生成多个单独时钟使能信号，多个单独时钟使能信号与多个内存芯片一一对应，第一时钟使能信号用于控制多个内存芯片的时钟信号，多个单独时钟使能信号分别用于单独控制多个内存芯片中的至少一个芯片的时钟信号。
可选地，作为另一实施例，图8的方法还包括：内存控制器向芯片控制器输出第二地址信号，第二地址信号携带单独时钟使能信息和单独时钟使能信息的地址信息。
根据本发明的实施例，地址信号还携带时钟使能策略信息，时钟使能策略信息用于指示单独时钟使能信息针对控制命令信号是否有效。
可选地，作为另一实施例，图8的方法还包括：内存控制器向芯片控制器输出第二单独时钟使能指示信号和第二时钟使能信号，其中第二单独时钟使能指示信号和第二时钟使能信号联合指示芯片控制器根据第二地址信号寄存单独时钟使能信息。
图9是根据本发明的一个实施例的芯片控制器的示意性结构图。芯片控制器900包括：寄存器910和控制器920，寄存器910和控制器920相连接，其中寄存器910用于寄存单独片选信息；控制器920用于：接收内存控制器输出的第一片选信号；根据第一片选信号和输出寄存器寄存的单独片选信息生成多个单独片选信号，其中多个单独片选信号与多个内存芯片一一对应，第一片选信号用于指示选择多个内存芯片，单独片选信息用于指示单独选择多个内存芯片中的至少一个内存芯片；分别向多个内存芯片输出多个单独片选信号，以便多个内存芯片中的至少一个内存芯片根据内存控制器输出的控制命令信号执行与控制命令信号对应的操作。
因此，本发明的技术方案通过在芯片控制器中寄存单独片选信息，根据从内存控制器接收到的片选信号和寄存的单独片选信息生成多个单独片选信号，并且分别向多个内存芯片输出多个单独片选信号。由于芯片控制器中寄存了单独片选信息，因此无需内存控制器针对每个命令都发送单独片选信息，从而减少了对传输带宽的占用。
根据本发明的实施例，寄存器还用于：在控制器根据第一片选信号和寄存器寄存的单独片选信息生成多个单独片选信号之前，接收内存控制器输出的第一地址信号，第一地址信号携带单独片选信息和单独片选信息的地址信息；根据第一地址信号寄存单独片选信息。
根据本发明的实施例，第一地址信号还携带片选策略信息，片选策略信息寄存在芯片控制器中并且与单独片选信息相对应，片选策略信息用于指示单独片选信息针对控制命令信号是否有效，控制器还用于接收内存控制器输出的控制命令信号，根据第一片选信号和芯片控制器中寄存的单独片选信息生成多个单独片选信号，包括：如果片选策略信息指示单独片选信息针对控制命令信号有效，则根据第一片选信号和单独片选信息生成多个单独片选信号；如果片选策略信息指示单独片选信息针对控制命令信号无效，则根据第一片选信号和预定的片选信息生成多个单独片选信号，预定的片选信息指示生成的多个单独片选信号选择对应的多个内存芯片。
根据本发明的实施例，寄存器还用于接收内存控制器输出的第二单独片选指示信号和第二片选信号，其中第二单独片选指示信号和第二片选信号联合指示芯片控制器根据第一地址信号寄存单独片选信息。
根据本发明的实施例，控制器还用于接收内存控制器输出的第一单独片选指示信号，其中第一单独片选指示信号和第一片选信号联合指示芯片控制器根据第一片选信号和芯片控制器中寄存的单独片选信息生成多个单独片选信号。
根据本发明的实施例，控制器还用于接收内存控制器输出的第一时钟使能指示信号、第一时钟使能信号，第一时钟使能指示信号和第一时钟使能信号联合指示芯片控制器根据第一时钟使能信号和芯片控制器中寄存的单独时钟使能信息生成多个单独时钟使能信号，寄存器还用于接收内存控制器输出的第二单独时钟使能指示信号、第二时钟使能信号和第二地址信号，第二单独时钟使能指示信号和第二时钟使能信号联合指示芯片控制器根据第二地址信号寄存单独时钟使能信息，第二地址信号携带单独时钟使能信息、单独时钟使能信息的地址信息。
图10是根据本发明的一个实施例的内存的示意性结构图。内存1000包括：多个内存芯片1010和如图9的芯片控制器900。
因此，本发明的技术方案通过在芯片控制器中寄存单独片选信息，根据从内存控制器接收到的片选信号和寄存的单独片选信息生成多个单独片选信号，并且分别向多个内存芯片输出多个单独片选信号。由于芯片控制器中寄存了单独片选信息，因此无需内存控制器针对每个命令都发送单独片选信息，从而减少了对传输带宽的占用。
图11是根据本发明的一个实施例的内存控制器的示意性结构图。内存控制器1100，包括：处理器1110和发送器1120，其中处理器1110和发送器1120相连接，处理器1110用于生成第一片选信号、第一单独片选指示信号和控制命令信号；发送器1120，用于向芯片控制器输出第一片选信号和第一单独片选指示信号，其中第一单独片选指示信号和第一片选信号联合指示芯片控制器根据第一片选信号和芯片控制器中寄存的单独片选信息生成多个单独片选信号，单独片选信息用于生成多个单独片选信号，多个单独片选信号与多个内存芯片一一对应，第一片选信号用于指中的至示选择多个内存芯片，单独片选信息用于指示单独选择多个内存芯片少一个内存芯片，其中，发送器1120还用于向多个内存芯片输出控制命令信号，以便多个内存芯片中的至少一个内存芯片根据芯片控制输出的多个单独片选信号执行与控制命令信号对应的操作。
因此，本发明的技术方案通过在芯片控制器中寄存单独片选信息，根据从内存控制器接收到的片选信号和寄存的单独片选信息生成多个单独片选信号，并且分别向多个内存芯片输出多个单独片选信号。由于芯片控制器中寄存了单独片选信息，因此无需内存控制器针对每个命令都发送单独片选信息，从而减少了对传输带宽的占用。
根据本发明的实施例，发送器还用于向芯片控制器输出第一地址信号，地址信号携带单独片选信息和单独片选信息的地址信息。
根据本发明的实施例，地址信号还携带片选策略信息，片选策略信息用于指示单独片选信息针对控制命令信号是否有效，其中，发送器还用于向芯片控制器输出控制命令信号。
根据本发明的实施例，发送器还用于向芯片控制器输出第二单独片选指示信号和第二片选信号，其中第二单独片选指示信号和第二片选信号联合指示芯片控制器根据地址信息寄存单独片选信息。
根据本发明的实施例，发送器还用于向芯片控制器输出第二单独片选指示信号和第二片选信号，第二单独片选指示信号和第二片选信号联合指示芯片控制器根据地址信息寄述单独片选信息。
本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一 种“或”的关系。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本发明实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以是两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到本发明可以用硬件实现，或固件实现，或它们的组合方式来实现。当使用软件实现时，可以将上述功能存储在计算机可读介质中或作为计算机可读介质上的一个或多个指令或代码进行传输。计算机可读介质包括计算机存储介质和通信介 质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是计算机能够存取的任何可用介质。以此为例但不限于：计算机可读介质可以包括RAM、ROM、EEPROM、CD-ROM或其他光盘存储、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质。此外。任何连接可以适当的成为计算机可读介质。例如，如果软件是使用同轴电缆、光纤光缆、双绞线、数字用户线(DSL)或者诸如红外线、无线电和微波之类的无线技术从网站、服务器或者其他远程源传输的，那么同轴电缆、光纤光缆、双绞线、DSL或者诸如红外线、无线和微波之类的无线技术包括在所属介质的定影中。如本发明所使用的，盘(Disk)和碟(disc)包括压缩光碟(CD)、激光碟、光碟、数字通用光碟(DVD)、软盘和蓝光光碟，其中盘通常磁性的复制数据，而碟则用激光来光学的复制数据。上面的组合也应当包括在计算机可读介质的保护范围之内。
总之，以上所述仅为本发明技术方案的较佳实施例而已，并非用于限定本发明的保护范围。凡在本发明的原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (21)

  1. 一种芯片控制器，其特征在于，包括：
    寄存模块，用于寄存单独片选信息；
    控制模块，用于：接收内存控制器输出的第一片选信号；根据所述第一片选信号和所述寄存模块寄存的单独片选信息生成多个单独片选信号，其中所述多个单独片选信号与多个内存芯片一一对应，所述第一片选信号用于指示选择所述多个内存芯片，所述单独片选信息用于指示单独选择所述多个内存芯片中的至少一个内存芯片；分别向多个内存芯片输出所述多个单独片选信号，以便所述多个内存芯片中的至少一个内存芯片根据所述内存控制器输出的控制命令信号执行与所述控制命令信号对应的操作。
  2. 根据权利要求1所述的方法，其特征在于，所述寄存模块还用于：在所述控制模块根据所述第一片选信号和所述寄存模块寄存的单独片选信息生成多个单独片选信号之前，
    接收所述内存控制器输出的第一地址信号，所述第一地址信号携带所述单独片选信息和所述单独片选信息的地址信息；
    根据所述第一地址信号寄存所述单独片选信息。
  3. 根据权利要求2所述的方法，其特征在于，所述第一地址信号还携带片选策略信息，所述片选策略信息寄存在所述芯片控制器中并且与所述单独片选信息相对应，所述片选策略信息用于指示所述单独片选信息针对所述控制命令信号是否有效，所述控制模块还用于接收所述内存控制器输出的所述控制命令信号，
    所述根据所述第一片选信号和所述芯片控制器中寄存的单独片选信息生成多个单独片选信号，包括：
    如果所述片选策略信息指示所述单独片选信息针对所述控制命令信号有效，则根据所述第一片选信号和所述单独片选信息生成所述多个单独片选信号；
    如果所述片选策略信息指示所述单独片选信息针对所述控制命令信号无效，则根据所述第一片选信号和预定的片选信息生成多个单独片选信号，所述预定的片选信息指示生成的所述多个单独片选信号选择对应的所述多个内存 芯片。
  4. 根据权利要求2或3所述的方法，其特征在于，所述寄存模块还用于接收所述内存控制器输出的第二单独片选指示信号和第二片选信号，其中所述第二单独片选指示信号和所述第二片选信号联合指示所述芯片控制器根据所述第一地址信号寄存所述单独片选信息。
  5. 根据权利要求1-4中的任一项所述的方法，其特征在于，所述控制模块还用于接收所述内存控制器输出的第一单独片选指示信号，其中所述第一单独片选指示信号和所述第一片选信号联合指示所述芯片控制器根据所述第一片选信号和所述芯片控制器中寄存的单独片选信息生成所述多个单独片选信号。
  6. 根据权利要求1-5中的任一项所述的方法，其特征在于，
    所述控制模块还用于接收所述内存控制器输出的第一时钟使能指示信号、第一时钟使能信号，所述第一时钟使能指示信号和所述第一时钟使能信号联合指示所述芯片控制器根据所述第一时钟使能信号和所述芯片控制器中寄存的单独时钟使能信息生成所述多个单独时钟使能信号，
    所述寄存模块还用于接收所述内存控制器输出的第二单独时钟使能指示信号、第二时钟使能信号和第二地址信号，所述第二单独时钟使能指示信号和所述第二时钟使能信号联合指示所述芯片控制器根据所述第二地址信号寄存所述单独时钟使能信息，所述第二地址信号携带单独时钟使能信息、所述单独时钟使能信息的地址信息。
  7. 一种内存，其特征在于，包括：多个内存芯片和如权利要求1至6中的任一项所述的芯片控制器。
  8. 一种内存控制器，其特征在于，包括：
    生成模块，用于生成第一片选信号、第一单独片选指示信号和控制命令信号，其中所述第一单独片选指示信号和所述第一片选信号联合指示所述芯片控制器根据所述第一片选信号和所述芯片控制器中寄存的单独片选信息生成所述多个单独片选信号，
    输出模块，用于向芯片控制器输出第一片选信号和第一单独片选指示信号，所述单独片选信息用于生成多个单独片选信号，所述多个单独片选信号与多个内存芯片一一对应，所述第一片选信号用于指示选择所述多个内存芯片， 所述单独片选信息用于指示单独选择所述多个内存芯片中的至少一个内存芯片，
    所述输出模块还用于向所述多个内存芯片输出控制命令信号，以便所述多个内存芯片中的至少一个内存芯片根据所述芯片控制输出的多个单独片选信号执行与所述控制命令信号对应的操作。
  9. 根据权利要求8所述的方法，其特征在于，所述输出模块还用于向所述芯片控制器输出第一地址信号，所述地址信号携带所述单独片选信息和所述单独片选信息的地址信息。
  10. 根据权利要求9所述的方法，其特征在于，所述地址信号还携带片选策略信息，所述片选策略信息用于指示所述单独片选信息针对所述控制命令信号是否有效，
    所述输出模块还用于向所述芯片控制器输出所述控制命令信号。
  11. 根据权利要求9-10中的任一项所述的方法，其特征在于，
    所述输出模块还用于向所述芯片控制器输出第二单独片选指示信号和第二片选信号，其中所述第二单独片选指示信号和所述第二片选信号联合指示所述芯片控制器根据所述地址信息寄存所述单独片选信息。
  12. 一种控制内存的方法，其特征在于，包括：
    芯片控制器接收内存控制器输出的第一片选信号；
    所述芯片控制器根据所述第一片选信号和所述芯片控制器中寄存的单独片选信息生成多个单独片选信号，其中所述多个单独片选信号与多个内存芯片一一对应，所述第一片选信号用于指示选择所述多个内存芯片，所述单独片选信息用于指示单独选择所述多个内存芯片中的至少一个内存芯片；
    所述芯片控制器分别向所述多个内存芯片输出所述多个单独片选信号，以便所述多个内存芯片中的至少一个内存芯片根据所述内存控制器输出的控制命令信号执行与所述控制命令信号对应的操作。
  13. 根据权利要求12所述的方法，其特征在于，在所述芯片控制器根据所述第一片选信号和所述芯片控制器中寄存的单独片选信息生成多个单独片选信号之前，所述方法还包括：
    所述芯片控制器接收所述内存控制器输出的第一地址信号，所述第一地址信号携带所述单独片选信息和所述单独片选信息的地址信息；
    所述芯片控制器根据所述第一地址信号寄存所述单独片选信息。
  14. 根据权利要求13所述的方法，其特征在于，所述第一地址信号还携带片选策略信息，所述片选策略信息寄存在所述芯片控制器中并且与所述单独片选信息相对应，所述片选策略信息用于指示所述单独片选信息针对所述控制命令信号是否有效，
    其中，所述方法还包括：
    所述芯片控制器接收所述内存控制器输出的所述控制命令信号，
    其中，所述芯片控制器根据所述第一片选信号和所述芯片控制器中寄存的单独片选信息生成多个单独片选信号，包括：
    如果所述片选策略信息指示所述单独片选信息针对所述控制命令信号有效，则所述芯片控制器根据所述第一片选信号和所述单独片选信息生成所述多个单独片选信号；
    如果所述片选策略信息指示所述单独片选信息针对所述控制命令信号无效，则所述芯片控制器根据所述第一片选信号和预定的片选信息生成多个单独片选信号，所述预定的片选信息指示生成的所述多个单独片选信号选择对应的所述多个内存芯片。
  15. 根据权利要求13或14所述的方法，其特征在于，还包括：
    所述芯片控制器接收所述内存控制器输出的第二单独片选指示信号和第二片选信号，其中所述第二单独片选指示信号和所述第二片选信号联合指示所述芯片控制器根据所述第一地址信号寄存所述单独片选信息。
  16. 根据权利要求12-15中的任一项所述的方法，其特征在于，还包括：
    所述芯片控制器接收所述内存控制器输出的第一单独片选指示信号，其中所述第一单独片选指示信号和所述第一片选信号联合指示所述芯片控制器根据所述第一片选信号和所述芯片控制器中寄存的单独片选信息生成所述多个单独片选信号。
  17. 根据权利要求12-16中的任一项所述的方法，其特征在于，还包括：
    所述芯片控制器接收所述内存控制器输出的第一时钟使能指示信号、第一时钟使能信号，第二单独时钟使能指示信号、第二时钟使能信号和第二地址信号，其中所述第一时钟使能指示信号和所述第一时钟使能信号联合指示所述芯片控制器根据所述第一时钟使能信号和所述芯片控制器中寄存的单独时钟使 能信息生成所述多个单独时钟使能信号，所述第二单独时钟使能指示信号和所述第二时钟使能信号联合指示所述芯片控制器根据所述第二地址信号寄存所述单独时钟使能信息，所述第二地址信号携带单独时钟使能信息、所述单独时钟使能信息的地址信息。
  18. 一种控制内存芯片的方法，其特征在于，包括：
    内存控制器向芯片控制器输出第一片选信号和第一单独片选指示信号，其中所述第一单独片选指示信号和所述第一片选信号联合指示所述芯片控制器根据所述第一片选信号和所述芯片控制器中寄存的单独片选信息生成所述多个单独片选信号，所述单独片选信息用于生成多个单独片选信号，所述多个单独片选信号与多个内存芯片一一对应，所述第一片选信号用于指示选择所述多个内存芯片，所述单独片选信息用于指示单独选择所述多个内存芯片中的至少一个内存芯片；
    所述内存控制器向所述多个内存芯片输出控制命令信号，以便所述多个内存芯片中的至少一个内存芯片根据所述芯片控制输出的多个单独片选信号执行与所述控制命令信号对应的操作。
  19. 根据权利要求18所述的方法，其特征在于，还包括：
    所述内存控制器向所述芯片控制器输出第一地址信号，所述地址信号携带所述单独片选信息和所述单独片选信息的地址信息。
  20. 根据权利要求19所述的方法，其特征在于，所述地址信号还携带片选策略信息，所述片选策略信息用于指示所述单独片选信息针对所述控制命令信号是否有效，
    所述方法还包括：所述内存控制器向所述芯片控制器输出所述控制命令信号。
  21. 根据权利要求19-20中的任一项所述的方法，其特征在于，还包括：
    所述内存控制器向所述芯片控制器输出第二单独片选指示信号和第二片选信号，其中所述第二单独片选指示信号和所述第二片选信号联合指示所述芯片控制器根据所述地址信息寄存所述单独片选信息。
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