WO2015139248A1 - 极性码的速率匹配方法和速率匹配装置 - Google Patents

极性码的速率匹配方法和速率匹配装置 Download PDF

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Publication number
WO2015139248A1
WO2015139248A1 PCT/CN2014/073719 CN2014073719W WO2015139248A1 WO 2015139248 A1 WO2015139248 A1 WO 2015139248A1 CN 2014073719 W CN2014073719 W CN 2014073719W WO 2015139248 A1 WO2015139248 A1 WO 2015139248A1
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bits
interleaved
group
interleaved bits
rate
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PCT/CN2014/073719
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English (en)
French (fr)
Inventor
沈晖
李斌
陈军
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to BR112016021434A priority Critical patent/BR112016021434A2/pt
Priority to PCT/CN2014/073719 priority patent/WO2015139248A1/zh
Priority to CN201480071627.4A priority patent/CN105874736B/zh
Priority to KR1020167027730A priority patent/KR101937547B1/ko
Priority to EP14886441.6A priority patent/EP3113398B1/en
Publication of WO2015139248A1 publication Critical patent/WO2015139248A1/zh
Priority to US15/269,553 priority patent/US10009146B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2739—Permutation polynomial interleaver, e.g. quadratic permutation polynomial [QPP] interleaver and quadratic congruence interleaver
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/6306—Error control coding in combination with Automatic Repeat reQuest [ARQ] and diversity transmission, e.g. coding schemes for the multiple transmission of the same information or the transmission of incremental redundancy
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H04L1/0068—Rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1812—Hybrid protocols; Hybrid automatic repeat request [HARQ]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1812—Hybrid protocols; Hybrid automatic repeat request [HARQ]
    • H04L1/1819—Hybrid protocols; Hybrid automatic repeat request [HARQ] with retransmission of additional or different redundancy
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1867—Arrangements specially adapted for the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1829—Arrangements specially adapted for the receiver end
    • H04L1/1835—Buffer management
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W28/00—Network traffic management; Network resource management
    • H04W28/02—Traffic management, e.g. flow control or congestion control
    • H04W28/10—Flow control between communication endpoints
    • H04W28/14—Flow control between communication endpoints using intermediate storage

Definitions

  • Embodiments of the present invention relate to the field of codecs, and more particularly, to a rate matching method and rate matching apparatus for a Polar code (polar code). Background technique
  • the Polar code (polar code) is an encoding method that can achieve Shannon capacity and has low coding and decoding complexity.
  • F is a transposed matrix, such as a bit reversal matrix c
  • the Polar code can use the traditional random (quasi-random) punctured hybrid automatic repeat request (HARQ) technology.
  • the so-called random (quasi-random) puncturing is the random (quasi-random) selection of the location of the puncturing.
  • the LLR at the puncturing is set to 0, and the decoding module and method of the mother code are still used.
  • This random (quasi-random) puncturing method has a higher error rate and a poor HARQ performance. Summary of the invention
  • Embodiments of the present invention provide a rate matching method and a rate matching apparatus for a Polar code, which can improve HARQ performance of a Polar code.
  • a rate matching method for a Polar code including: dividing a system Polar code output by a Polar code encoder into system bits and parity bits; and interleaving the system bits to obtain a first group of interleaved bits, Interleaving the check bits to obtain a second set of interleaved bits; The first set of interleaved bits and the second set of interleaved bits determine a rate matched output sequence.
  • the interleaving the system bits to obtain the first set of interleaved bits comprises: performing a second Quadaratic interleaving on the system bits to obtain the first group Interleaved bits.
  • the interleaving the check bits to obtain the second set of interleaved bits includes: performing Quadaratic interleaving on the check bits The second set of interleaved bits.
  • the determining, by the first set of interleaved bits and the second set of interleaved bits, a rate matching output sequence includes: The first set of interleaved bits and the second set of interleaved bits are sequentially written into the circular buffer; determining a starting position of the rate matched output sequence in the circular buffer according to the redundancy version; The starting position reads the rate matched output sequence from the circular buffer.
  • the determining, by the first set of interleaved bits and the second set of interleaved bits, a rate matching output sequence includes: The first set of interleaved bits and the second set of interleaved bits are sequentially combined into a third set of interleaved bits; the bits of the third set of interleaved bits are sequentially truncated or repeatedly extracted to obtain a rate matched output sequence.
  • a rate matching apparatus including: a grouping unit, configured to divide a system Polar code output by a polar Polar code encoder into system bits and check bits; and an interleaving unit, configured to use the system bits Interleaving to obtain a first set of interleaved bits, interleaving the check bits to obtain a second set of interleaved bits; determining unit, configured to determine a rate matched output based on the first set of interleaved bits and the second set of interleaved bits sequence.
  • the interleaving unit is specifically configured to perform second Quadradatic interleaving on the system bits to obtain the first set of interleaved bits, and/or perform the verification
  • the bits are Quadratic interleaved to obtain the second set of interleaved bits.
  • the determining unit is specifically configured to sequentially write the first set of interleaved bits and the second set of interleaved bits into a circular buffer And determining, according to the redundancy version, a starting position of the rate matched output sequence in the circular buffer, and reading the rate matched output sequence from the circular buffer according to the starting position.
  • the determining unit is specifically configured to sequentially combine the first group of interleaved bits and the second group of interleaved bits into a third The group interleaves bits, sequentially truncating or repeatedly extracting bits of the third set of interleaved bits to obtain the output sequence of the rate matching.
  • a wireless communication device comprising a polar Polar code encoder, a rate matching device as described above, and a transmitter.
  • the system bit and the check bit are separately interleaved, thereby obtaining a rate matching output sequence, so that the interleaved sequence structure is more random, and the FER (Frame Error Rate) can be reduced, thereby improving HARQ performance ensures the reliability of data transmission.
  • FER Fre Error Rate
  • FIG. 1 shows a wireless communication system of an embodiment of the present invention.
  • Fig. 2 shows a system for executing a processing method of a Polar code in a wireless communication environment.
  • FIG. 3 is a flow chart of a rate matching method of a Polar code according to an embodiment of the present invention.
  • FIG. 4 is a block diagram of a rate matching device in accordance with an embodiment of the present invention.
  • Figure 5 is a schematic diagram of an access terminal that facilitates the processing of a Polar code in a wireless communication system.
  • FIG. 6 is a schematic diagram of a system having a method of processing a Polar code in a wireless communication environment.
  • FIG. 7 shows a system capable of using a rate matching method of a Polar code in a wireless communication environment.
  • a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer.
  • an application running on a computing device and a computing device can be a component.
  • One or more components can reside within a process and/or execution thread, and the components can be located on one computer and/or distributed between two or more computers.
  • these components can execute from various computer readable media having various data structures stored thereon.
  • a component may, for example, be based on a signal having one or more data packets (eg, data from two components interacting with another component between the local system, the distributed system, and/or the network, such as the Internet interacting with other systems) Communicate through local and/or remote processes.
  • data packets eg, data from two components interacting with another component between the local system, the distributed system, and/or the network, such as the Internet interacting with other systems
  • An access terminal may also be called a system, a subscriber unit, a subscriber station, a mobile station, a mobile station, a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communication device, a user agent, a user device, or a UE (User Equipment, User equipment).
  • the access terminal can be a cellular phone, a cordless phone, a SIP (Session Initiation Protocol) phone, a WLL (Wireless Local Loop) station, a PDA (Personal Digital Assistant), with wireless communication.
  • the base station can be used for communicating with a mobile device, and the base station can be a GSM (Global System of Mobile communication) or a BTS (Base Transceiver Station) in CDMA (Code Division Multiple Access), or NB (NodeB, base station;) in WCDMA (Wideband Code Division Multiple Access), and may also be an eNB or an eNodeB (Evolutional Node B) in LTE (Long Term Evolution) , or a relay station or access point, or a base station device in a future 5G network.
  • GSM Global System of Mobile communication
  • BTS Base Transceiver Station
  • CDMA Code Division Multiple Access
  • NB NodeB, base station
  • WCDMA Wideband Code Division Multiple Access
  • eNB or an eNodeB Evolutional Node B
  • LTE Long Term Evolution
  • relay station or access point or a base station device in a future 5G network.
  • the term "article of manufacture” as used in this application encompasses a computer program accessible from any computer-readable device, carrier, or media.
  • the computer readable medium may include, but is not limited to, a magnetic storage device (eg, a hard disk, a floppy disk, or a magnetic tape), and an optical disk (eg, a CD (Compact Disk), a DVD (Digital Versatile Disk) Etc.), smart cards and flash memory devices (such as EPROM (Erasable Programmable Read-Only Memory), cards, sticks or key drives, etc.).
  • various storage media described herein can represent one or more devices and/or other machine readable media for storing information.
  • the term "machine readable medium” may include, but is not limited to, a wireless channel and capable of being stored, contained, and/or carried Various other media for instructions and/or data.
  • System 100 includes a base station 102, which may include multiple antenna groups.
  • one antenna group may include antennas 104 and 106
  • another antenna group may include antennas 108 and 110
  • additional groups may include antennas 112 and 114.
  • Two antennas are shown for each antenna group, although more or fewer antennas may be used for each group.
  • Base station 102 can additionally include a transmitter chain and a receiver chain, as will be understood by those of ordinary skill in the art, which can include multiple components associated with signal transmission and reception (e.g., processor, modulator, multiplexer, demodulation) , demultiplexer or antenna, etc.).
  • Base station 102 can communicate with one or more access terminals (e.g., access terminal 116 and access terminal 122). However, it will be appreciated that base station 102 can communicate with substantially any number of access terminals similar to access terminals 116 and 122. Access terminals 116 and 122 can be, for example, cellular telephones, smart phones, portable computers, handheld communication devices, handheld computing devices, satellite radios, global positioning systems, PDAs, and/or any other for communicating over wireless communication system 100. Suitable for equipment. As shown, access terminal 116 is in communication with antennas 112 and 114, wherein antennas 112 and 114 transmit information to access terminal 116 over forward link 118 and receive information from access terminal 116 over reverse link 120.
  • access terminal 116 is in communication with antennas 112 and 114, wherein antennas 112 and 114 transmit information to access terminal 116 over forward link 118 and receive information from access terminal 116 over reverse link 120.
  • access terminal 122 is in communication with antennas 104 and 106, wherein antennas 104 and 106 transmit information to access terminal 122 over forward link 124 and receive information from access terminal 122 via reverse link 126.
  • FDD Frequency Division Duplex
  • the forward link 118 can utilize a different frequency band than that used by the reverse link 120
  • the forward link 124 can utilize the reverse link 126.
  • Different frequency bands used can be used.
  • forward link 118 and reverse link 120 can use a common frequency band
  • forward link 124 and reverse link 126 can use a common frequency band.
  • Each set of antennas and/or regions designed for communication is referred to as a sector of base station 102.
  • the antenna group can be designed to communicate with access terminals in sectors of the coverage area of base station 102.
  • the transmit antenna of base station 102 can utilize beamforming to improve the signal to noise ratio for forward links 118 and 124 of access terminals 116 and 122.
  • the base station 102 transmits to the randomly dispersed access terminals 116 and 122 in the relevant coverage area by using the single antenna to transmit to all of its access terminals, the mobile devices in the adjacent cells are subject to Less dry 4 especially.
  • base station 102, access terminal 116, and/or access terminal 122 may be transmitting wireless communication devices and/or receiving wireless communication devices.
  • the transmitting wireless communication device can The data is encoded for transmission.
  • the transmitting wireless communication device can have (eg, generate, obtain, store in memory, etc.) a certain number of information bits to be transmitted over the channel to the receiving wireless communication device.
  • Such information bits can be included in a transport block (or multiple transport blocks) of data that can be segmented to produce multiple code blocks.
  • the transmitting wireless communication device can encode each code block using a Polar code encoder (not shown).
  • System 200 includes a wireless communication device 202 that is shown to transmit data via a channel. Although shown as transmitting data, the wireless communication device 202 can also receive data via a channel (eg, the wireless communication device 202 can transmit and receive data simultaneously, the wireless communication device 202 can transmit and receive data at different times, or a combination thereof, etc.) .
  • the wireless communication device 202 can be, for example, a station (e.g., base station 102 of FIG. 1), an access terminal (e.g., access terminal 116 of FIG. 1, access terminal 122 of FIG. 1, etc.), and the like.
  • the wireless communication device 202 can include a Polar code encoder 204, a rate matching device 205, and a transmitter 206.
  • the Polar code encoder 204 is configured to encode the data to be transmitted, and obtain corresponding
  • the rate matching device 205 can be used to divide the system Polar code output by the Polar code encoder 204 into system bits and check bits, and interleave the system bits to obtain the first The group interleaves bits, interleaves the check bits to obtain a second set of interleaved bits, and then determines a rate matched output sequence based on the first set of interleaved bits and the second set of interleaved bits.
  • the rate matching means 205 can be used to perform overall interleaving of the non-system Polar code to obtain interleaved bits, and then determine a rate matched output sequence based on the interleaved bits.
  • transmitter 206 can then transmit the rate matched output sequence processed by rate matching device 205 over the channel.
  • transmitter 206 can transmit relevant data to other different wireless communication devices (not shown).
  • the Polar code encoded by the Polar code encoder 204 is a system code, it may be referred to as a system Polar code; if it is a non-system code, it may be referred to as a non-system Polar code.
  • system code refers to a code whose generating matrix G has the following form or its equivalent code:
  • G [I k , P] , Where I k is a k-order identity matrix and P is a check matrix.
  • a code other than the system code may be referred to as a non-system code.
  • FIG. 3 is a flow chart of a rate matching method of a Polar code according to an embodiment of the present invention. The method of Figure 3 is performed by the encoding and transmitting end of the Polar code (e.g., rate matching device 205 of Figure 2).
  • the systematic bits are bits corresponding to the unit matrix I k portion in the above-described generation matrix G
  • the parity bits are bits corresponding to the check matrix P portion in the above-described generation matrix G.
  • Interleave system bits to obtain a first set of interleaved bits (Setl), and interleave the check bits to obtain a second set of interleaved bits (Set2).
  • the system bits and the check bits are separately interleaved, which can further improve the minimum distance of the interleaved bits, thereby improving the rate matching performance of the Polar code. .
  • the embodiment of the present invention does not limit the type of interleaving process used in step 302.
  • quadratic interleaving can be employed.
  • the mapping function of the Quadratic interleave is: c(m) c(m + l) (modN) 0 ⁇ m ⁇ N.
  • the cth (m)th bit is mapped to the cth (m + 1) (mod N) bits of the interleaved bits.
  • mod is the modulo operation.
  • the systematic bits may be quadraticly interleaved to obtain the first set of interleaved bits.
  • the check bits when the check bits are interleaved to obtain the second set of interleaved bits in step 302, the check bits may be quadraticly interleaved to obtain a second set of interleaved bits.
  • a circular buffer may be utilized.
  • the first set of interleaved bits and the second set of interleaved bits may be sequentially written into the circular buffer, that is, the first set of interleaved bits are first written into the circular buffer, and then the second set of interleaved bits are written into the loop. buffer.
  • the start position of the rate-matched output sequence in the circular buffer can be determined according to the redundancy version (RV, Redundancy Version), and the bit is read from the circular buffer as the output sequence of the rate matching according to the starting position.
  • RV Redundancy Version
  • the HARQ process of the Polar code the importance of the systematic bits and the check bits are different. Specifically, the systematic bits are more important than the check bits. It is assumed that the first set of interleaved bits obtained by interleaving the system bits is Set1, and the second set of interleaved bits obtained by interleaving the check bits is Set2. Writing Setl to the circular buffer before Set2 allows the system to retain more system bits in the rate-matched output sequence, thereby improving the HARQ performance of the Polar code.
  • the first set of interleaved bits (Set1) and the second set of interleaved bits may be used.
  • (Set2) is sequentially combined into a third set of interleaved bits (Set3), ie in Set3, all bits of Setl are before all bits of Set2.
  • the bits in Set3 can then be sequentially intercepted or repeatedly extracted to obtain a rate matched output sequence required for each retransmission.
  • a partial bit of length La can be intercepted from Set3 as an output sequence of rate matching.
  • the bits of Set3 can be read again from the beginning after reading all the bits of Set3, and thus repeating until the rate matching of the length La is read. The output sequence.
  • the HARQ process of the Polar code the importance of the systematic bits and the check bits are different. Specifically, the systematic bits are more important than the check bits. Therefore, the first set of interleaved bits Set1 obtained by interleaving the system bits are placed into a third set of interleaved bits Set3 before the second set of interleaved bits Set2 obtained by interleaving the check bits, so that the final rate matching can be obtained.
  • the system bits are more reserved in the output sequence, thereby improving the HARQ performance of the Polar code.
  • Rate matching device of Figure 4 is a block diagram of a rate matching device in accordance with an embodiment of the present invention. Rate matching device of Figure 4
  • the 400 may be located at a base station or user equipment, including a packet unit 401, an interleaving unit 402, and a determining unit 403.
  • the grouping unit 401 divides the system Polar code into system bits and parity bits.
  • the interleaving unit 402 interleaves the systematic bits to obtain a first set of interleaved bits, and interleaves the parity bits to obtain a second set of interleaved bits.
  • the determining unit 403 determines a rate matched output sequence based on the first set of interleaved bits and the second set of interleaved bits.
  • the system bits and the check bits are separately interleaved, thereby obtaining a rate matched output sequence, so that the interleaved sequence structure is more random, and the FER can be reduced, thereby improving HARQ performance and ensuring data transmission reliability. .
  • the system bits and the check bits are separately interleaved, which can further improve the minimum distance of the interleaved bits, thereby improving the rate matching performance of the Polar code. .
  • the type of the interleaving process used by the interleaving unit 402 is not limited in the embodiment of the present invention.
  • the interleaving unit 402 can employ quadratic interleaving.
  • the interleaving unit 402 may perform quadratic interleaving on the system bits to obtain a first set of interleaved bits, and/or perform quadratic interleaving on the parity bits to obtain a second set of interleaved bits.
  • the determining unit 403 may sequentially write the first set of interleaved bits and the second set of interleaved bits into the circular buffer, and determine the output sequence of the rate matching according to the redundancy version in the circular buffer.
  • the starting position, and the rate matching output sequence is read from the circular buffer based on the starting position.
  • the HARQ process of the Polar code the importance of the systematic bits and the check bits are different. Specifically, the systematic bits are more important than the check bits. It is assumed that the first set of interleaved bits obtained by interleaving the system bits is Set1, and the second set of interleaved bits obtained by interleaving the check bits is Set2. Writing Setl to the circular buffer before Set2 allows the system to retain more system bits in the rate-matched output sequence, thereby improving the HARQ performance of the Polar code.
  • the determining unit 403 may sequentially combine the first set of interleaved bits and the second set of interleaved bits into a third set of interleaved bits, and sequentially extract or repeatedly extract the bits in the third set of interleaved bits to Obtain a rate matched output sequence.
  • the HARQ process of the Polar code the importance of the systematic bits and the check bits are different. Specifically, the systematic bits are more important than the check bits. Therefore, the first set of interleaved bits Set1 obtained by interleaving the system bits are placed into a third set of interleaved bits Set3 before the second set of interleaved bits Set2 obtained by interleaving the check bits, so that the final rate matching can be obtained.
  • the system bits are more reserved in the output sequence, thereby improving the HARQ performance of the Polar code.
  • Access terminal 500 includes a receiver 502 for receiving signals from, for example, a receiving antenna (not shown) and performing typical actions on the received signals (e.g., filtering, Amplify, downconvert, etc.), and digitize the adjusted signal to obtain samples.
  • Receiver 502 can be, for example, an MMSE (Minimum Mean-Squared Error) receiver.
  • Access terminal 500 can also include a demodulator 504 that can be used to demodulate received symbols and provide them to processor 506 for channel estimation.
  • MMSE Minimum Mean-Squared Error
  • Processor 506 can be a processor dedicated to analyzing information received by receiver 502 and/or generating information transmitted by transmitter 516, a processor for controlling one or more components of access terminal 500, and/or A controller for analyzing information received by receiver 502, generating information transmitted by transmitter 516, and controlling one or more components of access terminal 500.
  • Access terminal 500 can additionally include a memory 508 operatively coupled to processor 506 and storing the following data: data to be transmitted, received data, and any other related to performing various actions and functions described herein. Suitable for information.
  • Memory 508 can additionally store associated protocols and/or algorithms for Polar code processing.
  • non-volatile memory may include: ROM (Read-Only Memory), PROM (Programmable ROM), EPROM (Erasable PROM, Erasable Programmable) Read only memory), EEPROM (Electrically EEPROM) or flash memory.
  • Volatile memory can include: RAM (Random Access Memory), which acts as an external cache.
  • RAM Random Access Memory
  • SRAM Static RAM, Static Random Access Memory
  • DRAM Dynamic RAM
  • SDRAM Synchronous DRAM
  • Synchronous Dynamic Random Access Memory DDR SDRAM (Double Data Rate SDRAM)
  • ESDRAM Enhanced SDRAM, Enhanced Synchronous Dynamic Random Access Memory
  • SLDRAM Synchronous Connection Dynamic Random Access Memory
  • DR RAM Direct Rambus RAM, Direct Memory Bus Random Access Memory
  • receiver 502 can also be coupled to rate matching device 510.
  • the rate matching device 510 can be substantially similar to the rate matching device 205 of FIG. 2, and the access terminal 500 can also include a Polar code encoder 512.
  • the Polar code encoder 512 is substantially similar to the Polar code encoder 204 of FIG. If the Polar code encoder 512 encodes the system Polar code, the rate matching device 510 can be used to divide the system Polar code into system bits and check bits, and interleave the system bits to obtain a first set of interleaved bits (Setl). The bit is interleaved to obtain a second set of interleaved bits (Set2), and a rate matched output sequence is determined based on the first set of interleaved bits and the second set of interleaved bits.
  • Setl first set of interleaved bits
  • Set2 second set of interleaved bits
  • the system bits and the check bits are separately interleaved, thereby obtaining a rate matched output sequence, so that the interleaved sequence structure is more random, and the FER can be reduced, thereby improving HARQ performance and ensuring data transmission reliability.
  • the system bits and the check bits are separately interleaved, which can further improve the minimum distance of the interleaved bits, thereby improving the rate matching performance of the Polar code. . .
  • the rate matching device 510 can be configured to globally interleave the non-system Polar code to obtain interleaved bits, and determine a rate matched output sequence based on the interleaved bits.
  • the non-systematic Polar code is integrally interleaved, and the minimum distance of the interleaved bits is improved, thereby improving the rate matching performance of the Polar code.
  • the type of the interleaving process used in the rate matching device 510 is not limited in the embodiment of the present invention.
  • quadratic interleaving can be used.
  • the mapping function of the Quadratic interleave is: c(m) c(m + l) (modN) 0 ⁇ m ⁇ N .
  • the cth (m)th bit is mapped to the cth (m + 1) (mod N) bits of the interleaved bits.
  • mod is the modulo operation.
  • the rate matching device 510 may perform a quadratic interleaving of the systematic bits to obtain a first set of interleaved bits when the system bits are interleaved to obtain the first set of interleaved bits.
  • the parity matching device 510 when the parity matching device 510 interleaves the parity bits to obtain the second group of interleaved bits, the parity bits may be quadraticly interleaved to obtain a second group of interleaved bits.
  • the rate matching device 510 may utilize a circular buffer when determining a rate matched output sequence based on the first set of interleaved bits and the second set of interleaved bits. Specifically, the rate matching device 510 may first write the first set of interleaved bits and the second set of interleaved bits sequentially. In the ring buffer, the first set of interleaved bits are first written to the circular buffer, and the second set of interleaved bits are written to the circular buffer. Then, the start position of the rate matched output sequence in the circular buffer can be determined according to the redundancy version, and the bit is read from the circular buffer as a rate matched output sequence according to the starting position.
  • the HARQ process of the Polar code the importance of the systematic bits and the check bits are different. Specifically, the systematic bits are more important than the check bits. It is assumed that the first set of interleaved bits obtained by interleaving the system bits is Set1, and the second set of interleaved bits obtained by interleaving the check bits is Set2. Writing Setl to the circular buffer before Set2 allows the system to retain more system bits in the rate-matched output sequence, thereby improving the HARQ performance of the Polar code.
  • the rate matching device 510 may interleave the first set of interleaved bits (Set1) and the second group when determining a rate matched output sequence based on the first set of interleaved bits and the second set of interleaved bits.
  • the bits (Set2) are sequentially combined into a third set of interleaved bits (Set3), ie in Set3, all bits of Setl precede all bits of Set2.
  • the bits in Set3 can then be sequentially intercepted or repeatedly extracted to obtain a rate matched output sequence required for each retransmission.
  • a partial bit of length La can be intercepted from Set3 as an output sequence of rate matching.
  • the bits of Set3 can be read again from the beginning, and thus repeated until the rate matching of the length La is read. The output sequence.
  • the HARQ process of the Polar code the importance of the systematic bits and the check bits are different. Specifically, the systematic bits are more important than the check bits. Therefore, the first set of interleaved bits Set1 obtained by interleaving the system bits are placed into a third set of interleaved bits Set3 before the second set of interleaved bits Set2 obtained by interleaving the check bits, so that the final rate matching can be obtained.
  • the system bits are more reserved in the output sequence, thereby improving the HARQ performance of the Polar code.
  • the rate matching device 510 may perform quadratic interleaving on the non-systematic Polar code to obtain interleaved bits when the non-system Polar code is integrally interleaved to obtain interleaved bits.
  • the rate matching device 510 determines the output sequence of the rate matching based on the interleaved bits
  • the interleaved bits may be written into the circular buffer, and the output sequence of the rate matching is determined according to the redundancy version in the circular buffer.
  • the starting position in the device reads the rate matched output sequence from the circular buffer based on the starting position.
  • the rate matching device 510 determines the rate matched output sequence based on the interleaved bits
  • the bits in the interleaved bits may be sequentially intercepted or repeatedly extracted to obtain a rate matched output required for each retransmission. sequence.
  • access terminal 500 can also include a modulator 514 and a transmitter 516 for transmitting signals to, for example, a base station, another access terminal, and the like.
  • a modulator 514 and a transmitter 516 for transmitting signals to, for example, a base station, another access terminal, and the like.
  • Polar code encoder 512, rate matching device 510 and/or modulator 514 can be part of processor 506 or a plurality of processors (not shown).
  • FIG. 6 is a schematic illustration of a system 600 having a method of processing the aforementioned Polar code in a wireless communication environment.
  • System 600 includes a base station 602 (e.g., an access point, a NodeB or an eNB, etc.) having a receiver 610 that receives signals from one or more access terminals 604 through a plurality of receive antennas 606, and through a transmit antenna 608 to one or A plurality of access terminals 604 transmit signals to the transmitter 624.
  • Receiver 610 can receive information from receive antenna 606 and is operatively associated to a demodulator 612 that demodulates the received information.
  • the demodulated symbols are analyzed by a processor similar to processor 614 described with respect to Figure 7, which is coupled to a memory 616 for storing to be transmitted to access terminal 604 (or a different base station ( The data of not shown)) or data received from access terminal 604 (or a different base station (not shown)) and/or any other suitable information related to performing the various actions and functions described herein.
  • Processor 614 can also be coupled to Polar code encoder 618 and rate matching device 620.
  • the rate matching device 620 can be configured to divide the system Polar code output by the Polar code encoder 618 into system bits and check bits, and interleave systematic bits to obtain a first set of interleaved bits (Setl And interleaving the check bits to obtain a second set of interleaved bits (Set2), and determining a rate matched output sequence based on the first set of interleaved bits and the second set of interleaved bits.
  • the system bits and the check bits are separately interleaved, thereby obtaining a rate matched output sequence, so that the interleaved sequence structure is more random, and the FER can be reduced, thereby improving HARQ performance and ensuring data transmission reliability.
  • the system bits and the check bits are separately interleaved, which can further improve the minimum distance of the interleaved bits, thereby improving the rate matching performance of the Polar code. . .
  • the rate matching device 620 can be configured to perform overall interleaving on the non-systematic Polar code output by the Polar code encoder 618 to obtain interleaved bits, and determine a rate matched output sequence based on the interleaved bits.
  • the non-systematic Polar code is integrally interleaved, and the minimum distance of the interleaved bits is improved, thereby improving the rate matching performance of the Polar code.
  • the type of the interleaving process used in the rate matching device 620 is not limited in the embodiment of the present invention.
  • quadratic interleaving can be used.
  • the mapping function of Quadratic interleaving is: c(m) c(m + l) (modN) Q ⁇ m ⁇ N .
  • the cth (m)th bit is mapped to the cth (m + 1) (mod N) bits of the interleaved bits.
  • mod is the modulo operation.
  • the rate matching device 620 may perform a quadratic interleaving of the systematic bits to obtain a first set of interleaved bits when the system bits are interleaved to obtain the first set of interleaved bits.
  • the parity matching device 620 when the parity matching device 620 interleaves the parity bits to obtain the second group of interleaved bits, the parity bits may be quadraticly interleaved to obtain a second group of interleaved bits.
  • the rate matching device 620 may utilize a circular buffer when determining a rate matched output sequence based on the first set of interleaved bits and the second set of interleaved bits. Specifically, the rate matching device 620 may first sequentially write the first set of interleaved bits and the second set of interleaved bits into the circular buffer, that is, first write the first set of interleaved bits into the circular buffer, and then interleave the second set of interleaving bits. The bit is written to the circular buffer. Then, the start position of the rate-matched output sequence in the loop buffer can be determined based on the redundancy version, and the bit is read from the circular buffer as a rate-matched output sequence based on the start position.
  • the HARQ process of the Polar code the importance of the systematic bits and the check bits are different. Specifically, the systematic bits are more important than the check bits. It is assumed that the first set of interleaved bits obtained by interleaving the system bits is Set1, and the second set of interleaved bits obtained by interleaving the check bits is Set2. Writing Setl to the circular buffer before Set2 can make the system bits more reserved in the rate-matched output sequence, thereby improving the HARQ performance of the Polar code.
  • the rate matching device 620 may interleave the first group of interleaved bits (Setl) and the second group when determining a rate matched output sequence based on the first set of interleaved bits and the second set of interleaved bits.
  • the bits (Set2) are sequentially combined into a third set of interleaved bits (Set3), ie in Set3, all bits of Setl precede all bits of Set2. Then, it can be intercepted or repeated sequentially
  • the bits in Set3 are extracted to obtain a rate matched output sequence required for each retransmission.
  • a partial bit of length La may be intercepted from Set3 as an output sequence of rate matching.
  • the bits of Set3 can be read again from the beginning, and thus repeated until the rate matching of the length La is read. The output sequence.
  • the HARQ process of the Polar code the importance of the systematic bits and the check bits are different. Specifically, the systematic bits are more important than the check bits. Therefore, the first set of interleaved bits Set1 obtained by interleaving the systematic bits are combined into a third set of interleaved bits Set3 before the second set of interleaved bits Set2 obtained by interleaving the check bits, so that the output sequence of the finally obtained rate matching can be obtained.
  • the system bits are more reserved, thereby improving the HARQ performance of the Polar code.
  • the rate matching device 620 may perform quadratic interleaving on the non-systematic Polar code to obtain interleaved bits when the non-system Polar code is integrally interleaved to obtain interleaved bits.
  • the rate matching device 620 determines the output sequence of the rate matching based on the interleaved bits
  • the interleaved bits may be written into the circular buffer, and the output sequence of the rate matching is determined according to the redundancy version in the circular buffer.
  • the starting position in the device reads the rate matched output sequence from the circular buffer based on the starting position.
  • the rate matching device 620 determines the rate matched output sequence based on the interleaved bits
  • the bits in the interleaved bits may be sequentially intercepted or repeatedly extracted to obtain a rate matched output required for each retransmission. sequence.
  • modulator 622 can multiplex frames for transmission by transmitter 624 to access terminal 604 via antenna 608, although shown separate from processor 614, but it will be appreciated that Polar code encoder 618 Rate matching device 620 and/or modulator 622 may be part of processor 614 or a plurality of processors (not shown).
  • the embodiments described herein can be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof.
  • the processing unit can be implemented in one or more ASICs (Application Specific Integrated Circuits), DSP (Digital Signal Processing, Digital Signal Processing), DSPD (DSP Device, Digital Signal Processing Equipment), PLD ( Programmable Logic Device, FPGA (Field-Programmable Gate Array), processor, controller, A microcontroller, microprocessor, other electronic unit for performing the functions described herein, or a combination thereof.
  • ASICs Application Specific Integrated Circuits
  • DSP Digital Signal Processing, Digital Signal Processing
  • DSPD DSP Device, Digital Signal Processing Equipment
  • PLD Programmable Logic Device
  • FPGA Field-Programmable Gate Array
  • a code segment can represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software grouping, a class, or any combination of instructions, data structures, or program statements.
  • a code segment can be combined into another code segment or hardware circuit by transmitting and/or receiving information, data, arguments, parameters, or memory contents.
  • Information, arguments, parameters, data, etc. can be communicated, forwarded, or transmitted using any suitable means including memory sharing, messaging, token passing, network transmission, and the like.
  • modules such as procedures, functions, and so on that perform the functions described in this article can be used.
  • the memory unit can be implemented in the processor or external to the processor, in the latter case the memory unit can be communicatively coupled to the processor via various means known in the art.
  • system 700 capable of using a rate matching method of a Polar code in a wireless communication environment is shown.
  • system 700 can reside at least partially in a base station.
  • system 700 can reside at least partially in an access terminal.
  • system 700 can be represented as a functional block, which can be a functional block representing functionality implemented by a processor, software, or combination thereof (e.g., firmware).
  • System 700 includes a logical grouping 702 of electronic components with joint operations.
  • logical grouping 702 can include an electrical component 704 for dividing a system Polar code into system bits and parity bits for interleaving system bits to obtain a first set of interleaved bits and interleaving the parity bits to obtain a second set Interleaved bit electronic component 706.
  • Logical group 702 can also include an electrical component 708 for determining a rate matched output sequence based on the first set of interleaved bits and the second set of interleaved bits.
  • the system bits and the check bits are separately interleaved, thereby obtaining a rate matched output sequence, so that the interleaved sequence structure is more random, and the FER can be reduced, thereby improving HARQ performance and ensuring data transmission reliability.
  • the system bits and the check bits are separately interleaved, which can further improve the minimum distance of the interleaved bits, thereby improving the rate matching performance of the Polar code. . .
  • system 700 can include a memory 712 that retains instructions for executing functions associated with electronic components 704, 706, and 708. Although shown external to memory 712, it will be appreciated that one or more of electronic components 704, 706, and 708 may be present in memory 712.
  • memory 712 retains instructions for executing functions associated with electronic components 704, 706, and 708.
  • electronic components 704, 706, and 708 may be present in memory 712.
  • Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods to implement the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present invention.
  • the disclosed systems, devices, and methods may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be electrical, mechanical or otherwise.
  • the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product.
  • the technical solution of the present invention which is essential to the prior art or part of the technical solution, may be embodied in the form of a software product stored in a storage medium, including
  • the instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and the like, which can store program codes. .

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Abstract

一种Polar码的速率匹配方法和速率匹配装置。该方法包括：将Polar码编码器输出的系统Polar码分为系统比特和校验比特；对所述系统比特进行交织得到第一组交织比特，对所述校验比特进行交织得到第二组交织比特；基于第一组交织比特和第二组交织比特确定速率匹配的输出序列。通过对系统比特和校验比特分开进行交织，进而得到速率匹配的输出序列，使得交织后的序列结构更具随机性，能够降低FER，从而能够改善HARQ性能，保证数据传输的可靠性。

Description

极性码的速率匹配方法和速率匹配装置 技术领域
本发明实施例涉及编解码领域， 并且更具体地， 涉及 Polar码（极性码） 的速率匹配方法和速率匹配装置。 背景技术
通信系统通常采用信道编码提高数据传输的可靠性， 保证通信的质量。 Polar码（极性码）是可以取得香农容量且具有低编译码复杂度的编码方式。 Polar码是一种线性块码。 其生成矩阵为 GN, 其编码过程为 x = u GN，这里 GN = BNF¾n , 码长 N=2n, n>0o
1 0
这里 F : BN是转置矩阵， 例如比特反转（bit reversal )矩阵 c
1 1
F¾n是 F的克罗内克幂（ Kronecker power ), 定义为 F¾n = F ® F¾(n )。 Polar 码 用 陪 集 码 可 以 表 示 为 (N，K，A，uA。) ， 其 编 码 过 程 为 ： x = uAGN.(A)© uACGN.(Ac) , 这里 A为信息 （information ) 比特索引的集合， GN.(A)是 GN.中由集合 A中的索引对应的行得到的子矩阵， GN.(AC)是 GN.中 由集合 Ac中的索引对应的行得到的子矩阵。 uAc是冻结 （frozen ) 比特， 其 数量为 (N-K), 是已知比特。 为了筒单， 这些冻结比特可以设为 0。
Polar 码可以采用传统的随机 （准随机） 打孔的混合自动重传请求 ( HARQ, Hybrid Automatic Repeat Request )技术。 所谓的随机 (准随机 ) 打孔就是随机（准随机）地选择打孔的位置。 在接收端， 打孔处的 LLR置 为 0, 任然使用母码的译码模块和方法。 这种随机（准随机）打孔方式的误 帧率较高， HARQ性能较差。 发明内容
本发明实施例提供一种 Polar码的速率匹配方法和速率匹配装置， 能够 提高 Polar码的 HARQ性能。
第一方面， 提供了一种 Polar码的速率匹配方法， 包括： 将 Polar码编码 器输出的系统 Polar码分为系统比特和校验比特； 对所述系统比特进行交织 得到第一组交织比特， 对所述校验比特进行交织得到第二组交织比特； 基于 所述第一组交织比特和所述第二组交织比特确定速率匹配的输出序列。 结合第一方面， 在第一方面的一种实现方式中， 所述对所述系统比特进 行交织得到第一组交织比特， 包括： 对所述系统比特进行二次 Quadaratic交 织得到所述第一组交织比特。
结合第一方面及其上述实现方式， 在第一方面的另一实现方式中， 所述 对所述校验比特进行交织得到第二组交织比特， 包括： 对所述校验比特进行 Quadaratic交织得到所述第二组交织比特。
结合第一方面及其上述实现方式， 在第一方面的另一实现方式中， 所述 基于所述第一组交织比特和所述第二组交织比特确定速率匹配的输出序列， 包括： 将所述第一组交织比特和所述第二组交织比特顺序地写入循环緩沖器 中； 根据冗余版本确定所述速率匹配的输出序列在所述循环緩沖器中的起始 位置； 根据所述起始位置从所述循环緩沖器中读取所述速率匹配的输出序 列。
结合第一方面及其上述实现方式， 在第一方面的另一实现方式中， 所述 基于所述第一组交织比特和所述第二组交织比特确定速率匹配的输出序列， 包括： 将所述第一组交织比特和所述第二组交织比特顺序地组合为第三组交 织比特； 顺序截取或者重复提取所述第三组交织比特中的比特以获得速率匹 配的输出序列。
第二方面， 提供了一种速率匹配装置， 包括： 分组单元， 用于将极性 Polar码编码器输出的系统 Polar码分为系统比特和校验比特； 交织单元， 用 于对所述系统比特进行交织得到第一组交织比特，对所述校验比特进行交织 得到第二组交织比特； 确定单元， 用于基于所述第一组交织比特和所述第二 组交织比特确定速率匹配的输出序列。
结合第二方面， 在第二方面的一种实现方式中， 所述交织单元具体用于 对所述系统比特进行二次 Quadaratic交织得到所述第一组交织比特，和 /或对 所述校验比特进行 Quadaratic交织得到所述第二组交织比特。
结合第二方面及其上述实现方式， 在第二方面的另一实现方式中， 所述 确定单元具体用于将所述第一组交织比特和所述第二组交织比特顺序地写 入循环緩沖器中，根据冗余版本确定速率匹配的输出序列在所述循环緩沖器 中的起始位置， 并根据所述起始位置从所述循环緩沖器中读取所述速率匹配 的输出序列。 结合第二方面及其上述实现方式， 在第二方面的另一实现方式中， 所述 确定单元具体用于将所述第一组交织比特和所述第二组交织比特顺序地组 合为第三组交织比特，顺序截取或者重复提取所述第三组交织比特中的比特 以获得所述速率匹配的输出序列。
第三方面， 提供了一种无线通信装置， 包括极性 Polar码编码器、 如上 所述的速率匹配装置和发射机。
本发明实施例对系统比特和校验比特分开进行交织，进而得到速率匹配 的输出序列，这样交织后的序列结构更具随机性，能够降低 FER( Frame Error Rate, 误帧率）， 从而能够改善 HARQ性能， 保证数据传输的可靠性。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例或现有技 术描述中所需要使用的附图作筒单地介绍， 显而易见地， 下面描述中的附图 仅仅是本发明的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造 性劳动的前提下， 还可以根据这些附图获得其他的附图。
图 1示出了本发明实施例的无线通信系统。
图 2示出了在无线通信环境中执行 Polar码的处理方法的系统。
图 3是本发明一个实施例的 Polar码的速率匹配方法的流程图。
图 4是本发明一个实施例的速率匹配装置的框图。
图 5是在无线通信系统中有助于执行 Polar码的处理方法的接入终端的 示意图。
图 6是在无线通信环境中有执行 Polar码的处理方法的系统的示意图。 图 7示出在无线通信环境中能够使用 Polar码的速率匹配方法的系统。 具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行 清楚、 完整地描述， 显然， 所描述的实施例是本发明一部分实施例， 而不是 全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有作出创 造性劳动前提下所获得的所有其他实施例， 都属于本发明保护的范围。
在本说明书中使用的术语 "部件"、 "模块"、 "系统 "等用于表示计算机 相关的实体、 硬件、 固件、 硬件和软件的组合、 软件、 或执行中的软件。 例 如， 部件可以是但不限于， 在处理器上运行的进程、 处理器、 对象、 可执行 文件、 执行线程、 程序和 /或计算机。 通过图示， 在计算设备上运行的应用和 计算设备都可以是部件。一个或多个部件可驻留在进程和 /或执行线程中，部 件可位于一个计算机上和 /或分布在两个或更多个计算机之间。此外，这些部 件可从在上面存储有各种数据结构的各种计算机可读介质执行。部件可例如 根据具有一个或多个数据分组 (例如来自与本地系统、 分布式系统和 /或网络 间的另一部件交互的二个部件的数据， 例如通过信号与其它系统交互的互联 网）的信号通过本地和 /或远程进程来通信。
此外， 结合接入终端描述了各个实施例。 接入终端也可以称为系统、 用 户单元、 用户站、 移动站、 移动台、 远方站、 远程终端、 移动设备、 用户终 端、 终端、 无线通信设备、 用户代理、 用户装置或 UE ( User Equipment, 用 户设备 )。 接入终端可以是蜂窝电话、 无绳电话、 SIP ( Session Initiation Protocol, 会话启动协议）电话、 WLL ( Wireless Local Loop, 无线本地环路） 站、 PDA ( Personal Digital Assistant, 个人数字处理）、 具有无线通信功能的 手持设备、 计算设备或连接到无线调制解调器的其它处理设备。 此外， 结合 基站描述了各个实施例。 基站可用于与移动设备通信， 基站可以是 GSM ( Global System of Mobile communication, 全球移动通讯 )或 CDMA ( Code Division Multiple Access, 码分多址)中的 BTS ( Base Transceiver Station, 基 站）， 也可以是 WCDMA ( Wideband Code Division Multiple Access, 宽带码 分多址） 中的 NB ( NodeB, 基站；)， 还可以是 LTE ( Long Term Evolution, 长期演进） 中的 eNB或 eNodeB ( Evolutional Node B, 演进型基站）， 或者 中继站或接入点， 或者未来 5G网络中的基站设备等。
此外， 本发明的各个方面或特征可以实现成方法、 装置或使用标准编程 和 /或工程技术的制品。 本申请中使用的术语 "制品"涵盖可从任何计算机可 读器件、 载体或介质访问的计算机程序。 例如， 计算机可读介质可以包括， 但不限于:磁存储器件（例如，硬盘、软盘或磁带等 ),光盘（例如， CD( Compact Disk, 压缩盘）、 DVD ( Digital Versatile Disk, 数字通用盘）等）， 智能卡和 闪存器件 (例^口, EPROM ( Erasable Programmable Read-Only Memory, 可 擦写可编程只读存储器）、 卡、 棒或钥匙驱动器等）。 另外， 本文描述的各种 存储介质可代表用于存储信息的一个或多个设备和 /或其它机器可读介质。术 语 "机器可读介质"可包括但不限于， 无线信道和能够存储、 包含和 /或承载 指令和 /或数据的各种其它介质。
现在， 参照图 1 , 示出根据本文所述的各个实施例的无线通信系统 100。 系统 100包括基站 102, 后者可包括多个天线组。 例如， 一个天线组可包括 天线 104和 106,另一个天线组可包括天线 108和 110,附加组可包括天线 112 和 114。 对于每个天线组示出了 2个天线， 然而可对于每个组使用更多或更 少的天线。 基站 102可附加地包括发射机链和接收机链， 本领域普通技术人 员可以理解，它们均可包括与信号发送和接收相关的多个部件（例如处理器、 调制器、 复用器、 解调器、 解复用器或天线等）。
基站 102可以与一个或多个接入终端 （例如接入终端 116和接入终端 122 )通信。 然而， 可以理解， 基站 102可以与类似于接入终端 116和 122 的基本上任意数目的接入终端通信。接入终端 116和 122可以是例如蜂窝电 话、 智能电话、 便携式电脑、 手持通信设备、 手持计算设备、 卫星无线电装 置、 全球定位系统、 PDA和 /或用于在无线通信系统 100上通信的任意其它 适合设备。 如图所示， 接入终端 116与天线 112和 114通信， 其中天线 112 和 114通过前向链路 118向接入终端 116发送信息， 并通过反向链路 120从 接入终端 116接收信息。 此外， 接入终端 122与天线 104和 106通信， 其中 天线 104和 106通过前向链路 124向接入终端 122发送信息， 并通过反向链 路 126从接入终端 122接收信息。 在 FDD ( Frequency Division Duplex, 频 分双工） 系统中， 例如， 前向链路 118可利用与反向链路 120所使用的不同 频带， 前向链路 124可利用与反向链路 126所使用的不同频带。 此外， 在 TDD ( Time Division Duplex, 时分双工）系统中， 前向链路 118和反向链路 120可使用共同频带， 前向链路 124和反向链路 126可使用共同频带。
被设计用于通信的每组天线和 /或区域称为基站 102的扇区。例如，可将 天线组设计为与基站 102覆盖区域的扇区中的接入终端通信。在通过前向链 路 118和 124的通信中，基站 102的发射天线可利用波束成形来改善针对接 入终端 116和 122的前向链路 118和 124的信噪比。 此外， 与基站通过单个 天线向它所有的接入终端发送相比，在基站 102利用波束成形向相关覆盖区 域中随机分散的接入终端 116和 122发送时， 相邻小区中的移动设备会受到 较少的干 4尤。
在给定时间， 基站 102、 接入终端 116和 /或接入终端 122可以是发送无 线通信装置和 /或接收无线通信装置。 当发送数据时， 发送无线通信装置 可 对数据进行编码以用于传输。具体地，发送无线通信装置可具有（例如生成、 获得、 在存储器中保存等）要通过信道发送至接收无线通信装置的一定数目 的信息比特。 这种信息比特可包含在数据的传输块（或多个传输块） 中， 其 可被分段以产生多个代码块。 此外， 发送无线通信装置可使用 Polar码编码 器（未示出） 来对每个代码块编码。
现在转到图 2, 示出在无线通信环境中执行 Polar码的处理方法的系统 200。 系统 200包括无线通信装置 202 ,该无线通信装置 202被显示为经由信 道发送数据。 尽管示出为发送数据， 但无线通信装置 202还可经由信道接收 数据 (例如， 无线通信装置 202可同时发送和接收数据， 无线通信装置 202 可以在不同时刻发送和接收数据， 或其组合等）。 无线通信装置 202例如可 以^ ϋ站（例如图 1的基站 102等）、 接入终端 （例如图 1的接入终端 116、 图 1的接入终端 122等）等。
无线通信装置 202可包括 Polar码编码器 204、 速率匹配装置 205和发 射机 206。
其中， Polar码编码器 204用于对要传送的数据进行编码， 得到相应的
Polar码。
如果 Polar码编码器 204编码后的 Polar码为系统码， 则速率匹配装置 205可用于将 Polar码编码器 204输出的系统 Polar码分为系统比特和校验比 特， 对系统比特进行交织得到第一组交织比特， 对校验比特进行交织得到第 二组交织比特， 然后基于第一组交织比特和第二组交织比特确定速率匹配的 输出序列。
如果 Polar码编码器 204编码后的 Polar码为非系统码，则速率匹配装置 205可用于对非系统 Polar码进行整体交织以得到交织比特， 然后基于交织 比特确定速率匹配的输出序列。
此外，发射机 206可随后在信道上传送经过速率匹配装置 205处理后的 速率匹配的输出序列。 例如， 发射机 206可以将相关数据发送到其它不同的 无线通信装置 （未示出）。
本发明实施例中， Polar码编码器 204编码后的 Polar码若为系统码， 则 可称为系统 Polar码； 若为非系统码， 则可称为非系统 Polar码。
一般地， 系统码是指其生成矩阵 G具有如下形式的码或其等价码：
G=[Ik , P] , 其中 Ik为 k阶单位矩阵， P为校验矩阵。
除了系统码之外的码可称为非系统码。
图 3是本发明一个实施例的 Polar码的速率匹配方法的流程图。 图 3的 方法由 Polar码的编码和发射端 （如图 2的速率匹配装置 205 )执行。
301 , 将系统 Polar码分为系统比特和校验比特。
系统比特是对应于上述生成矩阵 G中的单位矩阵 Ik部分的比特， 校验 比特是对应于上述生成矩阵 G中的校验矩阵 P部分的比特。
302 , 对系统比特进行交织得到第一组交织比特（Setl ), 对校验比特进 行交织得到第二组交织比特（Set2 )。
303 ,基于第一组交织比特和第二组交织比特确定速率匹配的输出序列。 本发明实施例对系统比特和校验比特分开进行交织，进而得到速率匹配 的输出序列， 这样交织后的序列结构更具随机性， 能够降低 FER, 从而能够 改善 HARQ性能， 保证数据传输的可靠性。
另外， 由于交织处理对系统比特和校验比特的最小距离的影响不同， 对 系统比特和校验比特分开进行交织， 能够进一步提高交织后的比特的最小距 离， 从而改善了 Polar码的速率匹配性能。
本发明实施例对步骤 302中所采用的交织处理的类型不作限制。 例如， 可以采用二次（Quadaratic ) 交织。
对以 N为 2的整数次幂， 定义函数：
c(m) = , k是一个奇数， 0 m<N;
Figure imgf000008_0001
Quadratic 交织的映射函数为： c(m) c(m + l) (modN) 0≤m < N。 换句话 说，第 c(m)个比特被映射至交织比特中的第 c(m+l)(mod N)个比特。这里 mod 是取模操作。
可选地， 作为一个实施例， 在步骤 302中对系统比特进行交织得到第一 组交织比特时， 可对系统比特进行二次（Quadaratic ) 交织得到第一组交织 比特。
可选地， 作为另一实施例， 在步骤 302中对校验比特进行交织得到第二 组交织比特时， 可对校验比特进行二次（Quadaratic ) 交织得到第二组交织 比特。
可选地， 作为另一实施例， 在步骤 303中基于第一组交织比特和第二组 交织比特确定速率匹配的输出序列时， 可利用循环緩沖器（Circular Buffer )。 具体地，可首先将第一组交织比特和第二组交织比特顺序地写入循环緩沖器 中， 即先将第一组交织比特写入循环緩沖器， 再将第二组交织比特写入循环 緩沖器。 然后， 可根据冗余版本（RV, Redundancy Version )确定速率匹配 的输出序列在循环緩沖器中的起始位置， 并根据起始位置从循环緩沖器中读 取比特作为速率匹配的输出序列。
在 Polar码的 HARQ过程中， 系统比特和校验比特的重要性是不同的， 具体地， 系统比特比校验比特更重要。 假设对系统比特交织得到的第一组交 织比特为 Setl , 对校验比特交织得到的第二组交织比特为 Set2。 将 Setl在 Set2之前写入循环緩沖器，可以使得速率匹配的输出序列中能更多地保留系 统比特， 由此可以提高 Polar码的 HARQ性能。
可选地， 作为另一实施例， 在步骤 303中基于第一组交织比特和第二组 交织比特确定速率匹配的输出序列时， 可将第一组交织比特（Setl )和第二 组交织比特（Set2 )顺序地组合为第三组交织比特（Set3 ), 即在 Set3 中， Setl 的所有比特在 Set2的所有比特之前。 然后， 可顺序截取或者重复提取 Set3中的比特以获得每次重传所需的速率匹配的输出序列。 例如， 当需要重 传的比特的长度 La短于 Set3的长度 Lb时， 可以从 Set3 中截取长度为 La 的部分比特作为速率匹配的输出序列。 再例如， 当需要重传的比特的长度 La长于 Set3的长度 Lb时， 可以在读取 Set3的所有比特之后， 从头开始再 次读取 Set3的比特，如此重复直至读取到长度为 La的速率匹配的输出序列。
在 Polar码的 HARQ过程中， 系统比特和校验比特的重要性是不同的， 具体地， 系统比特比校验比特更重要。 因此， 将对系统比特交织得到的第一 组交织比特 Setl放在对校验比特交织得到的第二组交织比特 Set2之前， 组 合为第三组交织比特 Set3 ,这样可以在最终得到的速率匹配的输出序列中更 多地保留系统比特， 从而提高 Polar码的 HARQ性能。
图 4是本发明一个实施例的速率匹配装置的框图。 图 4的速率匹配装置
400可以位于基站或用户设备， 包括分组单元 401、 交织单元 402和确定单 元 403。
分组单元 401将系统 Polar码分为系统比特和校验比特。 交织单元 402 对系统比特进行交织得到第一组交织比特，对校验比特进行交织得到第二组 交织比特。确定单元 403基于第一组交织比特和第二组交织比特确定速率匹 配的输出序列。 本发明实施例对系统比特和校验比特分开进行交织，进而得到速率匹配 的输出序列， 这样交织后的序列结构更具随机性， 能够降低 FER, 从而能够 改善 HARQ性能， 保证数据传输的可靠性。
另外， 由于交织处理对系统比特和校验比特的最小距离的影响不同， 对 系统比特和校验比特分开进行交织， 能够进一步提高交织后的比特的最小距 离， 从而改善了 Polar码的速率匹配性能。
本发明实施例对交织单元 402所采用的交织处理的类型不作限制。例如， 交织单元 402可以采用二次（ Quadaratic ) 交织。
可选地， 作为一个实施例， 交织单元 402 可以对系统比特进行二次 ( Quadaratic ) 交织得到第一组交织比特， 和 /或对校验比特进行二次 ( Quadaratic ) 交织得到第二组交织比特。
可选地， 作为另一实施例， 确定单元 403可以将第一组交织比特和第二 组交织比特顺序地写入循环緩沖器中，根据冗余版本确定速率匹配的输出序 列在循环緩沖器中的起始位置， 并根据起始位置从循环緩沖器中读取速率匹 配的输出序列。
在 Polar码的 HARQ过程中， 系统比特和校验比特的重要性是不同的， 具体地， 系统比特比校验比特更重要。 假设对系统比特交织得到的第一组交 织比特为 Setl , 对校验比特交织得到的第二组交织比特为 Set2。 将 Setl在 Set2之前写入循环緩沖器，可以使得速率匹配的输出序列中能更多地保留系 统比特， 由此可以提高 Polar码的 HARQ性能。
可选地， 作为另一实施例， 确定单元 403可以将第一组交织比特和第二 组交织比特顺序地组合为第三组交织比特，顺序截取或者重复提取第三组交 织比特中的比特以获得速率匹配的输出序列。
在 Polar码的 HARQ过程中， 系统比特和校验比特的重要性是不同的， 具体地， 系统比特比校验比特更重要。 因此， 将对系统比特交织得到的第一 组交织比特 Setl放在对校验比特交织得到的第二组交织比特 Set2之前， 组 合为第三组交织比特 Set3 ,这样可以在最终得到的速率匹配的输出序列中更 多地保留系统比特， 从而提高 Polar码的 HARQ性能。
图 5是在无线通信系统中有助于执行前述 Polar码的处理方法的接入终 端 500的示意图。 接入终端 500包括接收机 502, 接收机 502用于从例如接 收天线（未示出）接收信号， 并对所接收的信号执行典型的动作（例如过滤、 放大、 下变频等）， 并对调节后的信号进行数字化以获得采样。 接收机 502 可以是例如 MMSE (最小均方误差， Minimum Mean-Squared Error )接收机。 接入终端 500还可包括解调器 504, 解调器 504可用于解调所接收的符号并 将它们提供至处理器 506用于信道估计。处理器 506可以是专用于分析由接 收机 502接收的信息和 /或生成由发射机 516发送的信息的处理器、用于控制 接入终端 500的一个或多个部件的处理器、和 /或用于分析由接收机 502接收 的信息、生成由发射机 516发送的信息并控制接入终端 500的一个或多个部 件的控制器。
接入终端 500 可以另外包括存储器 508, 后者可操作地耦合至处理器 506, 并存储以下数据： 要发送的数据、 接收的数据以及与执行本文所述的 各种动作和功能相关的任意其它适合信息。 存储器 508可附加地存储 Polar 码处理的相关的协议和 /或算法。
可以理解， 本文描述的数据存储装置（例如存储器 508 )可以是易失性 存储器或非易失性存储器， 或可包括易失性和非易失性存储器两者。 通过示 例但不是限制性的， 非易失性存储器可包括： ROM ( Read-Only Memory, 只读存储器）、 PROM ( Programmable ROM, 可编程只读存储器）、 EPROM ( Erasable PROM , 可擦除可编程只读存储器）、 EEPROM ( Electrically EPROM, 电可擦除可编程只读存储器）或闪存。 易失性存储器可包括： RAM ( Random Access Memory, 随机存取存储器）， 其用作外部高速緩存。 通过 示例性但不是限制性说明，许多形式的 RAM可用，例如 SRAM( Static RAM, 静态随机存取存储器）、 DRAM ( Dynamic RAM, 动态随机存取存储器）、 SDRAM ( Synchronous DRAM, 同步动态随机存取存储器）、 DDR SDRAM ( Double Data Rate SDRAM, 双倍数据速率同步动态随机存取存储器）、 ESDRAM ( Enhanced SDRAM,增强型同步动态随机存取存储器 )、 SLDRAM ( Synchlink DRAM, 同步连接动态随机存取存储器）和 DR RAM ( Direct Rambus RAM, 直接内存总线随机存取存储器）。 本文描述的系统和方法的 存储器 508旨在包括但不限于这些和任意其它适合类型的存储器。
实际的应用中， 接收机 502还可以耦合至速率匹配设备 510。 速率匹配 设备 510可基本类似于图 2的速率匹配装置 205, 此外， 接入终端 500还可 包括 Polar码编码器 512。 Polar码编码器 512基本类似于图 2的 Polar码编 码器 204。 如果 Polar码编码器 512编码得到系统 Polar码， 则速率匹配设备 510 可以用于将系统 Polar码分为系统比特和校验比特， 对系统比特进行交织得 到第一组交织比特（ Setl ),对校验比特进行交织得到第二组交织比特（ Set2 ), 基于第一组交织比特和第二组交织比特确定速率匹配的输出序列。
本发明实施例对系统比特和校验比特分开进行交织，进而得到速率匹配 的输出序列， 这样交织后的序列结构更具随机性， 能够降低 FER, 从而能够 改善 HARQ性能， 保证数据传输的可靠性。
另外， 由于交织处理对系统比特和校验比特的最小距离的影响不同， 对 系统比特和校验比特分开进行交织， 能够进一步提高交织后的比特的最小距 离， 从而改善了 Polar码的速率匹配性能。。
另一方面，如果 Polar码编码器 512编码得到非系统 Polar码，则速率匹 配设备 510可以用于对非系统 Polar码进行整体交织以得到交织比特， 基于 交织比特确定速率匹配的输出序列。
本发明实施例对非系统的 Polar码进行整体交织， 交织后的比特的最小 距离有所提高， 从而改善了 Polar码的速率匹配性能。
本发明实施例对速率匹配设备 510 中所采用的交织处理的类型不作限 制。 例如， 可以采用二次（ Quadaratic ) 交织。
对以 N为 2的整数次幂， 定义函数：
c(m) = , k是一个奇数， 0 m<N;
Figure imgf000012_0001
Quadratic 交织的映射函数为： c(m) c(m + l) (modN) 0 < m < N 。 换句话 说，第 c(m)个比特被映射至交织比特中的第 c(m+l)(mod N)个比特。这里 mod 是取模操作。
可选地， 作为一个实施例， 速率匹配设备 510在对系统比特进行交织得 到第一组交织比特时， 可对系统比特进行二次（Quadaratic ) 交织得到第一 组交织比特。
可选地， 作为另一实施例， 速率匹配设备 510在对校验比特进行交织得 到第二组交织比特时， 可对校验比特进行二次（Quadaratic ) 交织得到第二 组交织比特。
可选地， 作为另一实施例， 速率匹配设备 510在基于第一组交织比特和 第二组交织比特确定速率匹配的输出序列时， 可利用循环緩沖器。 具体地， 速率匹配设备 510可首先将第一组交织比特和第二组交织比特顺序地写入循 环緩沖器中， 即先将第一组交织比特写入循环緩沖器， 再将第二组交织比特 写入循环緩沖器。 然后， 可根据冗余版本确定速率匹配的输出序列在循环緩 沖器中的起始位置， 并根据起始位置从循环緩沖器中读取比特作为速率匹配 的输出序列。
在 Polar码的 HARQ过程中， 系统比特和校验比特的重要性是不同的， 具体地， 系统比特比校验比特更重要。 假设对系统比特交织得到的第一组交 织比特为 Setl , 对校验比特交织得到的第二组交织比特为 Set2。 将 Setl在 Set2之前写入循环緩沖器，可以使得速率匹配的输出序列中能更多地保留系 统比特， 由此可以提高 Polar码的 HARQ性能。
可选地， 作为另一实施例， 速率匹配设备 510在基于第一组交织比特和 第二组交织比特确定速率匹配的输出序列时， 可将第一组交织比特（Setl ) 和第二组交织比特（ Set2 )顺序地组合为第三组交织比特（ Set3 ), 即在 Set3 中， Setl 的所有比特在 Set2 的所有比特之前。 然后， 可顺序截取或者重复 提取 Set3中的比特以获得每次重传所需的速率匹配的输出序列。例如， 当需 要重传的比特的长度 La短于 Set3的长度 Lb时， 可以从 Set3中截取长度为 La 的部分比特作为速率匹配的输出序列。 再例如， 当需要重传的比特的长 度 La长于 Set3的长度 Lb时， 可以在读取 Set3的所有比特之后， 从头开始 再次读取 Set3的比特， 如此重复直至读取到长度为 La的速率匹配的输出序 列。
在 Polar码的 HARQ过程中， 系统比特和校验比特的重要性是不同的， 具体地， 系统比特比校验比特更重要。 因此， 将对系统比特交织得到的第一 组交织比特 Setl放在对校验比特交织得到的第二组交织比特 Set2之前， 组 合为第三组交织比特 Set3 ,这样可以在最终得到的速率匹配的输出序列中更 多地保留系统比特， 从而提高 Polar码的 HARQ性能。
可选地， 作为一个实施例， 速率匹配设备 510在对非系统的 Polar码进 行整体交织以得到交织比特时，可对非系统的 Polar码进行二次（ Quadaratic ) 交织以得到交织比特。
可选地， 作为另一实施例， 速率匹配设备 510在基于交织比特确定速率 匹配的输出序列时， 可将交织比特写入循环緩沖器中， 根据冗余版本确定速 率匹配的输出序列在循环緩沖器中的起始位置，根据起始位置从循环緩沖器 中读取速率匹配的输出序列。 可选地， 作为另一实施例， 速率匹配设备 510在基于交织比特确定速率 匹配的输出序列时， 可顺序截取或者重复提取交织比特中的比特以获得每次 重传所需的速率匹配的输出序列。
此外，接入终端 500还可以包括调制器 514和发射机 516,该发射机 516 用于向例如基站、 另一接入终端等发送信号。 尽管示出与处理器 506分离， 但是可以理解， Polar码编码器 512, 速率匹配设备 510和 /或调制器 514可 以是处理器 506或多个处理器（未示出） 的一部分。
图 6是在无线通信环境中有执行前述 Polar码的处理方法的系统 600的 示意图。 系统 600包括基站 602 (例如接入点， NodeB或 eNB等）， 基站 602 具有通过多个接收天线 606从一个或多个接入终端 604接收信号的接收机 610, 以及通过发射天线 608向一个或多个接入终端 604发射信号的发射机 624。 接收机 610可以从接收天线 606接收信息， 并且可操作地关联至对接 收信息进行解调的解调器 612。 通过相对于图 7描述的处理器类似的处理器 614来分析所解调的符号， 该处理器 614连接至存储器 616, 该存储器 616 用于存储要发送至接入终端 604 (或不同的基站（未示出））的数据或从接入 终端 604 (或不同的基站（未示出））接收的数据和 /或与执行本文所述的各 个动作和功能相关的任意其它适合信息。 处理器 614还可耦合至 Polar码编 码器 618和速率匹配装置 620。
根据本发明实施例的一个方面， 该速率匹配装置 620可以用于将 Polar 码编码器 618输出的系统 Polar码分为系统比特和校验比特， 对系统比特进 行交织得到第一组交织比特（Setl ) ,对校验比特进行交织得到第二组交织比 特（ Set2 )，基于第一组交织比特和第二组交织比特确定速率匹配的输出序列。
本发明实施例对系统比特和校验比特分开进行交织，进而得到速率匹配 的输出序列， 这样交织后的序列结构更具随机性， 能够降低 FER, 从而能够 改善 HARQ性能， 保证数据传输的可靠性。
另外， 由于交织处理对系统比特和校验比特的最小距离的影响不同， 对 系统比特和校验比特分开进行交织， 能够进一步提高交织后的比特的最小距 离， 从而改善了 Polar码的速率匹配性能。。
根据本发明实施例的另一方面， 该速率匹配装置 620可以用于对 Polar 码编码器 618输出的非系统 Polar码进行整体交织以得到交织比特， 基于交 织比特确定速率匹配的输出序列。 本发明实施例对非系统的 Polar码进行整体交织， 交织后的比特的最小 距离有所提高， 从而改善了 Polar码的速率匹配性能。
本发明实施例对速率匹配装置 620 中所采用的交织处理的类型不作限 制。 例如， 可以采用二次（ Quadaratic ) 交织。
对以 N为 2的整数次幂， 定义函数：
c(m) = , k是一个奇数， 0 m<N;
Figure imgf000015_0001
Quadratic 交织的映射函数为： c(m) c(m + l) (modN) Q < m < N 。 换句话 说，第 c(m)个比特被映射至交织比特中的第 c(m+l)(mod N)个比特。这里 mod 是取模操作。
可选地， 作为一个实施例， 速率匹配装置 620在对系统比特进行交织得 到第一组交织比特时， 可对系统比特进行二次（Quadaratic ) 交织得到第一 组交织比特。
可选地， 作为另一实施例， 速率匹配装置 620在对校验比特进行交织得 到第二组交织比特时， 可对校验比特进行二次（Quadaratic ) 交织得到第二 组交织比特。
可选地， 作为另一实施例， 速率匹配装置 620在基于第一组交织比特和 第二组交织比特确定速率匹配的输出序列时， 可利用循环緩沖器。 具体地， 速率匹配装置 620可首先将第一组交织比特和第二组交织比特顺序地写入循 环緩沖器中， 即先将第一组交织比特写入循环緩沖器， 再将第二组交织比特 写入循环緩沖器。 然后， 可根据冗余版本确定速率匹配的输出序列在循环緩 沖器中的起始位置， 并根据起始位置从循环緩沖器中读取比特作为速率匹配 的输出序列。
在 Polar码的 HARQ过程中， 系统比特和校验比特的重要性是不同的， 具体地， 系统比特比校验比特更重要。 假设对系统比特交织得到的第一组交 织比特为 Setl , 对校验比特交织得到的第二组交织比特为 Set2。 将特 Setl 在 Set2之前写入循环緩沖器，可以使得速率匹配的输出序列中能更多地保留 系统比特， 由此可以提高 Polar码的 HARQ性能。
可选地， 作为另一实施例， 速率匹配装置 620在基于第一组交织比特和 第二组交织比特确定速率匹配的输出序列时， 可将第一组交织比特（Setl ) 和第二组交织比特（ Set2 )顺序地组合为第三组交织比特（ Set3 ), 即在 Set3 中， Setl 的所有比特在 Set2 的所有比特之前。 然后， 可顺序截取或者重复 提取 Set3中的比特以获得每次重传所需的速率匹配的输出序列。例如， 当需 要重传的比特的长度 La短于 Set3的长度 Lb时， 可以从 Set3中截取长度为 La 的部分比特作为速率匹配的输出序列。 再例如， 当需要重传的比特的长 度 La长于 Set3的长度 Lb时， 可以在读取 Set3的所有比特之后， 从头开始 再次读取 Set3的比特， 如此重复直至读取到长度为 La的速率匹配的输出序 列。
在 Polar码的 HARQ过程中， 系统比特和校验比特的重要性是不同的， 具体地， 系统比特比校验比特更重要。 因此， 将对系统比特交织得到的第一 组交织比特 Setl在对校验比特交织得到的第二组交织比特 Set2之前组合为 第三组交织比特 Set3 ,这样可以在最终得到的速率匹配的输出序列中更多地 保留系统比特， 从而提高 Polar码的 HARQ性能。
可选地， 作为一个实施例， 速率匹配装置 620在对非系统的 Polar码进 行整体交织以得到交织比特时，可对非系统的 Polar码进行二次（ Quadaratic ) 交织以得到交织比特。
可选地， 作为另一实施例， 速率匹配装置 620在基于交织比特确定速率 匹配的输出序列时， 可将交织比特写入循环緩沖器中， 根据冗余版本确定速 率匹配的输出序列在循环緩沖器中的起始位置，根据起始位置从循环緩沖器 中读取速率匹配的输出序列。
可选地， 作为另一实施例， 速率匹配装置 620在基于交织比特确定速率 匹配的输出序列时， 可顺序截取或者重复提取交织比特中的比特以获得每次 重传所需的速率匹配的输出序列。
此外， 在系统 600中， 调制器 622可以对帧进行复用以用于发射机 624 通过天线 608发送到接入终端 604尽管示出为与处理器 614分离，但是可以 理解， Polar码编码器 618、 速率匹配装置 620和 /或调制器 622可以是处理 器 614或多个处理器（未示出） 的一部分。
可以理解的是， 本文描述的这些实施例可以用硬件、 软件、 固件、 中间 件、 微码或其组合来实现。 对于硬件实现， 处理单元可以实现在一个或多个 ASIC ( Application Specific Integrated Circuits, 专用集成电路）、 DSP ( Digital Signal Processing, 数字信号处理器）、 DSPD ( DSP Device, 数字信号处理设 备）、 PLD ( Programmable Logic Device , 可编程逻辑设备）、 FPGA ( Field-Programmable Gate Array, 现场可编程门阵列）、 处理器、 控制器、 微控制器、微处理器、用于执行本申请所述功能的其它电子单元或其组合中。 当在软件、 固件、 中间件或微码、 程序代码或代码段中实现实施例时， 它们可存储在例如存储部件的机器可读介质中。 代码段可表示过程、 函数、 子程序、 程序、 例程、 子例程、 模块、 软件分组、 类、 或指令、 数据结构或 程序语句的任意组合。 代码段可通过传送和 /或接收信息、 数据、 自变量、 参 数或存储器内容来稿合至另一代码段或硬件电路。 可使用包括存储器共享、 消息传递、 令牌传递、 网络传输等任意适合方式来传递、 转发或发送信息、 自变量、 参数、 数据等。
对于软件实现， 可通过执行本文所述功能的模块（例如过程、 函数等） 行。 存储器单元可以在处理器中或在处理器外部实现， 在后一种情况下存储 器单元可经由本领域己知的各种手段以通信方式耦合至处理器。
参照图 7, 示出在无线通信环境中能够使用 Polar码的速率匹配方法的 系统 700。 例如， 系统 700可至少部分地驻留在基站中。 居另一示例， 系 统 700可至少部分地驻留在接入终端中。 应理解的是， 系统 700可表示为包 括功能框， 其可以是表示由处理器、 软件或其组合（例如固件）实现的功能 的功能框。 系统 700包括具有联合操作的电子部件的逻辑组 702。
例如， 逻辑组 702可包括用于将系统 Polar码分为系统比特和校验比特 的电子部件 704, 用于对系统比特进行交织得到第一组交织比特并对校验比 特进行交织得到第二组交织比特的电子部件 706。 逻辑组 702还可以包括用 于基于第一组交织比特和第二组交织比特确定速率匹配的输出序列的电子 部件 708。
本发明实施例对系统比特和校验比特分开进行交织，进而得到速率匹配 的输出序列， 这样交织后的序列结构更具随机性， 能够降低 FER, 从而能够 改善 HARQ性能， 保证数据传输的可靠性。
另外， 由于交织处理对系统比特和校验比特的最小距离的影响不同， 对 系统比特和校验比特分开进行交织， 能够进一步提高交织后的比特的最小距 离， 从而改善了 Polar码的速率匹配性能。。
此外， 系统 700可包括存储器 712, 后者保存用于执行与电子部件 704, 706和 708相关的功能的指令。 尽管示出为在存储器 712的外部， 但是可理 解， 电子部件 704、 706和 708中的一个或多个可存在于存储器 712中。 本领域普通技术人员可以意识到， 结合本文中所公开的实施例描述的各 示例的单元及算法步骤， 能够以电子硬件、 或者计算机软件和电子硬件的结 合来实现。 这些功能究竟以硬件还是软件方式来执行， 取决于技术方案的特 定应用和设计约束条件。 专业技术人员可以对每个特定的应用来使用不同方 法来实现所描述的功能， 但是这种实现不应认为超出本发明的范围。
所属领域的技术人员可以清楚地了解到， 为描述的方便和筒洁， 上述描 述的系统、 装置和单元的具体工作过程， 可以参考前述方法实施例中的对应 过程， 在此不再赘述。
在本申请所提供的几个实施例中， 应该理解到， 所揭露的系统、 装置和 方法， 可以通过其它的方式实现。 例如， 以上所描述的装置实施例仅仅是示 意性的， 例如， 所述单元的划分， 仅仅为一种逻辑功能划分， 实际实现时可 以有另外的划分方式， 例如多个单元或组件可以结合或者可以集成到另一个 系统， 或一些特征可以忽略， 或不执行。 另一点， 所显示或讨论的相互之间 的耦合或直接耦合或通信连接可以是通过一些接口， 装置或单元的间接耦合 或通信连接， 可以是电性， 机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作 为单元显示的部件可以是或者也可以不是物理单元， 即可以位于一个地方， 或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或 者全部单元来实现本实施例方案的目的。
另外， 在本发明各个实施例中的各功能单元可以集成在一个处理单元 中， 也可以是各个单元单独物理存在， 也可以两个或两个以上单元集成在一 个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使 用时， 可以存储在一个计算机可读取存储介质中。 基于这样的理解， 本发明 的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部 分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质 中， 包括若干指令用以使得一台计算机设备（可以是个人计算机， 服务器， 或者网络设备等）执行本发明各个实施例所述方法的全部或部分步骤。 而前 述的存储介质包括： U盘、移动硬盘、只读存储器（ ROM, Read-Only Memory )、 随机存取存储器（RAM, Random Access Memory ), 磁碟或者光盘等各种可 以存储程序代码的介质。 以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保护 范围应所述以权利要求的保护范围为准。

Claims

权利要求
1、 一种极性 Polar码的速率匹配方法， 其特征在于， 包括：
将 Polar码编码器输出的系统 Polar码分为系统比特和校验比特； 对所述系统比特进行交织得到第一组交织比特，对所述校验比特进行交 织得到第二组交织比特；
基于所述第一组交织比特和所述第二组交织比特确定速率匹配的输出 序列。
2、 如权利要求 1所述的方法， 其特征在于， 所述对所述系统比特进行 交织得到第一组交织比特， 包括：
对所述系统比特进行二次 Quadaratic交织得到所述第一组交织比特。
3、 如权利要求 1或 2所述的方法， 其特征在于， 所述对所述校验比特 进行交织得到第二组交织比特， 包括：
对所述校验比特进行 Quadaratic交织得到所述第二组交织比特。
4、 如权利要求 1-3任一项所述的方法， 其特征在于， 所述基于所述第 一组交织比特和所述第二组交织比特确定速率匹配的输出序列， 包括： 将所述第一组交织比特和所述第二组交织比特顺序地写入循环緩沖器 中；
根据冗余版本确定所述速率匹配的输出序列在所述循环緩沖器中的起 始位置；
根据所述起始位置从所述循环緩沖器中读取所述速率匹配的输出序列。
5、 如权利要求 1-3任一项所述的方法， 其特征在于， 所述基于所述第 一组交织比特和所述第二组交织比特确定速率匹配的输出序列， 包括： 将所述第一组交织比特和所述第二组交织比特顺序地组合为第三组交 织比特；
顺序截取或者重复提取所述第三组交织比特中的比特以获得速率匹配 的输出序列。
6、 一种速率匹配装置， 其特征在于， 包括：
分组单元，用于将极性 Polar码编码器输出的系统 Polar码分为系统比特 和校验比特；
交织单元， 用于对所述系统比特进行交织得到第一组交织比特， 对所述 校验比特进行交织得到第二组交织比特； 确定单元，用于基于所述第一组交织比特和所述第二组交织比特确定速 率匹配的输出序列。
7、 如权利要求 6所述的速率匹配装置， 其特征在于， 所述交织单元具 体用于对所述系统比特进行二次 Quadaratic交织得到所述第一组交织比特， 和 /或对所述校验比特进行 Quadaratic交织得到所述第二组交织比特。
8、 如权利要求 6或 7所述的速率匹配装置， 其特征在于， 所述确定单 元具体用于将所述第一组交织比特和所述第二组交织比特顺序地写入循环 緩沖器中，根据冗余版本确定速率匹配的输出序列在所述循环緩沖器中的起 始位置， 并根据所述起始位置从所述循环緩沖器中读取所述速率匹配的输出 序列。
9、 如权利要求 6或 7所述的速率匹配装置， 其特征在于， 所述确定单 元具体用于将所述第一组交织比特和所述第二组交织比特顺序地组合为第 三组交织比特，顺序截取或者重复提取所述第三组交织比特中的比特以获得 所述速率匹配的输出序列。
10、 一种无线通信装置， 包括极性 Polar码编码器、 如权利要求 6-9任 一项所述的速率匹配装置和发射机。
PCT/CN2014/073719 2014-03-19 2014-03-19 极性码的速率匹配方法和速率匹配装置 WO2015139248A1 (zh)

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US20170005753A1 (en) 2017-01-05

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