WO2015120657A1 - 一种多值非易失性有机阻变存储器及制备方法 - Google Patents

一种多值非易失性有机阻变存储器及制备方法 Download PDF

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WO2015120657A1
WO2015120657A1 PCT/CN2014/074359 CN2014074359W WO2015120657A1 WO 2015120657 A1 WO2015120657 A1 WO 2015120657A1 CN 2014074359 W CN2014074359 W CN 2014074359W WO 2015120657 A1 WO2015120657 A1 WO 2015120657A1
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parylene
electrode
bottom electrode
layer
volatile organic
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蔡一茂
刘业帆
方亦陈
王宗巍
李强
余牧溪
潘越
黄如
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Peking University
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    • G11C11/5664—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using organic memory material storage elements
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    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0014—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material
    • G11C13/0016—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material comprising polymers
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    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/023—Formation of switching materials, e.g. deposition of layers by chemical vapor deposition, e.g. MOCVD, ALD
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    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
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    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/15—Current-voltage curve
    • G—PHYSICS
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Definitions

  • the invention belongs to the field of organic electronics and CMOS hybrid integrated circuit technology. Specifically, it relates to a multi-value non-volatile organic resistive memory (organic resistive random access memory) Structure and preparation method thereof.
  • resistive memory has received extensive attention in the field of integrated circuits and has made great progress.
  • the resistive memory is a non-volatile memory, and the share of non-volatile memory in the current market is mainly flash memory. Occupy (flash). With the further development of integrated circuits, resistive memory is reduced in size, operating voltage, etc. The advantages make it a strong competitor in the new generation of memory.
  • the basic principle of resistive memory is that The resistor embodied in the memory structure can be in a high-impedance state ("0" state) under the application of an applied voltage or current.
  • Multivalue storage has always been a research topic of interest in non-volatile memory.
  • Multivalued Storage has a very significant effect on increasing storage density.
  • resistive memory a multi-value implementation method Is to introduce an intermediate resistance between the high-resistance state and the low-resistance state, so that each memory cell can store more than two state.
  • the method of achieving the intermediate resistance state is roughly divided into two types: 1.
  • the present invention is directed to the above problems, and proposes an organic realization of multi-value storage based on multi-layered parylene. Resistive memory and its preparation method.
  • a multi-valued non-volatile organic resistive memory comprising a top electrode, a bottom electrode, and a top electrode and a bottom An intermediate functional layer between the electrodes, the intermediate functional layer being at least two layers of parylene.
  • the top electrode and the bottom electrode are made of an inert electrode, preferably a W electrode, and the thickness is 200 nm to 500 nm.
  • the above resistive memory uses a silicon substrate.
  • the parylene layer as a functional layer has a total thickness of 40 nm to 80 nm and is divided into a plurality of layers. The two layers were exposed to air for 1 day for oxidation of the surface, and the thickness of each layer was controlled to be 10 nm to 20 nm.
  • the polymer of parylene is parylene C type, parylene type N or poly pair Xylene type D.
  • the present invention also provides a method for fabricating the above multi-value non-volatile organic resistive memory, including the following step:
  • the bottom electrode material is grown on the substrate by physical vapor deposition (PVD) method, and standard photolithography is used. Technology to pattern the bottom electrode;
  • PVD physical vapor deposition
  • the top electrode and the bottom electrode are made of W and have a thickness of 200 nm to 500 nm, and the substrate is Silicon substrate.
  • the parylene layer as a functional layer has a total thickness of 40 nm to 80 nm and is divided into a plurality of layers. The two layers were exposed to air for 1 day for oxidation of the surface, and the thickness of each layer was controlled to be 10 nm to 20 nm.
  • step 2) when the parylene is grown by the Polymer CVD method, the deposition rate is 1 nm/min to 10 nm/min.
  • the polymer of parylene is parylene C type, parylene type N or poly pair Xylene type D.
  • step 3 is that the user etches into an RIE etch.
  • the beneficial effects of the invention under the condition that the basic structure of the device is not changed, the use of both sides is relatively inert
  • the electrode and the deposition of a plurality of layers of parylene achieve a multi-value storage function with a self-limiting effect.
  • FIG. 1 is a schematic diagram showing a current-voltage characteristic curve of a resistive process of a multi-valued non-volatile organic resistive memory of the present invention
  • 2 to 7 are schematic diagrams showing the steps of the steps of the method for preparing a resistive memory in the embodiment.
  • Figure 8 is a diagrammatic illustration of Figures 2-7.
  • the present invention proposes a new resistive memory structure to implement multi-valued storage with self-limiting current characteristics.
  • the resistive memory can be fabricated on a silicon substrate, and the device unit is a MIM (Metal-Insulator-Metal) capacitor junction. Structure, using upper and lower layer structure, the intermediate functional layer adopts parylene with excellent resistance change characteristics (parylene-C), the top electrode and the bottom electrode of the MIM structure are preferably W.
  • the device is characterized by The parylene layer of the energy layer is deposited multiple times, by the difference in the number of depositions and the thickness of each deposition. To achieve the function of device multi-value storage.
  • the device resistance mechanism caused by the active electrode is mainly caused by the diffusion of the electrode.
  • the device of the present invention avoids this situation by using W electrodes on both sides, and is formed by The change in resistance determined by the inherent defects in the functional layer of the parylene layer and the interfacial defects of the different layers of parylene.
  • the present invention preferably employs an inert electrode W, where inertness is primarily directed to electrode ionization that does not occur. The diffusion into the parylene occurs later.
  • Pt electrodes or electrically active TiNs can also be used (but No ionization diffusion will occur) and so on.
  • inert electrodes are mainly to avoid the formation of a conductive mode of metal filament channels. Because the formation/breaking of metal filaments is difficult to react completely, it is only necessary to break a layer after the formation of the reset process. Therefore, only a low resistance / high resistance state is shown. Using the defects of parylene itself to conduct electricity can be effectively realized High resistance recovery.
  • the current-voltage (I-V) characteristic curve of the resistive memory of the resistive memory of the present invention is shown in FIG.
  • a SET RESET for each resistance state of a three-layer parylene (thickness 10/10/20 nm) structure is given.
  • the voltage scanning direction of each curve is as shown by the arrow, we can see that there are three different sets of the device SET and RESET processes and three sets of states that can be switched between each other (state1 and state5, state2 and state3, State4 and state5), the SET1 and RESET1 procedures implement the conversion between state1 and state5; SET2 and The RESET2 process implements the conversion between state2 and state3; the SET3 and RESET3 processes implement state4 Conversion between and state5.
  • the switching between the three groups of states is completed by the RESET process, we can see
  • the curve of RESET1 can be divided into two large mutation phases, corresponding to the device from the state1 state RESET To the state3 and state5 states, so the controller can be adjusted by adjusting the magnitude of the cutoff voltage during RESET1 A transition between different sets of states.
  • the state to be utilized is only 2N-1, that is, 5. Since the thickness of the parylene monolayer is difficult to prepare below 10 nm, Under this limitation, after the number of parylene layers increases, the total thickness of the device becomes large, and the state can be effectively distinguished. The number should be less than 2N, but the resistance of the device is reduced after the parylene layer is turned on based on at most half of the thickness. The layer-by-layer conduction of the parylene layer resistance can be distinguished, so that at least N states can be realized. Polylayer The thickness of xylene affects the ratio between a set of low-resistance/high-resistance states corresponding to its turn-on/turn-off. The larger the ratio between the corresponding low resistance/high resistance states. The present invention generally selects a total thickness of parylene of 40 nm. Between 80 nm, the thickness of each layer is controlled between 10 nm and 20 nm.
  • Parylene-C (polyparaxylene C type) layer is grown by Polymer CVD technology, as shown in the figure. 3, the layer thickness is 20nm; deposition using poly-p-xylene Polymer CVD equipment, process equipment Standard parameters, deposition rate between 1nm/min and 10nm/min;
  • the layer thickness is 10nm; deposition using poly-p-xylene Polymer CVD equipment, process selection equipment standard parameters, deposition rate Degree between 1nm/min and 10nm/min;
  • the third layer of Parylene-C layer is grown by Polymer CVD technology, as shown in Figure 5, the layer thickness is 10nm; deposition using poly-p-xylene Polymer CVD equipment, process selection equipment standard parameters, deposition rate Degree between 1nm/min and 10nm/min;
  • the thickness is 500 nm, and the standard is used. Quasi-lithography technology to pattern the lower electrode (bottom electrode);
  • Parylene-D (polyparaxylene N type) layer is grown by Polymer CVD technology. Degree is 10nm; deposition using poly-p-xylene Polymer CVD equipment, the standard parameters of the process equipment, The product speed is between 1 nm/min and 10 nm/min;
  • the thickness of the multilayer parylene in this embodiment is 10/20/10 nm, respectively, and the SET/RESET process occurs.
  • the layer is also 10/20/10 nm in order, since the intermediate layer is 20 nm thick, the operating voltage of the intermediate state should be better than that of the embodiment.
  • the larger of 1 is also better to distinguish the operating voltage range of different layers of parylene, which can be compared with that in Embodiment 1. Achieve better device performance.

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Abstract

一种多值非易失性有机阻变存储器及其制备方法。该阻变存储器包括顶电极、底电极以及位于顶电极和底电极之间的中间功能层，中间功能层为至少两层聚对二甲苯。该方法包括：采用PVD方法在衬底上生长底电极材料，并采用标准光刻技术使底电极图形化；采用聚合物化学气相淀积方法在底电极上依次生长多层聚对二甲苯材料；通过光刻和刻蚀定义底层电极的引出通孔；采用PVD方法在聚对二甲苯材料上生长顶电极材料，通过光刻、剥离定义顶层电极，并将底电极引出。在不改变器件基本结构的条件下，通过采用两侧均为较惰性电极以及多层聚对二甲苯的淀积来实现具有自限流效果的多值存储功能。

Description

一种多值非易失性有机阻变存储器及制备方法
相关申请的交叉引用
本申请要求于2014年2月11日提交的中国专利申请（201410047253.4）的优先 权，其全部内容通过引用合并于此。
技术领域
本发明属于有机电子学（organic electronics）和CMOS混合集成电路技术领域， 具体涉及一种多值非易失性有机阻变存储器（organic resistive random access memory） 的结构及其制备方法。
背景技术
近年来，阻变存储器在集成电路领域得到了广泛的关注并取得了很大的进展， 阻变存储器属于非易失性存储器，非易失性存储器在当前市场上的份额主要被闪存 （flash）所占据。随着集成电路的进一步发展，阻变存储器在尺寸缩小、操作电压等 方面的优势使之成为了新一代存储器中的有力竞争者。阻变存储器的基本原理在于， 存储器结构所体现出的电阻在外加电压或者电流的激励下可以在高阻态（“0”状态） 和低阻态（“1”状态）之间实现可逆的转换，从而实现数据的存储，我们通常称使器 件从高阻态向低阻态转变的操作为SET过程，从低阻态向高阻态转变的操作为 RESET过程。在阻变存储器材料的选择中，有机材料体现了巨大的优势。有机材料 种类丰富，合成、制备工艺简单，成本低。同时，有机材料可以用于实现如透明纸张 （e-paper），电子显示（OLED）等透明电子系统。
另一方面，多值存储一直是非易失性存储器中的一个备受关注研究方向。多值 存储对于提高存储密度有非常显著的作用，在阻变存储器中，一种多值实现的方法就 是引入介于高阻态和低阻态之间的中间阻态，可以使每个存储单元能存储超过两种状 态。当前的研究中，根据器件的特性不同，实现中间阻态的方法大致分为两种：1.在 SET过程中施加限制电流，使器件的SET不充分，从而实现阻值较高的低阻态；2.在 RESET过程中施加不同幅度的电压，使器件的RESET过程不充分，从而实现阻值较 低的高阻态。然而，以上两种方法首先对外部控制电路提出了一定的要求，其次不同 阻态的区分通常不够明显，在实际使用中存在相当大的困难，如何设计实现更加实用 的多值非易失性阻变存储器是一个重要的研究方向。
发明内容
本发明针对上述问题，提出了一种基于多层聚对二甲苯的实现多值存储的有机 阻变存储器及其制备方法。
本发明采用的技术方案如下：
一种多值非易失性有机阻变存储器，包括顶电极、底电极以及位于顶电极和底 电极之间的中间功能层，所述中间功能层为至少两层聚对二甲苯。
优选地，所述顶电极和底电极采用惰性电极，优选采用W电极，厚度为 200nm～500nm。
优选地，上述阻变存储器采用硅衬底。
优选地，所述作为功能层的聚对二甲苯层总厚度为40nm～80nm，分为多层淀积， 两层淀积之间在空气中暴露1天用于表面的氧化，每层厚度控制在10nm～20nm。
优选地，所述聚对二甲苯的聚合物为聚对二甲苯C型、聚对二甲苯N型或聚对 二甲苯D型。
本发明同时提供一种上述多值非易失性有机阻变存储器的制备方法，包括如下 步骤：
1）采用物理气相淀积（PVD）方法在衬底上生长底电极材料，并采用标准光刻 技术使底电极图形化；
2）采用聚合物化学气相淀积（Polymer CVD）方法在底电极上依次生长多层聚 对二甲苯材料；
3）通过光刻和刻蚀定义底层电极的引出通孔；
4）采用物理气相淀积（PVD）方法在聚对二甲苯材料上生长顶电极材料，通过 光刻、剥离定义顶层电极，并将底电极引出。
优选地，所述顶电极和底电极的材料为W，厚度在200nm～500nm，所述衬底为 硅衬底。
优选地，所述作为功能层的聚对二甲苯层总厚度为40nm～80nm，分为多层淀积， 两层淀积之间在空气中暴露1天用于表面的氧化，每层厚度控制在10nm～20nm。
优选地，步骤2）采用Polymer CVD方法生长聚对二甲苯时，淀积速度为 1nm/min～10nm/min。
优选地，所述聚对二甲苯的聚合物为聚对二甲苯C型、聚对二甲苯N型或聚对 二甲苯D型。
优选地，步骤3）所是用户刻蚀为RIE刻蚀。
本发明的有益效果：在不改变器件基本结构的条件下，通过采用两侧均为较惰 性电极以及多层聚对二甲苯的淀积来实现具有自限流效果的多值存储功能。
附图说明
图1本发明的多值非易失性有机阻变存储器的阻变过程电流-电压特性曲线示意 图。
图2-图7是实施例中阻变存储器制备方法的各步骤的器件示意图。
图8为图2-7的图例说明。
具体实施方式
下面结合附图和具体实施例，对本发明进行进一步描述。
本发明提出了一种新的阻变存储器结构来实现具有自限流特性的多值存储。该 阻变存储器可以制备在硅衬底上，器件单元为MIM（Metal-Insulator-Metal）电容结 构，采用上下层状结构，中间功能层采用具有优良阻变特性的聚对二甲苯 （parylene-C），该MIM结构的顶电极和底电极优选采用W。该器件的特征在于，功 能层的聚对二甲苯层分多次进行淀积，通过淀积次数的不同以及每次淀积厚度的不同 来实现器件多值存储的功能。
传统的阻变存储器中，活性电极导致的器件阻变机制主要由电极扩散导致的金 属通道所决定，本发明的器件由于两侧均使用W电极，避免了这种情况，形成了由 功能层聚对二甲苯层中固有缺陷以及不同层聚对二甲苯界面缺陷所决定的电阻变化。 对于电极，本发明优选采用惰性电极W，这里的惰性主要是针对不会发生电极电离 后发生向聚对二甲苯内的扩散。此外，也可以使用Pt电极或者电学活性的TiN（但 不会发生电离扩散）等等。采用惰性电极主要是避免形成金属细丝通道这种导电模式， 因为金属细丝的形成/断裂很难反应完全，形成后reset过程只需要断裂一层就可以， 因而只会显示出一种低阻/高阻状态。利用parylene本身缺陷来导电可以有效地实现 高阻的恢复。
本发明的阻变存储器其阻变过程的电流-电压（I-V）特性曲线如图1所示。图中 给出了一个三层聚对二甲苯（厚度为10/10/20nm）结构的各个阻态的SET，RESET 过程，各条曲线的电压扫描方向如箭头所示，我们可以看到该器件存在三组不同的 SET和RESET过程以及三组互相之间可以切换的状态（state1和state5，state2和state3， state4和state5），SET1和RESET1过程实现了state1和state5之间的转换；SET2和 RESET2过程实现了state2和state3之间的转换；SET3和RESET3过程则实现了state4 和state5之间的转换。三组状态之间的切换通过RESET过程完成，我们可以看到 RESET1的曲线可以分为两个大的突变阶段，分别对应于器件从state1状态RESET 到state3和state5状态，因此可以通过调节RESET1过程中截止电压的大小来控制器 件不同组状态之间的转换。
关于聚对二甲苯层数、各层厚度、与阻变存储器值数的说明：
由于该器件的多值是通过不同层的聚对二甲苯逐一发生SET/RESET操作来实 现的，因而每一层聚对二甲苯的导通/关断应当对应生成一组独立的低阻态和高阻态。 根据该原理可知，如果淀积了N层聚对二甲苯层，则可以实现2N个不同的阻态。但 由于聚对二甲苯的厚度不同，当未发生导通的聚对二甲苯层总厚度相对导通的聚对二 甲苯层总厚度较大时，这些情况下的器件高阻态和低阻态之间的区分就不够明显，正 如图1中所示，state5和state1直接reset得到的最高阻态之间基本很难区分，因而可 以利用的态只有2N-1即5个。由于聚对二甲苯单层的厚度很难制备到10nm以下， 受到这一限制，在聚对二甲苯层数变多之后，器件总厚度变大，可以有效区分的态的 数目应当不足2N个，但基于至多一半厚度的聚对二甲苯层导通后，器件的电阻降低， 逐层导通的聚对二甲苯层电阻开始可以区分，因而至少可以实现N个态。各层聚对 二甲苯的厚度则会影响其导通/关断对应的一组低阻/高阻态之间的比例，单层厚度越 大则对应的低阻/高阻态之间比例越大。本发明一般选择聚对二甲苯的总厚度为40nm 到80nm之间，每层厚度控制在10nm到20nm之间。
下面提供本发明的阻变存储器的制备方法的实施例。
实施例1：
1）在Si衬底上利用PVD方法生长W作为底电极，厚度为500nm，并采用标 准光刻技术使下电极（底电极）图形化，如图2所示；
2）利用Polymer CVD技术生长第一层Parylene-C（聚对二甲苯C型）层，如图 3所示，层厚度为20nm；淀积采用聚对二甲苯Polymer CVD设备，工艺选用设备的 标准参数，淀积速度在1nm/min至10nm/min之间；
3）利用Polymer CVD技术生长第二层Parylene-C层，如图4所示，层厚度为 10nm；淀积采用聚对二甲苯Polymer CVD设备，工艺选用设备的标准参数，淀积速 度在1nm/min至10nm/min之间；
4）利用Polymer CVD技术生长第三层Parylene-C层，如图5所示，层厚度为 10nm；淀积采用聚对二甲苯Polymer CVD设备，工艺选用设备的标准参数，淀积速 度在1nm/min至10nm/min之间；
5）通过光刻，RIE刻蚀定义底层电极引出通孔，如图6所示；
6）采用PVD工艺溅射W，厚度为200nm，通过常规工艺的光刻、剥离定义顶 层电极，同时将底电极引出，如图7所示。
实施例2：
1）在Si衬底上利用PVD方法生长W作为底电极，厚度为500nm，并采用标 准光刻技术使下电极（底电极）图形化；
2）利用Polymer CVD技术生长第一层Parylene-D（聚对二甲苯N型）层，层厚 度为10nm；淀积采用聚对二甲苯Polymer CVD设备，工艺选用设备的标准参数，淀 积速度在1nm/min至10nm/min之间；
3）利用Polymer CVD技术生长第二层Parylene-N层，层厚度为20nm；淀积采 用聚对二甲苯Polymer CVD设备，工艺选用设备的标准参数，淀积速度在1nm/min 至10nm/min之间；
4）利用Polymer CVD技术生长第三层Parylene-N层，层厚度为10nm；淀积采 用聚对二甲苯Polymer CVD设备，工艺选用设备的标准参数，淀积速度在1nm/min 至10nm/min之间；
5）通过光刻，RIE刻蚀定义底层电极引出通孔；
6）采用PVD工艺溅射W，厚度为500nm，通过常规工艺的光刻、剥离定义顶 层电极，同时将底电极引出。
该实施例中多层聚对二甲苯的厚度分别为10/20/10nm，发生SET/RESET过程的 层也依次为10/20/10nm，由于中间层为20nm较厚，中间态的操作电压应该比实施例 1中的更大，也更好的区分了不同层聚对二甲苯的操作电压区间，能够较实施例1中 实现更好的器件性能。
以上实施例仅用以说明本发明的技术方案而非对其进行限制，本领域的普通技 术人员可以对本发明的技术方案进行修改或者等同替换，而不脱离本发明的精神和范 围，本发明的保护范围应以权利要求所述为准。

Claims (10)

  1. 一种多值非易失性有机阻变存储器，其特征在于，包括顶电极、底电极 以及位于顶电极和底电极之间的中间功能层，所述中间功能层为至少两层聚对二 甲苯。
  2. 如权利要求1所述多值非易失性有机阻变存储器，其特征在于：所述顶 电极和底电极为惰性电极。
  3. 如权利要求2所述多值非易失性有机阻变存储器，其特征在于：所述顶 电极和底电极为W电极，厚度为200nm～500nm。
  4. 如权利要求1所述多值非易失性有机阻变存储器，其特征在于：所述作 为功能层的聚对二甲苯的总厚度为40nm～80nm，每层厚度为10nm～20nm。
  5. 如权利要求1所述多值非易失性有机阻变存储器，其特征在于：所述聚 对二甲苯的聚合物为聚对二甲苯C型、聚对二甲苯N型或聚对二甲苯D型。
  6. 一种制备权利要求1所述多值非易失性有机阻变存储器的方法，其步骤 包括：
    1）采用物理气相淀积方法在衬底上生长底电极材料，并采用标准光刻技术 使底电极图形化；
    2）采用聚合物化学气相淀积方法在底电极上依次生长多层聚对二甲苯材料；
    3）通过光刻和刻蚀定义底层电极的引出通孔；
    4）采用物理气相淀积方法在聚对二甲苯材料上生长顶电极材料，通过光刻、 剥离定义顶层电极，并将底电极引出。
  7. 如权利要求6所述的方法，其特征在于：所述顶电极和底电极为惰性电 极，所述聚对二甲苯的聚合物为聚对二甲苯C型、聚对二甲苯N型或聚对二甲 苯D型。
  8. 如权利要求7所述的方法，其特征在于：所述顶电极和底电极为W电极， 厚度为200nm～500nm。
  9. 如权利要求6所述的方法，其特征在于：所述作为功能层的聚对二甲苯 的总厚度为40nm～80nm，每层厚度为10nm～20nm，两层淀积之间在空气中暴露 一定时间用于表面的氧化。
  10. 如权利要求6所述的方法，其特征在于：步骤2）采用聚合物化学气相 淀积方法生长聚对二甲苯时，淀积速度为1nm/min～10nm/min。
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