WO2015103968A1 - 一种电子器件互连体 - Google Patents

一种电子器件互连体 Download PDF

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Publication number
WO2015103968A1
WO2015103968A1 PCT/CN2015/070220 CN2015070220W WO2015103968A1 WO 2015103968 A1 WO2015103968 A1 WO 2015103968A1 CN 2015070220 W CN2015070220 W CN 2015070220W WO 2015103968 A1 WO2015103968 A1 WO 2015103968A1
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conductive plate
unidirectional conductive
pad
pads
electronic device
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PCT/CN2015/070220
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English (en)
French (fr)
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申宇慈
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申宇慈
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors

Definitions

  • This invention relates generally to integrated circuit semiconductor package technology, and more particularly to conductive interconnect technology between integrated circuit semiconductor chips and their packages and circuit substrates or printed wiring boards.
  • flip chip interconnect technology can accommodate very high input/output ports per pin area or pin count, it is widely used in semiconductor device packages where the outer end of the input and output ports arranged on the flip chip surface is usually a A pad, which is interconnected with a corresponding pad on a circuit substrate or a printed circuit board by a metal bump to achieve mutual communication between the flip chip and the circuit substrate or printed circuit board.
  • the flip chip interconnect technology since the chip is interconnected face down by a metal bump and a circuit substrate or a printed circuit board, the chip is called a flip chip, and the pad on the surface thereof is generally called a bump.
  • UBM Under Bump Metal. Solder balls are one of the most widely used metal bumps for connecting flip-chip pads to circuit boards or printed circuit board pads.
  • the height is about 100 to 200 microns.
  • the ratio of height to pad diameter is about Around 1, that is, the interconnect has an aspect ratio of about 1.
  • the reliability of interconnects is one of the most interesting issues in flip chip packaging. In general, the greater the height of the interconnect, the higher the reliability of the interconnect; the greater the aspect ratio of the interconnect, the higher the reliability of the interconnect. In the case where the metal bumps used for the interconnection are solder balls, increasing the height of the interconnection means increasing the diameter of the pads and the pad pitch, which means reducing the number of pins per unit area of the chip.
  • Bump Pitch pad diameter and pitch or bump pitch
  • the solder ball interconnect is made by a reflow process of solder distributed in advance on the pad, while the copper post in the copper stud bump interconnect is first opened and then filled with copper in a layer of carrier material.
  • 100 in Figure 1A illustrates the broadest of the two bump interconnects currently used in products, namely the solder ball bumps and copper stud bump interconnects, and some of the basic components and features.
  • 110 in FIG. 1A illustrates an interconnect formed by solder ball bumps between a flip chip and a substrate, wherein the numeral symbols 11, 12, 13, 14 and 15 respectively represent a chip, an input/output pad (Pad) on the chip, and a chip.
  • a first inert protective layer (Passivation 1, which is usually a silicon nitride layer), a second inert protective layer on the chip (Passivation 2, which is usually a polymer soft layer such as a polyimide layer) and under the bump (UBM: Under Bump Metal)
  • numeral symbols 16 and 17 represent solder ball bumps and underfill materials, respectively
  • numeral symbols 20, 21, 22, and 23 represent circuit substrates, respectively, soldering the upper surface of the circuit substrate.
  • FIG. 1A illustrates an interconnect made of a copper stud bump between the flip chip and the substrate, wherein the numeral symbols 30 and 31
  • the solders on the top of the copper posts and the copper posts, respectively, are shown in other components.
  • the second inert protective layer 14 and the underfill material 17 on the chip are both for protecting the interconnect structure from premature destruction, wherein the protective layer 14 is for slowing the solder ball bump 16 or the copper stud bump 30 and the chip 11.
  • the stress concentration at the corners of the connection is concentrated, while the underfill material 17 is to relieve the stress acting directly on the interconnect structure.
  • the numeral symbols 200, 300, and 400 in FIG. 1B illustrate flip chip package structures based on solder ball bump interconnects, wherein 200 represents a flip chip package without a stiffener, and 300 and 400 are respectively illustrated with a stiffener 41 and The flip chip package of the cover 43, wherein the numeral symbols 42 and 44 respectively represent bonding materials for bonding the reinforcing ring 41 and the cover 43 to the circuit substrate, and 40 and 45 respectively represent the corners formed by the underfill material 17 at the edge of the chip ( Filet) and the thermal interface material (TIM: Thermal Interface Material) between the cover 43 and the chip.
  • the purpose of adhering a reinforcing ring 41 or cover 43 to the circuit substrate is to increase the rigidity of the circuit substrate from excessive warpage.
  • Other interconnect structures such as copper stud bump interconnect flip-chip packages, use similar package structures in the prior art.
  • Figure 1C shows a basic step of fabricating a copper stud bump, comprising: 1) forming a layer of carrier material on the chip and opening a hole in the carrier material layer as shown at 510; 2) as shown at 520, The holes are filled with copper to form a copper pillar; 3) as shown at 530, the carrier material layer is removed and the chip is interconnected with the substrate by solder.
  • the height of the copper pillars thus produced is usually from about 20 microns to about 60 microns, rarely exceeding 100. Micron.
  • No. 8525350B2 and CN101208799A which disclose a method of fabricating a copper pillar interconnect based on a template, as shown at 600 in Figure 1C, which includes the following basic steps: as shown at 610: 1) attaching a template 60 to a carrier first. And opening a hole 61 therein; 2) filling the hole with copper material to form a copper column 62; 3) exposing the copper column end portion 63 by etching; as shown by 620: 4) placing the template containing the copper column 68 and 69 are interconnected with chip 64 and substrate 67 by solders 65 and 66.
  • the height of the copper pillars produced is from about 40 microns to 106 microns and the aspect ratio of the copper posts is from about 0.5 to 5, wherein the substrate 69 of the template can be used as an underfill material.
  • the prior art methods for fabricating flip-chip packages or interconnects have a number of limitations, including: 1) the height of the interconnect bumps made by the process steps of first opening and then refilling is generally below about 100 microns. Moreover, the manufacturing process is very time consuming and expensive, and 2) the method of manufacturing the wire support one by one on the pads by using the wire cutter, and then forming the bumps on the wire support with solder is more time consuming and expensive, and The claimed interconnect bumps are also only 300 microns high. 3) It is very difficult to fabricate Fine Bump Pitch and have a certain height of interconnect, such as less than 50 micron bump pitch and a height of 100 microns or more. The interconnection, 4) The gradual improvement of these interconnection technologies failed to fundamentally solve the stress caused by the mismatch of thermal expansion coefficient between the chip and the substrate and the interconnection failure or cracking problem caused by the interconnection.
  • these components in the flip chip package shown in FIGS. 1A and 1B that is, the second inert protective layer 14, the underfill material 17, the reinforcing ring 41 and the cover 43 on the chip are both for improving the package or
  • the structural reliability of the interconnect is prevented from prematurely cracking or failing, regardless of the functional improvement of the semiconductor chip; in other words, if there is no structural reliability problem of the package or interconnect, it is not necessary to use these components. It takes up most of the time and expense of manufacturing flip chip packages.
  • the invention adopts the unidirectional conductive plate described in the Chinese invention patent application CN201310737666.0 filed on December 27, 2013, to manufacture a semiconductor chip or an interconnection of a semiconductor chip package and a circuit substrate or a printed circuit board. All of the limitations of the prior art described above are overcome and have many new advantages and features.
  • the interconnects of the present invention can easily have interconnect heights in excess of 1000 microns, interconnect aspect ratios greater than 10, and pad pitches less than 50 microns, and are inexpensive to manufacture and efficient.
  • the electronic device interconnect of the present invention comprises: an electronic device comprising a conductive contact or pad in communication with the outside; a unidirectional conductive plate comprising a base material and a wire for interconnection; wherein the unidirectional conduction
  • the plate comprises a wire characterized in that it is unidirectionally arranged in the thickness direction of the plate, penetrates the base material, and is exposed on one or both surfaces of the plate or is exposed in the middle portion of the plate; It forms a conductive path along the thickness of the plate; it has an outer layer of insulating protection; each wire consists of a wire or a bundle of wires or wires formed of a plurality of wires; it has a thickness of from about 100 microns to about 200 mm
  • the length preferably, has a length of from about 200 microns to about 20 mm; it has an aspect ratio of from about 2 to 2000, preferably, an aspect ratio of from 5 to 200.
  • the electronic device interconnect of the present invention wherein the wires in the unidirectional conductive plate form a tight arrangement having a wire edge to a wire edge of less than about 10 microns, preferably less than about 5 microns.
  • the electronic device interconnect of the present invention wherein the wires in the unidirectional conductive plate form a regular arrangement at a set pitch, having from about 10 microns to about 500 microns, preferably from about 20 The micron to about 150 microns spacing from the edge of the wire to the edge of the wire and having a diameter of from about 10 microns to about 150 microns, preferably from about 20 microns to about 80 microns.
  • the electronic device interconnect of the present invention wherein the wires in the unidirectional conductive plate form a tight arrangement or form a regular arrangement at a set pitch, characterized in that it comprises an electronic device and a a unidirectional conductive plate, wherein the electronic device is a semiconductor chip, a circuit substrate or a printed circuit board having one surface having aligned pins or pads; and one surface of the unidirectional conductive plate has a set solder The disk or set circuit and pad, while the other surface has exposed wires; the pads on one surface of the unidirectional conductive plate are interconnected with the pins or pads of the electronic device by solder.
  • the electronic device interconnect of the present invention wherein the wires in the unidirectional conductive plate form a tight Arranging or forming a regular arrangement at a set pitch, characterized in that it comprises an electronic device and a unidirectional conductive plate, wherein the electronic device is a semiconductor chip, a circuit substrate or a printed circuit board, One surface has aligned pins or pads; one surface of the unidirectional conductive plate has exposed wires, and the other surface has set pads or set circuits and pads, or the unidirectional conductive Both surfaces of the board have exposed wires; wherein the bare wires on one surface of the unidirectional conductive plate are interconnected correspondingly to the pins or pads of the electronic device.
  • the electronic device interconnect of the present invention wherein the wires in the unidirectional conductive plate form a tight arrangement or form a regular arrangement at a set pitch, characterized in that it comprises an electronic device and a a unidirectional conductive plate, wherein the electronic device is a semiconductor chip, a circuit substrate or a printed circuit board having one surface having aligned pins or pads; both surfaces of the unidirectional conductive plate have a set a pad or a set circuit and a pad, and the middle portion has a bare wire; wherein a pad on one surface of the unidirectional conductive plate and a pin or a pad of the electronic device correspond to each other by solder even.
  • the electronic device interconnect of the present invention wherein the wires in the unidirectional conductive plate form a tight arrangement or form a regular arrangement at a set pitch, characterized in that it comprises two electronic devices and a a unidirectional conductive plate, wherein one electronic device is a circuit substrate having a pad on the surface, and the other electronic device is a semiconductor chip or a semiconductor chip package having a pad on the surface; one surface of the unidirectional conductive plate has a set solder a disk or a set circuit and a pad, the other surface having a bare wire; wherein the pads on one surface of the unidirectional conductive plate are interconnected by solder corresponding to the pads of the circuit substrate, and The bare wires on the other surface of the unidirectional conductive plate are interconnected corresponding to the pads of the chip or chip package.
  • the electronic device interconnect of the present invention wherein the wires in the unidirectional conductive plate form a tight arrangement or form a regular arrangement at a set pitch, characterized in that it comprises two electronic devices and a a unidirectional conductive plate, wherein one electronic device is a circuit substrate having a pad on the surface, and the other electronic device is a semiconductor chip or a semiconductor chip package having a pad on the surface; one surface of the unidirectional conductive plate has a bare wire, The other surface has a set pad or set circuit and pad; wherein the bare wire on one surface of the unidirectional conductive plate is interconnected by solder correspondingly to the pad of the circuit substrate, and The pads on the other surface of the unidirectional conductive plate are interconnected by solder corresponding to the pads of the chip or chip package.
  • the electronic device interconnect of the present invention wherein the wires in the unidirectional conductive plate form a tight arrangement or form a regular arrangement at a set pitch, characterized in that it comprises two electronic devices and a a unidirectional conductive plate, wherein one electronic device is a circuit substrate having a pad on the surface, and the other electronic device is a semiconductor chip or a semiconductor chip package having a pad on the surface; both surfaces of the unidirectional conductive plate have a bare surface a wire; wherein a bare wire on one surface of the one-way conductive plate is interconnected by a solder corresponding to a pad of the circuit substrate, and a bare wire on the other surface of the one-way conductive plate passes The solder is interconnected corresponding to the pads of the chip or chip package.
  • the electronic device interconnect of the present invention wherein the wires in the unidirectional conductive plate form a tight arrangement or form a regular arrangement at a set pitch, characterized in that it comprises two electronic devices and a a unidirectional conductive plate, wherein one electronic device is a circuit substrate having a pad on the surface, and the other electronic device is a semiconductor chip or a semiconductor chip package having a pad on the surface; both surfaces of the unidirectional conductive plate have settings Pad or set circuit and pad, while the middle portion has bare wires; wherein pads on one surface of the unidirectional conductive plate are interconnected correspondingly to pads of the circuit substrate by solder And the pads on the other surface of the unidirectional conductive plate are interconnected by solder corresponding to the pads of the chip or chip package.
  • the electronic device interconnect of the present invention wherein the wires in the unidirectional conductive plate form a tight arrangement or form a regular arrangement at a set pitch, characterized in that it comprises more than two electronic devices and a unidirectional conductive plate, wherein one of the electronic devices is a circuit substrate having a pad on the surface, and the other electronic device is a semiconductor chip or a semiconductor chip package having a pad on the surface; one surface of the unidirectional conductive plate has the same height Exposed wires or set pads or set circuits and pads, the other surface of the unidirectional conductive plate having exposed wires of different heights forming a stepped groove; wherein, in the single guide The bare conductors or set pads of the same height on one surface of the electric board are interconnected correspondingly to the pads of the circuit substrate by solder, and have stepped recesses on the other surface of the unidirectional conductive plate The exposed wires of the slots are interconnected correspondingly to the pads of the plurality of chip or chip packages, wherein each step or rece
  • the electronic device interconnect of the present invention wherein the wires in the unidirectional conductive plate form a tight arrangement or form a regular arrangement at a set pitch, characterized in that it comprises more than two electronic devices and a unidirectional conductive plate, wherein one of the electronic devices is a circuit substrate having a pad on the surface, and the other electronic device is a semiconductor chip or a semiconductor chip package having a pad on the surface; the unidirectional conductive plate a surface having the same height of exposed wires or set pads or set circuits and pads, the other surface of the unidirectional conductive plate having exposed wires of different heights forming a stepped groove; The same height of exposed wires or set pads or set circuits and pads on one surface of the unidirectional conductive plate are soldered to one of the plurality of chips or chip packages by solder The discs are correspondingly interconnected, and the stepped bare conductors on the other surface of the unidirectional conductive plate and the pads of the other chip or chip package in the plurality of chip or chip packages and
  • the electronic device interconnect of the present invention wherein the wires in the unidirectional conductive plate form a tight arrangement or form a regular arrangement at a set pitch, characterized in that it comprises more than two electronic devices and a unidirectional conductive plate, wherein one electronic device is a circuit substrate having a pad on the surface, and other electronic devices are semiconductor chips or semiconductor chip packages having pads on the surface; one surface of the unidirectional conductive plate has the same height of bareness a wire, and the other surface of the unidirectional conductive plate has a set pad or a set circuit and a pad; wherein the bare wire on one surface of the unidirectional conductive plate is soldered to the circuit substrate
  • the pads are correspondingly interconnected, the pads on the other surface of the unidirectional conductive plate being interconnected correspondingly to the pads of the plurality of chip or chip packages by solder; the plurality of chips or chips being packaged in the An in-plane interconnect is formed over the unidirectional conductive plates.
  • the electronic device interconnect of the present invention is characterized in that the bare conductor in the unidirectional conductive plate has a solder material head at its end, thereby eliminating the need to use additional solder in the interconnect solder.
  • the electronic device interconnect of the present invention is characterized in that the base material in the unidirectional conductive plate is a highly thermally conductive material having a heat transfer coefficient greater than about 10 W/mK, which is used in the unidirectional conductive plate
  • the interconnected bare conductors have a set length, such as greater than about 2 millimeters, preferably greater than about 10 millimeters, such that the bare conductors for conductive interconnections have a heat dissipation effect; further characterized by the unidirectional conductive plates Larger than other electronic devices, with the exception of wires for conductive interconnections, other excess substrates and wires are used to further enhance heat dissipation through the unidirectional conductive plates.
  • a key idea in the present invention is to fabricate interconnects of electronic devices by a unidirectional conductive plate comprising bare elongated wires, which is completely different from the prior art ideas and methods.
  • Advantages and features of the present invention include: 1) the interconnect of the present invention employs an elongated wire having an aspect ratio of more than 5, 10 or 100, thereby having Excellent flexibility to eliminate interconnect failure caused by thermal stress, thus eliminating the need for the second inert protective layer and underfill material on the upper layer of the chip used to improve the reliability of the interconnect structure used in the prior art.
  • 1A is a schematic view showing an interconnection structure between a flip chip pad and a substrate pad widely used in the prior art, including a solder ball bump interconnection and a copper pillar bump interconnection structure;
  • 1B is a schematic diagram of a flip chip package structure including a solder ball bump interconnect and a copper pillar bump interconnect in the prior art
  • 1C is a schematic view of an interconnection structure between a flip chip pad and a substrate pad disclosed in the prior art and a basic manufacturing step thereof;
  • FIG. 2 is a schematic view of a unidirectional conductive plate and a basic manufacturing step thereof adopted by the present invention
  • FIG. 2A is a partial enlarged view of the unidirectional conductive plate shown in FIG. 2, showing that the unidirectional conductive plate comprises wires arranged in a tight arrangement, and may include various forms of exposed wires and pads on the surface thereof:
  • 2B is a partially enlarged schematic view of the unidirectional conductive plate shown in FIG. 2, showing that the unidirectional conductive plate includes wires formed into an arrangement having a set pitch, and may include various forms of bare wires on the surface thereof and Pad
  • 3A is a schematic diagram of an interconnect formed by a unidirectional conductive plate and a circuit substrate or a printed circuit board in an embodiment of the present invention, wherein the unidirectional conductive plate comprises closely arranged wires;
  • 3B is a schematic diagram of an interconnect formed by a unidirectional conductive plate and a circuit substrate or a printed circuit board in an embodiment of the present invention, wherein the unidirectional conductive plate includes wires arranged at a set pitch;
  • FIG. 4A is a schematic diagram of an interconnect formed by a flip chip through a unidirectional conductive plate and a circuit substrate or a printed circuit board in an embodiment of the present invention, wherein the unidirectional conductive plate comprises closely arranged wires;
  • 4B is a schematic diagram of an interconnect formed by a flip chip through a unidirectional conductive plate and a circuit substrate or a printed circuit board in an embodiment of the present invention, wherein the unidirectional conductive plate includes wires arranged at a set pitch;
  • 4C is a schematic diagram of an interconnect of a flip chip formed by a unidirectional conductive plate and a circuit substrate or a printed circuit board in an embodiment of the present invention, wherein the unidirectional conductive plate has a larger size;
  • FIG. 5 is a schematic diagram of an interconnect formed by a plurality of flip chips through a unidirectional conductive plate and a circuit substrate or a printed circuit board in an embodiment of the present invention, wherein the plurality of chips form a stacked structure on the wire steps;
  • FIG. 6 is a schematic diagram of an interconnect formed by a plurality of flip chips through a unidirectional conductive plate and a circuit substrate or a printed circuit board in an embodiment of the present invention, wherein the stacked structure of the plurality of chips is a chip located at Above the unidirectional conductive plate, and other chips are located in the wire steps below the unidirectional conductive plate;
  • FIG. 7 is a schematic diagram of an interconnect formed by a plurality of flip chips through a unidirectional conductive plate and a circuit substrate or a printed circuit board in an embodiment of the present invention, wherein the plurality of chips are on the unidirectional conductive plate Forming an in-plane interconnection above;
  • FIG. 8 is a schematic diagram of an interconnect of a flip chip and a chip package formed by a unidirectional conductive plate and a circuit substrate or a printed circuit board in an embodiment of the present invention, wherein the flip chip and the chip are packaged on the wire Forming a stacked structure on the steps;
  • Figure 9 is a schematic view of an embodiment of the present invention, including: each of the unidirectional conductive plates is composed of a wire or a wire bundle or a wire formed of a plurality of wires, and the ends of the wires are provided with solder Head, the basic manufacturing steps of the interconnect.
  • a unidirectional conductive plate which represents a sheet which is electrically conductive in the thickness direction of the board and insulated in the in-plane direction of the board.
  • the material in which the conductivity in the thickness direction of the plate does not mean that any position of the plate is electrically conductive in the thickness direction of the plate, but means that any position of the plate is electrically conductive in the thickness direction of the plate on a relatively large scale, or means Conductive in the thickness direction of the board at a position arranged at a set pitch; and in the case where the base bonding material is a conductive material, such as a low melting point metal material, unidirectional conduction represents a wire in the in-plane direction of the board Insulating each other, each wire is a conductive path along the thickness of the plate; 2) a base material, a material in a unidirectional conductive plate that connects and solidifies the unidirectionally aligned wires; 3) a pin or a pad, A small piece of solderable metal at the input and output port of the electronic device, the shape of which is not limited to a circular shape; 4) a circuit and a pad, wherein the circuit may be a multi-layer circuit, and the
  • FIG. 2 is a schematic diagram 1000 of a unidirectional conductive plate and its basic fabrication steps for use in the present invention for fabricating a unidirectional conductive plate by a wire assembly comprising closely spaced wires with outer layers.
  • the numeral symbol 100 in Fig. 2 represents a wire integrated body including closely arranged wires with outer layers
  • 101 and 102 represent a plan view and a side view of a unidirectional conductive plate which is formed by dividing a wire integrated body, wherein 101 103, 104, 105, small black dots and arrows represent enlarged views of the wires with outer layers contained in the wire integrated body 100 or the unidirectional conductive plate 101 and their close arrangement, 109 in 102 represents a further Magnified local area.
  • the wire illustrated in 103 has a very thin insulating outer layer and an equilateral triangle closely aligned.
  • the wires 106 and 105 have a thickness of outer layer 106 and a square closely aligned, wherein the wire core of the wire illustrated in 105 is a
  • a wire core composed of a plurality of wires has better flexibility than a wire core of a single wire.
  • the method of manufacturing the unidirectional conductive plate comprises the following basic steps: 1) providing a wire with an outer layer; 2) bringing together the wires with the outer layer to form a tight arrangement and solidifying into a whole, thereby making A wire assembly comprising a unidirectional closely aligned wire; 3) dividing the wire assembly into pieces to form a plurality of unidirectional conductive plates that conduct electricity in a thickness direction as needed.
  • the wire core in the unidirectional conductive plate produced by the above steps is not exposed but embedded in the conductive plate, that is, the unidirectional conductive plate is a unidirectional conductive plate having an embedded wire core.
  • the above method of manufacturing a unidirectional conductive plate may further include the step of removing a part or all of a desired surface of the unidirectional conductive plate a base material other than the wire core, thereby being formed on the surface Part or all of the area has a unidirectional conductive plate with a bare wire core.
  • a unidirectional conductive plate with a bare wire core can create a flexible interconnection between the electronic devices, thereby increasing the reliability of the interconnection between the electronic devices.
  • the unidirectional conductive plate can be further divided into a number of small cells, each of which can be used in an integrated circuit semiconductor package or other application.
  • FIG. 2A is an enlarged schematic view of a portion 109 of the unidirectional conductive plate 102 of FIG. 2, which is fabricated based on the closely spaced wires shown at 103 in FIG.
  • the unidirectional conductive plate illustrated by numeral numeral 1110 in FIG. 2A includes an embedded wire 111 and a base material 112; by further processing the surface of the unidirectional conductive plate 1110, the numeral symbols 1120, 1130 in FIG. 2A can be formed.
  • 1140 and 1150 illustrate a unidirectional conductive plate, wherein one surface of the unidirectional conductive plate illustrated by 1120 has a bare wire 113, the other surface has a set pad 120, and the exposed wire of the unidirectional conductive plate indicated by 1130 has a step
  • the two sides of the unidirectional conductive plate indicated by the grooves 130, 1140 have exposed wires 141 and 142, and the two surfaces of the unidirectional conductive plate indicated by 1150 have exposed wires 151 and 152, but one side of the unidirectional conductive plate
  • the bare wire 151 has a stepped recess 150 to accommodate the stacked chips.
  • the bare conductor has a thin insulating outer layer to avoid short circuits caused by mutual contact in an application; in addition, a pad on one surface of the unidirectional conductive plate, as shown at 120 in 1120 , can have the size and spacing set as needed to match a practical application.
  • FIG. 2B is an enlarged schematic view of a portion 109 of the unidirectional conductive plate 102 shown in FIG. 2, which is formed based on a square arrangement of wires of an outer layer 106 having a certain thickness shown in FIG. 2, wherein the wire core is formed. It is a wire rope formed by a plurality of wires, and the thickness of the outer layer 106 sets the spacing between the wires.
  • the unidirectional conductive plate illustrated by numeral numeral 1210 in FIG. 2B includes an embedded wire 211 and a base material 212, wherein the base material 212 is composed of the outer layer 106 of the wire and the bonding material 107 shown by 105 in FIG.
  • FIG. 2 Further processing of the surface of the unidirectional conductive plate 1210 can result in a unidirectional conductive plate as illustrated by numeral symbols 1220, 1230, 1240 and 1250 in FIG. 2B; wherein one surface of the unidirectional conductive plate illustrated by 1220 has a bare surface The other surface has a pad 210 disposed on the surface of the base material layer 222, and the bare wire of the unidirectional conductive plate illustrated by 1230 has two stepped grooves 230 for accommodating stacked chips, 1240 of two unidirectional conductive plates Wires 241 and 243 are exposed on the surface. It is to be noted that the pads 210 on the surfaces of the unidirectional conductive plates 1220 and 1230 shown in FIG.
  • the disk 120 is arbitrarily set as needed, and can only be set according to the corresponding position of the wire, which has certain limitations in the application. To do this, eliminate this limitation by first setting up a circuit layer and then laying the pads, as shown in Figure 2B.
  • the symbol 1250 illustrates a unidirectional conductive plate in which the circuit layer 251 is used to integrate the connection of the wires 213 with the pads 250 so that the number, size and spacing of the pads 250 can be arbitrarily set as needed.
  • 2B has pads or circuits and pads on both surfaces, and includes a bare wire in the middle portion, which can pass through both surfaces of the unidirectional conductive plate shown at 1210.
  • 3A is a schematic illustration of an interconnect formed by a unidirectional conductive plate and a circuit substrate or printed circuit board in accordance with one embodiment of the present invention, wherein the unidirectional conductive plate includes closely spaced wires.
  • 3A are illustrative examples of an interconnect formed by a unidirectional conductive plate and a circuit substrate or printed circuit board; wherein 2120 indicates that one side has pads and the other side has the same height
  • the unidirectional conductive plate 320 of the bare wire is connected to a circuit substrate or printed circuit board 321 through the connection of the pad 323, the solder 322 and the pad 324; 2130 represents a bare wire having the same height on one side, and the other side
  • An unidirectional conductive plate 330 having a stepped bare conductor and a circuit substrate or printed circuit board 331 are formed by interconnecting bare wires, solder 332 and pads; 2140 means that one side has pads and the other side has the same height
  • the unidirectional conductive plate 340 of the bare conductor is connected to a circuit substrate or printed circuit board 341 by an exposed conductor, a solder 342 and a pad.
  • FIG. 3B is a schematic illustration of an interconnect of a unidirectional conductive plate and a circuit substrate or printed circuit board in accordance with one embodiment of the present invention, wherein the unidirectional conductive plate includes wires arranged at a set pitch.
  • the numeral symbols 2210, 2220 and 2230 in Fig. 3B are schematic examples of an interconnect formed by a unidirectional conductive plate and a circuit substrate or printed circuit board; wherein 2210 indicates that one side has pads and the other side has the same height
  • the unidirectional conductive plate 420 of the bare wire is connected to a circuit substrate or printed circuit board 421 through the connection of the pad 423, the solder 422 and the pad 424; the 2220 indicates that one side has the pad and the other side has the same height.
  • the unidirectional conductive plate 430 of the bare wire is connected to a circuit substrate or printed circuit board 431 through an exposed wire, and the solder 432 and the pad are connected; 2230 indicates that one side has a pad and the other side has a stepped bare wire.
  • the unidirectional conductive plate 450 is interconnected with a circuit substrate or printed circuit board 451 through pads, solder and pads.
  • the interconnect shown in FIGS. 3A and 3B is a circuit substrate or a printed circuit board including exposed wires.
  • a chip or a chip package may be mounted over the exposed wires, and pads on the lower surface thereof, such as 2210. As shown in 425, it can be connected to other electronic devices.
  • the circuit substrate or the printed circuit board may also be a semiconductor chip, so that the interconnect shown in FIG. 3A and FIG. 3B becomes an inclusion.
  • a semiconductor chip with a bare wire; in an application, the semiconductor chip including the bare wire may be mounted on a circuit substrate or a printed circuit board through a bare wire.
  • FIG. 4A is a schematic illustration of an interconnect of a flip chip formed by a unidirectional conductive plate and a circuit substrate or printed circuit board in accordance with one embodiment of the present invention, wherein the unidirectional conductive plate includes closely spaced wires.
  • 4A are schematic examples of an interconnect formed by a flip chip 510 through a unidirectional conductive plate 500 or 509 and a circuit substrate or printed circuit board 502; wherein 3110 is shown
  • the exposed wires of the unidirectional conductive plates are connected to the flip chip by solder 504, and the pads of the unidirectional conductive plates are connected to the pads of the circuit substrate or the printed circuit board through the solder 503; and the connection manner shown by 3120 is a unidirectional conductive plate.
  • the pads are connected to the flip chip by solder 506, and the bare wires of the unidirectional conductive plate are connected to the pads of the circuit substrate or printed circuit board through solder 505.
  • the unidirectional conductive plate adopts closely arranged thin wires, and the size and spacing thereof are much smaller than the pads to which they are connected, and a plurality of interconnected pads include a plurality of wires;
  • the pads in the flip chip are not necessarily required to have the same size and pitch.
  • FIG. 4B is a schematic illustration of an interconnect of a flip chip through a unidirectional conductive plate and a circuit substrate or printed circuit board in accordance with one embodiment of the present invention, wherein the unidirectional conductive plate includes wires arranged at a set pitch.
  • 4B are schematic examples of an interconnect formed by a flip chip 511 through a unidirectional conductive plate 500, 520 or 530 and a circuit substrate or printed circuit board 512; Shown is that the exposed wires 515 of the unidirectional conductive plate are connected to the pads of the flip chip by the solder 514, and the pads of the unidirectional conductive plate are connected to the pads of the circuit substrate or the printed circuit board by the solder 513;
  • the connection method is that the pad of the unidirectional conductive plate is connected to the pad of the flip chip, and the exposed wire of the unidirectional conductive plate is connected to the pad of the circuit substrate or the printed circuit board, and the two surfaces of the unidirectional conductive plate in the 3230 Both are bare conductors, as shown in 537 and 538, the base material 536 is used to hold the wires, and the solders 533 and 534 connect the ends of the bare wires 537 and 538 to the pads of the circuit substrate or printed circuit board, respectively.
  • the unidirectional conductive plate adopts wires arranged at a set interval, and the size and spacing thereof are equivalent to the pads to which they are connected, and a pair of pads are interconnected by one wire; therefore, the flip chip
  • the pads in the middle cannot have random sizes and spacing.
  • a flip chip having an irregular arrangement and size of pads in order to use a unidirectional conductive plate including wires arranged at a set pitch, it is necessary to first provide a circuit layer on one surface of the unidirectional conductive plate, and then lay a solder.
  • the disk is integrated with the pad of the flip chip, such as the one-way conductive plate shown at 1250 in Figure 2B.
  • 4C is a schematic diagram of an interconnect of a flip chip through a unidirectional conductive plate and a circuit substrate or a printed circuit board in an embodiment of the present invention, wherein the unidirectional conductive plate has a larger size;
  • the unidirectional conductive plate has a larger size;
  • other excess substrates and wires are used to further enhance heat dissipation through the unidirectional conductive plates.
  • 4C are schematic examples of an interconnect formed by a flip chip 511 through a unidirectional conductive plate 540 or 550 and a circuit substrate or printed circuit board 512;
  • One surface of the conductive plate has a bare wire 545, and the other surface has a pad on the base material 546, and the bare wire 545 is connected to the pad of the circuit substrate or the printed circuit board 512 by solder, and the pad is inverted
  • the pads of the chip are connected by solder; wherein both surfaces of the unidirectional conductive plate shown at 3250 have exposed wires 557 and 558 which are soldered to the pad and flip chip of the circuit substrate or printed circuit board 512, respectively.
  • the pads of 511 are connected.
  • the unidirectional conductive plates 540 and 550 shown in FIG. 4C have a larger size, with the portion shown at 554 to further enhance heat dissipation through the unidirectional conductive plates.
  • the preferred base materials 546 and 556 should be a material having a high thermal conductivity, such as a material having a thermal conductivity greater than 40 W/mK.
  • Figure 5 is a schematic illustration of an interconnect of a plurality of flip chips formed by a unidirectional conductive plate and a circuit substrate or printed circuit board in accordance with one embodiment of the present invention, wherein the plurality of chips form a stacked structure on the wire steps.
  • Numerous symbols 4130 and 4220 in FIG. 5 are illustrative examples of interconnects in which a plurality of flip chips are formed by a unidirectional conductive plate 610 or 640 and a circuit substrate or printed circuit board 630 or 660.
  • a unidirectional conductive plate 610 comprising closely spaced wires, wherein a plurality of flip chips 621, 622, 623 are located in the exposed wire grooves of the unidirectional conductive plate 610, a single guide Both surfaces of the electric board 610 have bare wires 627 and 628 and are respectively connected to the pads of the circuit substrate or the printed circuit board 630 and the pads of the plurality of flip chips 621, 622, 623 by solder; the unidirectional conductive plate The base material 626 of 610 is used to hold the bare wires together; the interconnect shown in 4220 of FIG.
  • the base material 646 in the unidirectional conductive plate 640 is used to hold the bare wires together.
  • FIG. 6 is a schematic diagram of an interconnect of a plurality of flip-chips through a unidirectional conductive plate and a circuit substrate or a printed circuit board in an embodiment of the present invention, wherein a stacked structure of the plurality of chips is a chip located at the The unidirectional conductive plate is above, and the other chips are located in the wire steps below the unidirectional conductive plate.
  • Numerals 4430 and 4520 in FIG. 6 are interconnects formed by a plurality of flip chip 721, 722, 723 and a circuit substrate or printed circuit board 730 through a unidirectional conductive plate 710 or 740 including circuit layers and pads. An illustrative example. The interconnect shown in 4430 of FIG.
  • a unidirectional conductive plate 710 comprising closely spaced wires, wherein one of the plurality of flip chips is located above the unidirectional conductive plate 710 and passes through the solder and the unidirectional conductive plate.
  • the circuit layer 711 on the upper surface of 710 is connected to the pads, and the other flip chip 722 and 723 are located in the exposed wire grooves below the unidirectional conductive plate 710 and are connected to the ends of the bare wires 715 by solder.
  • a unidirectional conductive plate 740 comprising wires arranged at a set pitch, wherein one of the plurality of flip chips is located above the unidirectional conductive plate 740 and is soldered and The circuit layer 741 on the upper surface of the unidirectional conductive plate 740 is connected to the pads, and the other flip chip 722 and 723 are located in the exposed wire grooves below the unidirectional conductive plate 740 and are connected to the ends of the bare wires 745 by solder.
  • the difference of the stacked structures of the plurality of flip chips in FIG. 5 and FIG. 6 is that the plurality of flip chips in FIG. 5 communicate through the circuit substrate or the printed circuit board, and the plurality of FIG. 6
  • the flip chip has direct communication with each other through the circuit layers on the surface of the unidirectional conductive plate before communicating with the circuit substrate or the printed circuit board.
  • the base materials 716 and 746 of the unidirectional conductive plate of FIG. 6 preferably have a thermal expansion coefficient close to that of the flip chip to avoid solder between the circuit layers 711 and 714 and the chip 721 on the surface of the unidirectional conductive plate.
  • the layer which may be selected from glass, ceramic, silicon or other materials; in addition, the solder layer between the circuit layers 711 and 714 and the chip 721 on the surface of the unidirectional conductive plate may be filled with a protective material to enhance the The strength of the solder layer.
  • FIG. 7 is a schematic diagram of an interconnection of a plurality of flip chips through a unidirectional conductive plate and a circuit substrate or a printed circuit board in an embodiment of the present invention, wherein the plurality of chips are above the unidirectional conductive plate Form an in-plane interconnect.
  • Numerals 5110 and 5210 in FIG. 6 are formed by a plurality of flip chip 821, 822, 823 formed by a unidirectional conductive plate 810 or 840 including a circuit layer 811 or 841 and pads, and a circuit substrate or printed circuit board 830.
  • An illustrative example of an interconnect The interconnect shown in 5110 of FIG.
  • the interconnect shown in 5210 of FIG. 7 employs a unidirectional conductive plate 840 comprising wires arranged at a set pitch, wherein a plurality of flip chips are positioned over the unidirectional conductive plate 840 and pass the solder and the unidirectional conductive plate 840.
  • the circuit layer 841 on the upper surface is connected to the pad, and the bare wire 845 of the unidirectional conductive plate 840 is connected.
  • the solder 843 is connected to a pad on the circuit substrate or printed circuit board 840.
  • the base materials 816 and 846 of the unidirectional conductive plate of FIG. 7 preferably have a thermal expansion coefficient close to that of the flip chip to avoid cracking of the solder layer between the circuit layers 811 and 814 of the unidirectional conductive plate surface and the chip 721, which may Selected from glass, ceramic, silicon or other materials; in addition, the solder layer between the circuit layers 811 and 814 on the surface of the unidirectional conductive plate and the chips 821, 822, 823 may be filled with a protective material to strengthen the solder layer. Strength of.
  • FIG. 8 is an example 6000 of a schematic diagram of a chip package 861 and a flip chip 862 formed by a unidirectional conductive plate 850 and a circuit substrate or printed circuit board 870 in an embodiment of the present invention, wherein The flip chip 862 and the chip package 861 form a stacked structure on the stepped wire 855; wherein the upper surface of the unidirectional conductive plate 850 is a closely arranged bare wire having a groove and the lower surface thereof has a pad, The pads of the flip chip 862 and the chip package 861 are connected to the bare wires by solder, and the pads of the lower surface of the unidirectional conductive plate 850 are connected to the pads of the circuit substrate or the printed circuit board 870.
  • the base material 856 in the unidirectional conductive plate 850 may have different thicknesses in the middle portion and the edge; since the base material 856 is located on the side of the circuit substrate or the printed circuit board 870, the material properties thereof should preferably have the same circuit substrate. Or the thermal expansion coefficient of the printed circuit board is close to each other; the unidirectional conductive plate 850 adopts closely arranged wires, and it can also adopt wires arranged at a set interval.
  • FIG. 9 is an illustration 7000 of an embodiment of the present invention, which depicts the basic fabrication steps of an electronic device interconnect, and illustrates that each of the wires in the unidirectional conductive plate may be composed of one wire or a plurality of wires. The formed bundle of wires or wires and the ends of the wires may be provided with solder tips.
  • numeral 901 represents a chip layer
  • 902 represents a solder layer
  • 903 represents a pad layer in a unidirectional conductive plate
  • 904 represents another solder layer
  • 905 represents a pad layer on the upper surface of the circuit substrate
  • 906 represents a circuit substrate.
  • solder layer 902 is used to connect the chip layer 901 to the pad layer 903 above the unidirectional conductive plate, which may be disposed on the pad of the chip layer 901 or above the unidirectional conductive plate On the pad layer 903, it may be solder paste or an interconnect bump pre-formed on the pad; the solder layer 904 is used to expose the bare conductor under the unidirectional conductive plate to the pad layer on the upper surface of the circuit substrate.
  • each of the unidirectional conductive plates may be composed of one wire or a wire bundle or wire formed of a plurality of wires, and the ends of the wires may have solder heads 912 for interconnection. This eliminates the need to place solder paste or solder bumps on the interconnect pads.
  • the bare wire in the above description has a thin insulating protective outer layer, which can avoid the short circuit caused by the contact of the wires when the aspect ratio of the wire is large, in addition to resisting environmental corrosion and oxidation.
  • the protective outer layer is not drawn in the drawings.
  • the base material other than the wire may not necessarily be an insulating material, or may be a conductive substrate such as a low melting point metal, in which case each wire is a separate conductive path.
  • one of the essential elements of the present invention is that the elongated wires are interconnected by electronic devices through the unidirectional conductive plates, and the electronic devices fabricated by using a unidirectional conductive plate as shown in the above figures.
  • the present invention is merely illustrative, and all possible combinations are not shown in the drawings and embodiments, so the description of the present invention has been described by way of example only and not by way of limitation. Those skilled in the art will be able to make modifications based on this and obtain equivalent embodiments.

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Abstract

一种基于一个单向导电板的电子器件互连体，其特征在于，单向导电板（1110）的表面包含用来连接电子器件的裸露导线（113），其具有设定的排列和间距，其可以具有不同的高度从而形成台阶形凹槽（150），其长度可从100微米到200毫米，其纵横比可从2到2000，每根裸露导线可由一根导线构成或由多根导线形成的导线束或导线绳构成。

Description

一种电子器件互连体
相关申请的交叉引用
本申请要求享有于2014年1月7日提交的名称为“一种电子器件互连体”的中国专利申请CN201410006462.4的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明一般地涉及集成电路半导体封装技术，特别地涉及集成电路半导体芯片及其封装与电路基板或印刷线路板间的导电互连技术。
背景技术
由于倒装芯片互连技术能够容纳非常高的单位面积输入输出端口或引脚数，其被广泛用于半导体器件的封装，其中排列在倒装芯片表面上的输入输出端口的外端通常是一个焊盘，其通过金属凸块(Metal Bump)与电路基板或印刷电路板上相应的焊盘互连，从而达到所述倒装芯片与所述电路基板或印刷电路板之间的相互通讯。在所述倒装芯片互连技术中，由于芯片面朝下通过金属凸块与电路基板或印刷电路板互连，所述芯片被称作倒装芯片，其表面上的焊盘通常称作凸块下方的金属(UBM：Under Bump Metal)。焊料球是一种目前使用最广泛的连接倒装芯片焊盘与电路基板或印刷电路板焊盘的金属凸块，其高度大约在100到200微米微米左右，其高度与焊盘直径的比值大约在1左右，即所述互连的纵横比大约为1左右。互连的可靠性是倒装芯片封装中最被关注的问题之一。一般来说，互连的高度越大，互连的可靠性越高；互连的纵横比越大，互连的可靠性越高。对用于互连的金属凸块是焊料球的情况，提高互连的高度意味着增加焊盘的直径和焊盘间距，也就意味着减少芯片的单位面积引脚数。而受到不断提高芯片功能的驱动，芯片的发展趋势是不断增加单位面积引脚数，即要求更小的焊盘直径和间距或凸块间距(Bump Pitch)。为了解决这个矛盾，一些其它的用于互连的金属凸块被发展和采用，其中在产品中用的最广的是所谓的铜柱凸块(Copper Pillar  Bump)，其可以制造更小的焊盘间距或凸块间距(Bump Pitch)，其高度大约在60微米左右，其纵横比大约在2左右。
焊料球互连是通过事先分布在焊盘上的焊料的回流(Reflow)工艺制成，而铜柱凸块互连中的铜柱是通过在一层载体材料中先开孔然后再填充铜料的工艺制成。图1A中100示意目前在产品中用的最广的这两种凸块互连方式，即所述的焊料球凸块和铜柱凸块互连，及其中的一些基本构件和特征。图1A中110示意倒装芯片和基板间通过焊料球凸块制成的互连体，其中数字符号11，12，13，14和15分别代表芯片，芯片上的输入输出盘(Pad)，芯片上的第一惰性保护层(Passivation 1，其通常是一个氮化硅层)，芯片上的第二惰性保护层(Passivation 2，其通常是一个聚合物软层，如polyimide层)和凸块下方的金属(UBM：Under Bump Metal)，数字符号16和17分别代表焊料球凸块和底部填充材料(Underfill)，和数字符号20，21，22和23分别代表电路基板，电路基板上表面的焊盘，事先在焊盘上准备的焊料(Presolder)和焊料罩(Solder Mask)；图1A中120示意倒装芯片和基板间通过铜柱凸块制成的互连体，其中数字符号30和31分别代表铜柱和铜柱顶部的焊料，其它构件如110中所示。芯片上的第二惰性保护层14和底部填充材料17都是为了保护这个互连结构免于过早地破坏，其中保护层14是为了减缓焊料球凸块16或铜柱凸块30与芯片11连接的角点处的应力集中，而底部填充材料17是为了减缓直接作用在互连结构上的应力。
图1B中数字符号200，300和400示意基于焊料球凸块互连的倒装芯片封装结构，其中200示意没带加强构件的倒装芯片封装，而300和400分别示意带有加强环41和盖子43的倒装芯片封装，其中数字符号42和44分别代表把加强环41和盖子43粘接在电路基板上的粘接材料，40和45分别代表底部填充材料17在芯片边缘形成的拐角(Filet)和盖子43与芯片间的热界面材料(TIM：Thermal Interface Material)。在电路基板上粘附一个加强环41或盖子43的目的是为了提高电路基板的刚度以免其过量的翘曲。在现有技术中采用其它互连结构，如铜柱凸块互连的倒装芯片封装都采用类似的封装结构。
图1C中500示意制造铜柱凸块的基本步骤，包括：1)如510所示，先在芯片上形成一层载体材料，并在载体材料层中开孔；2)如520所示，在孔中填充铜料，从而形成铜柱；3)如530所示，去除载体材料层，并通过焊料把芯片与基板互连。如此制造的铜柱的高度通常在约20微米到60微米左右，很少超过100 微米。
参见US2013/0241071A1，其公开了一种制造空心柱互连和细铜柱互连的方法，其基于类似的先开孔然后再填充的工艺步骤制成空心柱和细铜柱互连，其是铜柱互连的一个改进，其优点是具有比铜柱更好的柔韧性和更大的纵横比，但其并不能增加铜柱的高度。
参见US8525350B2和CN101208799A其公开了一种基于一个模板制造铜柱互连的方法，如图1C中600所示，其包括以下基本步骤：如610所示：1)先把一个模板60附着在一个载体上，并在其中开孔61；2)在孔中填充铜料，从而形成铜柱62；3)通过刻蚀暴露铜柱端部63；如620所示的：4)把包含铜柱的模板68和69通过焊料65和66与芯片64和基板67互连。据其声称，其制造的铜柱的高度大约从40微米到106微米和铜柱的纵横比大约从0.5到5，其中模板的基体69可用作底部填充材料。
参见CN101051614B，其公开了一种利用焊丝器在基板70的焊盘上制造金属线支架71，然后再用焊料在所述金属线支架上形成凸块72的制造芯片73与基板70互连的方法，如图1C中700所示的制造步骤710和720。其声称可制造高达300微米的高度和大于1.5的长宽比或纵横比的互连凸块。需要指出的是，基于先开孔然后再填充的工艺步骤制成的互连凸块很难达到300微米的高度。
现有技术中用于制造倒装芯片封装或互连的方法具有许多局限性，包括：1)先开孔然后再填充的工艺步骤制成的互连凸块的高度一般在约100微米以下，且其制造工艺非常费时和昂贵，2)利用焊丝器先在焊盘上一个一个地制造金属线支架，然后再用焊料在所述金属线支架上形成凸块的方法更加费时和昂贵，且其声称的互连凸块的高度也只是300微米，3)制造精细凸块间距(Fine Bump Pitch)且具有一定高度的互连是非常困难的，比如小于50微米凸块间距且具有100微米以上高度的互连，4)这些互连技术的逐步改进没能从根本上解决芯片与基板间热膨胀系数失配导致的应力及其引起的互连失效或开裂问题。
需要指出的是，图1A和图1B所示的倒装芯片封装中的这些构件，即芯片上的第二惰性保护层14，底部填充材料17，加强环41和盖子43都是为了提高封装或互连体的结构可靠性以免其过早地开裂或失效，而与半导体芯片的功能提高无关；换句话说，如果没有封装或互连体的结构可靠性问题，则没有必要采用这些构件，其占用了大部分的制造倒装芯片封装的时间和费用。
发明内容
本发明采用本申请人于2013年12月27日提交的中国发明专利申请CN201310737666.0中所描述的单向导电板制造半导体芯片或半导体芯片封装与电路基板或印刷电路板的互连体，其克服了以上所述现有技术中的所有局限性，且具有许多新的优点和特征。例如，本发明的互连体可轻易地具有超过1000微米的互连高度，大于10的互连纵横比和小于50微米的焊盘间距，且其制造是便宜和高效的。
本发明的电子器件互连体，包括：电子器件，其包含与外界通讯的导电触点或焊盘；单向导电板，其包含基体材料和用于互连的导线；其中所述单向导电板包含的导线的特征在于：其在板的厚度方向单向地排列，贯通所述的基体材料，并在所述板的一个或两个表面是裸露的或在板的中间部分是裸露的；其形成沿板厚度方向的导电通道；其带有绝缘保护外层；每根导线由一根导线构成或由多根导线形成的导线束或导线绳构成；其具有从约100微米到约200毫米的长度，优选地，具有从约200微米到约20毫米的长度；其具有从约2到2000的纵横比，优选地，具有从5到200的纵横比。
本发明的所述电子器件互连体，其特征在于，其中所述单向导电板中的导线形成一个紧密的排列，具有小于约10微米，优选地小于约5微米的从导线边缘到导线边缘的间距，并且具有小于约30微米的直径，优选地小于约15微米的直径。
本发明的所述电子器件互连体，其特征在于，其中所述单向导电板中的导线形成一个按设定间距的规则排列，具有从约10微米到约500微米，优选地从约20微米到约150微米的从导线边缘到导线边缘的间距，并且具有从约10微米到约150微米，优选地从约20微米到约80微米的直径。
本发明的所述电子器件互连体，其中所述单向导电板中的导线形成一个紧密的排列或者形成一个按设定间距的规则排列，其特征在于，其包含一个电子器件和一个所述的单向导电板，其中所述的电子器件是一个半导体芯片，电路基板或印刷电路板，其一个表面具有排列的引脚或焊盘；所述单向导电板的一个表面具有设定的焊盘或设定的电路及焊盘，而另一个表面具有裸露的导线；所述单向导电板的一个表面上的焊盘与所述电子器件的引脚或焊盘通过焊料对应地互连。
本发明的所述电子器件互连体，其中所述单向导电板中的导线形成一个紧密 的排列或者形成一个按设定间距的规则排列，其特征在于，其包含一个电子器件和一个所述单向导电板，其中所述的电子器件是一个半导体芯片，电路基板或印刷电路板，其一个表面具有排列的引脚或焊盘；所述单向导电板的一个表面具有裸露的导线，而另一个表面具有设定的焊盘或设定的电路及焊盘，或所述单向导电板的两个表面都具有裸露的导线；其中，所述单向导电板的一个表面上的裸露导线与所述电子器件的引脚或焊盘对应地互连。
本发明的所述电子器件互连体，其中所述单向导电板中的导线形成一个紧密的排列或者形成一个按设定间距的规则排列，其特征在于，其包含一个电子器件和一个所述单向导电板，其中所述的电子器件是一个半导体芯片，电路基板或印刷电路板，其一个表面具有排列的引脚或焊盘；所述单向导电板的两个表面都具有设定的焊盘或设定的电路及焊盘，而中间部分具有裸露的导线；其中，所述单向导电板的一个表面上的焊盘与所述电子器件的引脚或焊盘通过焊料对应地互连。
本发明的所述电子器件互连体，其中所述单向导电板中的导线形成一个紧密的排列或者形成一个按设定间距的规则排列，其特征在于，其包含两个电子器件和一个所述单向导电板，其中一个电子器件是表面具有焊盘的电路基板，另一个电子器件是表面具有焊盘的半导体芯片或半导体芯片封装；所述单向导电板的一个表面具有设定的焊盘或设定的电路及焊盘，另一个表面具有裸露的导线；其中，在所述单向导电板的一个表面上的焊盘通过焊料与所述电路基板的焊盘对应地互连，而在所述单向导电板的另一个表面上的裸露导线与所述芯片或芯片封装的焊盘对应地互连。
本发明的所述电子器件互连体，其中所述单向导电板中的导线形成一个紧密的排列或者形成一个按设定间距的规则排列，其特征在于，其包含两个电子器件和一个所述单向导电板，其中一个电子器件是表面具有焊盘的电路基板，另一个电子器件是表面具有焊盘的半导体芯片或半导体芯片封装；所述单向导电板的一个表面具有裸露的导线，另一个表面具有设定的焊盘或设定的电路及焊盘；其中，在所述单向导电板的一个表面上的裸露导线通过焊料与所述电路基板的焊盘对应地互连，而在所述单向导电板的另一个表面上的焊盘通过焊料与所述芯片或芯片封装的焊盘对应地互连。
本发明的所述电子器件互连体，其中所述单向导电板中的导线形成一个紧密的排列或者形成一个按设定间距的规则排列，其特征在于，其包含两个电子器件和一个所述单向导电板，其中一个电子器件是表面具有焊盘的电路基板，另一个电子器件是表面具有焊盘的半导体芯片或半导体芯片封装；所述单向导电板的两个表面都具有裸露的导线；其中，在所述单向导电板的一个表面上的裸露导线通过焊料与所述电路基板的焊盘对应地互连，而在所述单向导电板的另一个表面上的裸露导线通过焊料与所述芯片或芯片封装的焊盘对应地互连。
本发明的所述电子器件互连体，其中所述单向导电板中的导线形成一个紧密的排列或者形成一个按设定间距的规则排列，其特征在于，其包含两个电子器件和一个所述单向导电板，其中一个电子器件是表面具有焊盘的电路基板，另一个电子器件是表面具有焊盘的半导体芯片或半导体芯片封装；所述单向导电板的两个表面都具有设定的焊盘或设定的电路及焊盘，而中间部分具有裸露的导线；其中，在所述单向导电板的一个表面上的焊盘通过焊料与所述电路基板的焊盘对应地互连，而在所述单向导电板的另一个表面上的焊盘通过焊料与所述芯片或芯片封装的焊盘对应地互连。
本发明的所述电子器件互连体，其中所述单向导电板中的导线形成一个紧密的排列或者形成一个按设定间距的规则排列，其特征在于，其包含两个以上的电子器件和一个所述单向导电板，其中一个电子器件是表面具有焊盘的电路基板，其它的电子器件是表面具有焊盘的半导体芯片或半导体芯片封装；所述单向导电板的一个表面具有相同高度的裸露导线或设定的焊盘或设定的电路及焊盘，所述单向导电板的另一个表面具有不同高度的裸露导线，其形成台阶形的凹槽；其中，在所述单向导电板的一个表面上的相同高度的裸露导线或设定的焊盘通过焊料与所述电路基板的焊盘对应地互连，而在所述单向导电板另一个表面上的具有台阶形凹槽的裸露导线与所述多个芯片或芯片封装的焊盘对应地互连，其中每一个台阶或凹槽容纳一个芯片或芯片封装，所述多个芯片或芯片封装在所述单向导电板的导线台阶上形成堆叠结构。
本发明的所述电子器件互连体，其中所述单向导电板中的导线形成一个紧密的排列或者形成一个按设定间距的规则排列，其特征在于，其包含两个以上的电子器件和一个单向导电板，其中一个电子器件是表面具有焊盘的电路基板，其它的电子器件是表面具有焊盘的半导体芯片或半导体芯片封装；所述单向导电板的 一个表面具有相同高度的裸露导线或设定的焊盘或设定的电路及焊盘，所述单向导电板的另一个表面具有不同高度的裸露导线，其形成台阶形的凹槽；其中，所述单向导电板的一个表面上的相同高度的裸露导线或设定的焊盘或设定的电路及焊盘通过焊料与所述多个芯片或芯片封装中的一个芯片或芯片封装的焊盘对应地互连，而在所述单向导电板的另一个表面上的台阶形的裸露导线与所述多个芯片或芯片封装中的其它芯片或芯片封装的焊盘及所述电路基板的焊盘对应地互连，其中最高台阶中的导线与电路基板互连，而其它每一个导线台阶或凹槽容纳一个芯片或芯片封装；所述多个芯片或芯片封装的堆叠结构是一个芯片或芯片封装位于所述单向导电板的上方，而其它芯片或芯片封装位于所述单向导电板下方的导线台阶中。
本发明的所述电子器件互连体，其中所述单向导电板中的导线形成一个紧密的排列或者形成一个按设定间距的规则排列，其特征在于，其包含两个以上的电子器件和一个单向导电板，其中一个电子器件是表面具有焊盘的电路基板，其它的电子器件是表面具有焊盘的半导体芯片或半导体芯片封装；所述单向导电板的一个表面具有相同高度的裸露导线，而所述单向导电板的另一个表面具有设定的焊盘或设定的电路及焊盘；其中，所述单向导电板的一个表面上的裸露导线与所述电路基板的焊盘对应地互连，所述单向导电板的另一个表面上的焊盘通过焊料与所述多个芯片或芯片封装的焊盘对应地互连；所述多个芯片或芯片封装在所述单向导电板的上方形成面内互连。
本发明的所述电子器件互连体，其特征在于，所述单向导电板中的裸露导线在其端部具有焊接材料头，从而免去在互连焊接中使用另外的焊料。
本发明的所述电子器件互连体，其特征在于，所述单向导电板中的基体材料是高导热材料，其具有大于约10W/mK的热传导系数，所述单向导电板中用于互连的裸露导线具有设定的长度，如大于约2毫米，优选地大于约10毫米，从而用于导电互连的裸露导线兼具散热作用；其进一步的特征在于，所述单向导电板比其它电子器件的尺寸大，其中除用于导电互连的导线，其它多出的基体和导线用于进一步加强经由单向导电板的散热。
本发明中的关键构思是通过一个包含裸露的细长导线的单向导电板制造电子器件的互连体，其完全不同于现有技术中的思路和方法。本发明的优点和特征包括：1)本发明的互连体采用纵横比超过5，10或100的细长导线，从而具有 极好的柔韧性，可消除热应力引起的互连失效问题，从而可以免去在现有技术中采用的用来提高互连结构可靠性的位于芯片上层的第二惰性保护层和底部填充材料(Underfill)及其工艺步骤，其在倒装芯片的封装工艺中占了很大一部分时间和费用；2)可消除热应力引起的电路基板的翘曲问题(Warpage)，从而可以免去使用在现有技术中采用的用来控制基板翘曲的金属盖或金属加强环及其工艺步骤；3)当用于互连的导线设定在约10毫米以上时，除导电外，其可兼具散热的能力，类似于一个散热器上的散热柱。本发明的这些优点，特征和相关的发明性概念在本发明的具体实施方式中通过参照下面的附图说明被加以详述。
附图说明
图1A是现有技术中广泛采用的倒装芯片焊盘与基板焊盘间的互连结构的示意图，包括焊料球凸块互连和铜柱凸块互连结构；
图1B是现有技术中包含焊料球凸块互连和铜柱凸块互连的倒装芯片封装结构的示意图；
图1C是现有技术中公开的倒装芯片焊盘与基板焊盘间的互连结构的示意图及其基本的制造步骤；
图2是本发明采用的一种单向导电板及其基本的制造步骤的示意图；
图2A是图2所示的单向导电板的局部放大示意图，其显示所述单向导电板包含的导线形成一个紧密的排列，并且在其表面可包含各种形态的裸露导线和焊盘：
图2B是图2所示的单向导电板的局部放大示意图，其显示所述单向导电板包含的导线形成一个具有设定间距的排列，并且在其表面可包含各种形态的裸露导线和焊盘；
图3A是本发明一个实施例中一个单向导电板与一个电路基板或印刷电路板形成的互连体的示意图，其中的单向导电板包含紧密排列的导线；
图3B是本发明一个实施例中一个单向导电板与一个电路基板或印刷电路板形成的互连体的示意图，其中的单向导电板包含按设定间距排列的导线；
图4A是本发明一个实施例中一个倒装芯片通过一个单向导电板与一个电路基板或印刷电路板形成的互连体的示意图，其中的单向导电板包含紧密排列的导线；
图4B是本发明一个实施例中一个倒装芯片通过一个单向导电板与一个电路基板或印刷电路板形成的互连体的示意图，其中的单向导电板包含按设定间距排列的导线；
图4C是本发明一个实施例中一个倒装芯片通过一个单向导电板与一个电路基板或印刷电路板形成的互连体的示意图，其中的单向导电板具有一个较大的尺寸；
图5是本发明一个实施例中多个倒装芯片通过一个单向导电板与一个电路基板或印刷电路板形成的互连体的示意图，其中所述多个芯片在导线台阶上形成堆叠结构；
图6是本发明一个实施例中多个倒装芯片通过一个单向导电板与一个电路基板或印刷电路板形成的互连体的示意图，其中所述多个芯片的堆叠结构是一个芯片位于所述单向导电板的上方，而其它芯片位于所述单向导电板下方的导线台阶中；
图7是本发明一个实施例中多个倒装芯片通过一个单向导电板与一个电路基板或印刷电路板形成的互连体的示意图，其中所述多个芯片在所述单向导电板的上方形成面内互连；
图8是本发明一个实施例中一个倒装芯片和一个芯片封装通过一个单向导电板与一个电路基板或印刷电路板形成的互连体的示意图，其中所述倒装芯片和芯片封装在导线台阶上形成堆叠结构；
图9是本发明一个实施例的示意图，包括，所述单向导电板中的每根导线由一根导线构成或由多根导线形成的导线束或导线绳构成，导线的端部带有焊料头，互连体的基本制造步骤。
具体实施方式
为清楚地通过参照附图说明本发明的具体实施方式，首先对一些使用的术语解释如下：1)单向导电板，其代表在板的厚度方向导电而在板的面内方向绝缘的一个片状材料，其中在板的厚度方向导电并不意味板的任意位置在板的厚度方向都导电，而是意味在一个相对大的尺度上，板的任意位置在板的厚度方向导电，或是意味在按设定间距排列的位置处在板的厚度方向导电；而对于基体粘接材料是导电材料，如一个低熔点金属材料的情况，单向导电代表在板的面内方向导线 间相互绝缘，每一根导线是沿板厚度方向的一个导电通道；2)基体材料，单向导电板中把单向排列的导线连接并固化在一起的材料；3)引脚或焊盘，在电子器件的输入输出端口处的一小片可焊接的金属，其形状不限于圆形；4)电路及焊盘，其中电路可以是多层的电路，焊盘位于电路的最上层并与电路相连，从而在所述的表面具有电路及焊盘的单向导电板中，焊盘不需要与其中的导线对齐，数量也不必相同。需要注意的是，以上的术语解释仅是为了说明的目的，而不限制本发明的范围和精神。
图2是本发明采用的一种单向导电板及其基本的制造步骤的示意图1000，其通过一个包含紧密排列的带有外层的导线的导线集成体制造单向导电板。图2中的数字符号100代表一个包含紧密排列的带有外层的导线的导线集成体，101和102代表通过分割导线集成体而制成的单向导电板的俯视图和侧视图，其中101中的103，104，105，小黑点和箭头代表包含在导线集成体100或单向导电板101中的带有外层的导线及其紧密排列方式的放大示意图，102中的109代表一个将要进一步放大的局部区域。在103中示意的导线具有非常薄的绝缘外层和正三角形紧密排列，在104和105中示意的导线具有一定厚度的外层106和方形紧密排列，其中在105中示意的导线的导线芯是一个由多根导线组成的导线束或一个多根导线拧成的导线绳，外层106的厚度设定了导线芯间到间距，导线由粘接材料107连接并固化在一起。与单根导线的导线芯相比，由多根导线组成的导线芯具有更好的柔韧性。
关于本文所述的单向导电板的结构及制造，可参阅本申请人于2013年12月27日提交的中国发明专利申请CN201310737666.0，该申请通过引用结合于本文中。
制造所述单向导电板的方法包括如下基本步骤：1)提供带有外层的导线；2)把带有外层的导线聚在一起形成一个紧密的排列，并固化成一个整体，从而制成一个包含单向紧密排列的导线的导线集成体；3)把所述导线集成体分割成片，从而制成多个按照需要在厚度方向导电的单向导电板。通过以上所述步骤制成的单向导电板中的导线芯不是裸露的而是嵌入在导电板中的，即单向导电板是具有嵌入式导线芯的单向导电板。为了制成在表面包含裸露的导线芯的单向导电板，以上所述的制造单向导电板的方法可进一步包含如下步骤：在所述单向导电板的所需表面的部分或全部区域去除导线芯粘以外的基体材料，从而制成在所述表面 的部分或全部区域具有裸露的导线芯的单向导电板。具有裸露的导线芯的单向导电板可在电子器件之间制造柔性的互连，从而提高电子器件之间互连的可靠性。在实际应用中，所述单向导电板可以进一步分割成许多小的单元，每一个单元可用于一个集成电路半导体封装或其它的应用。
图2A是图2所示的单向导电板102的局部109的放大示意图，其基于图2中103所示的紧密排列的导线制成。图2A中的数字符号1110示意的单向导电板包含嵌入式导线111和基体材料112；通过对单向导电板1110的表面做进一步的处理可制成如图2A中的数字符号1120，1130，1140和1150示意的单向导电板，其中1120示意的单向导电板的一个表面具有裸露的导线113，另一个表面具有设定的焊盘120，1130示意的单向导电板的裸露导线具有台阶形的凹槽130，1140示意的单向导电板的两个表面都有裸露的导线141和142，1150示意的单向导电板的两个表面都有裸露的导线151和152，但其一面的裸露导线151具有台阶形的凹槽150，以容纳堆叠的芯片。需要指出的是，所述裸露导线具有一个薄绝缘外层以避免在应用中相互接触导致的短路；另外，在所述单向导电板的一个表面上的焊盘，如1120中的120所示，可具有按需要设定的尺寸和间距以匹配一个实际应用。
图2B是图2所示的单向导电板102的局部109的放大示意图，其基于图2中105所示的带有一定厚度的外层106的导线的方形紧密排列制成，其中的导线芯是多根导线形成的导线绳，外层106的厚度设定了导线芯间到间距。图2B中的数字符号1210示意的单向导电板包含嵌入式导线211和基体材料212，其中的基体材料212是由图2中105所示的导线的外层106和粘接材料107组成；通过对单向导电板1210的表面做进一步的处理可制成如图2B中的数字符号1220，1230，1240和1250示意的单向导电板；其中1220示意的单向导电板的一个表面具有裸露的导线213，另一个表面具有设置在基体材料层222表面的焊盘210，1230示意的单向导电板的裸露导线具有容纳堆叠芯片的台阶形凹槽230，1240示意的单向导电板的两个表面都裸露的导线241和243。需要指出的是，图2B所示的单向导电板1220和1230的表面上的焊盘210不能象图2A所示的包含紧密排列的细导线的单向导电板1120和1130的表面上的焊盘120那样按照需要随意设置，而只能按照导线的相应位置设置，其在应用中有一定的局限性。为此，可通过先设置一个电路层，然后再铺设焊盘来消除这个局限性，如图2B中的数字 符号1250示意的单向导电板，其中的电路层251用来整合导线213与焊盘250的联系，从而焊盘250的数量，大小和间距都可以按照需要随意设置。图2B中1260所示的单向导电板在两个表面都具有焊盘或电路及焊盘，而在中间部分包含裸露导线，其可以通过在1210所示的单向导电板的两个表面先制作焊盘或电路及焊盘，然后再去除中间部分的基体材料的步骤制成，其中在上方的焊盘260和基体材料262之间也可以设置一个电路层，从而使焊盘260的设置更加灵活。
图3A是本发明一个实施例中一个单向导电板与一个电路基板或印刷电路板形成的互连体的示意图，其中的单向导电板包含紧密排列的导线。图3A中的数字符号2120，2130和2140是一个单向导电板与一个电路基板或印刷电路板形成的互连体的示意性的例子；其中2120表示一个一面具有焊盘，另一面具有相同高度的裸露导线的单向导电板320与一个电路基板或印刷电路板321通过焊盘323，焊料322和焊盘324的相连形成的互连体；2130表示一个一面具有相同高度的裸露导线，另一面具有台阶形裸露导线的单向导电板330与一个电路基板或印刷电路板331通过裸露导线，焊料332和焊盘的相连形成的互连体；2140表示一个一面具有焊盘，另一面具有相同高度的裸露导线的单向导电板340与一个电路基板或印刷电路板341通过裸露导线，焊料342和焊盘的相连形成的互连体。
图3B是本发明一个实施例中一个单向导电板与一个电路基板或印刷电路板的互连体的示意图，其中的单向导电板包含按设定间距排列的导线。图3B中的数字符号2210，2220和2230是一个单向导电板与一个电路基板或印刷电路板形成的互连体的示意性的例子；其中2210表示一个一面具有焊盘，另一面具有相同高度的裸露导线的单向导电板420与一个电路基板或印刷电路板421通过焊盘423，焊料422和焊盘424的相连形成的互连体；2220表示一个一面具有焊盘，另一面具有相同高度的裸露导线的单向导电板430与一个电路基板或印刷电路板431通过裸露导线，焊料432和焊盘的相连形成的互连体；2230表示一个一面具有焊盘，另一面具有台阶形裸露导线的单向导电板450与一个电路基板或印刷电路板451通过焊盘，焊料和焊盘的相连形成的互连体。
图3A和图3B所示的互连体是一种包含裸露导线的电路基板或印刷电路板，在应用中，其裸露导线的上方可以安装芯片或芯片封装，其下表面的焊盘，如2210中425所示，可以连接到其它电子设备。需要指出的是，所述的电路基板或印刷电路板也可以是一个半导体芯片，从而图3A和图3B所示的互连体成为一种包含 裸露导线的半导体芯片；在应用中，所述包含裸露导线的半导体芯片可以通过裸露导线安装在一个电路基板或印刷电路板上。
图4A是本发明一个实施例中一个倒装芯片通过一个单向导电板与一个电路基板或印刷电路板形成的互连体的示意图，其中的单向导电板包含紧密排列的导线。图4A中的数字符号3110和3120是一个倒装芯片510通过一个单向导电板500或509与一个电路基板或印刷电路板502形成的互连体的示意性的例子；其中3110所示的是单向导电板的裸露导线通过焊料504与倒装芯片相连，单向导电板的焊盘通过焊料503与电路基板或印刷电路板的焊盘相连；而3120所示的连接方式是单向导电板的焊盘通过焊料506与倒装芯片相连，单向导电板的裸露导线通过焊料505与电路基板或印刷电路板的焊盘相连。需要指出的是，所述单向导电板采用了紧密排列的细导线，其尺寸和间距比其连接的焊盘小很多，一对互连的焊盘间包含了多根导线；另外，对所述较大尺寸的焊盘来说，由于所述单向导电板在任意位置都在厚度方向导电，所述倒装芯片中的焊盘不必要求具有相同的尺寸和间距。
图4B是本发明一个实施例中一个倒装芯片通过一个单向导电板与一个电路基板或印刷电路板的互连体的示意图，其中的单向导电板包含按设定间距排列的导线。图4B中的数字符号3210，3220和3230是一个倒装芯片511通过一个单向导电板500，520或530与一个电路基板或印刷电路板512形成的互连体的示意性的例子；其中3210所示的是单向导电板的裸露导线515与倒装芯片的焊盘通过焊料514相连，单向导电板的焊盘与电路基板或印刷电路板的焊盘通过焊料513相连；3220所示的连接方式是单向导电板的焊盘与倒装芯片的焊盘相连，单向导电板的裸露导线与电路基板或印刷电路板的焊盘相连，而3230中的单向导电板的两个表面都是裸露的导线，如537和538所示，基体材料536用于保持这些导线，焊料533和534把裸露的导线537和538的端部分别连接到电路基板或印刷电路板的焊盘和倒装芯片的焊盘。需要指出的是，所述单向导电板采用了按设定间距排列的导线，其尺寸和间距与其连接的焊盘相当，一对焊盘由一根导线互连；因此，所述倒装芯片中的焊盘不能具有随意的尺寸和间距。对于焊盘具有不规则的排列和尺寸的倒装芯片，为了采用包含按设定间距排列的导线的单向导电板，需要在单向导电板的一个表面先设置一个电路层，然后再铺设焊盘来整合与所述倒装芯片的焊盘的连接，如图2B中1250所示的单向导电板。
图4C是本发明一个实施例中一个倒装芯片通过一个单向导电板与一个电路基板或印刷电路板的互连体的示意图，其中的单向导电板具有一个较大的尺寸；其中除用于导电互连的导线，其它多出的基体和导线用于进一步加强经由单向导电板的散热。图4C中的数字符号3240和3250是一个倒装芯片511通过一个单向导电板540或550与一个电路基板或印刷电路板512形成的互连体的示意性的例子；其中3240所示的单向导电板的一个表面具有裸露导线545，另一个表面在基体材料546上具有焊盘，所述裸露导线545与电路基板或印刷电路板512的焊盘通过焊料相连，而所述焊盘与倒装芯片的焊盘通过焊料相连；其中3250所示的单向导电板的两个表面都具有裸露导线557和558，其通过焊料分别与与电路基板或印刷电路板512的焊盘和倒装芯片511的焊盘相连。需要指出的是，图4C中所示的单向导电板540和550具有一个较大的尺寸，其中554所示的部分是为了进一步加强经由单向导电板的散热。在这个实施例中，优选的基体材料546和556应该是一种热传导系数高的材料，如热传导系数大于40W/mK的材料。
图5是本发明一个实施例中多个倒装芯片通过一个单向导电板与一个电路基板或印刷电路板形成的互连体的示意图，其中所述多个芯片在导线台阶上形成堆叠结构。图5中的数字符号4130和4220是多个倒装芯片通过一个单向导电板610或640与一个电路基板或印刷电路板630或660形成的互连体的示意性的例子。图5中4130所示的互连体采用了包含紧密排列导线的单向导电板610，其中的多个倒装芯片621，622，623位于单向导电板610的裸露导线凹槽中，单向导电板610的两个表面都具有裸露的导线627和628并通过焊料分别与电路基板或印刷电路板630的焊盘和多个倒装芯片621，622，623的焊盘相连；单向导电板610中的基体材料626用于把裸露的导线保持在一起；图5中4220所示的互连体采用了包含按设定间距排列的导线的单向导电板640，其中的多个倒装芯片651，652，653位于单向导电板640的裸露导线凹槽中，单向导电板640的另一个表面具有焊盘，其通过焊料与电路基板或印刷电路板660的焊盘相连，而导线645通过焊料与多个倒装芯片651，652，653的焊盘相连。单向导电板640中的基体材料646用于把裸露的导线保持在一起。
图6是本发明一个实施例中多个倒装芯片通过一个单向导电板与一个电路基板或印刷电路板的互连体的示意图，其中所述多个芯片的堆叠结构是一个芯片位于所述单向导电板的上方，而其它芯片位于所述单向导电板下方的导线台阶中。 图6中的数字符号4430和4520是多个倒装芯片721，722，723通过一个包含电路层和焊盘的单向导电板710或740与一个电路基板或印刷电路板730形成的互连体的示意性的例子。图6中4430所示的互连体采用了包含紧密排列导线的单向导电板710，其中多个倒装芯片中的一个芯片721位于单向导电板710的上方并通过焊料与单向导电板710上表面的电路层711和焊盘相连，另外的倒装芯片722和723位于单向导电板710下方的裸露导线凹槽中并通过焊料与裸露导线715的端部相连。图6中4520所示的互连体采用了包含按设定间距排列的导线的单向导电板740，其中多个倒装芯片中的一个芯片721位于单向导电板740的上方并通过焊料与单向导电板740上表面的电路层741和焊盘相连，另外的倒装芯片722和723位于单向导电板740下方的裸露导线凹槽中并通过焊料与裸露导线745的端部相连。
需要指出的是，图5和图6中多个倒装芯片的堆叠结构的区别在于图5中的多个倒装芯片之间通过电路基板或印刷电路板进行通讯，而图6中的多个倒装芯片在与电路基板或印刷电路板通讯之前通过单向导电板上表面的电路层具有相互间的直接通讯。另外需要指出的是，图6中单向导电板的基体材料716和746优选地具有与倒装芯片接近的热膨胀系数以避免单向导电板上表面的电路层711和714与芯片721之间焊料层的开裂，其可以从玻璃，陶瓷，硅或其它的材料中挑选；另外，单向导电板上表面的电路层711和714与芯片721之间的焊料层可以填充一个保护材料以加强所述焊料层的强度。
图7是本发明一个实施例中多个倒装芯片通过一个单向导电板与一个电路基板或印刷电路板的互连体的示意图，其中所述多个芯片在所述单向导电板的上方形成面内互连。图6中的数字符号5110和5210是多个倒装芯片821，822，823通过一个包含电路层811或841和焊盘的单向导电板810或840与一个电路基板或印刷电路板830形成的互连体的示意性的例子。图7中5110所示的互连体采用了包含紧密排列导线的单向导电板810，其中多个倒装芯片中位于单向导电板810的上方并通过焊料与单向导电板810上表面的电路层811和焊盘相连，而单向导电板810的裸露导线815通过焊料813与电路基板或印刷电路板830上方的焊盘相连。图7中5210所示的互连体采用了包含按设定间距排列的导线的单向导电板840，其中多个倒装芯片位于单向导电板840的上方并通过焊料与单向导电板840上表面的电路层841和焊盘相连，而单向导电板840的裸露导线845通 过焊料843与电路基板或印刷电路板840上方的焊盘相连。图7中单向导电板的基体材料816和846优选地具有与倒装芯片接近的热膨胀系数以避免单向导电板上表面的电路层811和814与芯片721之间焊料层的开裂，其可以从玻璃，陶瓷，硅或其它的材料中挑选；另外，单向导电板上表面的电路层811和814与芯片821，822，823之间的焊料层可以填充一个保护材料以加强所述焊料层的强度。
图8是本发明一个实施例中860所示的芯片封装861和倒装芯片862通过一个单向导电板850与一个电路基板或印刷电路板870形成的互连体的示意图的例子6000，其中所述倒装芯片862和芯片封装861在台阶形的导线855上形成堆叠结构；其中的单向导电板850的上表面是紧密排列的具有凹槽的裸露导线而其下表面具有焊盘，所述的倒装芯片862和芯片封装861的焊盘通过焊料相连到所述的裸露导线，单向导电板850的下表面的焊盘与电路基板或印刷电路板870的焊盘相连。需要指出的是，单向导电板850中的基体材料856在中部和边缘可以具有不同的厚度；由于基体材料856位于电路基板或印刷电路板870一侧，其材料性质优选地应该具有与电路基板或印刷电路板相接近的热膨胀系数；单向导电板850采用了紧密排列的导线，其也可采用按设定间距排列的导线。
图9是本发明一个实施例中示意图的例子7000，其描述电子器件互连体的基本制造步骤，并示意所述单向导电板中的每根导线可以由一根导线构成或由多根导线形成的导线束或导线绳构成和导线的端部可以带有焊料头。图9中的数字符号901代表芯片层，902代表焊料层，903代表单向导电板中的焊盘层，904代表另一个焊料层，905代表电路基板上表面的焊盘层，906代表电路基板下表面的焊盘层；其中焊料层902用于把芯片层901与单向导电板上方的焊盘层903相连，其可以设置在芯片层901的焊盘上也可以设置在单向导电板上方的焊盘层903上，其可以是焊膏也可以是预先制作在焊盘上的互连凸块；焊料层904用于把单向导电板下方的裸露导线与电路基板上表面的焊盘层905相连，其可以设置在电路基板上表面的焊盘层905上也可以设置在裸露导线的端部，如910中的912所示；其可以是焊膏也可以是预先制作在焊盘上或导线端部的焊料凸块。另外，需要指出的是，导线与焊盘的互连也可以不基于焊料，而采用热压焊接或热超声焊接方法。图9中的数字符号910示意单向导电板中每根导线可以由一根导线构成或由多根导线形成的导线束或导线绳构成，导线的端部可带有用于互连的焊料头912，从而免去在互连焊盘上设置焊膏或焊料凸块。
需要说明的是，以上附图说明中的裸露导线具有一个薄的绝缘保护外层，除为了抗环境腐蚀和氧化外，其可避免当导线的纵横比很大时导线相互接触引发的短路，此保护外层没有在附图中画出。当裸露导线具有一个薄绝缘外层时，导线以外的基体材料可以不必是绝缘材料，也可以是一种导电基体，如一种低熔点金属，这时，每一根导线是一个独立的导电通道。
需要说明的是，本发明的基本要素之一是通过所述的单向导电板使细长导线成为电子器件之间的互连，以上附图所示的通过一个单向导电板制造的电子器件互连体仅是示意说明，在附图和实施例中没有列出所有可能的组合，所以以上参照实施例和附图说明对本发明的描述仅为举例说明，而不是限定本发明的精神和范围，熟悉此技术者当可据此进行修改而得到等效实施例。

Claims (16)

  1. 一种电子器件互连体，包括：
    电子器件，其包含与外界通讯的导电引脚或焊盘；
    单向导电板，其包含基体材料和用于把所述电子器件相互连接起来的导线；
    其特征在于：所述导线在板的厚度方向单向地排列，贯通所述的基体材料，并在所述板的一个或两个表面是裸露的或在板的中间部分是裸露的；所述导线形成沿板厚度方向的导电通道；所述导线带有绝缘保护外层；每根导线由一根导线构成或由多根导线形成的导线束或导线绳构成；所述导线具有从约100微米到约200毫米的长度，优选地具有从约200微米到约20毫米的长度；所述导线具有从约2到约2000的纵横比，优选地具有从约5到约200的纵横比。
  2. 如权利要求1所述的电子器件互连体，其特征在于，所述单向导电板中的导线形成一个紧密的排列，具有小于约10微米，优选地小于约5微米的从导线边缘到导线边缘的间距，并且具有小于约30微米的直径，优选地小于约15微米的直径。
  3. 如权利要求1所述的电子器件互连体，其特征在于，所述单向导电板中的导线形成一个按设定间距的规则的排列，具有从约10微米到约500微米，优选地从约20微米到约150微米的从导线边缘到导线边缘的间距，并且具有从约10微米到约150微米，优选地从约20微米到约80微米的直径。
  4. 如权利要求2或权利要求3所述的电子器件互连体，其特征在于，其包含一个电子器件和一个所述的单向导电板，其中所述的电子器件是一个半导体芯片、电路基板或印刷电路板，其一个表面具有排列的引脚或焊盘；所述单向导电板的一个表面具有设定的焊盘或设定的电路及焊盘，而另一个表面具有裸露的导线；所述单向导电板的一个表面上的焊盘与所述电子器件的引脚或焊盘通过焊料对应地互连。
  5. 如权利要求2或权利要求3所述的电子器件互连体，其特征在于，其包含一个电子器件和一个所述单向导电板，其中所述的电子器件是一个半导体芯片、电路基板或印刷电路板，其一个表面具有排列的引脚或焊盘；所述单向导电板的一个表面具有裸露的导线，而另一个表面具有设定的焊盘或设定的电路及焊盘，或所述单向导电板的两个表面都具有裸露的导线；其中，所述单向导电板的 一个表面上的裸露导线与所述电子器件的引脚或焊盘对应地互连。
  6. 如权利要求2或权利要求3所述的电子器件互连体，其特征在于，其包含一个电子器件和一个所述单向导电板，其中所述的电子器件是一个半导体芯片、电路基板或印刷电路板，其一个表面具有排列的引脚或焊盘；所述单向导电板的两个表面都具有设定的焊盘或设定的电路及焊盘，而中间部分具有裸露的导线；其中，所述单向导电板的一个表面上的焊盘与所述电子器件的引脚或焊盘通过焊料对应地互连。
  7. 如权利要求2或权利要求3所述的电子器件互连体，其特征在于，其包含两个电子器件和一个所述单向导电板，其中一个电子器件是表面具有焊盘的电路基板，另一个电子器件是表面具有焊盘的半导体芯片或半导体芯片封装；所述单向导电板的一个表面具有设定的焊盘或设定的电路及焊盘，另一个表面具有裸露的导线；其中，在所述单向导电板的一个表面上的焊盘通过焊料与所述电路基板的焊盘对应地互连，而在所述单向导电板的另一个表面上的裸露导线与所述芯片或芯片封装的焊盘对应地互连。
  8. 如权利要求2或权利要求3所述的电子器件互连体，其特征在于，其包含两个电子器件和一个所述单向导电板，其中一个电子器件是表面具有焊盘的电路基板，另一个电子器件是表面具有焊盘的半导体芯片或半导体芯片封装；所述单向导电板的一个表面具有裸露的导线，另一个表面具有设定的焊盘或设定的电路及焊盘；其中，在所述单向导电板的一个表面上的裸露导线通过焊料与所述电路基板的焊盘对应地互连，而在所述单向导电板的另一个表面上的焊盘通过焊料与所述芯片或芯片封装的焊盘对应地互连。
  9. 如权利要求2或权利要求3所述的电子器件互连体，其特征在于，其包含两个电子器件和一个所述单向导电板，其中一个电子器件是表面具有焊盘的电路基板，另一个电子器件是表面具有焊盘的半导体芯片或半导体芯片封装；所述单向导电板的两个表面都具有裸露的导线；其中，在所述单向导电板的一个表面上的裸露导线通过焊料与所述电路基板的焊盘对应地互连，而在所述单向导电板的另一个表面上的裸露导线通过焊料与所述芯片或芯片封装的焊盘对应地互连。
  10. 如权利要求2或权利要求3所述的电子器件互连体，其特征在于，其包含两个电子器件和一个所述单向导电板，其中一个电子器件是表面具有焊盘的电路基板，另一个电子器件是表面具有焊盘的半导体芯片或半导体芯片封装；所述 单向导电板的两个表面都具有设定的焊盘或设定的电路及焊盘，而中间部分具有裸露的导线；其中，在所述单向导电板的一个表面上的焊盘通过焊料与所述电路基板的焊盘对应地互连，而在所述单向导电板的另一个表面上的焊盘通过焊料与所述芯片或芯片封装的焊盘对应地互连。
  11. 如权利要求2或权利要求3所述的电子器件互连体，其特征在于，其包含两个以上的电子器件和一个所述单向导电板，其中一个电子器件是表面具有焊盘的电路基板，其它的电子器件是表面具有焊盘的半导体芯片或半导体芯片封装；所述单向导电板的一个表面具有相同高度的裸露导线或设定的焊盘或设定的电路及焊盘，所述单向导电板的另一个表面具有不同高度的裸露导线，其形成台阶形的凹槽；其中，在所述单向导电板的一个表面上的相同高度的裸露导线或设定的焊盘通过焊料与所述电路基板的焊盘对应地互连，而在所述单向导电板另一个表面上的具有台阶形凹槽的裸露导线与所述多个芯片或芯片封装的焊盘对应地互连，其中每一个台阶或凹槽容纳一个芯片或芯片封装，所述多个芯片或芯片封装在所述单向导电板的导线台阶上形成堆叠结构。
  12. 如权利要求2或权利要求3所述的电子器件互连体，其特征在于，其包含两个以上的电子器件和一个单向导电板，其中一个电子器件是表面具有焊盘的电路基板，其它的电子器件是表面具有焊盘的半导体芯片或半导体芯片封装；所述单向导电板的一个表面具有相同高度的裸露导线或设定的焊盘或设定的电路及焊盘，所述单向导电板的另一个表面具有不同高度的裸露导线，其形成台阶形的凹槽；其中，所述单向导电板的一个表面上的相同高度的裸露导线或设定的焊盘或设定的电路及焊盘通过焊料与所述多个芯片或芯片封装中的一个芯片或芯片封装的焊盘对应地互连，而在所述单向导电板的另一个表面上的台阶形的裸露导线与所述多个芯片或芯片封装中的其它芯片或芯片封装的焊盘及所述电路基板的焊盘对应地互连，其中最高台阶中的导线与电路基板互连，而其它每一个导线台阶或凹槽容纳一个芯片或芯片封装；所述多个芯片或芯片封装的堆叠结构是一个芯片或芯片封装位于所述单向导电板的上方，而其它芯片或芯片封装位于所述单向导电板下方的导线台阶中。
  13. 如权利要求2或权利要求3所述的电子器件互连体，其特征在于，其包含两个以上的电子器件和一个单向导电板，其中一个电子器件是表面具有焊盘的电路基板，其它的电子器件是表面具有焊盘的半导体芯片或半导体芯片封装；所 述单向导电板的一个表面具有相同高度的裸露导线，而所述单向导电板的另一个表面具有设定的焊盘或设定的电路及焊盘；其中，所述单向导电板的一个表面上的裸露导线与所述电路基板的焊盘对应地互连，所述单向导电板的另一个表面上的焊盘通过焊料与所述多个芯片或芯片封装的焊盘对应地互连；所述多个芯片或芯片封装在所述单向导电板的上方形成面内互连。
  14. 如权利要求1所述的电子器件互连体，其特征在于，所述单向导电板中的裸露导线在其端部具有用于互连焊接的焊料头。
  15. 如权利要求1所述的电子器件互连体，其特征在于，所述单向导电板中的基体材料具有大于约10W/mK的热传导系数，所述单向导电板中用于互连的裸露导线具有设定的长度，如大于约2毫米，优选地大于约10毫米。
  16. 如权利要求15所述的电子器件互连体，其特征在于，所述单向导电板比其它电子器件的尺寸大。
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CN103762206A (zh) * 2014-01-07 2014-04-30 申宇慈 一种电子器件互连体
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US20190295968A1 (en) * 2018-03-23 2019-09-26 Analog Devices Global Unlimited Company Semiconductor packages

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050223553A1 (en) * 2004-03-31 2005-10-13 Loy Garry M Method for providing an electrical connection
CN101295633A (zh) * 2007-04-24 2008-10-29 中芯国际集成电路制造(上海)有限公司 金属-绝缘体-金属电容器及其制造方法
CN103762206A (zh) * 2014-01-07 2014-04-30 申宇慈 一种电子器件互连体

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08279570A (ja) * 1995-04-04 1996-10-22 Fujitsu Ltd 半導体装置
CN102208372B (zh) * 2011-05-19 2015-12-02 华进半导体封装先导技术研发中心有限公司 一种高密度导电通道基板及其制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050223553A1 (en) * 2004-03-31 2005-10-13 Loy Garry M Method for providing an electrical connection
CN101295633A (zh) * 2007-04-24 2008-10-29 中芯国际集成电路制造(上海)有限公司 金属-绝缘体-金属电容器及其制造方法
CN103762206A (zh) * 2014-01-07 2014-04-30 申宇慈 一种电子器件互连体

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