WO2015085690A1 - 显示装置、阵列基板及其制作方法 - Google Patents

显示装置、阵列基板及其制作方法 Download PDF

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Publication number
WO2015085690A1
WO2015085690A1 PCT/CN2014/075673 CN2014075673W WO2015085690A1 WO 2015085690 A1 WO2015085690 A1 WO 2015085690A1 CN 2014075673 W CN2014075673 W CN 2014075673W WO 2015085690 A1 WO2015085690 A1 WO 2015085690A1
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Prior art keywords
electrode layer
transparent electrode
layer
array substrate
strip
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Ceased
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PCT/CN2014/075673
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English (en)
French (fr)
Inventor
莫再隆
石天雷
朴承翊
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to US14/418,412 priority Critical patent/US9874791B2/en
Publication of WO2015085690A1 publication Critical patent/WO2015085690A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • G02F1/134309Electrodes characterised by their geometrical arrangement
    • G02F1/134363Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1335Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509Filters, e.g. light shielding masks
    • G02F1/133512Light shielding layers, e.g. black matrix
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1335Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509Filters, e.g. light shielding masks
    • G02F1/133514Colour filters
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1337Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • G02F1/13439Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Definitions

  • Embodiments of the present invention relate to a display device, and more particularly to an array substrate for a display device, a display device including the array substrate, and a method of fabricating the array substrate. Background technique
  • the display modes of the TFT-LCD include TN (Twist Nematic), VA (Vertical Align), and IPS (In Plane Switch).
  • TN Transmission Nematic
  • VA Very Align
  • IPS In Plane Switch
  • the transverse electric field) mode, etc., the latter two are the current mainstream wide viewing angle technology, which basically solves the problem that the TN mode has a narrow viewing angle and a gray scale inversion is serious.
  • a multi-dimensional electric field is formed by an electric field generated by the edge of the slit pixel electrode in the same plane and an electric field generated between the slit pixel electrode layer and the plate-like common electrode layer. All of the aligned liquid crystal molecules between the slit electrodes in the liquid crystal cell and directly above the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced high-dimensional field switching technology can improve the picture quality of TFT-LCD products.
  • TFT-LCD has high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no squeeze water ripple. Push Mura) and other advantages.
  • the size of the pixel becomes smaller and smaller, and the requirement for the pixel aperture ratio is also continuously increased, so the width of the black matrix is reduced as much as possible; and since the common electrode of the ADSDS product is generally made of indium tin oxide ITO (Indium Tin Oxides, indium tin oxide) is fabricated, in which the resistance of the IT0 is high. In order to reduce the RC delay and increase the storage capacitance, the area of the common electrode is increased as much as possible when designing the common electrode. Generally, the IT0 and the data line are completely Overlapping design.
  • ITO Indium Tin Oxides, indium tin oxide
  • the existing high-resolution ADSDS product includes an array substrate and a color filter substrate, and the array substrate includes a first layer IT0 as a common electrode 14' as a second layer IT0 of the pixel electrode 16', Insulation layer 15' between metal electrode 14' and pixel electrode 16' and metal
  • the data line 12', the color filter substrate comprises a plurality of black matrices 22', a plurality of sub-pixel units 23 / 232 ' and an organic flat layer 24', and each sub-pixel unit is generally divided into sub-pixels of three colors of red, green and blue.
  • a black matrix 22' is disposed between the sub-pixel units 23 and 232', and the black matrix 22 is located above the data line 12.
  • the organic flat layer 13', the black matrix 22', the sub-pixel units 23 and 232', and the organic flat layer 24 may be made of a resin material, and the insulating layer 15 ' Can be made of silicon nitride material.
  • the liquid crystal layer 3 is located between the array substrate and the color filter substrate. When there is no electric field, the liquid crystal molecules in the liquid crystal layer 3 are not deflected, and no light emitted from the display panel is black. When the data voltage is applied to the sub-pixels, the IT0 pixel electrode and the IT0 common electrode generate a fringe electric field 32', which is located at the fringe electric field 32.
  • the liquid crystal molecules in the active region of the ' deflected, and the incident backlight 11' forms an outgoing light 2 on one side of the color filter substrate after passing through the array substrate.
  • the width of the black matrix of the ADSDS product with high resolution is generally less than 6.0 m, the overlap width of the black matrix and the data line is small. If a slight shift occurs to one side of the black matrix when the color filter substrate and the array substrate are paired, the edge electric field range formed by the IT0 of the pixel electrode and the IT0 of the common electrode may be close to or even beyond the other side of the black matrix, that is, the liquid crystal layer The range of deflection will be close to or even beyond the other side of the black matrix.
  • the LCD displays the red, green, and blue screens separately, that is, the data voltage is applied to the first sub-pixel unit 23, and the adjacent sub-pixel unit 232' does not load the voltage, except for the outgoing light 2 of the first sub-pixel unit 23, There will be a slight exit light 25' on the side of the black matrix near the adjacent sub-pixel unit 232'. Therefore, the monochromatic outgoing light (such as red) of the first sub-pixel unit 23 and the outgoing monochromatic light (such as green) of the adjacent sub-pixel unit 232' may be mixed (such as yellow), and the problem is in the side view. The situation will be more serious. Summary of the invention
  • an array substrate to avoid sub-pixel color mixing due to a slight shift of the color filter substrate and the array substrate during the operation of the cartridge.
  • an array substrate including: a first transparent electrode layer, an insulating layer, and a second transparent electrode layer disposed in sequence along a light transmission direction, wherein the second transparent electrode layer includes a plurality of Strip electrodes arranged at intervals;
  • At least one of the facing edges of the two adjacent strip electrodes and the portion of the first transparent electrode layer corresponding to the gap formed between the two adjacent strip electrodes is formed at a convex portion protruding in the transport direction such that an edge electric field formed by an edge of each of the strip electrodes and the first transparent electrode layer is offset toward an edge side of the strip electrode.
  • a portion of the first transparent electrode layer corresponding to a gap formed between the two adjacent strip electrodes forms a first convex portion that protrudes in the transport direction.
  • the facing edges of the two adjacent strip electrodes form a second convex portion that protrudes in the transport direction.
  • the first transparent electrode layer is a common electrode layer
  • the second transparent electrode layer is a pixel electrode layer
  • the array substrate further includes an organic flat layer disposed under the first transparent electrode layer, and a position corresponding to each of the first convex portions on the organic flat layer forms a third convex portion.
  • a position corresponding to the second convex portion of each of the strip electrodes forms a fourth convex portion.
  • the cross-sectional profile of the first convex portion is triangular or parabolic.
  • the angle between the second convex portion of the strip electrode and the horizontal portion of the strip electrode is less than 90 degrees.
  • the width of the first convex portion is 3. ( ⁇ 6. 0 ⁇ ⁇ , and the height of the first convex portion is 2. ( ⁇ 4.0 ⁇ m).
  • a display device including: a color filter substrate including a plurality of black matrices and a plurality of sub-pixel units, each of the sub-pixel units being disposed on two corresponding blacks And the array substrate according to any one of the preceding embodiments, wherein a black matrix between each of the sub-pixel units corresponds to a position of a convex portion provided on the first transparent electrode layer in the array substrate.
  • a method for fabricating an array substrate including the following steps:
  • first transparent electrode layer Forming a first transparent electrode layer from the first conductive film layer by a patterning process; forming an insulating layer on the first transparent electrode layer;
  • the second transparent electrode layer Forming a second transparent electrode layer from the second conductive film layer by a patterning process, the second transparent electrode layer comprising a plurality of spaced strip electrodes
  • At least one of the facing edges of the two adjacent strip electrodes and the portion of the first transparent electrode layer corresponding to the gap formed between the two adjacent strip electrodes is formed at a convex portion that protrudes in the light transmission direction such that an edge electric field formed by an edge of each of the strip electrodes and the first transparent electrode layer is shifted toward an edge side of the strip electrode.
  • the step of forming the first transparent electrode layer from the first conductive thin film layer by a patterning process in the step of forming the first transparent electrode layer from the first conductive thin film layer by a patterning process: forming a plurality of first convex portions on the first transparent electrode layer; and In the step of forming the second transparent electrode layer from the second conductive thin film layer, a second convex portion is formed on an edge of each of the strip electrodes corresponding to one of the first convex portions.
  • the cross-sectional profile of the first raised portion is triangular or parabolic.
  • the angle between the second convex portion of the strip electrode and the horizontal portion of the strip electrode is less than 90 degrees.
  • the array substrate, the display device, and the method of fabricating the array substrate are formed by forming a portion corresponding to a gap formed between two adjacent strip electrodes of the first transparent electrode layer. a raised portion, and/or a facing edge of the two adjacent strip electrodes forming a second raised portion, the edge electric field formed by the strip electrode edge and the first transparent electrode layer being oriented toward the strip
  • the edge side of the electrode is offset, thereby effectively defining the range of the edge electric field of the sub-pixel, even if the color film substrate and the array substrate are slightly offset in the operation of the cassette, the adjacent sub-pixel is not The effect is affected, so the phenomenon of color mixing of two adjacent sub-pixels can be effectively avoided.
  • 1 is a schematic plan view showing an array substrate in the prior art
  • FIG. 2 is a schematic cross-sectional view showing an array substrate in the prior art
  • Figure 3 is a cross-sectional view showing the array substrate shown in Figure 2 due to an offset in the operation of the cartridge;
  • FIG. 4 is a cross-sectional view showing an array substrate according to an exemplary embodiment of the present invention.
  • Fig. 5 is a cross-sectional view showing the array substrate shown in Fig. 4 when an offset occurs in the operation of the cartridge. detailed description
  • an array substrate including: a first transparent electrode layer, an insulating layer, and a second transparent electrode layer disposed in sequence along a light transmission direction, wherein the second transparent electrode layer includes A plurality of strip electrodes arranged at intervals. Two adjacent strips At least one of the facing edges of the electrodes and the portion of the first transparent electrode layer corresponding to the gap formed between the two adjacent strip electrodes is formed to protrude in the transport direction a raised portion such that an edge electric field formed by an edge of each of the strip electrodes and the first transparent electrode layer is offset toward an edge side of the strip electrode.
  • An array substrate which corresponds to a facing edge formed between two adjacent strip electrodes and a gap formed between the two adjacent strip electrodes of the first transparent electrode layer At least one of the portions forms a convex portion that protrudes in the transport direction, so that an edge electric field formed by the strip electrode edge and the first transparent electrode layer is offset toward an edge side of the strip electrode, thereby effectively
  • the range of the electric field of the fringe of the sub-pixel is defined, and even if the color film substrate and the array substrate are slightly offset in the operation of the cassette, the adjacent sub-pixels are not affected, so that two phases can be effectively avoided.
  • the first transparent electrode layer may be a common electrode layer, and the second transparent electrode layer may be a pixel electrode layer.
  • a portion of the first transparent electrode layer corresponding to a gap formed between the two adjacent strip electrodes forms a first protrusion that protrudes in the transport direction.
  • the facing edges of the two adjacent strip electrodes form a second raised portion that protrudes in the transport direction.
  • the structure of the first convex portion formed on the common electrode may be formed in various manners.
  • the thickness at a predetermined position in the common electrode layer may be formed to be larger than other positions. a thickness of the upper portion to form a first convex portion at the predetermined position; or first forming a third convex portion on the organic flat layer below the first substrate under the common electrode layer, and then on the organic flat layer A common electrode layer is formed to form a first bump at a position where the common electrode layer corresponds to the third bump.
  • the structure of the second convex portion of the strip electrode in the pixel electrode can also be formed by the above method.
  • a third convex portion is formed at a position corresponding to each of the first convex portions of the organic flat layer located under the second transparent electrode layer, thereby The first raised portion functions as a support.
  • the strip electrode between the second transparent electrode layer and the first transparent electrode layer The corresponding position of the second protrusion forms a raised fourth protrusion, so that the second protrusion of the edge portion of the strip electrode can be correspondingly supported.
  • FIG. 4 is a schematic cross-sectional view showing an array substrate including a first substrate (not shown) sequentially disposed in a transport direction of the backlight 11, and an organic flat layer, according to an exemplary embodiment of the present invention. 13.
  • a color filter substrate is disposed on the array substrate, and a liquid crystal 31 is disposed between the array substrate and the color filter substrate.
  • the color filter substrate includes an organic flat layer 24 in contact with the liquid crystal 31, a black matrix 22 disposed on the organic flat layer 24, and sub-pixel units 231 and 232 disposed on the organic flat layer 24 and located on both sides of the black matrix. Further, the black matrix 22 is located above the data line 12 to cover the data line 12.
  • the strip electrode 16b is a pixel electrode corresponding to the sub-pixel unit 231
  • the strip electrode 16a is a pixel electrode corresponding to the sub-pixel unit 232
  • the common electrode layer 14 is located at the strip electrode 16a and Below the gap between 16b (i.e., below the black matrix 22), a first boss portion 14a that protrudes in the transport direction of the backlight 11 is disposed.
  • the edge of the strip electrode 16b corresponding to the first protrusion 14a is lifted upward in the transport direction of the backlight 11 and forms a second convex portion
  • the edge of the strip electrode 16a corresponding to the first bump 14a is in backlight
  • the transport direction of 11 is upwardly lifted and a second raised portion is formed such that the first raised portion 14a and the strip electrode 16b form a fringe electric field 32 of the sub-pixel unit 231, and the first bumps 14a and 16a form a sub-pixel 232 The fringe electric field 33.
  • the edge electric field 32 of the sub-pixel unit 231 and the edge electric field 33 of the sub-pixel unit 232 are different in direction, and the fringe electric fields 32 and 33 are bounded by the boundary line 19 passing through the first convex portion 14a.
  • the black matrix 22 above the pixel electrode layer 16 is shifted toward the side where the sub-pixel unit 231 is located, and the first of the common electrode layer 14 is
  • the surface of the convex portion 14a is divided into two directions, and the second convex portion of the edge portion of the strip electrode 16b in the sub-pixel unit 231 also has a certain direction.
  • the fringe electric field 32 of the sub-pixel unit 231 When the data voltage is applied to the sub-pixel unit 231, the fringe electric field 32 of the sub-pixel unit 231 The range of action does not exceed the boundary line 19 passing through the first raised portion 17a, and since the boundary line 19 is still below the black matrix 22, the fringe electric field 32 of the sub-pixel unit 231 does not affect the adjacent sub-pixel unit 232.
  • the liquid crystal 31 in the region of the adjacent sub-pixel unit 232 can be effectively prevented from being deflected, so that the backlight 11 can only pass through the sub-pixel unit 231 and emit the emitted light 21, so that the backlight 11 can not pass through the sub-pixel unit 232.
  • the phenomenon of color mixing between the sub-pixel unit 231 and the sub-pixel unit 232 is avoided.
  • an organic flat layer 13 is disposed under the common electrode layer 14, and a position corresponding to the first convex portion 14a on the organic flat layer 13 is provided with a third convex portion 17, S, A projection 14a covers the third projection 17, so that the third projection 17 supports the first projection 14a.
  • an insulating layer 15 is provided between the common electrode layer 14 and the pixel electrode layer 16, and the insulating layer 15 is at an edge portion of the second protrusion which is lifted upward with the formation of the strip electrodes 16a and 16b
  • the corresponding positions are all tilted up to form a fourth protrusion.
  • the position 18 corresponding to the edge portion of the upwardly lifted second protrusion of the strip electrode 16a in the insulating layer 15 may be set to be lifted upward in the transport direction of the backlight 11. To form a fourth protrusion.
  • the cross-sectional profile of the first convex portion may be triangular or parabolic, and preferably may be an isosceles triangle.
  • the width of the first raised portion may be 3. ( ⁇ 6. 0 ⁇ m, and the height may be 2. ( ⁇ 4.0 ⁇ m).
  • the pixel electrode layer 16 may have a thickness of 500 A, and the insulating layer 15 may be made of a silicon nitride material and may have a thickness of 2000 A.
  • the angle between the upwardly raised edge portion of the strip electrode (ie, the second raised portion) and the horizontal portion of the strip electrode may be less than 90 degrees, and the width of the upwardly raised edge portion may be 2. ( ⁇ 3. 0 ⁇ ⁇ , the height at which the edge portion is lifted up may be 2. ( ⁇ 3. 0 ⁇ ⁇ .
  • the thickness of the common electrode layer 14 may be 700 ⁇ , and the organic flat layer 13 on the first substrate may be made of a resin material, thickness Can be 2. 0um.
  • the first convex portion is formed by a portion of the common electrode layer corresponding to the gap formed between the two adjacent strip electrodes, and/or Forming a facing edge of the two adjacent strip electrodes with a second raised portion corresponding to the first raised portion and having an upwardly lifted shape, thereby forming the strip electrode edge and the common electrode layer
  • the edge electric field is shifted toward the edge side of the strip electrode, and the range of the electric field of the sub-pixel edge can be effectively defined, even if the color film substrate and the array substrate are slightly offset in the operation of the cassette, It affects adjacent sub-pixels, so it can effectively reduce the risk of color mixing between two adjacent sub-pixel units.
  • the present invention further provides a display device comprising a color filter substrate and the array substrate according to any of the above embodiments, the color film substrate comprising an organic flat layer 24, and a plurality of black matrices disposed on the organic flat layer 24. And a plurality of sub-pixel units, each of the sub-pixel units being disposed between the corresponding two black matrices.
  • a black matrix between each of the sub-pixel units corresponds to a position of a convex portion provided on the first transparent electrode layer in the array substrate.
  • the display device can be: any product or component having a display function such as a liquid crystal panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a method for fabricating an array substrate including the following steps:
  • first conductive thin film layer on the substrate; forming a first transparent electrode layer from the first conductive thin film layer by a patterning process; forming an insulating layer on the first transparent electrode layer; depositing a second conductive thin film on the insulating layer And forming a second transparent electrode layer from the second conductive film layer by a patterning process, the second transparent electrode layer comprising a plurality of spaced strip electrodes.
  • At least one of the facing edges of two adjacent strip electrodes and a portion of the first transparent electrode layer corresponding to a gap formed between the two adjacent strip electrodes is formed in the light a convex portion protruding in the transport direction such that an edge electric field formed by an edge of each of the strip electrodes and the first transparent electrode layer is shifted toward an edge side of the strip electrode
  • a method of fabricating an array substrate according to the present invention in the step of forming a first transparent electrode layer from the first conductive thin film layer by a patterning process: forming a plurality of first raised portions on the first transparent electrode layer Forming the second conductive film layer by a patterning process In the step of the two transparent electrode layers, a second convex portion is formed on an edge of each of the strip electrodes corresponding to one of the first convex portions.
  • a first conductive thin film layer is deposited on the substrate as the first transparent electrode layer, and the first transparent electrode layer is provided with a first convex portion at a position below the gap between the strip electrodes to be formed.
  • the first bump covers the third boss.
  • a first conductive thin film layer is deposited on the substrate as a first transparent electrode layer, and the first transparent electrode layer is first formed at a position below a gap between strip electrodes to be formed. a raised portion; a first insulating film layer is deposited on the substrate as an organic flat layer, the organic flat layer is located under the first transparent electrode layer, and the organic flat layer is formed on the organic flat layer A plurality of third protrusions are formed, each of the third protrusions corresponding to each of the first protrusion positions to support the first protrusion.
  • a fourth convex portion is formed on the insulating layer, and the position of the fourth convex portion Corresponding to the position of the second raised portion of each of the strip electrodes.
  • a first conductive thin film layer is deposited on the substrate as a first transparent electrode layer, and the first transparent electrode layer is formed at a position below a gap between strip electrodes to be formed. a convex portion; after forming the first protruding portion, depositing a second insulating film layer on the substrate on which the first conductive thin film layer for forming the first transparent electrode layer is completed to be deposited as the second transparent electrode layer
  • An insulating layer between the first transparent electrode layers wherein the insulating layer is provided with a plurality of raised portions to form a fourth raised portion, and each of the raised portions and each of the strip electrodes are upward The raised edge portion corresponds.
  • the cross-sectional profile of the first raised portion is triangular or parabolic.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
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  • Liquid Crystal (AREA)

Abstract

一种显示装置、阵列基板及其制作方法。在阵列基板中沿光传输方向依次设置第一透明电极层(14)、绝缘层(15)和第二透明电极层(16)。第二透明电极层(16)包括多个间隔设置的条状电极(16a,16b)。两个相邻条状电极(16a,16b)的相面对的边缘、以及第一透明电极层(14)的与两个相邻条状电极(16a,16b)之间形成的间隙相对应的部位中的至少一个形成在光传输方向上凸出的凸起部(14a,17a,17),以使各条状电极(16a,16b)的边缘与第一透明电极层(14)形成的边缘电场(33)向条状电极(16a,16b)的边缘侧偏移。从而有效的限定亚像素单元的边缘电场作用范围,有效降低两个相邻的亚像素混色的风险。

Description

显示装置、 阵列基板及其制作方法 技术领域
本发明的实施例涉及一种显示装置, 尤其涉及一种用于显示装置 的阵列基板、 包括这种阵列基板的显示装置及阵列基板的制作方法。 背景技术
TFT-LCD ( Thin Film Transistor-Liquid Crystal Display , 薄 膜场效应晶体管-液晶显示器)的显示模式主要包括 TN (Twist Nematic, 旋转向列)、 VA (Vertical Align, 垂直取向)、 IPS (In Plane Switch, 横向电场)模式等, 其中后两者为目前主流的宽视角技术, 基本解决了 TN模式视角较窄和灰阶反转严重的问题。
基于 ADSDS (Advanced Super Dimension Switch,高级超维场转换 技术)技术, 通过在同一平面内狭缝像素电极边缘所产生的电场以及狭 缝像素电极层与板状公共电极层间产生的电场形成多维电场, 使液晶 盒内狭缝电极间、 电极正上方的所有取向液晶分子都能够产生旋转, 从而提高了液晶工作效率并增大了透光效率。 采用高级超维场开关技 术可以提高 TFT-LCD产品的画面品质, TFT-LCD具有高分辨率、 高透过 率、低功耗、 宽视角、高开口率、低色差、无挤压水波纹(Push Mura) 等优点。
随着产品分辨率的不断提高, 像素的尺寸越来越小, 对于像素开 口率的要求也不断提高, 所以黑矩阵宽度尽可能减小; 同时由于 ADSDS 产品的公共电极一般由铟锡氧化物 ITO ( Indium Tin Oxides, 铟锡氧 化物) 制作, 其中 IT0电阻较高, 为了减小 RC 延迟并增加存储电容, 在设计公共电极时会尽可能增加公共电极的面积, 一般地 IT0和数据线 会完全重叠设计。
如图 1和图 2所示, 现有高分辨率的 ADSDS产品包括阵列基板和彩膜 基板,阵列基板包括作为公共电极 14'的第一层 IT0,作为像素电极 16' 的第二层 IT0、 公共电极 14' 和像素电极 16' 之间的绝缘层 15' 和金属 数据线 12',彩膜基板包括多个黑矩阵 22 '、多个亚像素单元 23 /232 ' 和有机平坦层 24', 各亚像素单元通常分为红、 绿和蓝三种颜色的亚像 素单元, 各亚像素单元 23 和 232 ' 之间设置有黑矩阵 22', 且黑矩阵 22, 位于数据线 12, 上方。
图 2为图 1所示产品 A-B方向的截面示意图,其中,有机平坦层 13'、 黑矩阵 22 '、 亚像素单元 23 和 232 '、 有机平坦层 24, 均可以采用树 脂材料制作, 绝缘层 15 ' 可以采用氮化硅材料制作。 液晶层 3 位于 阵列基板和彩膜基板中间。 无电场作用时, 液晶层 3 中的液晶分子 无偏转, 显示面板无出射光呈黑态; 当对亚像素加载数据电压时, IT0 像素电极和 IT0公共电极产生边缘电场 32 ', 位于边缘电场 32 ' 的作用 区域内的液晶分子会发生偏转, 入射背光 11 ' 在通过阵列基板之后, 在彩膜基板的一侧形成出射光 2 。
如图 3所示, 由于具有高分辨率的 ADSDS产品的黑矩阵的宽度一般 都小于 6. 0 m, 黑矩阵和数据线的重叠宽度较小。 如果在彩膜基板和 阵列基板对盒时向黑矩阵的一侧发生轻微偏移时, 像素电极的 IT0和公 共电极的 IT0形成的边缘电场范围会接近甚至超出黑矩阵另一侧, 即液 晶层偏转的范围会接近甚至超出黑矩阵另一侧。当 LCD单独显示红、绿、 蓝画面, 即对第一个亚像素单元 23 加载数据电压, 相邻亚像素单元 232' 不加载电压, 则除第一个亚像素单元 23 的出射光 2 以外, 在靠近相邻亚像素单元 232 ' 的黑矩阵一侧会有较轻微的出射光 25 '。 因此, 会导致第一个亚像素单元 23 的单色出射光 (如红) 与相邻 亚像素单元 232' 的出射单色光 (如绿) 发生混色 (如黄色), 且该问 题在侧视角情况下会更加严重。 发明内容
针对现有技术中存在的上述以及其它技术问题, 本发明提供一种 阵列基板, 以避免由于彩膜基板和阵列基板在对盒操作时由于发生轻 微偏移而造成的亚像素混色的现象。 根据本发明的一个方面的实施例, 提供一种阵列基板, 包括: 沿 光传输方向依次设置的第一透明电极层、 绝缘层和第二透明电极层, 所述第二透明电极层包括多个间隔设置的条状电极;
其中, 两个相邻条状电极的相面对的边缘、 以及所述第一透明电 极层的与所述两个相邻条状电极之间形成的间隙相对应的部位中的至 少一个形成在所述传输方向上凸出的凸起部, 以使各所述条状电极的 边缘与所述第一透明电极层形成的边缘电场向所述条状电极的边缘侧 偏移。
在上述阵列基板中, 所述第一透明电极层的与所述两个相邻条状 电极之间形成的间隙相对应的部位形成在所述传输方向上凸出的第一 凸起部。
在上述阵列基板中, 所述两个相邻条状电极的相面对的边缘形成 在所述传输方向上凸出的第二凸起部。
在上述阵列基板中, 所述第一透明电极层为公共电极层, 所述第 二透明电极层为像素电极层。
上述阵列基板还包括设置于所述第一透明电极层下方的有机平坦 层, 所述有机平坦层上与每个所述第一凸起部相对应的位置均形成第 三凸起部。
在上述阵列基板中, 所述绝缘层的与每个所述条状电极的第二凸 起部对应的位置形成第四凸起部。
在上述阵列基板中, 所述第一凸起部的截面轮廓呈三角形或抛物 线形。
在上述阵列基板中, 所述条状电极的第二凸起部与所述条状电极 的水平部分之间的角度小于 90度。
在上述阵列基板中, 所述第一凸起部的宽度为 3. (Γ6. 0 μ ιη, 所述 第一凸起部的高度为 2. (Γ4. 0 μ m。
在上述阵列基板中,所述条状电极的第二凸起部的宽度为 2. (Γ3. 0 u m, 所述第二凸起部的高度为 2. (Γ3. 0 μ ηι。 根据本发明进一歩方面的实施例, 提供一种显示装置, 包括: 彩 膜基板, 包括多个黑矩阵和多个亚像素单元, 每个所述亚像素单元设 置于相应的两个所述黑矩阵之间; 以及上述任一实施例所述的阵列基 板, 各所述亚像素单元之间的黑矩阵与所述阵列基板中的第一透明电 极层上设置的凸起部的位置相对应。
根据本发明更进一歩方面的实施例, 提供一种阵列基板的制作方 法, 包括如下歩骤:
在基板上沉积第一导电薄膜层;
通过构图工艺由所述第一导电薄膜层形成第一透明电极层; 在第一透明电极层上形成绝缘层;
在所述绝缘层上沉积第二导电薄膜层; 以及
通过构图工艺由所述第二导电薄膜层形成第二透明电极层, 所述 第二透明电极层包括多个间隔设置的条状电极,
其中, 两个相邻条状电极的相面对的边缘、 以及所述第一透明电 极层的与所述两个相邻条状电极之间形成的间隙相对应的部位中的至 少一个形成在光的传输方向上凸出的凸起部, 以使各所述条状电极的 边缘与所述第一透明电极层形成的边缘电场向所述条状电极的边缘侧 偏移。
在上述方法中, 在通过构图工艺由所述第一导电薄膜层形成第一 透明电极层的歩骤中: 在所述第一透明电极层上形成多个第一凸起部; 以及在通过构图工艺由所述第二导电薄膜层形成第二透明电极层的歩 骤中, 在每个所述条状电极的与一个所述第一凸起部对应的边缘上形 成第二凸起部。
在上述方法中, 在执行在基板上沉积第一导电薄膜层的歩骤之前, 在基板上沉积有机平坦层, 在所述有机平坦层上形成第三凸起部, 所 条状电极的第二凸起部的位置对应。
在上述方法中, 所述第一凸起部的截面轮廓呈三角形或抛物线形。 在上述方法中, 所述条状电极的第二凸起部与所述条状电极的水 平部分之间的角度小于 90度。
根据本发明的上述各种实施例所述的阵列基板、 显示装置和阵列 基板的制作方法, 通过在第一透明电极层的与两相邻条状电极之间形 成的间隙相对应的部位形成第一凸起部, 和 /或将两个相邻条状电极的 相面对的边缘形成第二凸起部, 可以使该条状电极边缘与第一透明电 极层形成的边缘电场向该条状电极的边缘侧偏移, 从而有效地限定亚 像素的边缘电场的作用范围, 即使在彩膜基板和阵列基板在对盒操作 中发生轻微偏移的情况下, 也不会对相邻的亚像素造成影响, 因此可 以有效避免两个相邻的亚像素混色的现象。 附图说明
图 1是示出现有技术中的一种阵列基板的原理俯视图;
图 2是示出现有技术中的一种阵列基板的截面示意图;
图 3是示出图 2所示的阵列基板由于在对盒操作中发生偏移时的截 面示意图;
图 4是示出根据本发明的一种示例性实施例的一种阵列基板的截 面示意图; 以及
图 5是示出图 4所示的阵列基板在对盒操作中发生偏移时的截面示 意图。 具体实施方式
下面结合附图和实施例, 对本发明的具体实施方式作进一歩详细 描述。 以下实施例用于说明本发明, 但不用来限制本发明的范围。
根据本发明的总体上的发明构思, 提供了一种阵列基板, 包括: 沿 光传输方向依次设置的第一透明电极层、 绝缘层和第二透明电极层, 所述第二透明电极层, 包括多个间隔设置的条状电极。 两个相邻条状 电极的相面对的边缘、 以及所述第一透明电极层的与所述两个相邻条 状电极之间形成的间隙相对应的部位中的至少一个形成在所述传输方 向上凸出的凸起部, 以使各所述条状电极的边缘与所述第一透明电极 层形成的边缘电场向所述条状电极的边缘侧偏移。
根据本发明的阵列基板, 通过在两个相邻条状电极的相面对的边 缘、 以及所述第一透明电极层的与所述两个相邻条状电极之间形成的 间隙相对应的部位中的至少一个形成在所述传输方向上凸出的凸起部, 可以使该条状电极边缘与第一透明电极层形成的边缘电场向该条状电 极的边缘侧偏移, 从而有效地限定亚像素的边缘电场的作用范围, 即 使在彩膜基板和阵列基板在对盒操作中发生轻微偏移的情况下, 也不 会对相邻的亚像素造成影响, 因此可以有效避免两个相邻的亚像素混 色的现象。
其中, 所述第一透明电极层可以为公共电极层, 所述第二透明电极 层可以为像素电极层。 所述第一透明电极层的与所述两个相邻条状电 极之间形成的间隙相对应的部位形成在所述传输方向上凸出的第一凸 起部。 所述两个相邻条状电极的相面对的边缘形成在所述传输方向上 凸出的第二凸起部。
具体地, 形成在公共电极上的上述第一凸起部的结构可以采用多 种方式形成, 例如, 在形成公共电极层时, 可以将公共电极层中预设 位置上的厚度形成为大于其他位置上的厚度, 以便在该预设位置上形 成第一凸起部; 或者是首先在位于公共电极层下方、 第一基板上方的 有机平坦层上形成第三凸起部, 而后在有机平坦层上形成公共电极层, 以便在公共电极层与第三凸起对应的位置上形成第一凸起。 同理, 像 素电极中条状电极的第二凸起部的结构也可以通过上述方法形成。
根据本发明的示例性实施例的阵列基板, 在位于所述第二透明电 极层下方的有机平坦层的与每个所述第一凸起部相对应的位置均形成 第三凸起部, 从而对该第一凸起部起到支撑的作用。 所述第二透明电 极层与所述第一透明电极层之间的所述绝缘层的与每个所述条状电极 的第二突起部对应的位置形成翘起的第四凸起部, 从而能够对条状电 极的边缘部分的第二突起部起到相应的支撑作用。
图 4是示出根据本发明的一种示例性实施例的一种阵列基板的截 面示意图, 所述阵列基板包括沿背光 11的传输方向依次设置的第一基 板 (未示出)、 有机平坦层 13、 公共电极层 14、 绝缘层 15和像素电极 层 16, 像素电极层 16包括多个(图 4中示出了两个)间隔设置的条状 电极 16a和 16b。
该阵列基板上设置有彩膜基板, 在阵列基板和彩膜基板之间设置 液晶 31。 该彩膜基板包括与液晶 31接触的有机平坦层 24、 设置在有 机平坦层 24上的黑矩阵 22、 以及设置在有机平坦层 24上并位于黑矩 阵两侧的亚像素单元 231和 232。 进一歩地, 黑矩阵 22位于数据线 12 上方以覆盖数据线 12。 在一种示例性实施例中, 条状电极 16b为亚像 素单元 231对应的像素电极, 条状电极 16a为亚像素单元 232对应的 像素电极, 公共电极层 14在位于形成在条状电极 16a和 16b之间的间 隙下方 (即黑矩阵 22的下方) 设置有在背光 11的传输方向上凸出的 第一凸起部 14a。进一歩地, 条状电极 16b与第一凸起 14a对应的边缘 在背光 11的传输方向上向上翘起并形成第二凸起部, 条状电极 16a与 第一凸起 14a对应的边缘在背光 11的传输方向上向上翘起并形成第二 凸起部, 以便第一凸起部 14a与条状电极 16b形成亚像素单元 231的 边缘电场 32, 第一凸起 14a与 16a形成亚像素 232的边缘电场 33。 如 图 4所示, 该亚像素单元 231的边缘电场 32和亚像素单元 232的边缘 电场 33的方向不相同, 并且边缘电场 32和 33以经过第一凸起部 14a 的分界线 19为界限。
参见图 5, 当彩膜基板和阵列基板在对盒操作中发生轻微偏移时, 使得像素电极层 16上方的黑矩阵 22向亚像素单元 231所在一侧偏移, 公共电极层 14的第一凸起部 14a的表面分为两个方向, 同时亚像素单 元 231中的条状电极 16b的边缘部分的第二凸起部也具有一定方向。 当对亚像素单元 231加载数据电压时, 亚像素单元 231的边缘电场 32 的作用范围未超出经过第一凸起部 17a的分界线 19, 且由于分界线 19 仍位于黑矩阵 22的下方, 因此, 亚像素单元 231的边缘电场 32未影 响到相邻的亚像素单元 232,可以有效防止相邻的亚像素单元 232区域 内的液晶 31发生偏转, 从而使背光 11只能透过亚像素单元 231并发 出出射光 21, 而不能使背光 11透过亚像素单元 232, 进而避免了亚像 素单元 231和亚像素单元 232之间混色的现象。
参见图 4, 在该阵列基板中, 公共电极层 14下方设置有机平坦层 13, 该有机平坦层 13上与第一凸起部 14a相对应的位置设置有第三凸 起部 17, S , 第一突起部 14a覆盖在第三突起部 17上, 这样第三突起 部 17对该第一凸起部 14a起到支撑作用。
此外, 在该阵列基板中, 公共电极层 14和像素电极层 16之间设 置有绝缘层 15,该绝缘层 15在与条状电极 16a和 16b的形成向上翘起 的第二突起部的边缘部分对应的位置均向上翘起, 以形成第四突起部。 例如, 在亚像素单元 232中, 可以将绝缘层 15中与条状电极 16a的向 上翘起的第二突起部的边缘部分对应的位置 18设置为在背光 11的传 输方向上向上翘起的状态, 以形成在第四突起部。
根据本发明的一种示例性实施例的阵列基板, 该第一凸起部的截 面轮廓可以呈三角形或抛物线形, 优选地, 可以为等腰三角形。 该第 一凸起部的宽度可以为 3. (Γ6. 0 μ m, 高度可以为 2. (Γ4. 0 μ m。
根据本发明的一种示例性实施例的阵列基板, 像素电极层 16的厚 度可以为 500 A,绝缘层 15可以采用氮化硅材料制作,厚度可以为 2000 A。 条状电极的向上翘起的边缘部分(即第二凸起部) 与条状电极的水 平部分之间的角度可以小于 90度, 其向上翘起的边缘部分的宽度可以 为 2. (Γ3. 0 μ ηι, 边缘部分向上翘起的高度可以为 2. (Γ3. 0 μ ηι。 公共电 极层 14的厚度可以为 700 Α, 位于第一基板上的有机平坦层 13可以采 用树脂材料制作, 厚度可以为 2. 0um。
根据本发明的实施例的阵列基板, 通过在公共电极层的与位于两 个相邻条状电极之间形成的间隙相对应的部位形成第一凸起部, 和 /或 将两个相邻条状电极的相面对的边缘形成与第一凸起部对应的、 具有 向上翘起的形状的第二凸起部, 从而使该条状电极边缘与公共电极层 形成的边缘电场向该条状电极的边缘侧偏移, 可以有效地限定亚像素 的边缘电场的作用范围, 即使在彩膜基板和阵列基板在对盒操作中发 生轻微偏移的情况下, 也不会对相邻的亚像素造成影响, 因此可以有 效降低两个相邻的亚像素单元混色的风险。
此外, 本发明还提供一种显示装置, 包括彩膜基板和上述任意实 施例所述的阵列基板, 所述彩膜基板包括有机平坦层 24、 以及设置在 有机平坦层 24上的多个黑矩阵和多个亚像素单元, 每个所述亚像素单 元设置于相应的两个黑矩阵之间。 各所述亚像素单元之间的黑矩阵与 所述阵列基板中的第一透明电极层上设置的凸起部的位置相对应。
该显示装置可以为: 液晶面板、 手机、 平板电脑、 电视机、 显示 器、 笔记本电脑、 数码相框、 导航仪等任何具有显示功能的产品或部 件。
此外, 根据本发明的另一方面的实施例, 还提供一种阵列基板的 制作方法, 包括如下歩骤:
在基板上沉积第一导电薄膜层; 通过构图工艺由所述第一导电薄 膜层形成第一透明电极层; 在第一透明电极层上形成绝缘层; 在所述 绝缘层上沉积第二导电薄膜层; 以及通过构图工艺由所述第二导电薄 膜层形成第二透明电极层, 所述第二透明电极层包括多个间隔设置的 条状电极。 两个相邻条状电极的相面对的边缘、 以及所述第一透明电 极层的与所述两个相邻条状电极之间形成的间隙相对应的部位中的至 少一个形成在光的传输方向上凸出的凸起部, 以使各所述条状电极的 边缘与所述第一透明电极层形成的边缘电场向所述条状电极的边缘侧 偏移
根据本发明的制作阵列基板的方法, 在通过构图工艺由所述第一 导电薄膜层形成第一透明电极层的歩骤中: 在所述第一透明电极层上 形成多个第一凸起部; 在通过构图工艺由所述第二导电薄膜层形成第 二透明电极层的歩骤中, 在每个所述条状电极的与一个所述第一凸起 部对应的边缘上形成第二凸起部。
具体而言, 在基板上沉积第一导电薄膜层以作为第一透明电极层, 且所述第一透明电极层在待形成的各条状电极之间的间隙下方的位置 均设置有第一凸起部; 在完成前述歩骤的基板上沉积第二导电薄膜层, 通过构图工艺形成包括每个所述条状电极的图形, 且每个所述条状电 极在与各所述第一凸起部对应的边缘向上翘起, 以形成第二凸起部。
进一歩地, 在执行在基板上沉积第一导电薄膜层的歩骤之前, 在 所述基板上沉积有机平坦层, 在所述有机平坦层上形成第三凸起部, 所述第一凸起部覆盖在所述第三凸起部上。
具体而言, 在所述基板上沉积第一导电薄膜层以作为第一透明电 极层, 且所述第一透明电极层在待形成的各条状电极之间的间隙下方 的位置均形成第一凸起部; 在形成第一突起部之前, 在基板上沉积第 一绝缘薄膜层以作为有机平坦层, 所述有机平坦层位于所述第一透明 电极层的下方, 且所述有机平坦层上形成多个第三凸起部, 各所述第 三凸起与各所述第一凸起位置相对应, 以支撑第一凸起部。
在本发明的阵列基板的制作方法中, 在执行在第一透明电极层上 形成绝缘层的歩骤中, 在所述绝缘层上形成第四凸起部, 所述第四凸 起部的位置与每个所述条状电极的第二凸起部的位置对应。
具体而言, 在所述基板上沉积第一导电薄膜层以作为第一透明电 极层, 且所述第一透明电极层在待形成的各条状电极之间的间隙下方 的位置均形成有第一凸起部; 在形成第一突起部之后, 在完成沉积用 于形成第一透明电极层的第一导电薄膜层的基板上沉积第二绝缘薄膜 层以作为位于所述第二透明电极层与所述第一透明电极层之间的绝缘 层, 且所述绝缘层上设置有多个翘起部分, 以形成第四凸起部, 各所 述翘起部分与各所述条状电极的向上翘起的边缘部分对应。
所述第一凸起部的截面轮廓呈三角形或抛物线形。
所述条状像电极的向上翘起的边缘部分所形成的第二凸起部与所 述条状电极的水平部分之间的角度小于 90度。
以上实施方式仅用于说明本发明, 而并非对本发明的限制, 有关 技术领域的普通技术人员, 在不脱离本发明的精神和范围的情况下, 还可以做出各种变化和变型, 因此所有等同的技术方案也属于本发明 的范畴, 本发明的专利保护范围应由权利要求限定。

Claims

权 利 要 求 书
1、 一种阵列基板, 包括: 沿光传输方向依次设置的第一透明电极 层、 绝缘层和第二透明电极层, 所述第二透明电极层包括多个间隔设 置的条状电极;
其中, 两个相邻条状电极的相面对的边缘、 以及所述第一透明电 极层的与所述两个相邻条状电极之间形成的间隙相对应的部位中的至 少一个形成在所述传输方向上凸出的凸起部, 以使各所述条状电极的 边缘与所述第一透明电极层形成的边缘电场向所述条状电极的边缘侧 偏移。
2、 根据权利要求 1所述的阵列基板, 其中, 所述第一透明电极层 的与所述两个相邻条状电极之间形成的间隙相对应的部位形成在所述 传输方向上凸出的第一凸起部。
3、 根据权利要求 1所述的阵列基板, 其中, 所述两个相邻条状电 极的相面对的边缘形成在所述传输方向上凸出的第二凸起部。
4、 根据权利要求 1-3中的任一项所述的阵列基板, 其中, 所述第 一透明电极层为公共电极层, 所述第二透明电极层为像素电极层。
5、 根据前述权利要求中的任一项所述的阵列基板, 还包括设置于 所述第一透明电极层下方的有机平坦层, 所述有机平坦层上与每个所 述第一凸起部相对应的位置均形成第三凸起部。
6、 根据前述权利要求中的任一项所述的阵列基板, 其中, 所述绝 缘层的与每个所述条状电极的第二凸起部对应的位置形成第四凸起部。
7、 根据权利要求 2所述的阵列基板, 其中, 所述第一凸起部的截 面轮廓呈三角形或抛物线形。
8、 根据权利要求 3所述的阵列基板, 其中, 所述条状电极的第二 凸起部与所述条状电极的水平部分之间的角度小于 90度。
9、 根据权利要求 2所述的阵列基板, 其特征在于, 所述第一凸起 部的宽度为 3. (Γ6. 0 μ m, 所述第一凸起部的高度为 2. (Γ4. 0 μ m。
10、 根据权利要求 3所述的阵列基板, 其特征在于, 所述条状电 极的第二凸起部的宽度为 2. (Γ3. 0 μ ιη, 所述第二凸起部的高度为 2. 0〜3. 0 μ m。
11、 一种显示装置, 包括:
彩膜基板, 包括多个黑矩阵和多个亚像素单元, 每个所述亚像素 单元设置于相应的两个所述黑矩阵之间; 以及
如权利要求 1-10中任一项所述的阵列基板, 各所述亚像素单元之 间的黑矩阵与所述阵列基板中的第一透明电极层上设置的凸起部的位 置相对应。
12、 一种阵列基板的制作方法, 包括如下歩骤:
在基板上沉积第一导电薄膜层;
通过构图工艺由所述第一导电薄膜层形成第一透明电极层; 在第一透明电极层上形成绝缘层;
在所述绝缘层上沉积第二导电薄膜层; 以及
通过构图工艺由所述第二导电薄膜层形成第二透明电极层, 所述 第二透明电极层包括多个间隔设置的条状电极,
其中, 两个相邻条状电极的相面对的边缘、 以及所述第一透明电 极层的与所述两个相邻条状电极之间形成的间隙相对应的部位中的至 少一个形成在光的传输方向上凸出的凸起部, 以使各所述条状电极的 边缘与所述第一透明电极层形成的边缘电场向所述条状电极的边缘侧 偏移。
13、 根据权利要求 12所述的方法, 其中, 在通过构图工艺由所述 第一导电薄膜层形成第一透明电极层的歩骤中:
在所述第一透明电极层上形成多个第一凸起部;
在通过构图工艺由所述第二导电薄膜层形成第二透明电极层的歩 骤中, 在每个所述条状电极的与一个所述第一凸起部对应的边缘上形 成第二凸起部。
14、 根据权利要求 13所述的方法, 其中, 在执行在基板上沉积第一导电薄膜层的歩骤之前, 在基板上沉积 有机平坦层, 在所述有机平坦层上形成第三凸起部, 所述第一凸起部 覆盖在所述第三突起部上。
15、 根据权利要求 13所述的方法, 其中, 在执行在第一透明电极 层上形成绝缘层的歩骤中, 在所述绝缘层上形成第四凸起部, 所述第 四凸起部的位置与每个所述条状电极的第二凸起部的位置对应。
16、 根据权利要求 13所述的方法, 其中, 所述第一凸起部的截面 轮廓呈三角形或抛物线形。
17、 根据权利要求 14所述的方法, 其中, 所述条状电极的第二凸 起部与所述条状电极的水平部分之间的角度小于 90度。
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