WO2015078141A1 - 非易失存储器及电子设备 - Google Patents

非易失存储器及电子设备 Download PDF

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Publication number
WO2015078141A1
WO2015078141A1 PCT/CN2014/076595 CN2014076595W WO2015078141A1 WO 2015078141 A1 WO2015078141 A1 WO 2015078141A1 CN 2014076595 W CN2014076595 W CN 2014076595W WO 2015078141 A1 WO2015078141 A1 WO 2015078141A1
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WIPO (PCT)
Prior art keywords
signal
decoder
switch
address sub
bank
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PCT/CN2014/076595
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English (en)
French (fr)
Inventor
李延松
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP14784396.5A priority Critical patent/EP2899639B1/en
Priority to US14/559,177 priority patent/US9424442B2/en
Publication of WO2015078141A1 publication Critical patent/WO2015078141A1/zh

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14Protection against unauthorised use of memory or access to memory
    • G06F12/1408Protection against unauthorised use of memory or access to memory by using cryptography
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20Employing a main memory using a specific memory technology
    • G06F2212/202Non-volatile memory
    • G06F2212/2024Rewritable memory not requiring erasing, e.g. resistive or ferroelectric RAM

Definitions

  • the present invention relates to data encryption techniques, and more particularly to non-volatile memories and electronic devices. Background technique
  • Non-volatile memory has non-volatile features that do not lose information after power-down, but when non-volatile memory is applied to certain scenes with high security requirements, non-volatile after power-down There is a risk of disclosure of information stored in the memory.
  • phase change memory in nonvolatile memory as an example.
  • a phase change memory is a nonvolatile memory that holds information by the different states of the phase change material.
  • the phase change material When the phase change material is in the crystalline state, the resistance is small, and when the phase change material is in the amorphous state, the resistance is large, and the corresponding data can be read by detecting the resistance of the phase change material.
  • the phase change memory has the advantages of fast reading and writing speed, wear resistance, low power consumption, high integration, etc. It is expected to gradually replace the flash memory, and may replace the dynamic random access memory (DRAM, Dynamic Random Access Memory) in the future. ) Used as an electronic device memory.
  • DRAM Dynamic Random Access Memory
  • the phase change memory is used as an electronic device memory
  • the original data transmitted may be encrypted and then transmitted, or the original data is encrypted and then saved to the hard disk
  • the application in the electronic device uses the encrypted data.
  • the original data is first decrypted and saved into the memory, so that the efficiency is improved when the original data is repeatedly used in the future, that is, the data in the memory is the original data, which is plaintext.
  • the electronic device is powered off, if someone pulls out the phase change memory as a memory stick and installs it on his own computer, using software tools to read and analyze the data in the phase change memory, the storage to the phase change memory can be obtained.
  • Raw data which may include sensitive information such as the user's sensitive information, resulting in poor security of the data stored in the phase change memory.
  • a nonvolatile memory and an electronic device are provided, which are capable of encrypting data stored in the nonvolatile memory and improving the security of data stored in the nonvolatile memory.
  • a nonvolatile memory including a bank decoder, and at least two bank banks, the bank including a memory array, a row decoder of a memory array, and a column decoder of the storage array, the nonvolatile memory further comprising: a random number generator, a first switch disposed between the first signal generator of the bank decoder and the first decoder, and a The first switch corresponds to a bank address sub-signal of the bank decoder; wherein
  • the random number generator is configured to randomly generate a selection signal for each first switch when the nonvolatile memory is powered on, and send the generated selection signal to the first switch corresponding to the selection signal.
  • the inverted signal of the bank address sub-signal is output to the first decoder; K; l ⁇ i 2 ⁇ im , l ⁇ n ⁇ im ,
  • the at least one bank further includes: a second exchange between the second signal generator and the second decoder disposed in the row decoder a second switch corresponding to a row address sub-signal of the row decoder;
  • the random number generator is further configured to: when the nonvolatile memory is powered on, separately generate a selection signal for each second switch, and send the generated selection signal to the second exchange corresponding to the selection signal.
  • the at least one bank further includes: n 3 firsts disposed between the third signal generator and the third decoder of the column decoder a third switch, a third switch corresponding to a column address sub-signal of the column decoder; wherein
  • the random number generator is further configured to: when the nonvolatile memory is powered on, separately generate a selection signal for each third switch, and send the generated selection signal to a third exchange corresponding to the selection signal.
  • Each of third bank of switches for the inverted signal of the k 2 th sub-signals receiving said column address of third switches corresponding to the first and the second column address k 2 th sub signal ; upon receiving the selection signal as a fifth signal, the column address k-2 outputs two signal sub-column address as a child of the first to third decoders k, the k-2 column address sub-signal inversion signal inverts the output signal of the column address of k 2 as the sub-signal to the third decoder; upon receiving the sixth signal as a selection signal, the second k 2 th inverted signal of the column address signal output sub-signal of the k 2 as the column addresses to the third sub-decoder, said first column address sub k 2 signal as the column address of k 2 sub-signals
  • the inverted signal is output to the third decoder; 1 1 ⁇ ⁇ 3 , lk 2 m 3 , l ⁇ n 3 ⁇ m 3 , m 3 is the column address
  • the at least one bank further includes: disposed between the third signal generator and the third decoder of the column decoder n 3 third switches, one third switch corresponding to a column address sub-signal of the column decoder;
  • the random number generator is further configured to: when the nonvolatile memory is powered on, separately generate a selection signal for each third switch, and send the generated selection signal to a third exchange corresponding to the selection signal.
  • each bank of a third switch for k 2 of the column addresses of the first sub-signal reception of third switches corresponding to k 2, and the second column address sub-signal phase signal; when the received selection signal to the fifth signal, said second column addresses k 2 sub-signals k 2 as the second column address signal is output to the third sub-decoder, the k-th inverted column address signals of the two sub-signals as an inverted signal of the k 2 output column address signals to the third sub-decoder; upon receiving the selection signal for the sixth signal, the k inverted column address signals of the two sub-signals k 2 as the second column address signal to a third sub-decoder, said first column address k 2 sub-signal as the second column address sub k 2
  • the inverted signal of the signal is output to the third decoder; 1 1 ⁇ 1 3 , lk 2 m 3 , l ⁇ n 3 ⁇ m 3 , m 3 is the column of the column decoder of
  • the random number generator includes: at least a bit linear feedback shift register, any two bits of the linear feedback shift register a signal obtained by performing an exclusive OR process as a shift input signal of the linear feedback shift register;
  • the first switches respectively correspond to one bit of the linear feedback shift register, and the corresponding bit is used as a selection signal sent by the random number generator.
  • the random number generator includes: a linear feedback shift register having at least one bit, the linear feedback shift a signal obtained by performing exclusive-OR processing on any two bits of the register as a shift input signal of the linear feedback shift register is a total number of first switches and second switches included in the non-volatile memory;
  • each of the first switch and each of the second switches respectively correspond to one bit of the linear feedback shift register, and the corresponding bit is used as a selection signal sent by the random number generator .
  • the random number generator includes: a linear feedback shift register having at least N 2 bits, the linear feedback a signal obtained by XOR processing any two bits of the shift register as a shift input signal of the linear feedback shift register; N 2 is a first converter and a third converter included in the nonvolatile memory The total number of;
  • each of the first switch and each of the third switches respectively correspond to one bit of the linear feedback shift register, and the corresponding bit is used as a selection signal sent by the random number generator .
  • the random number generator includes: a linear feedback shift register having at least N 3 bits, the linear feedback a signal obtained by XOR processing any two bits of the shift register as a shift input signal of the linear feedback shift register; N 3 is a first converter, a second converter and the non-volatile memory The total number of third converters;
  • each of the first switch, each of the second switch, and each of the third switches respectively correspond to one bit of the linear feedback shift register, and the corresponding bit is taken as The selection signal sent by the random number generator.
  • a nonvolatile memory including at least one bank, each bank including a memory array, a row decoder of a memory array, and a bank array
  • the coder further includes: a random number generator, at least one of the banks further comprising: a second switch disposed between the second signal generator of the row decoder and the second decoder, and a second exchange Corresponding row decoding a row address sub-signal of the device;
  • the random number generator is configured to randomly generate a selection signal for each second switch when the nonvolatile memory is powered on, and send the generated selection signal to the second switch corresponding to the selection signal.
  • each bank of second switches for the j two sub row address signal of the second receiving switch and the j corresponding to two inverter sub row address signals signal; when the received selection signal to the third signal, the second sub j 2 row address signal j 2 as the second row address signal to the second sub-decoder, said first j 2 inverted signal of the row address signal output sub-signals inverted two sub row address signal to the j as a second decoder; when the received signal is a fourth selection signal, the second j 2 inverted signal of the row address signal sub j 2 as the second row address signal to the second sub-decoder, said first row address j 2 as the second sub-signal j 2 sub row address signals
  • the inverted signal is output to the second decoder; l ⁇ n ⁇ l ⁇ j 2 ⁇ m 2 , l ⁇ n 2 ⁇ m 2 , m 2 is the row decoder of the second second switch The total number of row address sub-signals.
  • the at least one of the banks further includes: n 3 disposed between the third signal generator and the third decoder of the column decoder a third switch, a third switch corresponding to a column address sub-signal of the column decoder;
  • the random number generator is further configured to: when the non-volatile memory is powered on, separately generate a selection signal for each third switch, and send the generated selection signal to a third exchange corresponding to the selection signal.
  • each bank of a third switch for k 2 of the column addresses of the first sub-signal reception of third switches corresponding to k 2, and the second column address sub-signal phase signal; when the received selection signal to the fifth signal, said second column addresses k 2 sub-signals k 2 as the second column address signal is output to the third sub-decoder, the k-th inverted column address signals of the two sub-signals as an inverted signal of the k 2 output column address signals to the third sub-decoder; upon receiving the selection signal for the sixth signal, the k inverted column address signals of the two sub-signals k 2 as the second column address signal to a third sub-decoder, said first column address k 2 sub-signal as the second column address sub k 2
  • the inverted signal of the signal is output to the third decoder; 1 1 ⁇ 1 3 , lk 2 m 3 , l ⁇ n 3 ⁇ m 3 , m 3 is the column of the column decoder of
  • the random number generator includes: a linear feedback shift register having at least N 4 bits, any of the linear feedback shift registers a signal obtained by performing XOR processing on two bits as a shift input signal of the linear feedback shift register; N 4 is a total number of second switches included in the nonvolatile memory;
  • each of the second switches respectively corresponds to a bit of the linear feedback shift register, The corresponding bit is used as a selection signal transmitted by the random number generator.
  • the random number generator includes: a linear feedback shift register having at least N 5 bits, the linear feedback a signal obtained by XOR processing any two bits of the shift register as a shift input signal of the linear feedback shift register; N 5 is a total of the second switch and the third switch included in the nonvolatile memory Number
  • each of the second switch and each of the third switches respectively correspond to one bit of the linear feedback shift register, and the corresponding bit is used as a selection signal sent by the random number generator .
  • a nonvolatile memory including at least one bank, each bank including a memory array, a row decoder of a memory array, and a bank array
  • the coder further includes: a random number generator, at least one of the banks further comprising: n 3 third switches disposed between the third signal generator of the column decoder and the third decoder, one a third switch corresponding to a column address sub-signal of the column decoder; wherein
  • the random number generator is configured to randomly generate a selection signal for each third switch when the nonvolatile memory is powered on, and send the generated selection signal to the third switch corresponding to the selection signal.
  • the random number generator includes: a linear feedback shift register having at least N 6 bits, any of the linear feedback shift registers a signal obtained by performing exclusive-OR processing on two bits as a shift input signal of the linear feedback shift register; N 6 is a total number of non-volatile memories including a third selector;
  • Each of the third switches respectively corresponds to one bit of the linear feedback shift register, and the corresponding bit is used as a selection signal transmitted by the random number generator.
  • an electronic device comprising the nonvolatile memory of any of the above.
  • the nonvolatile memory of this embodiment includes a bank decoder, and at least two bank banks, the bank including a memory array, a row decoder of the memory array, and a column decoder of the memory array, characteristics thereof
  • the nonvolatile memory further includes: a random number generator, a first switch disposed between the first signal generator of the bank decoder and the first decoder, and the first switch Corresponding to a bank address sub-signal of the bank decoder; wherein the random number generator is configured to randomly generate a selection signal for each first switch when the non-volatile memory is powered on, and the generated selection is signal to the selection signal corresponding to the first exchanger; ⁇ th first exchanger of the bank decoder for th i 2 of the second bank address received th ⁇ corresponding to the first exchanger and the second sub-signal i 2 th sub-bank address signal inverted
  • is the total number of bank address sub-signals. Therefore, in this embodiment, the random number generator generates a selection signal when the nonvolatile memory is powered on, and each of the first converters in the control bank decoder keeps the corresponding bank address sub-signal and its inverted signal unchanged or Interchange, when the non-volatile memory is powered off and then powered on, the random number generator generates randomness of the selection signal, so that when the non-volatile memory is powered off and then powered on, compared with before the non-volatile memory is powered off.
  • the bank strobe signal corresponding to the same bank address sub-signal is different, so that the data stored before the non-volatile memory is powered off is shuffled after the non-volatile memory is powered off, and the encryption effect is achieved, so that the storage is performed.
  • the data to the non-volatile memory cannot be read in the original storage address order, so that other people cannot obtain the original data even when using the software tool to directly read the stored data in the non-volatile memory, which is difficult to place in the non-volatile memory.
  • the stored data is restored to the original data, ensuring the security of the data stored in the non-volatile memory.
  • FIG. 1 is a schematic structural diagram of a prior art nonvolatile memory
  • FIG. 2 is a schematic structural diagram of a prior art 3-8 line address decoder
  • FIG. 2A is a schematic structural diagram of a switch according to an embodiment of the present invention.
  • 2B is a schematic structural diagram of a 3-8 line address decoder provided with a switch according to an embodiment of the present invention
  • 2C is a schematic structural diagram of a pseudo random sequence generator according to an embodiment of the present invention.
  • FIG. 3 is a block diagram showing an example structure of a first embodiment of a nonvolatile memory of the present invention
  • FIG. 3A is a structural diagram showing an example of a random number generator in a first embodiment of the nonvolatile memory of the present invention
  • FIG. 4 is a block diagram showing an example structure of a second embodiment of a nonvolatile memory of the present invention.
  • 4A is a structural diagram showing an example of a random number generator in a second embodiment of the nonvolatile memory of the present invention.
  • FIG. 5 is a block diagram showing an example structure of a third embodiment of a nonvolatile memory according to the present invention.
  • 5A is a structural diagram of an example of a random number generator in a third embodiment of the nonvolatile memory of the present invention.
  • FIG. 6 is a block diagram showing an example structure of a fourth embodiment of a nonvolatile memory according to the present invention.
  • 6A is a structural diagram showing an example of a random number generator in a fourth embodiment of the nonvolatile memory of the present invention.
  • FIG. 7 is a structural diagram of a fifth embodiment of a nonvolatile memory of the present invention.
  • FIG. 7A is another structural diagram of a fifth embodiment of the nonvolatile memory of the present invention. detailed description
  • FIG. 1 is a schematic structural diagram of a prior art nonvolatile memory, wherein the nonvolatile memory includes at least one bank, a bank decoder, and each bank includes a memory array, a row decoder of the memory array, and Column decoder; only one bank structure is shown in FIG. 1, and the structure of other banks is the same, and will not be described here.
  • the storage array is arranged in a matrix by a large number of storage units in rows and columns. Each row of memory cells has a row strobe signal. Each row of memory cells is selected by a row strobe signal; each column of memory cells has a column strobe signal, and a column of strobe signals is selected each time a column of memory cells is selected. Data written or read from the memory array is input and output from the bit line.
  • a bank decoder configured to generate a bank strobe signal according to a bank address signal input by a controller of the nonvolatile memory, and strobe a bank indicated by the bank address signal to perform reading of the strobed bank or Write access.
  • the bank decoder is set in the nonvolatile memory. If the nonvolatile memory includes only one bank, the bank decoder can be omitted.
  • a general bank address is composed of at least one binary code. When a bank address signal is generated according to a bank address, each binary code corresponds to an address sub-signal, so the bank address signal includes a binary code number of address sub-signals, such as a bank address. ⁇ [0: 1] indicates that the bank address includes 2 Address sub-signals. Subsequent row address signals and column address signals are similar, including a plurality of row address sub-signals and a plurality of column address sub-signals, respectively.
  • a row decoder of each bank configured to generate a row strobe signal according to a row address signal input by a controller of the nonvolatile memory, and strobe a row of the storage indicated by the row address signal from a storage array of the bank to which the bank belongs Unit for read or write access.
  • a column decoder of each bank configured to generate a column strobe signal according to a column address signal input by a controller of the nonvolatile memory, and strobe a column of storage indicated by the column address signal from a storage array of the bank Unit for read or write access.
  • a bank is selected by a bank decoder, and a row and a column of memory cells in the bank are respectively selected by the row decoder and the column decoder, so that a certain memory cell in a bank can be uniquely selected, thereby The strobe of the memory cell is realized, thereby implementing read and write access to the memory cell.
  • each bank may also include other structures such as control logic, write driver, and sense amplifier in practical applications, which is not limited by the embodiment of the present invention.
  • the control logic is generally used to control a write driver to write access to the memory array according to a chip select, read and write signal provided by a device external to the nonvolatile memory, such as a controller of the nonvolatile memory, or to control the sense amplifier to perform read access to the memory array.
  • the write driver is generally used to store the data to be written sent by the controller of the nonvolatile memory to the storage unit selected by the row decoder and the column decoder, and specifically, may be written to the storage according to
  • the data of the unit is 0 or 1 and the write pulse signal corresponding to the waveform is sent to the storage unit;
  • the sense amplifier is generally used to read the data stored by the storage unit selected by the row decoder and the column decoder, and the data will be read.
  • the data signal is amplified and transmitted to the controller of the nonvolatile memory.
  • the address decoder is a common digital logic circuit that selects one of the multiple output signals to be active according to different combinations of input signals, and the other output signals are invalid.
  • the 3-8 line address decoder is composed of 8 AND gate circuits and 3 inverters. Wherein each of the three inverters corresponds to an input signal of the address decoder for generating an inverted signal for the corresponding input signal, 8 The AND gates are used to generate an output signal based on the input signal and its inverted signal.
  • the 3-8 line address decoder has 3 input signals A2, A1 and P A0, 8 output signals Q7-Q0, assuming that the output high level is an active level, denoted by 1, the input signal and the output signal The logical relationship between them is as follows:
  • the signal generator is configured to receive an input signal of the address decoder, output an input signal of the address decoder and an inverted signal thereof to the decoder; for example, 210 of the 3-8 line address decoder in FIG. Partially shown;
  • the decoder is operative to generate an output signal of the address decoder based on the input signal of the address decoder and its inverted signal, such as shown in section 220 of the 3-8 line address decoder of Figure 2.
  • the nonvolatile memory provided by the present invention realizes the storage into the nonvolatile memory by adding a random number generator and a converter therein.
  • the encryption of the data makes it difficult to restore the encrypted data to the original data, thereby improving the security of the data stored in the non-volatile memory.
  • the at least one address of the column address is exchanged, and then the data output by the controller to the nonvolatile memory is stored in the nonvolatile memory, and when the nonvolatile memory is powered off and then powered on, due to the random number
  • the generator generates the randomness of the selection signal, so that the bank strobe signal corresponding to the same bank address sub-signal is different from that before the non-volatile memory is powered off after the non-volatile memory is powered off, thereby making the non-volatile memory
  • the data stored before the volatile memory is powered off is disturbed when the non-volatile memory is powered off and then powered on.
  • the data stored in the non-volatile memory cannot be read in the order of the original storage address to achieve the encryption effect.
  • non-volatile memory storage array According to the address order of the storage array, the data of each row is sequentially read, which are MARP, EDOC, DROW, and ATAD, and it is difficult to analyze what data is actually stored in the nonvolatile memory, so that the nonvolatile memory reaches the pair of stored data.
  • the effect of encryption In particular, commonly used non-volatile memories generally have at least one bank, each bank includes thousands of rows and columns, and some or all of the banks and/or rows and/or columns are exchanged to disturb the storage.
  • the 3-8 line address decoder shown in Figure 2 is still taken as an example.
  • the 3-8 line address decoder is a combinational logic circuit, which is actually composed of 8 AND gate circuits and 3 inverters, as shown in Figure 2.
  • an exchanger structure as shown in Fig. 2A can be employed.
  • the implementation principle of the switch is illustrated by taking the input signals A and /A as examples. If the input signals of the switch are A, /A, and sel, the outputs are L and /L, where sel is the select signal used to determine the logic function of the circuit;
  • a random number generator may be set to randomly generate the bits of the random number generator.
  • the bit is used as the selection signal.
  • the random number generator is implemented in many ways.
  • a pseudo-random sequence generator as shown in FIG. 2C can be used, which is implemented by a linear feedback shift register, which is to take two bits of the linear feedback shift register.
  • a signal obtained by XOR processing of the lowest bit and the middle one bit is used as a shift input signal, and then passes under the control of the clock signal. Sub-shifting can produce random data.
  • the number of bits X of the linear feedback shift register can be set according to the actual application environment.
  • a nonvolatile memory comprising at least two bank banks, and a bank decoder, each bank including a memory array a row decoder and a column decoder of the memory array, the nonvolatile memory further comprising: a random number generator, disposed between the first signal generator of the bank decoder and the first decoder! a first switch, a first switch corresponding to a bank address sub-signal of the bank decoder; wherein, the random number generator is configured to randomly charge each of the first switches when the non-volatile memory is powered on Generating a selection signal, and transmitting the generated selection signal to the first switch corresponding to the selection signal;
  • Decoder in each bank ⁇ th first switch for receiving an inverted signal of the th i 2 th sub-bank address signal and the i-th bank address sub-signal corresponding to the first exchanger; when receiving a selection signal transmitted by the random number generator as a first signal, the first sub-i 2 th bank address signal as a second bank decoder i 2 th sub-bank address signals output to the first decoder, the first an inverted signal i 2 th sub-bank address signal as an inverted signal of the output i 2 th sub-bank address decoder signal to the first bank decoder; when receiving a selection signal transmitted by the random number generator for the first when the two signals, the inverted signal of the th i 2 sub-bank address signal as a second bank decoder i 2 th sub-bank address signals output to the first decoder, the first i 2 th bank address signal as a sub-bank outputs the inverted signal i 2 th sub-bank address signal decoder to the first decoder
  • ⁇ and 1 2 may be equal or unequal.
  • the total number of the first exchanger! ⁇ can be smaller than the input signal of the bank decoder, that is, the total number of bank address sub-signals nu, then only one bank address sub-signal and its inverted signal have a corresponding first switch; the total number of the first switch Alternatively, it may be equal to the input signal of the bank decoder, that is, the total number nu of the bank address sub-signals, and each bank address sub-signal and its inverted signal have a corresponding first switch. The closer the value is to mi , the better the encryption effect of the embodiment of the present invention.
  • the first signal in the embodiment of the present invention may be a high level signal, and the second signal may be a low level signal; or the first signal may be a low level signal, and the second signal may be High level signal.
  • the random number generator may include: a linear feedback shift register of at least one bit, and a signal obtained by XOR processing any two bits of the linear feedback shift register as a linear inverse a shift input signal to the shift register;
  • [ ⁇ ] ⁇ first switches correspond to one bit of the linear feedback shift register, respectively, and the corresponding bits are used as selection signals transmitted by the random number generator.
  • the nonvolatile memory 10 includes 2 ml bank1, and a bank decoder 12, each bank 11 including a memory array 111, a row decoder 112 of a memory array, and a column decoder 113. Only one of the bank1 structures is shown in FIG. 3, and the structure of the other bank1 is not shown; the nonvolatile memory further includes: a random number generator 13, and a first signal generator provided in the bank decoder 12. Between the first decoder 122 and the first decoder 122, a first switch 123 corresponds to a bank address sub-signal of the bank decoder 12;
  • the random number generator 13 is configured to randomly generate a selection signal for each of the first switches 123 when the non-volatile memory 10 is powered on, and send the generated selection signal to the corresponding first switch 123;
  • the first signal generator 121 outputs the respective bank address sub-signals and their inverted signals to the corresponding first switch 123; specifically, the first bank address sub-signal A1 and its inverted signal /A1 are transmitted.
  • the second bank address sub-signal A2 and its inverted signal /A2 are sent to the second first switch, ... the nu-th bank address sub-signal Aim and its inverted signal /Aim sent to the first! ⁇ The first switch.
  • the first first switch 123 is configured to receive a first bank address sub-signal corresponding to the first first switch 123 and an inverted signal of the second bank address sub-signal; when receiving the random number generator 13
  • the first bank address sub-signal is output as the first bank address sub-signal of the bank decoder 12 to the first decoder 122, and the inverse of the first bank address sub-signal
  • the phase signal is output to the first decoder 122 as an inverted signal of the first bank address sub-signal of the bank decoder 12; when the selection signal sent by the random number generator 13 is received as the second signal, the first signal
  • the inverted signal of the bank address sub-signal is output to the first decoder 122 as the first bank address sub-signal of the bank decoder 12, and the first bank address sub-signal is used as the first bank address of the bank decoder 12.
  • the inverted signal of the signal is output to the first decoder 122; the values are 1, 2, ..., respectively
  • the first decoder 122 is configured to generate a bank strobe signal according to the bank address sub-signal outputted by each of the first switches 123 and its inverted signal.
  • the random number generator 13 shown in FIG. 3 may include: a linear feedback shift register 130 of mi bits, and a first bit bitO of the linear feedback shift register 130. And the signal obtained by exclusive-OR processing with the second bit bitl is used as a shift input signal of the linear feedback shift register;
  • the first switch 123 corresponds to one bit of the linear feedback shift register, respectively, and the corresponding bit is used as the selection signal transmitted by the random number generator.
  • the specific correspondence between each first switch and the bit is not shown in FIG. 3A, and can be set autonomously in practical applications, and is not limited herein.
  • the signal obtained by exclusive-OR processing any two other bits of the linear feedback shift register 130 may be used as the shift input signal of the linear feedback shift register 130.
  • the non-volatile memory implementation structure shown in FIG. 3 and FIG. 3A is only a specific example. According to the example, those skilled in the art may use at least one bank address sub-signal and its inverted signal in the bank address decoder.
  • the foregoing first switch or the like is provided with a reasonable deformation of the example, and various implementation structures of the nonvolatile memory including two or more banks are obtained, which will not be further described herein. Specifically, 2 ml should be greater than or equal to the actual number of banks in the non-volatile memory.
  • the number of bits included in the random number generator 13 shown in FIG. 3A can be adaptively adjusted according to the number of first switches included in the nonvolatile memory.
  • the present embodiment is particularly applicable to a scenario in which a nonvolatile memory sequentially stores data in a memory cell of each bank when data is being stored. For example, if the data to be stored is A, B, C, then data A is stored in the first bank, data B is stored in the second bank, and data C is stored in the third bank.
  • the random number generator generates a selection signal when the nonvolatile memory is powered on, and each of the first converters in the control bank decoder maintains the corresponding bank address sub-signal and its inverted signal. Change or interchange, when the non-volatile memory is powered off and then powered on, the random number generator generates the randomness of the selection signal, so that the non-volatile memory is powered off and then powered on and the non-volatile memory is powered off.
  • the bank strobe signal corresponding to the same bank address sub-signal is different, so that the data stored before the non-volatile memory is powered off is shuffled after the non-volatile memory is powered off, and the encryption effect is achieved.
  • the data stored in the non-volatile memory cannot be read in the order of the original storage address, so that other people cannot obtain the original data even when directly reading the stored data in the non-volatile memory using the software tool, and it is difficult to The data stored in the memory is restored to the original data, ensuring the security of the data stored in the non-volatile memory.
  • At least one bank in the nonvolatile memory may further include the following structure: Second letter a second switch between the number generator and the second decoder, a second switch corresponding to a row address sub-signal of the row decoder; wherein, the random number generator can also be used for: When the memory is powered on, each of the second switches randomly generates a selection signal, and sends the generated selection signal to the corresponding second switch;
  • each bank of second switch for receiving the first 2 ⁇ j-th row address sub-signal corresponding to the second exchanger and the j-th inverted signals of the two sub row address signal; and when upon receiving a selection signal transmitted random number generator as a third signal, the first j 2 sub row address signal j 2 as the row decoder row address sub-signal to the second decoder, the j inverted signal of two sub row address signal as an inverted signal of the output of the j 2 sub row address signal a row decoder to the second decoder; when receiving a selection signal transmitted by the random number generator is a fourth signal, the inverted signals j-2 sub row address signal as a j-row decoder 2 outputs a row address signal to the second sub-decoder, the j two sub row address signals as row translation j 2 inverted signal of the output of the sub row address signal to the second vocoder decoder; 1 ⁇ ⁇ 2; l ⁇ j 2 ⁇ m 2, l
  • the total number n 2 of the second switch may be smaller than the total number of line decoders, that is, the total number of row address sub-signals m 2 , then only n 2 row address sub-signals and their inverted signals Having a corresponding second switch; the total number of second switches may also be equal to the input signal of the row decoder, that is, the total number of row address sub-signals m 2 , then each row address sub-signal and its inverted signal There is a corresponding second exchanger.
  • the closer the value of n 2 is to m 2 the better the encryption effect of the embodiment of the present invention.
  • the third signal in the embodiment of the present invention may be a high level signal, and the fourth signal may be a low level signal; or the third signal may be a low level signal, and the fourth signal may be High level signal.
  • the random number generator may include: a linear feedback shift register having at least ⁇ bits, and the signal obtained by XOR processing any two bits of the linear feedback shift register as a linear feedback shift a shift input signal of the register; ⁇ is the total number of the first switch and the second switch included in the nonvolatile memory;
  • Each of the first switch and each of the second switches respectively corresponds to a bit of the linear feedback shift register, and the corresponding bit is used as a selection signal transmitted by the random number generator.
  • FIG. 4 shows: If a bank in FIG. 3 includes n 2 numbers between the second signal generator 1121 and the second decoder 1122 provided in the row decoder. The implementation structure of the bank at the time of the second switch 1 123, and the connection relationship between the bank and the random number generator 13 in FIG. Other structures and connection relationships in 3 are not shown. Moreover, in the bank structure diagram shown in FIG.
  • the row decoder 112 of the bank includes the following structure:
  • the second signal generator 1121 outputs the respective row address sub-signals and their inverted signals to the corresponding second switch 1123; specifically, the first row address sub-signal A1 and its inverted signal /A1 are transmitted. through a second switch, the second sub-row address signal and an inverted signal A2 / A2 second message to the second switch, the second ... m 2 row address sub-signal and its inverse Am 2 Phase signal /Am 2 is sent to the m 2 second switches;
  • the second second switch 1123 of each bank is configured to receive the first row address sub-signal corresponding to the second second switch 1123 and the inverted signal of the first row address sub-signal; when receiving the random number
  • the second row address sub-signal is output as the second row address sub-signal of the row decoder 112 to the second decoder 1122, and the first row address is used.
  • the inverted signal of the signal is output to the second decoder 1122 as an inverted signal of the first row address sub-signal of the row decoder 112; when the selection signal sent by the random number generator 13 is received as the fourth signal, The inverted signal of the first row address sub-signal is output to the second decoder 1122 as the second row address sub-signal of the row decoder 112, and the second row address sub-signal is used as the row decoder 112.
  • the inverted signal of the first row address sub-signal is output to the second decoder 1122; the value of ⁇ is 1, 2 to m 2 .
  • the second decoder 1122 is configured to generate a row strobe signal based on the row address sub-signals output by the respective second switches 1123 and their inverted signals.
  • the random number generator 13 may include: a linear feedback shift register 131 having a bit, linear feedback shift The bit X and bit1 of the bit register 131 are subjected to XOR processing to obtain a signal as a shift input signal of the linear feedback shift register;
  • Each of the first switch 123 and each of the second switches 1123 corresponds to one bit of the linear feedback shift register 13 1 , respectively, and the corresponding bit is used as the selection signal transmitted by the random number generator 13 .
  • Ni is the sum of the number of second switches in each row decoder.
  • the number n 2 of the second switches of different banks may be different, and the ji, j 2 , etc. of different banks may take the same or different values, which is not limited herein.
  • the structure after setting the second switch in the row decoder in other banks is similar to the structure of the bank in FIG. 4, except that the value of n 2 may be different, and the values of ji and j 2 may be different, some rows may be different.
  • the address sub-signal may not have a corresponding second switch, which is not described here.
  • the nonvolatile memory implementation structure shown in FIG. 4 and FIG. 4A is only a specific example, and those skilled in the art according to the example are configured according to at least one bank address sub-signal and its inverted signal in the bank address decoder.
  • the foregoing first switch, the at least one row address sub-signal in the row decoder of the at least one bank, and the inversion signal thereof set the foregoing second switch, and the like are reasonably modified, and the embodiment includes 2 ⁇
  • Various implementation structures of non-volatile memory of infinity banks are not described here.
  • the random number generator generates a selection signal when the nonvolatile memory is powered up, except for controlling each of the first converters in the bank decoder.
  • the second converter in the control bank also controls the corresponding row address sub-signal and its inverted signal to remain unchanged or interchanged.
  • the random number generator When the non-volatile memory is powered down and then powered up, the random number generator generates a selection signal. The randomness of the bank address signal corresponding to the same bank address sub-signal is different from that of the non-volatile memory when the non-volatile memory is powered off and then powered on.
  • the row strobe signals are different, so that the data stored before the non-volatile memory is powered off is shuffled after the non-volatile memory is powered off, and the encryption effect is achieved, so that the data stored in the non-volatile memory cannot be followed.
  • the original storage addresses are read sequentially, so that other people cannot obtain the original data even when using the software tool to directly read the stored data in the non-volatile memory, which is difficult to Data stored in volatile memory restored to the original data to ensure the security of the data stored in the nonvolatile memory.
  • the at least one bank of the nonvolatile memory may further include: a third signal disposed in the column decoder n 3 third switches between the generator and the third decoder, one third switch corresponding to a column address sub-signal of the column decoder; wherein, the random number generator is further used for: When the memory is powered on, each of the third switches randomly generates a selection signal, and sends the generated selection signal to the corresponding third switch; [145] ⁇ 1 of each bank is a third switch, for receiving a ⁇ k 2 column addresses of the sub-signal corresponding to the third switch and the second column address k 2 th sub-signal of the first inverted signal ; when receiving a selection signal transmitted from the random number generator is a fifth signal, the first column address k 2 sub-signals of the column decoder as k 2 column address signal to a third sub-decoder, the
  • the total number n 3 of the third switch may be smaller than the total number of the column decoder input signals, that is, the column address sub-signal m 3 , then only n 3 column address sub-signals and their inversion
  • the signal has a corresponding third switch; the total number n 3 of the third switch can also be equal to the input signal of the column decoder, that is, the total number of column address sub-signals m 3 , then each column address sub-signal Its inverted signal has a corresponding third switch.
  • the closer the value of n 3 is to m 3 the better the encryption effect of the embodiment of the present invention.
  • the fifth signal in the embodiment of the present invention may be a high level signal, and the sixth signal may be a low level signal; or the fifth signal may be a low level signal, and the sixth signal may be High level signal.
  • the random number generator may include: a linear feedback shift register having at least N 2 bits, and the signal obtained by XOR processing any two bits of the linear feedback shift register as a linear feedback shift a shift input signal of the register; N 2 is a total number of first and third converters included in the nonvolatile memory;
  • Each of the first switch and each of the third switches respectively corresponds to one bit of the linear feedback shift register, and the corresponding bit is used as a selection signal transmitted by the random number generator.
  • the third signal generator 113 1 outputs the respective column address sub-signals and their inverted signals to the corresponding third switch 123; specifically, the first column address sub-signal A1 and its inverted signal /A1 transmitting through a third switch, sends the second column address sub-signal and the inverted signal A2 / A2 through the third switches 2, m 3 ... the first column address sub-signal and Am 3
  • the inverted signal /Am 3 is sent to the m 3rd third switch;
  • the third third switch 1133 of each bank is configured to receive the first ⁇ column address sub-signal corresponding to the third third switch 1133 and the inverted signal of the first ⁇ column address sub-signal; upon receiving the selection signal of the random number generator 13 transmits a fifth signal, the first column address sub-signal as the column decoder 113, column address of k 2 th sub-signal to the third decoder 1132, the first The inverted signal of the column address sub-signal is output to the third decoder 1132 as the inverted signal of the first column address sub-signal of the lining decoder 113; when the selection signal transmitted by the random number generator 13 is received When the signal is the sixth signal, the inverted signal of the first column address sub-signal is output to the third decoder 1132 as the first column address sub-signal of the column decoder 113, and the first column address sub-signal is used as the column.
  • the inverted signal of the first column address sub-signal of the decoder 113 is output
  • the third decoder 1132 is configured to generate a column strobe signal based on the column address sub-signals output by the respective third switches 1133 and their inverted signals.
  • the random number generator 13 may include: a linear feedback shift register 132 having N 2 bits, linear The signal obtained by performing exclusive-OR processing on the bitO and bit1 of the shift register 132 is used as a shift input signal of the linear feedback shift register;
  • Each of the first switch and each of the third switches respectively corresponds to one bit of the linear feedback shift register, and the corresponding bit is used as the selection signal transmitted by the random number generator 13.
  • any two bits of the linear feedback shift register 132 may be used in practical applications.
  • the bit signal is XORed to obtain a shifted input signal, which is not limited herein.
  • any two of the linear feedback shift registers 132 may be used in practical applications.
  • the signal of the bit is XORed to obtain a shifted input signal, which is not limited herein.
  • the correspondence between the first switch and the third switch and each bit is not shown in FIG. 5A, and the first switch and the third switch are only referred to by the switch. In practical applications, The correspondence between a switch and the third switch and each bit can be set autonomously, and is not limited herein.
  • the number n 3 of the third switches set in different banks may be different, and the ki, k 2 , etc. of different banks may take the same or different values, which is not limited herein.
  • the structure after setting the third switch in the column decoder in other banks is similar to the structure of the bank in FIG. 5, except that the value of n 3 may be different, the values of ki and k 2 are different, and some column addresses are different.
  • the sub-signal may not have a corresponding third switch, which is not described here.
  • the non-volatile memory implementation structure shown in FIG. 5 and FIG. 5A is only a specific example, and those skilled in the art according to the example set according to at least one bank address sub-signal and its inverted signal in the bank address decoder.
  • the foregoing first switch, the at least one column address sub-signal of the column decoder of the at least one bank, and the reverse-phase signal of the at least one bank are provided with the third converter and the like, and the example is reasonably modified, and the embodiment includes Various implementation structures of the nonvolatile memory of two or more banks are not described herein again.
  • the random number generator generates a selection signal when the nonvolatile memory is powered up, except for controlling each of the first converters in the bank decoder.
  • the third converter in the control bank also controls the corresponding column address sub-signal and its inverted signal to remain unchanged or interchanged.
  • the random number generator When the non-volatile memory is powered off and then powered on, the random number generator generates a selection signal.
  • the randomness of the bank strobe signal corresponding to the same bank address sub-signal is different from that before the non-volatile memory is powered off after the non-volatile memory is powered off, and the same column address sub-signal corresponds to The column strobe signals are different, so that the data stored before the non-volatile memory is powered off is shuffled after the non-volatile memory is powered off, and the encryption effect is achieved, so that the data stored in the non-volatile memory cannot be followed.
  • the original storage addresses are read sequentially, so that other people cannot obtain the original data even when using the software tool to directly read the stored data in the non-volatile memory, which is difficult to Data stored in volatile memory restored to the original data to ensure the security of the data stored in the nonvolatile memory.
  • the at least one bank in the nonvolatile memory may further include: a third set in the column decoder n 3 third switches between the signal generator and the third decoder, and a third switch corresponding to a column address sub-signal of the column decoder;
  • the random number generator is further configured to: when the non-volatile memory is powered on, separately generate a selection signal for each third switch, and send the generated selection signal to the corresponding third switch; [166] ⁇ 1 of each bank is a third switch, for receiving a ⁇ k 2 column addresses of the sub-signal corresponding to the third switch and the second column address k 2 th sub-signal of the first inverted signal ; when receiving a selection signal transmitted from the random number generator is a fifth signal, the first column address k 2 sub-signals of the column decoder as k 2 column address signal to a third sub-decoder, the k-th inverted signals of the two sub-column address signal as an inverted signal of the k 2 output sub-signals of column address decoder to the third row decoder; when receiving a selection signal transmitted by the random number generator for the first when six signals, the inverted signal of the k 2 column address sub-signal of the column decoder as k 2 column address signal to
  • the total number n 2 of the second switch may be smaller than the input signal of the row decoder, that is, the total number of row address sub-signals m 2 , then only n 2 row address sub-signals and their inverted signals Having a corresponding second switch; the total number of second switches may also be equal to the input signal of the row decoder, that is, the total number of row address sub-signals m 2 , then each row address sub-signal and its inverted signal There is a corresponding second exchanger.
  • the closer the value of n 2 is to m 2 the better the encryption effect of the embodiment of the present invention.
  • the first signal may be a high level signal, and the second signal may be a low level signal; or the first signal may be a low level signal, and the second signal may be High level signal.
  • the random number generator may include: a linear feedback shift register having at least N 3 bits, and a signal obtained by XOR processing any two bits of the linear feedback shift register as a linear feedback shift a shift input signal of the register; N 3 is a total number of the first converter, the second converter, and the third converter included in the nonvolatile memory;
  • Each of the first switch, each of the second converters, and each of the third switches respectively corresponds to one bit of the linear feedback shift register, and the corresponding bit is used as a selection signal transmitted by the random number generator.
  • each bank in the nonvolatile memory there are four possible implementation structures for each bank in the nonvolatile memory: 1.
  • the second switch is not set in the row decoder of the bank, and the third is not set in the column decoder.
  • a second switch is provided in the row decoder of the bank, and the third switch is not disposed in the column decoder; 3. the second switch is not disposed in the row decoder of the bank, and the column is decoded.
  • a third switch is disposed in the device; 4.
  • a second switch is disposed in the row decoder of the bank, and a third switch is disposed in the column decoder.
  • a second switch is provided in the row decoder of at least one bank in the nonvolatile memory, and a third switch is provided in the column decoder of at least one bank.
  • a non-volatile memory includes 4 banks, and bankl adopts a second possible implementation structure.
  • bank2 is implemented by the fourth possible implementation structure
  • bank3 is implemented by a third possible implementation structure
  • bank4 is implemented by the first possible implementation structure.
  • the random number generator 13 is configured to: when the nonvolatile memory is powered on, separately generate a selection signal for each of the second switch and the third switch, and send the generated selection signal to the corresponding second switch. And a third exchanger;
  • the second signal generator 1121, the second switch 1123, and the second decoder 1122 in the row decoder refer to the example shown in FIG. 4 regarding the second signal generator, the second switch, and the A description of the second decoder;
  • a description of the third signal generator 1131, the third switch 1133, and the third decoder 1132 in the column decoder refer to the third signal generator in the example shown in FIG.
  • the related descriptions of the three switches and the third decoder are not described here.
  • the random number generator 13 in this embodiment may include: a linear feedback shift register 133 having N 3 bits, two bits of bitO and bitl of the linear feedback shift register 133 The signal obtained after the exclusive OR processing is used as a shift input signal of the linear feedback shift register; each of the first switch, each of the second switches, and each of the third switches and one of the linear feedback shift registers 133, respectively Corresponding to the bit, the corresponding bit is used as the selection signal transmitted by the random number generator 13.
  • N 3 is the total number of all the first switches, the second switches, and the third switches in the nonvolatile memory.
  • any two bits of the linear feedback shift register 133 may be used in practical applications.
  • the bit signal is XORed to obtain a shifted input signal, which is not limited herein.
  • the correspondence between the first switch, the second switch, and the third switch and each bit is not shown in FIG. 6A, and only the switch is referred to as the first switch, the second switch, and the first Three switches. In practical applications, the correspondence between the first switch, the second switch, the third switch, and each bit may be from The main setting is not limited here.
  • the number of the second switch set in different bank n 2 can be different, in a different bank, j 2 and the like may take the same or different values, the number of the third switch set in different bank n 3 may be different, k 2 or the like of different banks may take the same or different values, and is not limited herein.
  • the structure in which the second switch is set in the row decoder in the other bank and the third switch is set in the column decoder is similar to the structure of the bank in FIG. 5, except that n 2 , n 3 , j 2 , The value of k 2 may be different.
  • Some row address sub-signals may not have corresponding second switches, and some column address sub-signals may not have corresponding third switches.
  • the non-volatile memory implementation structure shown in FIG. 6 and FIG. 6A is only a specific example, and those skilled in the art according to the example set according to at least one bank address sub-signal and its inverted signal in the bank address decoder.
  • the foregoing first switch, at least one row address sub-signal in the row decoder of the at least one bank, and the inverted signal thereof, the at least one of the foregoing second switch, the column decoder of the at least one bank The column address sub-signal and its inverted signal set the foregoing third switch and the like are reasonably modified to obtain various implementation structures of the non-volatile memory including 2 to infinity banks in this embodiment. A narrative.
  • the random number generator generates a selection signal when the nonvolatile memory is powered on, and controls each third in the bank in addition to controlling the first converter and the second converter.
  • the converter keeps the corresponding column address sub-signal and its inverted signal unchanged or interchanged, so that the column strobe signal actually outputted by the column decoder is the same as or different from the column strobe signal corresponding to the column address sub-signal.
  • the random number generator When the non-volatile memory is powered off and then powered on, the random number generator generates the randomness of the selection signal, so that the non-volatile memory is powered off and then powered on, compared with before the non-volatile memory is powered off.
  • the bank strobe signal corresponding to the bank address sub-signal is different.
  • the row strobe signal corresponding to the same row address sub-signal is different, and the column strobe signal corresponding to the same column address sub-signal is different, thereby making the non-volatile memory
  • the data stored before the power is interrupted after the non-volatile memory is powered off, and the encryption effect is achieved, so that the data stored in the non-volatile memory cannot be stored according to the original storage.
  • the address sequence is read so that other people cannot obtain the original data even when directly reading the stored data in the non-volatile memory using the software tool, and it is difficult to restore the data stored in the non-volatile memory to the original data, ensuring nonvolatile The security of the data stored in the memory.
  • the nonvolatile memory includes: at least one bank, each bank including a memory array, a row decoder of the memory array, and a column decoder, further comprising: random a number generator, the at least one bank further comprising: a second switch disposed between the second signal generator of the row decoder and the second decoder, each second switch corresponding to one of the row decoders Row address sub-signal; Medium,
  • a random number generator configured to randomly generate a selection signal for each of the second switches when the nonvolatile memory is powered up, and send the generated selection signal to the corresponding second switch;
  • each bank of second switch for receiving the first 2 ⁇ j-th row address sub-signal corresponding to the second exchanger and the j-th inverted signals of the two sub row address signal; and when upon receiving a selection signal transmitted random number generator as a third signal, the first j 2 sub row address signal j 2 as the row decoder row address sub-signal to the second decoder, the j inverted signal of two sub row address signal as an inverted signal of the output of the j 2 sub row address signal a row decoder to the second decoder; when receiving a selection signal transmitted by the random number generator is a fourth signal, the inverted signals j-2 sub row address signal as a j-row decoder 2 outputs a row address signal to the second sub-decoder, the j two sub row address signals as row translation j 2 inverted signal of the output of the sub row address signal to the second vocoder decoder; 1 ⁇ ⁇ 2; l ⁇ j 2 ⁇ m 2, l
  • the total number n 2 of the second switch may be smaller than the input signal of the row decoder, that is, the total number of row address sub-signals m 2 , then only n 2 row address sub-signals and their inverted signals Having a corresponding second switch; the total number of second switches may also be equal to the input signal of the row decoder, that is, the total number of row address sub-signals m 2 , then each row address sub-signal and its inverted signal There is a corresponding second exchanger.
  • the closer the value of n 2 is to m 2 the better the encryption effect of the embodiment of the present invention.
  • the first signal may be a high level signal, and the second signal may be a low level signal; or the first signal may be a low level signal, and the second signal may be High level signal.
  • the random number generator may include: a linear feedback shift register having at least N 4 bits, and the signal obtained by XOR processing any two bits of the linear feedback shift register as a linear feedback shift a shift input signal of the register; N 4 is a total number of second switches included in the nonvolatile memory;
  • Each of the second switches corresponds to a bit of the linear feedback shift register, and the corresponding bit is used as a selection signal transmitted by the random number generator.
  • the nonvolatile memory may include only one bank, for example, as shown in FIG. 7, but the specific implementation structure of setting the second switch in the row decoder is not shown in FIG.
  • the bank decoder may not be provided in the volatile memory; the nonvolatile memory may also include two or more banks, and the bank decoder is generally provided in the nonvolatile memory, for example, as shown by 7A, but The specific implementation structure in which the second switch is set in the row decoder is not shown in 7.
  • Bank decoding is set in nonvolatile memory When the device is in the bank decoder, the first switch may not be set, and the first switch may be set.
  • the implementation is similar to the nonvolatile memory structure of the second embodiment. Therefore, only the bank decoder or bank translation is not included in the nonvolatile memory in this embodiment.
  • the first switch is not provided in the encoder, and is implemented by the structure in the prior art.
  • the bank in the nonvolatile memory there are two possible implementation structures for the bank in the nonvolatile memory: 1.
  • the second switch is not set in the row decoder; 2.
  • the second switch is set in the row decoder.
  • at least one bank in the non-volatile memory is implemented by a second possible implementation structure.
  • the implementation of the random number generator in this embodiment may also refer to the random number generator example shown in FIG. 3A, except that the bit number of the random number generator in this embodiment may be N 4 , and Each bit is connected to a second switch.
  • the number n 2 of the second switches of different banks may be different, and the jij 2 and the like of different banks may take the same or different values, which is not limited herein.
  • the structure after setting the second switch in the row decoder in other banks is similar to the structure of the bank in FIG. 4, except that the value of n 2 may be different, the value may be different, and some row address sub-signals may be different. There may be no corresponding second switch, which is not described here.
  • the above example is reasonably modified according to the principle that at least one row address sub-signal in the row decoder of at least one bank and its inverted signal is disposed in the foregoing second switch.
  • Various implementation structures of the nonvolatile memory including any number of banks in the embodiment of the present invention can be obtained, and details are not described herein again.
  • the random number generator generates a selection signal when the nonvolatile memory is powered on, and controls each second converter to keep the corresponding row address sub-signal and its inverted signal unchanged or interchanged.
  • the random number generator When the non-volatile memory is powered off and then powered on, the random number generator generates the randomness of the selection signal, so that the non-volatile memory is powered off and then powered on, compared with before the non-volatile memory is powered off, the same line.
  • the row strobe signal corresponding to the address sub-signal is different, so that the data stored before the non-volatile memory is powered off is shuffled after the non-volatile memory is powered off, and the encryption effect is achieved, so that the storage is non-volatile.
  • the data of the memory cannot be read in the order of the original storage address, so that other people cannot obtain the original data even when directly reading the stored data in the nonvolatile memory by using the software tool, and it is difficult to recover the data stored in the nonvolatile memory.
  • Raw data ensures the security of data stored in non-volatile memory.
  • the at least one bank in the nonvolatile memory further includes: a third signal generator disposed in the column decoder n 3 third switches between the third decoder and a third switch corresponding to a column address sub-signal of the column decoder; wherein the random number generator is further used for: on the non-volatile memory When the power is generated, a selection signal is randomly generated for each third switch, and the generated selection signal is sent to the corresponding third switch;
  • ⁇ 1 of each bank is a third switch, for receiving a ⁇ k 2 column addresses of the sub-signal corresponding to the third switch and the second column address k 2 th sub-signal of the first inverted signal ; when receiving a selection signal transmitted from the random number generator is a fifth signal, the first column address k 2 sub-signals of the column decoder as k 2 column address signal to a third sub-decoder, the k-th inverted signals of the two sub-column address signal as an inverted signal of the k 2 output sub-signals of column address decoder to the third row decoder; when receiving a selection signal transmitted by the random number generator for the first when six signals, the inverted signal of the k 2 column address sub-signal of the column decoder as k 2 column address signal to a third sub-decoder, the first k 2 column as column address sub-signal an inverted signal of the output of the k 2 th column address decoder sub-signal to the third
  • the total number n 3 of the third switch may be smaller than the total number of the column decoder sub-signals, that is, the total number of column address sub-signals m 3 , then only n 3 column address sub-signals and their inversions
  • the signal has a corresponding third switch; the total number n 3 of the third switch can also be equal to the input signal of the column decoder, that is, the total number of column address sub-signals m 3 , then each column address sub-signal Its inverted signal has a corresponding third switch.
  • the closer the value of n 3 is to m 3 the better the encryption effect of the embodiment of the present invention.
  • the fifth signal may be a high level signal, and the sixth signal may be a low level signal; or the fifth signal may be a low level signal, and the sixth signal may be High level signal.
  • the random number generator may include: a linear feedback shift register having at least N 5 bits, and a signal obtained by XOR processing any two bits of the linear feedback shift register as a linear feedback shift a shift input signal of the register; N 5 is the total number of the second switch and the third switch included in the nonvolatile memory; each of the second switch and each of the third switches and the linear feedback shift register One bit corresponds to the corresponding bit as the selection signal sent by the random number generator.
  • the bank decoder when the nonvolatile memory includes only one bank, the bank decoder may not be provided, and when the nonvolatile memory includes two or more banks, the bank decoder may be set. Not limited.
  • the bank decoder When the bank decoder is set in the nonvolatile memory, the first bank may not be set in the bank decoder.
  • the converter, or the first switch can also be set.
  • the first switch When the first switch is set in the bank decoder, the implementation is similar to the nonvolatile memory structure of the second embodiment. Therefore, only the bank decoder or bank translation is not included in the nonvolatile memory in this embodiment.
  • the first switch is not provided in the encoder, and is implemented by the structure in the prior art.
  • each bank included in the nonvolatile memory there are four possible implementation structures for each bank included in the nonvolatile memory: 1.
  • the second switch is not set in the row decoder of the bank, and the second decoder is not set. 3.
  • the third switch is provided in the row decoder of the bank, and the third switch is not disposed in the column decoder; 3.
  • the second switch is not set in the bank decoder of the bank, A third switch is disposed in the coder; 4.
  • a second switch is disposed in the row decoder of the bank, and a third switch is disposed in the column decoder.
  • a second switch is provided in the row decoder of at least one bank in the nonvolatile memory, and a third switch is provided in the column decoder of at least one bank.
  • a nonvolatile memory includes 4 banks, bankl is implemented by a second possible implementation structure, bank2 is implemented by a fourth possible implementation structure, bank3 is implemented by a third possible implementation structure, and bank4 is The first possible implementation structure implementation.
  • the implementation of the random number generator in this embodiment may also refer to the random number generator example shown in FIG. 3A, except that the bit number of the random number generator in this embodiment may be N 5 , and Each bit is connected to a second switch or a third switch.
  • the number of the second switch set in different bank n 2 can be different, in a different bank, j 2 and the like may take the same or different values, the number of the third switch set in different bank n 3 may be different, k 2 or the like of different banks may take the same or different values, and is not limited herein.
  • the structure in which the second switch is set in the row decoder in the other bank and the third switch is set in the column decoder is similar to the structure of the bank in FIG. 6, except that n 2 , n 3 , j 2 , The value of k 2 may be different.
  • the row address sub-signals in some row decoders may not exist in the corresponding second switch, and the column address sub-signals in some column decoders may not exist corresponding to the third exchange.
  • Device the column address sub-signals in some row decoders may not exist in the corresponding second switch, and the column address sub-signals in some column decoders may not exist corresponding to the third exchange.
  • the random number generator generates a selection signal when the nonvolatile memory is powered up, and controls the respective column addresses of the respective third converters in addition to controlling the second converter.
  • the signal and its inverted signal remain unchanged or interchangeable.
  • the random number generator When the nonvolatile memory is powered off and then powered up, the random number generator generates randomness of the selection signal, so that the nonvolatile memory is powered off and then powered up.
  • the row strobe signal corresponding to the same row address sub-signal is different, and the column strobe signal corresponding to the same column address sub-signal is different, so that the non-volatile memory is powered off before power-off.
  • the stored data is scrambled when the non-volatile memory is powered off and then powered up, so that the encryption effect is achieved, so that the data stored in the non-volatile memory cannot be read in the original storage address order, so that others can use the software tool even if they use the software tool.
  • the stored data in the nonvolatile memory is directly read, the original data cannot be obtained, and it is difficult to restore the data stored in the nonvolatile memory to the original data.
  • Security nonvolatile memory card for storing data.
  • the nonvolatile memory includes: at least one bank, each bank including a memory array, a row decoder of the memory array, and a column decoder.
  • the nonvolatile memory further includes: a random number generator, the at least one bank further comprising: n 3 third switches disposed between the third signal generator of the column decoder and the third decoder, one The third switch corresponds to a column address sub-signal of the column decoder; wherein, the random number generator is configured to randomly generate a selection signal for each third switch when the non-volatile memory is powered on, and generate the generated selection signal Send to the corresponding third switch;
  • ⁇ 1 of each bank is a third switch, for receiving a ⁇ k 2 column addresses of the sub-signal corresponding to the third switch and the second column address k 2 th sub-signal of the first inverted signal ; when receiving a selection signal transmitted from the random number generator is a fifth signal, the first column address k 2 sub-signals of the column decoder as k 2 column address signal to a third sub-decoder, the k-th inverted signals of the two sub-column address signal as an inverted signal of the k 2 output sub-signals of column address decoder to the third row decoder; when receiving a selection signal transmitted by the random number generator for the first when six signals, the inverted signal of the k 2 column address sub-signal of the column decoder as k 2 column address signal to a third sub-decoder, the first k 2 column as column address sub-signal an inverted signal of the output of the k 2 th column address decoder sub-signal to the
  • the total number n 3 of the third switch may be smaller than the input signal of the column decoder, that is, the column address
  • the total number of signals m 3 then only n 3 column address sub-signals and their inverted signals have corresponding third switches; the total number of third switches n 3 can also be equal to the input signal of the column decoder That is, the total number m 3 of column address sub-signals, then each column address sub-signal and its inverted signal have a corresponding third switch.
  • the closer the value of n 3 is to m 3 the better the encryption effect of the embodiment of the present invention.
  • the fifth signal in the embodiment of the present invention may be a high level signal, and the sixth signal may be a low level signal; or the fifth signal may be a low level signal, and the sixth signal may be High level signal.
  • the random number generator may include: a linear feedback shift register having at least N 6 bits, and a signal obtained by XOR processing any two bits of the linear feedback shift register as a linear feedback shift register Shifting the input signal; N 6 is the total number of non-volatile memories including the third selector;
  • Each of the third switches corresponds to a bit of the linear feedback shift register, and the corresponding bit is used as a selection signal transmitted by the random number generator.
  • the bank decoder when the nonvolatile memory includes only one bank, the bank decoder may not be provided, and when the nonvolatile memory includes two or more banks, the bank decoder may be set. Not limited.
  • the first converter When the bank decoder is set in the nonvolatile memory, the first converter may not be provided in the bank decoder, or the first switch may be set.
  • the first switch When the first switch is set in the bank decoder, the implementation is similar to the nonvolatile memory structure of the second embodiment. Therefore, only the bank decoder or bank translation is not included in the nonvolatile memory in this embodiment.
  • the first switch is not provided in the encoder, and is implemented by the structure in the prior art.
  • the bank in the nonvolatile memory there are two possible implementation structures for the bank in the nonvolatile memory: 1.
  • the third switch is not set in the column decoder; 2.
  • the third switch is set in the column decoder.
  • at least one bank in the non-volatile memory is implemented by a second possible implementation structure.
  • the implementation of the random number generator in this embodiment may also refer to the random number generator example shown in FIG. 3A, except that the bit number of the random number generator may be N 6 in this embodiment, and Each bit is connected to a third switch.
  • the number n 3 of the third switches of different banks may be different, and the ki, k 2 , etc. of different banks may take the same or different values, which is not limited herein.
  • the structure after setting the third switch in the column decoder in other banks is similar to the structure of the bank in FIG. 5, except that the value of n 2 may not be The value of ji may be different. Some column address sub-signals may not exist in the corresponding third switch, and are not described here.
  • the above examples are reasonably modified according to the principle that at least one column address sub-signal in the column decoder of at least one bank and its inverted signal is set to the third converter.
  • Various implementation structures of the nonvolatile memory including any number of banks in the embodiment of the present invention can be obtained, and details are not described herein again.
  • the random number generator generates a selection signal when the nonvolatile memory is powered on, and each third converter in the control bank keeps the corresponding column address sub-signal and its inverted signal unchanged or mutually
  • the random number generator generates randomness of the selection signal, so that the non-volatile memory is powered off and then powered on before the non-volatile memory is powered off.
  • the column strobe signals corresponding to the same column address sub-signal are different, so that the data stored before the non-volatile memory is powered off is shuffled after the non-volatile memory is powered off, and the encryption effect is achieved, so that the storage is performed.
  • the data of the non-volatile memory cannot be read in the order of the original storage address, so that other people cannot obtain the original data even when directly reading the stored data in the non-volatile memory using the software tool, and it is difficult to store the non-volatile memory.
  • the data is restored to the original data, ensuring the security of the data stored in the non-volatile memory.
  • the nonvolatile memory in the embodiment of the present invention may be specifically a phase change memory, a variable resistance memory (ReRAM), or the like.
  • ReRAM variable resistance memory
  • an embodiment of the present invention further provides an electronic device, including the nonvolatile memory of any of the above embodiments.

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Abstract

一种非易失存储器及电子设备,所述非易失存储器在每次上电时,使用交换器将bank译码器和/或bank中的行译码器和/或bank中的列译码器中的至少1个地址子信号与其反相信号进行随机互换,从而使得非易失存储器下电前存储的数据在非易失存储器下电后再上电时被打乱,存储至非易失存储器的数据无法按照原来的存储地址顺序读取,达到加密效果,提高非易失存储器中所存储数据的安全性。

Description

非易失存储器及电子设备
本发明要求于 2013年 11月 27日提交中国专利局、申请号为 201310613032.4、 发明名称为 "非易失存储器及电子设备" 的中国专利申请的优先权, 其全部内容 通过引用结合在本发明中。 技术领域
[01] 本发明涉及数据加密技术, 尤其涉及非易失存储器及电子设备。 背景技术
[02] 非易失存储器具有掉电之后信息不会丢失的非易失性特点, 但是, 将非易失 存储器应用于某些对安全性要求较高的场景时, 掉电后的非易失存储器中存储的 信息会存在泄露的风险。
[03] 以非易失存储器中的相变存储器为例。相变存储器是一种通过相变材料的不 同状态来保存信息的非易失存储器。 当相变材料处于晶态时电阻较小, 处于非晶 态时电阻较大, 通过检测相变材料的电阻可以读出对应的数据。 相变存储器与现 有的闪存相比, 具有读写速度快、 耐磨损、 功耗低、 集成度高等优点, 目前有望 逐步取代闪存,今后将可能替代动态随机存储器( DRAM , Dynamic Random Access Memory) 作为电子设备内存使用。 在相变存储器作为电子设备内存使用时, 尽 管可以对传输的原始数据先加密再发送, 或者将原始数据加密后再保存到硬盘 中, 但是当电子设备中的应用程序使用这些加密后的数据时, 一般都会先解密得 到原始数据并保存到内存里, 以便今后重复使用所述原始数据时提高效率, 也就 是说内存里面的数据是原始数据, 是明文。 当电子设备下电之后, 如果有人将作 为内存条的相变存储器拔出并安装到自己的计算机上, 使用软件工具读取并分析 相变存储器中的数据, 就可以获取到存储至相变存储器的原始数据, 而所述原始 数据可能包括用户的敏感信息等需要保密的信息, 从而导致存储至相变存储器中 的数据的安全性较差。
[04] 基于以上可知, 由于非易失存储器的非易失性特点, 非易失存储器中所存储 数据的安全性差。 发明内容
[05] 本发明实施例中提供了一种非易失存储器及电子设备, 能够对存储至非易失存 储器中的数据进行加密, 提高非易失存储器中所存储数据的安全性。
[06] 第一方面, 提供一种非易失存储器, 所述非易失存储器包括 bank译码器、 以 及至少两个存储体 bank, 所述 bank包括存储阵列、 存储阵列的行译码器和存储 阵列的列译码器, 所述非易失存储器还包括: 随机数发生器、 设置于 bank译码 器的第一信号生成器与第一译码器之间的 个第一交换器,一个所述第一交换器 对应所述 bank译码器的一个 bank地址子信号; 其中,
[07] 所述随机数发生器, 用于在非易失存储器上电时, 分别为各个第一交换器随 机生成选择信号, 将生成的选择信号发送至所述选择信号对应的第一交换器;
[08] 所述 bank译码器的第 ^个第一交换器, 用于接收与所述第 个第一交换器 对应的第 i2个 bank地址子信号以及所述第 i2个 bank地址子信号的反相信号; 当 接收到的选择信号为第一信号时, 将所述第 i2个 bank地址子信号作为所述第 i2 个 bank地址子信号输出至第一译码器, 将所述第 i2个 bank地址子信号的反相信 号作为所述第 i2个 bank地址子信号的反相信号输出至第一译码器; 当接收到的 选择信号为第二信号时, 将所述第 i2个 bank地址子信号的反相信号作为所述第 i2个 bank地址子信号输出至第一译码器, 将所述第 i2个 bank地址子信号作为所 述第 i2个 bank地址子信号的反相信号输出至第一译码器; K ; l ^i2^ im , l ^n^ im , !^是 bank地址子信号的总个数。
[09] 结合第一方面, 在第一方面第一种实现方式中, 至少一个 bank还包括: 设置 于行译码器的第二信号生成器与第二译码器之间的 个第二交换器,一个第二交 换器对应行译码器的一个行地址子信号; 其中,
[10] 所述随机数发生器还用于: 在非易失存储器上电时, 分别为各个第二交换器 随机生成选择信号, 将生成的选择信号发送至所述选择信号对应的第二交换器;
[11] 每个 bank的第 ^个第二交换器, 用于接收与所述第 个第二交换器对应的 第 j2个行地址子信号以及所述第 j2个行地址子信号的反相信号; 当接收到的选择 信号为第三信号时, 将所述第 j2个行地址子信号作为所述第 j2个行地址子信号输 出至第二译码器,将所述第 j2个行地址子信号的反相信号作为所述第 j2个行地址 子信号的反相信号输出至第二译码器; 当接收到的选择信号为第四信号时, 将所 述第 j2个行地址子信号的反相信号作为所述第 j2个行地址子信号输出至第二译码 器,将所述第 j2个行地址子信号作为所述第 j2个行地址子信号的反相信号输出至 第二译码器; l ^ n^ l ^j2^ m2, l ^ n2^ m2, m2是所述第 ^个第二交换器所 属行译码器的行地址子信号的总个数。
[12] 结合第一方面, 在第一方面第二种实现方式中, 至少一个 bank还包括: 设置 于列译码器的第三信号生成器与第三译码器之间的 n3个第三交换器,一个第三交 换器对应列译码器的一个列地址子信号; 其中,
[13] 所述随机数发生器还用于: 在非易失存储器上电时, 分别为各个第三交换器 随机生成选择信号, 将生成的选择信号发送至所述选择信号对应的第三交换器;
[14] 每个 bank的第 个第三交换器,用于接收所述第 个第三交换器对应的第 k2个列地址子信号以及所述第 k2个列地址子信号的反相信号;当接收到的选择信 号为第五信号时, 将所述第 k2个列地址子信号作为所述第 k2个列地址子信号输 出至第三译码器, 将所述第 k2个列地址子信号的反相信号作为所述第 k2个列地 址子信号的反相信号输出至第三译码器; 当接收到的选择信号为第六信号时, 将 所述第 k2个列地址子信号的反相信号作为所述第 k2个列地址子信号输出至第三 译码器, 将所述第 k2个列地址子信号作为所述第 k2个列地址子信号的反相信号 输出至第三译码器; 1 1^ η3, l k2 m3, l ^ n3 ^ m3 , m3是所述第 个第三 交换器所属列译码器的列地址子信号的总个数。
[15] 结合第一方面第一种实现方式, 在第一方面第三种实现方式中, 至少一个 bank还包括: 设置于列译码器的第三信号生成器与第三译码器之间的 n3个第三 交换器, 一个第三交换器对应列译码器的一个列地址子信号; 其中,
[16] 所述随机数发生器还用于: 在非易失存储器上电时, 分别为各个第三交换器 随机生成选择信号, 将生成的选择信号发送至所述选择信号对应的第三交换器;
[17] 每个 bank的第 个所述第三交换器,用于接收所述第 个第三交换器对应 的第 k2个列地址子信号以及所述第 k2个列地址子信号的反相信号; 当接收到的 选择信号为第五信号时, 将所述第 k2个列地址子信号作为所述第 k2个列地址子 信号输出至第三译码器, 将所述第 k2个列地址子信号的反相信号作为所述第 k2 个列地址子信号的反相信号输出至第三译码器; 当接收到的选择信号为第六信号 时, 将所述第 k2个列地址子信号的反相信号作为所述第 k2个列地址子信号输出 至第三译码器, 将所述第 k2个列地址子信号作为所述第 k2个列地址子信号的反 相信号输出至第三译码器; 1 1^ 1 3, l k2 m3, l ^ n3^ m3 , m3是所述第 个第三交换器所属列译码器的列地址子信号的总个数。 [18] 结合第一方面, 在第一方面第四种实现方式中, 所述随机数发生器包括: 至 少^位的线性反馈移位寄存器,所述线性反馈移位寄存器的任意两个比特位进行 异或处理后得到的信号作为所述线性反馈移位寄存器的移位输入信号;
[19] 所述 个第一交换器分别与所述线性反馈移位寄存器的一个比特位对应, 将对应比特位作为所述随机数发生器发送的选择信号。
[20] 结合第一方面第一种实现方式, 在第一方面第五种实现方式中, 所述随机数 发生器包括: 具有至少 个比特位的线性反馈移位寄存器, 所述线性反馈移位 寄存器的任意两个比特位进行异或处理后得到的信号作为所述线性反馈移位寄 存器的移位输入信号 是非易失存储器中包括的第一交换器以及第二交换器的 总个数;
[21] 每个所述第一交换器和每个所述第二交换器分别与所述线性反馈移位寄存 器的一个比特位对应, 将对应比特位作为所述随机数发生器发送的选择信号。
[22] 结合第一方面第二种实现方式, 在第一方面第六种实现方式中, 所述随机数 发生器包括: 具有至少 N2个比特位的线性反馈移位寄存器, 所述线性反馈移位 寄存器的任意两个比特位进行异或处理后得到的信号作为所述线性反馈移位寄 存器的移位输入信号; N2是非易失存储器中包括的第一变换器和第三变换器的总 个数;
[23] 每个所述第一交换器和每个所述第三交换器分别与所述线性反馈移位寄存 器的一个比特位对应, 将对应比特位作为所述随机数发生器发送的选择信号。
[24] 结合第一方面第三种实现方式, 在第一方面第七种实现方式中, 所述随机数 发生器包括: 具有至少 N3个比特位的线性反馈移位寄存器, 所述线性反馈移位 寄存器的任意两个比特位进行异或处理后得到的信号作为所述线性反馈移位寄 存器的移位输入信号; N3是非易失存储器中包括的第一变换器、第二变换器和第 三变换器的总个数;
[25] 每个所述第一交换器、每个所述第二交换器和每个所述第三交换器分别与所 述线性反馈移位寄存器的一个比特位对应, 将对应比特位作为所述随机数发生器 发送的选择信号。
[26] 第二方面, 提供一种非易失存储器, 所述非易失存储器包括至少一个存储体 bank, 每个所述 bank 包括存储阵列、 存储阵列的行译码器和存储阵列的列译码 器, 还包括: 随机数发生器, 至少一个所述 bank还包括: 设置于行译码器的第 二信号生成器与第二译码器之间的 个第二交换器,一个第二交换器对应行译码 器的一个行地址子信号; 其中,
[27] 所述随机数发生器, 用于在非易失存储器上电时, 分别为各个第二交换器随 机生成选择信号, 将生成的选择信号发送至所述选择信号对应的第二交换器;
[28] 每个 bank的第 ^个第二交换器, 用于接收所述第 个第二交换器对应的第 j2个行地址子信号以及所述第 j2个行地址子信号的反相信号; 当接收到的选择信 号为第三信号时,将所述第 j2个行地址子信号作为所述第 j2个行地址子信号输出 至第二译码器, 将所述第 j2个行地址子信号的反相信号作为所述第 j2个行地址子 信号的反相信号输出至第二译码器; 当接收到的选择信号为第四信号时, 将所述 第 j2个行地址子信号的反相信号作为所述第 j2个行地址子信号输出至第二译码 器,将所述第 j2个行地址子信号作为所述第 j2个行地址子信号的反相信号输出至 第二译码器; l ^ n^ l ^j2^ m2, l ^ n2^ m2, m2是所述第 ^个第二交换器所 属行译码器的行地址子信号的总个数。
[29] 结合第二方面, 在第二方面第一种实现方式中, 至少一个所述 bank还包括: 设置于列译码器的第三信号生成器与第三译码器之间的 n3个第三交换器,一个第 三交换器对应列译码器的一个列地址子信号; 其中,
[30] 所述随机数发生器还用于: 在非易失存储器上电时, 分别为各个第三交换器 随机生成选择信号, 将生成的选择信号发送至所述选择信号对应的第三交换器;
[31] 每个 bank的第 个所述第三交换器,用于接收所述第 个第三交换器对应 的第 k2个列地址子信号以及所述第 k2个列地址子信号的反相信号; 当接收到的 选择信号为第五信号时, 将所述第 k2个列地址子信号作为所述第 k2个列地址子 信号输出至第三译码器, 将所述第 k2个列地址子信号的反相信号作为所述第 k2 个列地址子信号的反相信号输出至第三译码器; 当接收到的选择信号为第六信号 时, 将所述第 k2个列地址子信号的反相信号作为所述第 k2个列地址子信号输出 至第三译码器, 将所述第 k2个列地址子信号作为所述第 k2个列地址子信号的反 相信号输出至第三译码器; 1 1^ 1 3, l k2 m3, l ^ n3^ m3 , m3是所述第 个第三交换器所属列译码器的列地址子信号的总个数。
[32] 结合第二方面, 在第二方面第二种实现方式中, 所述随机数发生器包括: 具 有至少 N4个比特位的线性反馈移位寄存器, 所述线性反馈移位寄存器的任意两 个比特位进行异或处理后得到的信号作为所述线性反馈移位寄存器的移位输入 信号; N4为非易失存储器包括的第二交换器的总个数;
[33] 每个所述第二交换器分别与所述线性反馈移位寄存器的一个比特位对应,将 对应比特位作为所述随机数发生器发送的选择信号。
[34] 结合第二方面第一种实现方式, 在第二方面第三种实现方式中, 所述随机数 发生器包括: 具有至少 N5个比特位的线性反馈移位寄存器, 所述线性反馈移位 寄存器的任意两个比特位进行异或处理后得到的信号作为所述线性反馈移位寄 存器的移位输入信号; N5是非易失存储器包括的第二交换器和第三交换器的总个 数;
[35] 每个所述第二交换器和每个所述第三交换器分别与所述线性反馈移位寄存 器的一个比特位对应, 将对应比特位作为所述随机数发生器发送的选择信号。
[36] 第三方面, 提供一种非易失存储器, 所述非易失存储器包括至少一个存储体 bank, 每个所述 bank 包括存储阵列、 存储阵列的行译码器和存储阵列的列译码 器, 还包括: 随机数发生器, 至少一个所述 bank还包括: 设置于列译码器的第 三信号生成器与第三译码器之间的 n3个第三交换器,一个第三交换器对应列译码 器的一个列地址子信号; 其中,
[37] 所述随机数发生器, 用于在非易失存储器上电时, 分别为各个第三交换器随 机生成选择信号, 将生成的选择信号发送至所述选择信号对应的第三交换器;
[38] 每个 bank的第 1^个第三交换器,用于接收所述第 个第三交换器对应的第 k2个列地址子信号以及所述第 k2个列地址子信号的反相信号;当接收到的选择信 号为第五信号时, 将所述第 k2个列地址子信号作为所述第 k2个列地址子信号输 出至第三译码器, 将所述第 k2个列地址子信号的反相信号作为所述第 k2个列地 址子信号的反相信号输出至第三译码器; 当接收到的选择信号为第六信号时, 将 所述第 k2个列地址子信号的反相信号作为所述第 k2个列地址子信号输出至第三 译码器, 将所述第 k2个列地址子信号作为所述第 k2个列地址子信号的反相信号 输出至第三译码器; 1 1^ η3, l k2 m3, l ^ n3 ^ m3 , m3是所述第 个第三 交换器所属列译码器的列地址子信号的总个数。
[39] 结合第三方面, 在第三方面第一种实现方式中, 所述随机数发生器包括: 具 有至少 N6个比特位的线性反馈移位寄存器, 所述线性反馈移位寄存器的任意两 个比特位进行异或处理后得到的信号作为所述线性反馈移位寄存器的移位输入 信号; N6为非易失存储器中包括第三选择器的总个数;
[40] 每个所述第三交换器分别与所述线性反馈移位寄存器的一个比特位对应,将 对应比特位作为所述随机数发生器发送的选择信号。
[41] 第四方面, 提供一种电子设备, 包括上述任一项所述的非易失存储器。 [42] 本实施例的非易失存储器包括 bank译码器、 以及至少两个存储体 bank, 所 述 bank包括存储阵列、 存储阵列的行译码器和存储阵列的列译码器, 其特征在 于, 所述非易失存储器还包括: 随机数发生器、 设置于 bank译码器的第一信号 生成器与第一译码器之间的 个第一交换器,一个所述第一交换器对应所述 bank 译码器的一个 bank地址子信号; 其中, 所述随机数发生器, 用于在非易失存储 器上电时, 分别为各个第一交换器随机生成选择信号, 将生成的选择信号发送至 所述选择信号对应的第一交换器; 所述 bank译码器的第 ^个第一交换器, 用于 接收与所述第 ^个第一交换器对应的第 i2个 bank地址子信号以及所述第 i2个 bank 地址子信号的反相信号; 当接收到的选择信号为第一信号时, 将所述第 i2个 bank 地址子信号作为所述第 i2个 bank地址子信号输出至第一译码器, 将所述第 i2个 bank地址子信号的反相信号作为所述第 i2个 bank地址子信号的反相信号输出至 第一译码器; 当接收到的选择信号为第二信号时, 将所述第 i2个 bank地址子信 号的反相信号作为所述第 i2个 bank地址子信号输出至第一译码器, 将所述第 i2 个 bank地址子信号作为所述第 i2个 bank地址子信号的反相信号输出至第一译码 器; K ; l ^i2^ mi , l^m^ mi , 所述!^是 bank地址子信号的总个数。 从而本实施例中, 随机数发生器在非易失存储器上电时产生选择信号, 控制 bank 译码器中的各个第一变换器将对应的 bank地址子信号及其反相信号保持不变或 者互换, 当非易失存储器下电后再上电时, 由于随机数发生器产生选择信号的随 机性, 使得非易失存储器下电后再上电时与非易失存储器下电前相比, 同样的 bank地址子信号所对应的 bank选通信号不同, 从而使得非易失存储器下电前存 储的数据在非易失存储器下电后再上电时被打乱, 达到加密效果, 使得存储至非 易失存储器的数据无法按照原来的存储地址顺序读取, 从而使得其他人即便使用 软件工具直接读取非易失存储器中的存储数据时也无法获得原始数据, 难以将非 易失存储器中存储的数据恢复成原始数据, 保证非易失存储器中存储数据的安全 性。 附图说明
[43] 为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例 或现有技术描述中所需要使用的附图作简单地介绍, 显而易见地, 下面描述中的 附图仅仅是本发明的一些实施例, 对于本领域普通技术人员来讲, 在不付出创造 性劳动性的前提下, 还可以根据这些附图获得其他的附图。 [44] 图 1为现有技术非易失存储器结构示意图;
[45] 图 2为现有技术 3-8线地址译码器结构示意图;
[46] 图 2A为本发明实施例交换器结构示意图;
[47] 图 2B为本发明实施例设置有交换器的 3-8线地址译码器结构示意图;
[48] 图 2C为本发明实施例伪随机序列发生器结构示意图;
[49] 图 3为本发明非易失存储器第一实施例的实例结构图;
[50] 图 3A为本发明非易失存储器第一实施例中随机数发生器实例结构图;
[51] 图 4为本发明非易失存储器第二实施例的实例结构图;
[52] 图 4A为本发明非易失存储器第二实施例中随机数发生器实例结构图;
[53] 图 5为本发明非易失存储器第三实施例的实例结构图;
[54] 图 5A为本发明非易失存储器第三实施例中随机数发生器实例结构图;
[55] 图 6为本发明非易失存储器第四实施例的实例结构图;
[56] 图 6A为本发明非易失存储器第四实施例中随机数发生器实例结构图;
[57] 图 7为本发明非易失存储器第五实施例的一种结构图;
[58] 图 7A为本发明非易失存储器第五实施例的另一种结构图。 具体实施方式
[59] 参见图 1, 为现有技术非易失存储器的结构示意图, 其中, 非易失存储器包 括至少一个 bank, bank译码器, 每个 bank包括存储阵列、 存储阵列的行译码器 和列译码器; 在图 1中仅示出了其中一个 bank的结构, 其他 bank的结构与此相 同, 这里不赘述。 其中, 存储阵列是由大量的存储单元按行、 列排成矩阵形式。 每行存储单元有一个行选通信号, 通过行选通信号每次选中一行存储单元; 每列 存储单元有一个列选通信号, 通过列选通信号每次选中一列存储单元。 存储阵列 中写入或读出的数据都从位线上输入输出。
[60] bank 译码器, 用于根据非易失存储器的控制器输入的 bank 地址信号产生 bank选通信号, 选通该 bank地址信号指示的 bank, 以便进行该被选通的 bank 的读或写访问。 一般的, 非易失存储器包括至少两个 bank 时才会在非易失存储 器中设置 bank译码器, 如果非易失存储器仅包括一个 bank, 则 bank译码器可以 省略。 一般的 bank地址至少由 1位二进制代码构成, 在根据 bank地址产生 bank 地址信号时, 每位二进制代码对应着一个地址子信号, 因此 bank地址信号包括 二进制代码位数个地址子信号, 例如 bank地址 ΒΑ[0: 1]表示该 bank地址包括 2 个地址子信号。 后续的行地址信号和列地址信号与此类似, 分别包括若干个行地 址子信号和若干个列地址子信号。
[61] 每个 bank的行译码器, 用于根据非易失存储器的控制器输入的行地址信号 产生行选通信号, 从所属 bank 的存储阵列中选通所述行地址信号指示的一行存 储单元来进行读或写访问。
[62] 每个 bank的列译码器, 用于根据非易失存储器的控制器输入的列地址信号 产生列选通信号, 从所属 bank 的存储阵列中选通所述列地址信号指示的一列存 储单元来进行读或写访问。
[63] 通过 bank译码器选中一个 bank, 通过行译码器和列译码器分别选中 bank 中存储阵列的一行和一列存储单元, 就可以唯一选中某个 bank 中的某个存储单 元, 从而实现存储单元的选通, 进而实现对存储单元的读、 写访问等。
[64] 当然, 如图 1所示, 在实际应用中每个 bank还可以包括控制逻辑、 写驱动 器、 感应放大器等其他结构, 本发明实施例并不限制。 该控制逻辑一般用于根据 非易失存储器外部的器件例如非易失存储器的控制器提供的片选、 读写信号来控 制写驱动器对存储阵列进行写访问或者控制感应放大器对存储阵列进行读访问; 该写驱动器一般用于将非易失存储器的控制器发送来的待写入的数据存储到被 行译码器和列译码器选中的存储单元, 具体的, 可以根据待写入到存储单元的数 据是 0或 1而产生对应波形的写脉冲信号发送至存储单元; 该感应放大器一般用 于读取被行译码器和列译码器选中的存储单元所存储的数据, 将读取的数据信号 放大后传输至非易失存储器的控制器。
[65] 其中, 不管是 bank译码器、 行译码器、 列译码器, 都可以通过地址译码器 来实现。
[66] 地址译码器是一种常见的数字逻辑电路, 它可以根据输入信号的不同组合, 在多个输出信号中选择一个置为有效电平, 其他输出信号都无效。 地址译码器的 输出信号个数 n与输入信号个数 m之间的关系是: n= 2m, m、 n均为自然数。 当 bank译码器通过地址译码器实现时, bank地址信号作为地址译码器的输入信号, 而地址译码器的输出信号作为 bank选通信号。 行译码器、 列译码器与此类似, 不再赘述。
[67] 以下介绍地址译码器的实现原理。 这里, 以 3-8线地址译码器为例, 该 3-8 线地址译码器由 8个与门电路和 3个反相器组成。 其中, 3个反相器中的每个反 相器对应地址译码器的一个输入信号, 用于为对应的输入信号生成反相信号, 8 个与门用于根据输入信号及其反相信号生成输出信号。 其中, 3-8 线地址译码器 有 3个输入信号 A2、 A1禾 P A0, 8个输出信号 Q7-Q0, 假设输出高电平为有效电 平, 用 1表示, 输入信号和输出信号之间的逻辑关系如下:
[68] Q0=/A2*/A1 */A0, A2A1A0=000时 Q0为 1, 其他情况为 0 ;
[69] Q1=/A2*/A1 *A0, A2A1 A0=001时 Q 1为 1, 其他情况为 0;
[70] Q2=/A2*A1 */A0, A2A1A0=010时 Q2为 1, 其他情况为 0;
[71] Q3=/A2*A1 *A0 , A2A1 A0=011时 Q3为 1, 其他情况为 0;
[72] Q4=A2*/A1 */A0, A2A1A0=100时 Q4为 1, 其他情况为 0;
[73] Q5=A2*/A1 *A0 , A2A1 A0=101时 Q5为 1, 其他情况为 0;
[74] Q6=A2*A1 */A0 , A2A1 A0=110时 Q6为 1, 其他情况为 0;
[75] Q7=A2*A1 *A0 , A2A1A0=111时 Q7为 1, 其他情况为 0;
[76] 其中, /A表示对 A取反, 例如 A=0时 /A=l, A=l时 /A=0, *号表示逻辑与 的运算。
[77] 从上面的表达式可以看出, 三个输入信号对应于八个表达式, 如果 A2A1A0=000, 贝 U Q0=1 , 其他输出都是 0, 如果 A2A1A0=001, 贝 U Ql = l , 以此 类推。
[78] 以上为 3-8线地址译码器的电路和逻辑关系,其他地址译码器的实现原理与 此相同, 这里不赘述。 并且, 为了后续本发明实施例描述的简便, 本发明实施例 中将地址译码器划分为信号生成器和译码器两部分, 其中,
[79] 信号生成器用于接收地址译码器的输入信号,输出所述地址译码器的输入信 号及其反相信号至译码器; 例如图 2中 3-8线地址译码器的 210部分所示;
[80] 译码器用于根据地址译码器的输入信号及其反相信号生成地址译码器的输 出信号, 例如图 2中 3-8线地址译码器的 220部分所示。
[81] 在上述现有技术的非易失存储器的实现结构的基础上,本发明提供的非易失 存储器通过在其中增加随机数发生器以及变换器, 实现了对存储至非易失存储器 中的数据的加密, 使得加密后的数据难以恢复成原始数据, 从而提高了非易失存 储器中存储数据的安全性。
[82] 下面将结合本发明实施例中的附图, 对本发明实施例中的技术方案进行清 楚、 完整的描述, 显然, 所描述的实施例仅仅是本发明一部分实施例, 而不是全 部的实施例。 基于本发明中的实施例, 本领域普通技术人员在没有付出创造性劳 动前提下所获得的所有其他实施例, 都属于本发明保护的范围。 [83] 以下, 首先对本发明实施例对非易失存储器中存储数据加密的原理进行说 明。 在该说明中, 仍然以前述的 3-8线地址译码器为例。 假设 3-8线地址译码器 作为某一存储阵列的行译码器, 则 3-8线地址译码器的 8个输出信号 Q7-Q0可以 作为行选通信号, 如果行序号从 0开始算起, 那么: 当 A2A1A0=000时存储阵列 的第 0行被选中, 当 A2A1A0=001时存储阵列的第 1行被选中; 如果将 Q0和 Q1 表达式中的 A0、 /AO对换, 那么: 当 A2A1A0=000时, 被选中的是存储阵列的 第 1行, 而 A2A1A0=001时被选中的是第 0行, 相当于第 0行和第 1行互换了。 如果 A2、 Al、 AO同时发生这种对换, 那么表达式变为:
[84] Q0=A2*A1 *A0, A2A1A0=111时为 1, 其他情况为 0
[85] Q1=A2*A1 */A0, A2A1 A0=110时为 1, 其他情况为 0
[86] Q2=A2*/A1 *A0, A2A1 A0=101时为 1, 其他情况为 0
[87] Q3=A2*/A1 */A0, A2A1 A0=100时为 1, 其他情况为 0
[88] Q4=/A2*A1 *A0, A2A1A0=011时为 1, 其他情况为 0
[89] Q5=/A2*A1 */A0, A2A1 A0=010时为 1, 其他情况为 0
[90] Q6=/A2*/A1 *A0, A2A1A0=001时为 1, 其他情况为 0
[91] Q7=/A2*/A1 */A0, A2A1 A0=000时为 1, 其他情况为 0
[92] 对比两组表达式可以看出, Q7与 Q0互换了, Q6与 Q1互换了, 以此类推。 由于 Q7-Q0是行选通信号, 这种互换的结果是: 非易失存储器外部的器件例如控 制器给出存储阵列第 0行的地址, 非易失存储器实际选中的是存储阵列第 7行; 控制器给出存储阵列第 1行的地址,非易失存储器实际选中的是存储阵列第 6行, 以此类推。 如果 A与 /A的这种互换是随机发生的, 例如 A2 与 /A2互换了, 但 A1与 /A1没有互换等, 而且每次上电时非易失存储器中 bank地址、 行地址、 列 地址的至少一种地址进行这种互换, 那么该控制器向非易失存储器输出的数据被 非易失存储器存储后, 当非易失存储器下电后再上电时, 由于随机数发生器产生 选择信号的随机性, 使得非易失存储器下电后再上电时与非易失存储器下电前相 比, 同样的 bank地址子信号所对应的 bank选通信号不同, 从而使得非易失存储 器下电前存储的数据在非易失存储器下电后再上电时被打乱, 存储至非易失存储 器的数据无法按照原来的存储地址顺序读取, 达到加密效果。 举例说明如下:
[93] 假设现有技术中的非易失存储器在下电前保存 4个英语单词,分别位于存储 阵列的 1-4行, 第一行是 DATA, 第二行是 WORD, 第三行是 CODE, 第四号是 PRAM, 则存储阵列中数据的存储位置关系如下表 1所示: 表 1
Figure imgf000013_0001
[94] 而本发明的非易失存储器在下电后再上电时如果将第一行与第四行互换,将 第二行与第三行互换, 变为下表 2所示的存储位置关系:
表 2
Figure imgf000013_0002
[95] 在表 2的基础上, 如果本发明的非易失存储器再将第一列与第四列互换, 第 二列与第三列互换, 最终变为如下表 3所示的存储位置关系:
表 3
Figure imgf000013_0003
[96] 那么, 如果有人希望直接读取非易失存储器的存储阵列中存储的数据时, 依 照存储阵列的地址顺序依次读出每一行的数据, 分别为 MARP、 EDOC、 DROW 和 ATAD, 很难分析出非易失存储器中实际存储的是什么数据, 从而非易失存储 器达到了对存储数据进行加密的效果。 尤其是常用的非易失存储器中一般都有至 少一个 bank, 每个 bank包括几千个行、 列, 对其中的部分或者全部 bank和 /或 行和 /或列进行互换, 打乱所存储数据的存储位置和顺序, 那么最终顺序读取非易 失存储器中的数据时, 读取出来的数据之间的相关性很低, 恢复得到原始数据的 难度非常大。 这种加密方法只是修改了数据的存储位置和存储顺序, 数据本身并 没有变化, 类似于洗牌。
[97] 下面再讨论如何用电路实现这种互换方式, 仍然以图 2所示的 3-8线地址译 码器为例来说明。 3-8线地址译码器是一个组合逻辑电路, 其实就是 8个与门电 路和 3个反相器组成的, 如图 2所示。
[98] 为了实现 AO与 /A0、 A1与 /Al、 A2与 /A2之间的互换, 可以采用如图 2A所 示的交换器结构。 该交换器的实现原理以输入信号为 A和 /A为例来说明。 如果 交换器的输入信号是 A、 /A和 sel, 输出是 L和 /L, 其中 sel是选择信号, 用来决 定电路的逻辑功能; 贝 U,
[99] 当 sel=0时, L=A, /L=/A, 这是交换器的直通模式;
[100]当 sel=l时, L=/A, /L=A, 这是交换器的互换模式;
[101]如果 sel是随机变化的, 那么 L和 /L就会随机的等于 A或 /A了。
[102]如图 2B所示, 将 3个交换器设置于 3-8线地址译码器的信号生成器和译码 器之间, 用 L0替代 Α0, 用 /L0替代 /Α0, 用 L1替代 Al, 用 /L1替代 /Al, 用 L2 替代 Α2, 用 /L2替代 /Α2, 就可以实现 AO与 /A0、 A1与 /Al、 Α2与 /Α2之间的互 换。 另外, 在实际应用中可以不设置 3个交换器, 而设置 2个或 1个交换器, 实 现 AO与 /A0、 A1与 /Al、 A2与 /A2中任意 2组或 1组输入信号及其反相信号的 互换, 同样可以达到一定的加密效果。 当然为每组输入信号及其反相信号都设置 对应的交换器, 加密效果最好。
[103]另外, 为了让交换器的选择信号 sel, 例如图 2B 中 3个交换器的选择信号 sel2、 sell和 selO实现随机变化, 可以设置随机数发生器, 将随机数发生器随机 产生的比特位作为所述选择信号。 随机数发生器的实现方法很多, 例如可以使用 如图 2C所示的伪随机序列发生器, 它是通过线性反馈移位寄存器来实现的, 具 体做法是将线性反馈移位寄存器的两个比特位例如最低比特位与中间的一个比 特位经过异或处理得到的信号作为移位输入信号, 于是在时钟信号控制下经过多 次移位, 就能产生具有随机性的数据了。线性反馈移位寄存器的比特位数 X可以 根据实际应用环境设定。
[104]以下基于上述发明人提出的实现原理结合附图对本发明实施例非易失存储 器的实现进行说明。
[105]在本发明非易失存储器的第一实施例中, 提供一种非易失存储器, 该非易失 存储器包括至少两个存储体 bank、 以及 bank译码器, 每个 bank包括存储阵列、 存储阵列的行译码器和列译码器, 所述非易失存储器还包括: 随机数发生器、 设 置于 bank译码器的第一信号生成器与第一译码器之间的!^个第一交换器, 一个 第一交换器对应 bank译码器的一个 bank地址子信号; 其中, 随机数发生器, 用 于在非易失存储器上电时, 分别为各个第一交换器随机生成选择信号, 将生成的 选择信号发送至选择信号对应的第一交换器;
[106]每个 bank译码器的第 ^个第一交换器, 用于接收第 个第一交换器对应的 第 i2个 bank地址子信号以及第 i个 bank地址子信号的反相信号; 当接收到随机 数发生器发送的选择信号为第一信号时, 将第 i2个 bank地址子信号作为 bank译 码器的第 i2个 bank地址子信号输出至第一译码器, 将第 i2个 bank地址子信号的 反相信号作为 bank译码器的第 i2个 bank地址子信号的反相信号输出至第一译码 器; 当接收到随机数发生器发送的选择信号为第二信号时, 将第 i2个 bank地址 子信号的反相信号作为 bank译码器的第 i2个 bank地址子信号输出至第一译码器, 将第 i2个 bank地址子信号作为 bank译码器的第 i2个 bank地址子信号的反相信 号输出至第一译码器; K ; l ^i2^ mi , l ^m ^ mi , mi是 bank地址子信 号的总个数。
[107]其中, ^和12可以相等或不相等。
[108]其中, 第一交换器的总个数!^可以小于 bank译码器的输入信号也即 bank 地址子信号的总个数 nu , 则只有 个 bank地址子信号及其反相信号具有对应的 第一交换器;第一交换器的总个数 也可以等于 bank译码器的输入信号也即 bank 地址子信号的总个数 nu , 则每个 bank地址子信号及其反相信号具有对应的第一 交换器。 其中, 的数值越接近 mi, 则本发明实施例的加密效果越好。
[109]其中, 本发明实施例中的第一信号可以为高电平信号, 则第二信号可以为低 电平信号; 或者, 第一信号可以为低电平信号, 则第二信号可以为高电平信号。
[no]其中, 随机数发生器可以包括: 至少 个比特位的线性反馈移位寄存器, 线性反馈移位寄存器的任意两个比特位进行异或处理后得到的信号作为线性反 馈移位寄存器的移位输入信号;
[ιιι] ηι个第一交换器分别与线性反馈移位寄存器的一个比特位对应,将对应比特 位作为随机数发生器发送的选择信号。
[112]在图 3 中以非易失存储器包括 2ml个 bank, bank译码器通过 im- 2"11线地址 译码器实现, =1^、 第一交换器与 bank地址子信号依次对应也即 =i2为例, 对 第一实施例中非易失存储器的具体实现结构进行说明。
[113]参见图 3, 非易失存储器 10包括 2ml个 bankl l、 以及 bank译码器 12, 每个 bank 11包括存储阵列 111、 存储阵列的行译码器 112和列译码器 113, 在图 3中 仅示出了其中一个 bankl l的结构, 其他 bankl l的结构未示出; 非易失存储器还 包括: 随机数发生器 13、 设置于 bank译码器 12的第一信号生成器 121与第一译 码器 122之间的 ml个第一交换器 123,一个第一交换器 123对应 bank译码器 12 的一个 bank地址子信号; 其中,
[114]随机数发生器 13, 用于在非易失存储器 10上电时, 分别为各个第一交换器 123随机生成选择信号, 将生成的选择信号发送至对应的第一交换器 123 ;
[115]第一信号生成器 121将各个 bank地址子信号及其反相信号输出至对应的第 一交换器 123 ; 具体的, 将第 1个 bank地址子信号 A1及其反相信号 /A1发送至 第 1个第一交换器, 将第 2个 bank地址子信号 A2及其反相信号 /A2发送至第 2 个第一交换器, …将第 nu个 bank地址子信号 Aim及其反相信号 /Aim发送至第 !^个第一交换器。
[116]第 个第一交换器 123,用于接收第 个第一交换器 123对应的第 个 bank 地址子信号以及第 ^个 bank地址子信号的反相信号; 当接收到随机数发生器 13 发送的选择信号为第一信号时, 将第 ^个 bank地址子信号作为 bank译码器 12 的第 ^个 bank地址子信号输出至第一译码器 122, 将第 个 bank地址子信号的 反相信号作为 bank译码器 12的第 ^个 bank地址子信号的反相信号输出至第一 译码器 122; 当接收到随机数发生器 13 发送的选择信号为第二信号时, 将第 个 bank地址子信号的反相信号作为 bank译码器 12的第 个 bank地址子信号输 出至第一译码器 122, 将第 ^个 bank地址子信号作为 bank译码器 12的第 个 bank地址子信号的反相信号输出至第一译码器 122; 的取值分别为 1、 2、…!^。
[117]第一译码器 122用于根据各个第一交换器 123输出的 bank地址子信号及其 反相信号生成 bank选通信号。 [118]其中, 参见图 3A所示, 图 3中所示的随机数发生器 13可以包括: mi个比 特位的线性反馈移位寄存器 130, 线性反馈移位寄存器 130的第一个比特位 bitO 和第二个比特位 bitl进行异或处理后得到的信号作为线性反馈移位寄存器的移位 输入信号;
[119] !^个第一交换器 123 分别与线性反馈移位寄存器的一个比特位对应, 将对 应比特位作为随机数发生器发送的选择信号。 其中, 图 3A中未示出每个第一交 换器与比特位之间的具体对应关系, 在实际应用中可以自主设置, 这里不限制。
[120]其中,也可以将线性反馈移位寄存器 130任意其他两个比特位进行异或处理 后得到的信号作为线性反馈移位寄存器 130的移位输入信号。
[121]图 3和图 3A所示的非易失存储器实现结构仅为具体实例, 本领域技术人员 根据该实例, 可以通过为 bank地址译码器中至少一个 bank地址子信号及其反相 信号设置前述的第一交换器等对该实例的合理变形, 得到包括 2个以上 bank的 非易失存储器的各种实现结构, 这里不再一一赘述。 具体的, 2ml应该大于等于 非易失存储器中 bank 实际个数。 另外, 在不同的非易失存储器实现结构中, 图 3A所示的随机数发生器 13所包括的比特位数可以根据非易失存储器所包括的第 一交换器的个数适应性调整。
[122]本实施例尤其适用于非易失存储器在进行数据存储时, 依次在每个 bank的 一个存储单元中存入数据的场景下。 例如待存储的数据为 A、 B、 C, 则在第一个 bank存储数据 A, 在第二个 bank存储数据 B, 在第三个 bank存储数据 C。
[123]本实施例中,随机数发生器在非易失存储器上电时产生选择信号,控制 bank 译码器中的各个第一变换器将对应的 bank地址子信号及其反相信号保持不变或 者互换, 当非易失存储器下电后再上电时, 由于随机数发生器产生选择信号的随 机性, 使得非易失存储器下电后再上电时与非易失存储器下电前相比, 同样的 bank地址子信号所对应的 bank选通信号不同, 从而使得非易失存储器下电前存 储的数据在非易失存储器下电后再上电时被打乱, 达到加密效果, 使得存储至非 易失存储器的数据无法按照原来的存储地址顺序读取, 从而使得其他人即便使用 软件工具直接读取非易失存储器中的存储数据时也无法获得原始数据, 难以将非 易失存储器中存储的数据恢复成原始数据, 保证非易失存储器中存储数据的安全 性。
[124]本发明非易失存储器第二实施例中, 在第一实施例非易失存储器的基础上, 非易失存储器中至少一个 bank还可以包括以下结构: 设置于行译码器的第二信 号生成器与第二译码器之间的 个第二交换器,一个第二交换器对应行译码器的 一个行地址子信号; 其中, 随机数发生器还可以用于: 在非易失存储器上电时, 分别为各个第二交换器随机生成选择信号, 将生成的选择信号发送至对应的第二 交换器;
[125]每个 bank的第 ^个第二交换器, 用于接收第 ^个第二交换器对应的第 j2个 行地址子信号以及第 j2个行地址子信号的反相信号; 当接收到随机数发生器发送 的选择信号为第三信号时,将第 j2个行地址子信号作为行译码器的第 j2个行地址 子信号输出至第二译码器, 将第 j2个行地址子信号的反相信号作为行译码器的第 j2个行地址子信号的反相信号输出至第二译码器; 当接收到随机数发生器发送的 选择信号为第四信号时, 将第 j2个行地址子信号的反相信号作为行译码器的第 j2 个行地址子信号输出至第二译码器, 将第 j2个行地址子信号作为行译码器的第 j2 个行地址子信号的反相信号输出至第二译码器; 1 ^ η2 ; l ^j2^ m2 , l ^ n2^ m2, m2是第 个第二交换器所属行译码器的行地址子信号的总个数。
[126]其中, ^和』2的取值可以相同或不同。
[127]其中, 第二交换器的总个数 n2可以小于行译码器的输入信号也即行地址子 信号的总个数 m2, 则只有 n2个行地址子信号及其反相信号具有对应的第二交换 器;第二交换器的总个数 也可以等于行译码器的输入信号也即行地址子信号的 总个数 m2, 则每个行地址子信号及其反相信号具有对应的第二交换器。 其中, n2 的数值越接近 m2, 则本发明实施例的加密效果越好。
[128]其中, 本发明实施例中的第三信号可以为高电平信号, 则第四信号可以为低 电平信号; 或者, 第三信号可以为低电平信号, 则第四信号可以为高电平信号。
[129]其中, 随机数发生器可以包括: 具有至少 ^^个比特位的线性反馈移位寄存 器, 线性反馈移位寄存器的任意两个比特位进行异或处理后得到的信号作为线性 反馈移位寄存器的移位输入信号; ^是非易失存储器中包括的第一交换器以及第 二交换器的总个数;
[130]每个第一交换器和每个第二交换器分别与线性反馈移位寄存器的一个比特 位对应, 将对应比特位作为随机数发生器发送的选择信号。
[131]以下通过图 4的实例对本实施例非易失存储器的实现结构进行说明。由于实 现结构过于复杂, 在图 4中仅示出了: 图 3 中某个 bank如果包括设置于行译码 器的第二信号生成器 1121与第二译码器 1122之间的 n2个第二交换器 1 123时该 bank的实现结构, 以及该 bank与图 3中的随机数发生器 13之间的连接关系, 图 3 中的其他结构以及连接关系未示出。 而且, 在图 4示出的 bank结构图中设定 n2=m2, 第二交换器与行译码器的行地址子信号依次对应, 也即 j f ; 其中, 随 机数发生器 13还可以用于:在非易失存储器上电时,分别为各个第二交换器 1123 随机生成选择信号, 将生成的选择信号发送至对应的第二交换器 1123 ;
[132]该 bank的行译码器 112包括以下结构:
[133]第二信号生成器 1121将各个行地址子信号及其反相信号输出至对应的第二 交换器 1123 ; 具体的, 将第 1个行地址子信号 A1及其反相信号 /A1发送至第 1 个第二交换器, 将第 2个行地址子信号 A2及其反相信号 /A2发送至第 2个第二 交换器, …将第 m2个行地址子信号 Am2及其反相信号 /Am2发送至第 m2个第二 交换器;
[134]每个 bank的第 个第二交换器 1123, 用于接收第 个第二交换器 1123对 应的第 个行地址子信号以及第 个行地址子信号的反相信号; 当接收到随机数 发生器 13发送的选择信号为第三信号时, 将第 ^个行地址子信号作为行译码器 112的第 ^个行地址子信号输出至第二译码器 1122, 将第 个行地址子信号的反 相信号作为行译码器 112 的第 ^个行地址子信号的反相信号输出至第二译码器 1122; 当接收到随机数发生器 13发送的选择信号为第四信号时, 将第 ^个行地 址子信号的反相信号作为行译码器 112的第 ^个行地址子信号输出至第二译码器 1122, 将第 ^个行地址子信号作为行译码器 112的第 个行地址子信号的反相信 号输出至第二译码器 1122; ^的取值为 1、 2〜m2
[135]第二译码器 1122用于根据各个第二交换器 1123输出的行地址子信号及其反 相信号生成行选通信号。
[136]当图 3中的至少一个 bank通过图 4所示的结构实现时, 如图 4A所示, 随 机数发生器 13可以包括: 具有 个比特位的线性反馈移位寄存器 131, 线性反 馈移位寄存器 131的 bitO和 bitl两个比特位进行异或处理后得到的信号作为线性 反馈移位寄存器的移位输入信号;
[137]每个第一交换器 123和每个第二交换器 1123分别与线性反馈移位寄存器 13 1 的一个比特位对应, 将对应的比特位作为随机数发生器 13发送的选择信号。
[138]图 4A中虽然仅示出了 bitO和 bitl两个比特位进行异或处理得到移位输入信 号的实现方式, 但是, 在实际应用中可以将线性反馈移位寄存器 131的任意两个 比特位的信号进行异或处理得到移位输入信号, 这里不限定。
[139]其中, 如果图 3 中仅有一个 bank 的行译码器中设置第二交换器 1123, 则 , 如果图 3 中有至少两个 bank的行译码器中设置第二交换器 1123, 则
Ni是 与各个行译码器中第二交换器个数的总和。
[140]图 4A中未示出第一交换器和第二交换器与每个比特位之间的对应关系, 仅 以交换器代称第一交换器和第二交换器, 在实际应用中, 第一交换器和第二交换 器与每个比特位之间的对应关系可以自主设定, 这里不限制。
[141]在实际应用中, 不同 bank的第二交换器的数量 n2可以不同, 不同 bank的 ji 、 j2等可以取相同或不同的数值, 这里并不限定。 其他 bank 中在行译码器中 设置第二交换器后的结构与图 4中 bank的结构类似, 区别仅在于 n2的取值可能 不同, ji、 j2的取值可能不同, 某些行地址子信号可能不存在对应的第二交换器, 这里不赘述。
[142]图 4和图 4A所示的非易失存储器实现结构仅为具体实例, 本领域技术人员 根据该实例, 依照为 bank地址译码器中至少一个 bank地址子信号及其反相信号 设置前述的第一交换器、 为至少一个 bank 的行译码器中的至少一个行地址子信 号及其反相信号设置前述的第二交换器等原则对该实例进行合理变形, 得到本实 施例包括 2〜无穷大个 bank的非易失存储器的各种实现结构,这里不再一一赘述。
[143]本实施例相对于图 3和图 3A所示的实施例, 随机数发生器在非易失存储器 上电时产生选择信号,除了控制 bank译码器中的各个第一变换器外,还控制 bank 中的各个第二变换器将对应的行地址子信号及其反相信号保持不变或者互换, 当 非易失存储器下电后再上电时, 由于随机数发生器产生选择信号的随机性, 使得 非易失存储器下电后再上电时与非易失存储器下电前相比, 同样的 bank地址子 信号所对应的 bank选通信号不同, 同样的航地址子信号所对应的行选通信号不 同, 从而使得非易失存储器下电前存储的数据在非易失存储器下电后再上电时被 打乱, 达到加密效果, 使得存储至非易失存储器的数据无法按照原来的存储地址 顺序读取, 从而使得其他人即便使用软件工具直接读取非易失存储器中的存储数 据时也无法获得原始数据, 难以将非易失存储器中存储的数据恢复成原始数据, 保证非易失存储器中存储数据的安全性。
[144]在本发明非易失存储器第三实施例中, 在第一实施例非易失存储器的基础 上, 非易失存储器至少一个 bank还可以包括: 设置于列译码器的第三信号生成 器与第三译码器之间的 n3个第三交换器,一个第三交换器对应列译码器的一个列 地址子信号; 其中, 随机数发生器还用于: 在非易失存储器上电时, 分别为各个 第三交换器随机生成选择信号, 将生成的选择信号发送至对应的第三交换器; [145]每个 bank的第 1^个第三交换器, 用于接收第 1^个第三交换器对应的第 k2 个列地址子信号以及第 k2个列地址子信号的反相信号;当接收到随机数发生器发 送的选择信号为第五信号时, 将第 k2个列地址子信号作为列译码器的第 k2个列 地址子信号输出至第三译码器,将第 k2个列地址子信号的反相信号作为行列码器 的第 k2个列地址子信号的反相信号输出至第三译码器;当接收到随机数发生器发 送的选择信号为第六信号时,将第 k2个列地址子信号的反相信号作为列译码器的 第 k2个列地址子信号输出至第三译码器, 将第 k2个列地址子信号作为列译码器 的第 k2个列地址子信号的反相信号输出至第三译码器; 1 1^ 1 3, l k2 m3, l ^ n3^ m3 , m3是第 个第三交换器所属列译码器的列地址子信号的总个数。
[146]其中, 和1¾的取值可以相同或不同。
[147]其中, 第三交换器的总个数 n3 可以小于列译码器的输入信号也即列地址子 信号的总个数 m3, 则只有 n3个列地址子信号及其反相信号具有对应的第三交换 器;第三交换器的总个数 n3也可以等于列译码器的输入信号也即列地址子信号的 总个数 m3, 则每个列地址子信号及其反相信号具有对应的第三交换器。 其中, n3 的数值越接近 m3, 则本发明实施例的加密效果越好。
[148]其中, 本发明实施例中的第五信号可以为高电平信号, 则第六信号可以为低 电平信号; 或者, 第五信号可以为低电平信号, 则第六信号可以为高电平信号。
[149]其中, 随机数发生器可以包括: 具有至少 N2个比特位的线性反馈移位寄存 器, 线性反馈移位寄存器的任意两个比特位进行异或处理后得到的信号作为线性 反馈移位寄存器的移位输入信号; N2是非易失存储器中包括的第一变换器和第三 变换器的总个数;
[150]每个第一交换器和每个第三交换器分别与线性反馈移位寄存器的一个比特 位对应, 将对应比特位作为随机数发生器发送的选择信号。
[151]以下通过图 5的实例对本实施例非易失存储器的实现结构进行说明。由于实 现结构过于复杂, 在图 5中仅示出了: 图 3 中某个 bank如果包括设置于列译码 器 1 13 的第三信号生成器 113 1与第三译码器 1 132之间的 n3个第三交换器 1133 时该 bank的实现结构, 以及该 bank与图 3 中的随机数发生器 13之间的连接关 系, 图 3 中的其他结构以及连接关系未示出。 而且, 在图 5示出的 bank结构图 中设定 n3 =m3, 第三交换器与列译码器的列地址子信号依次对应, 也即 kfk 其中, 随机数发生器 13 还可以用于: 在非易失存储器上电时, 分别为各个第三 交换器 1133 随机生成选择信号, 将生成的选择信号发送至对应的第三交换器 1133;
[152]第三信号生成器 113 1将各个列地址子信号及其反相信号输出至对应的第三 交换器 123 ; 具体的, 将第 1个列地址子信号 A1及其反相信号 /A1发送至第 1个 第三交换器, 将第 2个列地址子信号 A2及其反相信号 /A2发送至第 2个第三交 换器, …将第 m3个列地址子信号 Am3及其反相信号 /Am3发送至第 m3个第三交 换器;
[153]每个 bank的第 个第三交换器 1133, 用于接收第 个第三交换器 1133对 应的第 1^个列地址子信号以及第 1^个列地址子信号的反相信号; 当接收到随机 数发生器 13发送的选择信号为第五信号时, 将第 个列地址子信号作为列译码 器 113的第 k2个列地址子信号输出至第三译码器 1132, 将第 1^个列地址子信号 的反相信号作为行列码器 113的第 1^个列地址子信号的反相信号输出至第三译码 器 1132; 当接收到随机数发生器 13发送的选择信号为第六信号时, 将第 个列 地址子信号的反相信号作为列译码器 113的第 个列地址子信号输出至第三译码 器 1132, 将第 1^个列地址子信号作为列译码器 113的第 个列地址子信号的反 相信号输出至第三译码器 1132; 1^的取值为 1、 2〜m3
[154]第三译码器 1132用于根据各个第三交换器 1133输出的列地址子信号及其反 相信号生成列选通信号。
[155]当图 3中的至少一个 bank通过图 5所示的结构实现时, 如图 5A所示, 随 机数发生器 13可以包括: 具有 N2个比特位的线性反馈移位寄存器 132, 线性反 馈移位寄存器 132的 bitO和 bitl两个比特位进行异或处理后得到的信号作为线性 反馈移位寄存器的移位输入信号;
[156]每个第一交换器和每个第三交换器分别与线性反馈移位寄存器的一个比特 位对应, 将对应的比特位作为随机数发生器 13发送的选择信号。
[157]图 5A中虽然仅示出了 bitO和 bitl两个比特位进行异或处理得到移位输入信 号的实现方式, 但是, 在实际应用中可以将线性反馈移位寄存器 132的任意两个 比特位的信号进行异或处理得到移位输入信号, 这里不限定。
[158]其中, 如果图 3 中仅有一个 bank 的列译码器中设置第三交换器 1133, 则 , 如果图 3中有至少两个 bank的列译码器中设置第三交换器 1133, 则 Ni是 与各个列译码器中第三交换器个数的总和。
[159]图 5A中虽然仅示出了 bitO和 bitl两个比特位进行异或处理得到移位输入信 号的实现方式, 但是, 在实际应用中可以将线性反馈移位寄存器 132的任意两个 比特位的信号进行异或处理得到移位输入信号, 这里不限定。
[160]图 5A中未示出第一交换器和第三交换器与每个比特位之间的对应关系, 仅 以交换器代称第一交换器和第三交换器, 在实际应用中, 第一交换器和第三交换 器与每个比特位之间的对应关系可以自主设定, 这里不限制。
[161]在实际应用中,不同 bank中设置的第三交换器的数量 n3可以不同,不同 bank 的 ki、 k2等可以取相同或不同的数值, 这里并不限定。 其他 bank中在列译码器 中设置第三交换器后的结构与图 5中 bank的结构类似, 区别仅在于 n3的取值可 能不同, ki、 k2的取值不同, 某些列地址子信号可能不存在对应的第三交换器, 这里不赘述。
[162]图 5和图 5A所示的非易失存储器实现结构仅为具体实例, 本领域技术人员 根据该实例, 依照为 bank地址译码器中至少一个 bank地址子信号及其反相信号 设置前述的第一交换器、 为至少一个 bank 的列译码器中的至少一个列地址子信 号及其反相信号设置前述的第三交换器等原则对该实例进行合理变形, 得到本实 施例包括 2个以上 bank的非易失存储器的各种实现结构, 这里不再一一赘述。
[163]本实施例相对于图 3和图 3A所示的实施例, 随机数发生器在非易失存储器 上电时产生选择信号,除了控制 bank译码器中的各个第一变换器外,还控制 bank 中的各个第三变换器将对应的列地址子信号及其反相信号保持不变或者互换, 当 非易失存储器下电后再上电时, 由于随机数发生器产生选择信号的随机性, 使得 非易失存储器下电后再上电时与非易失存储器下电前相比, 同样的 bank地址子 信号所对应的 bank选通信号不同, 同样的列地址子信号所对应的列选通信号不 同, 从而使得非易失存储器下电前存储的数据在非易失存储器下电后再上电时被 打乱, 达到加密效果, 使得存储至非易失存储器的数据无法按照原来的存储地址 顺序读取, 从而使得其他人即便使用软件工具直接读取非易失存储器中的存储数 据时也无法获得原始数据, 难以将非易失存储器中存储的数据恢复成原始数据, 保证非易失存储器中存储数据的安全性。
[164]在本发明非易失存储器第四实施例中, 在第二实施例非易失存储器的基础 上, 非易失存储器中至少一个 bank还可以包括: 设置于列译码器的第三信号生 成器与第三译码器之间的 n3个第三交换器,一个第三交换器对应列译码器的一个 列地址子信号; 其中,
[165]随机数发生器还用于: 在非易失存储器上电时, 分别为各个第三交换器随机 生成选择信号, 将生成的选择信号发送至对应的第三交换器; [166]每个 bank的第 1^个第三交换器, 用于接收第 1^个第三交换器对应的第 k2 个列地址子信号以及第 k2个列地址子信号的反相信号;当接收到随机数发生器发 送的选择信号为第五信号时, 将第 k2个列地址子信号作为列译码器的第 k2个列 地址子信号输出至第三译码器,将第 k2个列地址子信号的反相信号作为行列码器 的第 k2个列地址子信号的反相信号输出至第三译码器;当接收到随机数发生器发 送的选择信号为第六信号时,将第 k2个列地址子信号的反相信号作为列译码器的 第 k2个列地址子信号输出至第三译码器, 将第 k2个列地址子信号作为列译码器 的第 k2个列地址子信号的反相信号输出至第三译码器; 1 1^ 1 3, l k2 m3, l ^n3^ m3 , m3是第 个第三交换器所属列译码器的列地址子信号的总个数。
[167]其中, ^和』2的取值可以相同或不同。
[168]其中, 第二交换器的总个数 n2可以小于行译码器的输入信号也即行地址子 信号的总个数 m2, 则只有 n2个行地址子信号及其反相信号具有对应的第二交换 器;第二交换器的总个数 也可以等于行译码器的输入信号也即行地址子信号的 总个数 m2, 则每个行地址子信号及其反相信号具有对应的第二交换器。 其中, n2 的数值越接近 m2, 则本发明实施例的加密效果越好。
[169]其中, 本发明实施例中的第一信号可以为高电平信号, 则第二信号可以为低 电平信号; 或者, 第一信号可以为低电平信号, 则第二信号可以为高电平信号。
[170]其中, 随机数发生器可以包括: 具有至少 N3个比特位的线性反馈移位寄存 器, 线性反馈移位寄存器的任意两个比特位进行异或处理后得到的信号作为线性 反馈移位寄存器的移位输入信号; N3是非易失存储器中包括的第一变换器、第二 变换器和第三变换器的总个数;
[171]每个第一交换器、每个第二变换器和每个第三交换器分别与线性反馈移位寄 存器的一个比特位对应, 将对应比特位作为随机数发生器发送的选择信号。
[172]在本实施例中, 非易失存储器中的各个 bank存在四种可能的实现结构: 一、 bank的行译码器中未设置第二交换器, 列译码器中未设置第三交换器; 二、 bank 的行译码器中设置有第二交换器, 列译码器中未设置第三交换器; 三、 bank的行 译码器中未设置第二交换器, 列译码器中设置有第三交换器; 四、 bank的行译码 器中设置有第二交换器, 列译码器中设置有第三交换器。 但是, 非易失存储器中 至少一个 bank的行译码器中设置有第二交换器, 且至少一个 bank的列译码器中 设置有第三交换器。
[173]例如某个非易失存储器包括 4个 bank, bankl通过第二种可能的实现结构实 现, bank2 通过第四种可能的实现结构实现, bank3 通过第三种可能的实现结构 实现, bank4通过第一种可能的实现结构实现。
[174]对于 bank第一种可能的实现结构, 其与现有技术中 bank的实现结构相同, 这里不赘述; 对于 bank第二种可能的实现结构, 可以参考图 4所示 bank实现结 构举例,这里不赘述;对于 bank第三种可能的实现结构,可以参考图 5所示 bank 实现结构举例, 这里不赘述。
[175]以下通过图 6对 bank第四种可能的实现结构及其与随机数产生器之间的连 接关系进行说明。 而且, 在图 6示出的 bank结构图中设定: n2=m2, 第二交换器 与行译码器的行地址子信号依次对应, 也即 jf ; n3=m3, 第三交换器与列译码 器的列地址子信号依次对应, 也即 kfl^; 其中,
[176]随机数发生器 13用于: 在非易失存储器上电时, 分别为各个第二交换器和 第三交换器随机生成选择信号, 将生成的选择信号发送至对应的第二交换器和第 三交换器;
[177]行译码器中第二信号生成器 1121、 第二交换器 1123、 第二译码器 1122的描 述请参考图 4所示实例中关于第二信号生成器、 第二交换器和第二译码器的相关 描述; 列译码器中第三信号生成器 1131、 第三交换器 1133、 第三译码器 1132的 描述请参考图 5所示实例中关于第三信号生成器、 第三交换器和第三译码器的相 关描述, 这里不赘述。
[178]如图 6A所示, 本实施例中的随机数发生器 13可以包括: 具有 N3个比特位 的线性反馈移位寄存器 133, 线性反馈移位寄存器 133的 bitO和 bitl两个比特位 进行异或处理后得到的信号作为线性反馈移位寄存器的移位输入信号; 每个第一交换器、 每个第二交换器和每个第三交换器分别与线性反馈移位寄存器 133的一个比特位对应, 将对应的比特位作为随机数发生器 13发送的选择信号。
[179]其中, N3是非易失存储器中所有第一交换器、 第二交换器和第三交换器的 总个数。
[180]图 6A中虽然仅示出了 bitO和 bitl两个比特位进行异或处理得到移位输入信 号的实现方式, 但是, 在实际应用中可以将线性反馈移位寄存器 133的任意两个 比特位的信号进行异或处理得到移位输入信号, 这里不限定。
[181]图 6A中未示出第一交换器、 第二交换器和第三交换器与每个比特位之间的 对应关系, 仅以交换器代称第一交换器、 第二交换器和第三交换器。 在实际应用 中, 第一交换器、 第二交换器、 第三交换器与每个比特位之间的对应关系可以自 主设定, 这里不限制。
[182]在实际应用中,不同 bank中设置的第二交换器的数量 n2可以不同,不同 bank 的 、 j2等可以取相同或不同的数值, 不同 bank中设置的第三交换器的数量 n3 可以不同, 不同 bank的 k2等可以取相同或不同的数值, 这里并不限定。 其 他 bank 中在行译码器中设置第二交换器、 在列译码器中设置第三交换器后的结 构与图 5 中 bank的结构类似, 区别仅在于 n2、 n3、 j2、 k2的取值可能不 同, 某些行地址子信号可能不存在对应的第二交换器, 某些列地址子信号可能不 存在对应的第三交换器。
[183]图 6和图 6A所示的非易失存储器实现结构仅为具体实例, 本领域技术人员 根据该实例, 依照为 bank地址译码器中至少一个 bank地址子信号及其反相信号 设置前述的第一交换器、 为至少一个 bank 的行译码器中的至少一个行地址子信 号及其反相信号设置前述的第二交换器、 为至少一个 bank 的列译码器中的至少 一个列地址子信号及其反相信号设置前述的第三交换器等原则对该实例进行合 理变形, 得到本实施例包括 2〜无穷大个 bank的非易失存储器的各种实现结构, 这里不再一一赘述。
[184]本实施例相对于第二实施例,随机数发生器在非易失存储器上电时产生选择 信号, 除了控制第一变换器、 第二变换器外, 还控制 bank 中的各个第三变换器 将对应的列地址子信号及其反相信号保持不变或者互换, 使得列译码器中实际输 出的列选通信号与列地址子信号原来对应的列选通信号相同或不同, 当非易失存 储器下电后再上电时, 由于随机数发生器产生选择信号的随机性, 使得非易失存 储器下电后再上电时与非易失存储器下电前相比, 同样的 bank地址子信号所对 应的 bank选通信号不同, 同样的行地址子信号所对应的行选通信号不同, 同样 的列地址子信号所对应的列选通信号不同, 从而使得非易失存储器下电前存储的 数据在非易失存储器下电后再上电时被打乱, 达到加密效果, 使得存储至非易失 存储器的数据无法按照原来的存储地址顺序读取, 从而使得其他人即便使用软件 工具直接读取非易失存储器中的存储数据时也无法获得原始数据, 难以将非易失 存储器中存储的数据恢复成原始数据, 保证非易失存储器中存储数据的安全性。
[185]在本发明非易失存储器第五实施例中, 非易失存储器包括: 至少一个 bank, 每个 bank包括存储阵列、 存储阵列的行译码器和列译码器, 还包括: 随机数发 生器, 至少一个 bank还包括: 设置于行译码器的第二信号生成器与第二译码器 之间的 个第二交换器, 每个第二交换器对应行译码器的一个行地址子信号; 其 中,
[186]随机数发生器, 用于在非易失存储器上电时, 分别为各个第二交换器随机生 成选择信号, 将生成的选择信号发送至对应的第二交换器;
[187]每个 bank的第 ^个第二交换器, 用于接收第 ^个第二交换器对应的第 j2个 行地址子信号以及第 j2个行地址子信号的反相信号; 当接收到随机数发生器发送 的选择信号为第三信号时,将第 j2个行地址子信号作为行译码器的第 j2个行地址 子信号输出至第二译码器, 将第 j2个行地址子信号的反相信号作为行译码器的第 j2个行地址子信号的反相信号输出至第二译码器; 当接收到随机数发生器发送的 选择信号为第四信号时, 将第 j2个行地址子信号的反相信号作为行译码器的第 j2 个行地址子信号输出至第二译码器, 将第 j2个行地址子信号作为行译码器的第 j2 个行地址子信号的反相信号输出至第二译码器; 1 ^ η2 ; l ^j2^ m2 , l ^ n2^ m2, m2是第 个第二交换器所属行译码器的行地址子信号的总个数。
[188]其中, ^和』2的取值可以相同或不同。
[189]其中, 第二交换器的总个数 n2可以小于行译码器的输入信号也即行地址子 信号的总个数 m2, 则只有 n2个行地址子信号及其反相信号具有对应的第二交换 器;第二交换器的总个数 也可以等于行译码器的输入信号也即行地址子信号的 总个数 m2, 则每个行地址子信号及其反相信号具有对应的第二交换器。 其中, n2 的数值越接近 m2, 则本发明实施例的加密效果越好。
[190]其中, 本发明实施例中的第一信号可以为高电平信号, 则第二信号可以为低 电平信号; 或者, 第一信号可以为低电平信号, 则第二信号可以为高电平信号。
[191]其中, 随机数发生器可以包括: 具有至少 N4个比特位的线性反馈移位寄存 器, 线性反馈移位寄存器的任意两个比特位进行异或处理后得到的信号作为线性 反馈移位寄存器的移位输入信号; N4为非易失存储器包括的第二交换器的总个 数;
[192]每个第二交换器分别与线性反馈移位寄存器的一个比特位对应,将对应比特 位作为随机数发生器发送的选择信号。
[193]在本实施例中, 非易失存储器可以仅包括 1个 bank, 例如图 7所示, 但是 图 7中未示出行译码器中设置第二交换器的具体实现结构, 这时非易失存储器中 可以不设置 bank译码器; 非易失存储器也可以包括两个或者两个以上的 bank, 这时非易失存储器中一般设置有 bank译码器, 例如 7A所示, 但是图 7中未示出 行译码器中设置第二交换器的具体实现结构。 当非易失存储器中设置 bank译码 器时, bank 译码器中可以不设置第一交换器, 也可以设置第一交换器。 当 bank 译码器中设置第一交换器时, 其实现与第二实施例的非易失存储器结构相似, 因 此, 本实施例中仅说明非易失存储器中不包括 bank译码器或者 bank译码器中不 设置第一交换器, 通过现有技术中的结构实现的情况。
[194]在本实施例中, 非易失存储器中的 bank存在两种可能的实现结构: 一、 行 译码器中未设置第二交换器; 二、 行译码器中设置第二交换器。 但是, 非易失存 储器中至少一个 bank通过第二种可能的实现结构实现。
[195]对于 bank的第一种可能的实现结构,其与现有技术中 bank的实现结构相同, 这里不赘述。
[196]对于 bank的第二种可能的实现结构举例,可以参考图 4所举例的 bank实现 结构及其说明。
[197]其中, 本实施例中随机数发生器的实现也可以参考图 3A所示的随机数发生 器实例, 区别仅在于本实施例中随机数发生器的比特位数可以为 N4, 且每个比特 位连接的是第二交换器。
[198]在实际应用中, 不同 bank的第二交换器的数量 n2可以不同, 不同 bank的 j i j2等可以取相同或不同的数值, 这里并不限定。 其他 bank中在行译码器中设 置第二交换器后的结构与图 4中 bank的结构类似, 区别仅在于 n2的取值可能不 同, 、 的取值可能不同, 某些行地址子信号可能不存在对应的第二交换器, 这里不赘述。
[199]本领域技术人员根据上述实例, 依照为至少一个 bank的行译码器中的至少 一个行地址子信号及其反相信号设置前述的第二交换器等原则对上述实例进行 合理变形, 可以得到本发明实施例包括任意个数个 bank 的非易失存储器的各种 实现结构, 这里不再一一赘述。
[200]本实施例中, 随机数发生器在非易失存储器上电时产生选择信号, 控制各个 第二变换器将对应的行地址子信号及其反相信号保持不变或者互换, 当非易失存 储器下电后再上电时, 由于随机数发生器产生选择信号的随机性, 使得非易失存 储器下电后再上电时与非易失存储器下电前相比, 同样的行地址子信号所对应的 行选通信号不同, 从而使得非易失存储器下电前存储的数据在非易失存储器下电 后再上电时被打乱, 达到加密效果, 使得存储至非易失存储器的数据无法按照原 来的存储地址顺序读取, 从而使得其他人即便使用软件工具直接读取非易失存储 器中的存储数据时也无法获得原始数据, 难以将非易失存储器中存储的数据恢复 成原始数据, 保证非易失存储器中存储数据的安全性。
[201]本发明非易失存储器第六实施例中, 在第五实施例非易失存储器基础上, 非 易失存储器中至少一个 bank还包括: 设置于列译码器的第三信号生成器与第三 译码器之间的 n3个第三交换器,一个第三交换器对应列译码器的一个列地址子信 号; 其中, 随机数发生器还用于: 在非易失存储器上电时, 分别为各个第三交换 器随机生成选择信号, 将生成的选择信号发送至对应的第三交换器;
[202]每个 bank的第 1^个第三交换器, 用于接收第 1^个第三交换器对应的第 k2 个列地址子信号以及第 k2个列地址子信号的反相信号;当接收到随机数发生器发 送的选择信号为第五信号时, 将第 k2个列地址子信号作为列译码器的第 k2个列 地址子信号输出至第三译码器,将第 k2个列地址子信号的反相信号作为行列码器 的第 k2个列地址子信号的反相信号输出至第三译码器;当接收到随机数发生器发 送的选择信号为第六信号时,将第 k2个列地址子信号的反相信号作为列译码器的 第 k2个列地址子信号输出至第三译码器, 将第 k2个列地址子信号作为列译码器 的第 k2个列地址子信号的反相信号输出至第三译码器; 1 1^ 1 3, l k2 m3, l ^ n3^ m3 , m3是第 个第三交换器所属列译码器的列地址子信号的总个数。
[203]其中, 和1¾的取值可以相同或不同。
[204]其中, 第三交换器的总个数 n3可以小于列译码器的输入信号也即列地址子 信号的总个数 m3, 则只有 n3个列地址子信号及其反相信号具有对应的第三交换 器;第三交换器的总个数 n3也可以等于列译码器的输入信号也即列地址子信号的 总个数 m3, 则每个列地址子信号及其反相信号具有对应的第三交换器。 其中, n3 的数值越接近 m3, 则本发明实施例的加密效果越好。
[205]其中, 本发明实施例中的第五信号可以为高电平信号, 则第六信号可以为低 电平信号; 或者, 第五信号可以为低电平信号, 则第六信号可以为高电平信号。
[206]其中, 随机数发生器可以包括: 具有至少 N5个比特位的线性反馈移位寄存 器, 线性反馈移位寄存器的任意两个比特位进行异或处理后得到的信号作为线性 反馈移位寄存器的移位输入信号; N5是非易失存储器包括的第二交换器和第三交 换器的总个数; 每个第二交换器和每个第三交换器分别与线性反馈移位寄存器的 一个比特位对应, 将对应比特位作为随机数发生器发送的选择信号。
[207]在本实施例中, 非易失存储器仅包括 1个 bank时可以不设置 bank译码器, 非易失存储器包括两个或者两个以上的 bank时可以设置 bank译码器, 这里并不 限定。 当非易失存储器中设置 bank译码器时, bank译码器中可以不设置第一交 换器, 或者也可以设置第一交换器。 当 bank译码器中设置第一交换器时, 其实 现与第二实施例的非易失存储器结构相似, 因此, 本实施例中仅说明非易失存储 器中不包括 bank译码器或者 bank译码器中不设置第一交换器, 通过现有技术中 的结构实现的情况。
[208]在本实施例中,非易失存储器中包括的各个 bank存在四种可能的实现结构: 一、 bank的行译码器中未设置第二交换器, 列译码器中未设置第三交换器; 二、 bank的行译码器中设置有第二交换器, 列译码器中未设置第三交换器; 三、 bank 的行译码器中未设置第二交换器, 列译码器中设置有第三交换器; 四、 bank的行 译码器中设置有第二交换器, 列译码器中设置有第三交换器。 但是, 非易失存储 器中至少一个 bank的行译码器中设置有第二交换器, 且至少一个 bank的列译码 器中设置有第三交换器。
[209]例如某个非易失存储器包括 4个 bank, bankl通过第二种可能的实现结构实 现, bank2 通过第四种可能的实现结构实现, bank3 通过第三种可能的实现结构 实现, bank4通过第一种可能的实现结构实现。
[210]对于 bank第一种可能的实现结构, 其与现有技术中 bank的实现结构相同, 这里不赘述; 对于 bank第二种可能的实现结构, 可以参考图 4所示 bank实现结 构举例,这里不赘述;对于 bank第三种可能的实现结构,可以参考图 5所示 bank 实现结构举例, 这里不赘述。
[211]对于 bank第四种可能的实现结构,可以参考图 6所举例的 bank实现结构及 其说明。
[212]其中, 本实施例中随机数发生器的实现也可以参考图 3A所示的随机数发生 器实例, 区别仅在于本实施例中随机数发生器的比特位数可以为 N5, 且每个比特 位连接的是第二交换器或者第三交换器。
[213]在实际应用中,不同 bank中设置的第二交换器的数量 n2可以不同,不同 bank 的 、 j2等可以取相同或不同的数值, 不同 bank中设置的第三交换器的数量 n3 可以不同, 不同 bank的 k2等可以取相同或不同的数值, 这里并不限定。 其 他 bank 中在行译码器中设置第二交换器、 在列译码器中设置第三交换器后的结 构与图 6中 bank的结构类似, 区别仅在于 n2、 n3、 j2、 k2的取值可能不 同、 某些行译码器中的行地址子信号可能不存在对应的第二交换器、 某些列译码 器中的列地址子信号可能不存在对应的第三交换器。
[214]本领域技术人员根据本实施例及其实例, 依照为至少一个 bank的行译码器 中的至少一个行地址子信号及其反相信号设置前述的第二交换器、 为至少一个 bank 的列译码器中的至少一个列地址子信号及其反相信号设置前述的第三交换 器等原则对该实例进行合理变形, 得到本实施例包括任意个数个 bank 的非易失 存储器的各种实现结构, 这里不再一一赘述。
[215]本实施例相对于第五实施例,随机数发生器在非易失存储器上电时产生选择 信号, 除了控制第二变换器外, 还控制各个第三变换器将对应的列地址子信号及 其反相信号保持不变或者互换, 当非易失存储器下电后再上电时, 由于随机数发 生器产生选择信号的随机性, 使得非易失存储器下电后再上电时与非易失存储器 下电前相比, 同样的行地址子信号所对应的行选通信号不同, 同样的列地址子信 号所对应的列选通信号不同, 从而使得非易失存储器下电前存储的数据在非易失 存储器下电后再上电时被打乱, 达到加密效果, 使得存储至非易失存储器的数据 无法按照原来的存储地址顺序读取, 从而使得其他人即便使用软件工具直接读取 非易失存储器中的存储数据时也无法获得原始数据, 难以将非易失存储器中存储 的数据恢复成原始数据, 保证非易失存储器中存储数据的安全性。
[216]在本发明非易失存储器第七实施例中, 非易失存储器包括: 至少一个 bank, 每个 bank包括存储阵列、 存储阵列的行译码器和列译码器。 该非易失存储器还 包括: 随机数发生器, 至少一个 bank还包括: 设置于列译码器的第三信号生成 器与第三译码器之间的 n3个第三交换器,一个第三交换器对应列译码器的一个列 地址子信号; 其中, 随机数发生器, 用于在非易失存储器上电时, 分别为各个第 三交换器随机生成选择信号, 将生成的选择信号发送至对应的第三交换器;
[217]每个 bank的第 1^个第三交换器, 用于接收第 1^个第三交换器对应的第 k2 个列地址子信号以及第 k2个列地址子信号的反相信号;当接收到随机数发生器发 送的选择信号为第五信号时, 将第 k2个列地址子信号作为列译码器的第 k2个列 地址子信号输出至第三译码器,将第 k2个列地址子信号的反相信号作为行列码器 的第 k2个列地址子信号的反相信号输出至第三译码器;当接收到随机数发生器发 送的选择信号为第六信号时,将第 k2个列地址子信号的反相信号作为列译码器的 第 k2个列地址子信号输出至第三译码器, 将第 k2个列地址子信号作为列译码器 的第 k2个列地址子信号的反相信号输出至第三译码器; 1 1^ 1 3, l k2 m3, l ^ n3^ m3 , m3是第 个第三交换器所属列译码器的列地址子信号的总个数。
[218]其中, 和1¾的取值可以相同或不同。
[219]其中, 第三交换器的总个数 n3可以小于列译码器的输入信号也即列地址子 信号的总个数 m3, 则只有 n3个列地址子信号及其反相信号具有对应的第三交换 器;第三交换器的总个数 n3也可以等于列译码器的输入信号也即列地址子信号的 总个数 m3, 则每个列地址子信号及其反相信号具有对应的第三交换器。 其中, n3 的数值越接近 m3, 则本发明实施例的加密效果越好。
[220]其中, 本发明实施例中的第五信号可以为高电平信号, 则第六信号可以为低 电平信号; 或者, 第五信号可以为低电平信号, 则第六信号可以为高电平信号。
[221]随机数发生器可以包括: 具有至少 N6个比特位的线性反馈移位寄存器, 线 性反馈移位寄存器的任意两个比特位进行异或处理后得到的信号作为线性反馈 移位寄存器的移位输入信号; N6为非易失存储器中包括第三选择器的总个数;
[222]每个第三交换器分别与线性反馈移位寄存器的一个比特位对应,将对应比特 位作为随机数发生器发送的选择信号。
[223]在本实施例中, 非易失存储器仅包括 1个 bank时可以不设置 bank译码器, 非易失存储器包括两个或者两个以上的 bank时可以设置 bank译码器, 这里并不 限定。 当非易失存储器中设置 bank译码器时, bank译码器中可以不设置第一交 换器, 或者也可以设置第一交换器。 当 bank译码器中设置第一交换器时, 其实 现与第二实施例的非易失存储器结构相似, 因此, 本实施例中仅说明非易失存储 器中不包括 bank译码器或者 bank译码器中不设置第一交换器, 通过现有技术中 的结构实现的情况。
[224]在本实施例中, 非易失存储器中的 bank存在两种可能的实现结构: 一、 列 译码器中未设置第三交换器; 二、 列译码器中设置第三交换器。 但是, 非易失存 储器中至少一个 bank通过第二种可能的实现结构实现。
[225]对于 bank的第一种可能的实现结构,其与现有技术中 bank的实现结构相同, 这里不赘述。
[226]对于 bank的第二种可能的实现结构举例,可以参考图 5所举例的 bank实现 结构及其说明。
[227]其中, 本实施例中随机数发生器的实现也可以参考图 3A所示的随机数发生 器实例, 区别仅在于本实施例中随机数发生器的比特位数可以为 N6, 且每个比特 位连接的是第三交换器。
[228]在实际应用中, 不同 bank的第三交换器的数量 n3可以不同, 不同 bank的 ki、 k2等可以取相同或不同的数值, 这里并不限定。 其他 bank中在列译码器中设 置第三交换器后的结构与图 5中 bank的结构类似, 区别仅在于 n2的取值可能不 同, ji、 的取值可能不同, 某些列地址子信号可能不存在对应的第三交换器, 这里不赘述。
[229]本领域技术人员根据上述实例, 依照为至少一个 bank的列译码器中的至少 一个列地址子信号及其反相信号设置前述的第三交换器等原则对上述实例进行 合理变形, 可以得到本发明实施例包括任意个数个 bank 的非易失存储器的各种 实现结构, 这里不再一一赘述。
[230]本实施例中,随机数发生器在非易失存储器上电时产生选择信号,控制 bank 中的各个第三变换器将对应的列地址子信号及其反相信号保持不变或者互换, 当 非易失存储器下电后再上电时, 由于随机数发生器产生选择信号的随机性, 使得 非易失存储器下电后再上电时与非易失存储器下电前相比, 同样的列地址子信号 所对应的列选通信号不同, 从而使得非易失存储器下电前存储的数据在非易失存 储器下电后再上电时被打乱, 达到加密效果, 使得存储至非易失存储器的数据无 法按照原来的存储地址顺序读取, 从而使得其他人即便使用软件工具直接读取非 易失存储器中的存储数据时也无法获得原始数据, 难以将非易失存储器中存储的 数据恢复成原始数据, 保证非易失存储器中存储数据的安全性。
[231]其中, 本发明实施例中非易失存储器可以具体为相变存储器、可变电阻式存 储器 (ReRAM) 等。
[232]另外, 本发明实施例还提供一种电子设备, 包括上述任一实施例的非易失存 储器。
[233]本说明书中的各个实施例均采用递进的方式描述,各个实施例之间相同相似 的部分互相参见即可, 每个实施例重点说明的都是与其他实施例的不同之处。 尤 其, 对于系统实施例而言, 由于其基本相似于方法实施例, 所以描述的比较简单, 相关之处参见方法实施例的部分说明即可。
[234]以上的本发明实施方式, 并不构成对本发明保护范围的限定。任何在本发明 的精神和原则之内所作的修改、 等同替换和改进等, 均应包含在本发明的保护范 围之内。

Claims

权 利 要 求
1、 一种非易失存储器, 所述非易失存储器包括 bank译码器、 以及至少 两个存储体 bank, 所述 bank包括存储阵列、 存储阵列的行译码器和存储阵 列的列译码器, 其特征在于, 所述非易失存储器还包括: 随机数发生器、 设 置于 bank译码器的第一信号生成器与第一译码器之间的!^个第一交换器, 一个所述第一交换器对应所述 bank译码器的一个 bank地址子信号; 其中, 所述随机数发生器, 用于在非易失存储器上电时, 分别为各个第一交换 器随机生成选择信号, 将生成的选择信号发送至所述选择信号对应的第一交 换器;
所述 bank译码器的第 ^个第一交换器, 用于接收与所述第 ^个第一交 换器对应的第 i2个 bank地址子信号以及所述第 i2个 bank地址子信号的反相 信号; 当接收到的选择信号为第一信号时, 将所述第 i2个 bank地址子信号 作为所述第 i2个 bank地址子信号输出至第一译码器, 将所述第 i2个 bank地 址子信号的反相信号作为所述第 i2个 bank地址子信号的反相信号输出至第 一译码器; 当接收到的选择信号为第二信号时, 将所述第 i2个 bank地址子 信号的反相信号作为所述第 i2个 bank地址子信号输出至第一译码器, 将所 述第 i2个 bank地址子信号作为所述第 i2个 bank地址子信号的反相信号输出 至第一译码器; K rn ; l ^i2^ mi , l ^m ^ mi , nu是 bank地址子信号的 总个数。
2、 根据权利要求 1所述的非易失存储器, 其特征在于, 至少一个 bank 还包括:设置于行译码器的第二信号生成器与第二译码器之间的 个第二交 换器, 一个第二交换器对应行译码器的一个行地址子信号; 其中,
所述随机数发生器还用于: 在非易失存储器上电时, 分别为各个第二交 换器随机生成选择信号, 将生成的选择信号发送至所述选择信号对应的第二 交换器;
每个 bank的第 ^个第二交换器, 用于接收与所述第 ^个第二交换器对 应的第 j2个行地址子信号以及所述第 j2个行地址子信号的反相信号; 当接收 到的选择信号为第三信号时, 将所述第 j2个行地址子信号作为所述第 j2个行 地址子信号输出至第二译码器, 将所述第 j2个行地址子信号的反相信号作为 所述第 j2个行地址子信号的反相信号输出至第二译码器; 当接收到的选择信 号为第四信号时, 将所述第 j2个行地址子信号的反相信号作为所述第 j2个行 地址子信号输出至第二译码器, 将所述第 j2个行地址子信号作为所述第 j2个 行地址子信号的反相信号输出至第二译码器; Kji n^ l ^j2^ m2 , l ^ n2 m2, m2是所述第^个第二交换器所属行译码器的行地址子信号的总个数。
3、 根据权利要求 1所述的非易失存储器, 其特征在于, 至少一个 bank 还包括:设置于列译码器的第三信号生成器与第三译码器之间的 n3个第三交 换器, 一个第三交换器对应列译码器的一个列地址子信号; 其中,
所述随机数发生器还用于: 在非易失存储器上电时, 分别为各个第三交 换器随机生成选择信号, 将生成的选择信号发送至所述选择信号对应的第三 交换器;
每个 bank的第 个第三交换器,用于接收所述第 个第三交换器对应 的第 k2个列地址子信号以及所述第 k2个列地址子信号的反相信号; 当接收 到的选择信号为第五信号时, 将所述第 k2个列地址子信号作为所述第 k2个 列地址子信号输出至第三译码器,将所述第 k2个列地址子信号的反相信号作 为所述第 k2个列地址子信号的反相信号输出至第三译码器; 当接收到的选择 信号为第六信号时, 将所述第 k2个列地址子信号的反相信号作为所述第 k2 个列地址子信号输出至第三译码器,将所述第 k2个列地址子信号作为所述第 k2个列地址子信号的反相信号输出至第三译码器; 1 1^ 1 3, l k2 m3, 1 ^ n3^ m3 , m3是所述第 个第三交换器所属列译码器的列地址子信号的总 个数。
4、 根据权利要求 2所述的非易失存储器, 其特征在于, 至少一个 bank 还包括:设置于列译码器的第三信号生成器与第三译码器之间的 n3个第三交 换器, 一个第三交换器对应列译码器的一个列地址子信号; 其中,
所述随机数发生器还用于: 在非易失存储器上电时, 分别为各个第三交 换器随机生成选择信号, 将生成的选择信号发送至所述选择信号对应的第三 交换器;
每个 bank的第 个所述第三交换器,用于接收所述第 个第三交换器 对应的第 k2个列地址子信号以及所述第 k2个列地址子信号的反相信号; 当 接收到的选择信号为第五信号时, 将所述第 k2个列地址子信号作为所述第 k2个列地址子信号输出至第三译码器,将所述第 k2个列地址子信号的反相信 号作为所述第 k2个列地址子信号的反相信号输出至第三译码器; 当接收到的 选择信号为第六信号时,将所述第 k2个列地址子信号的反相信号作为所述第 k2个列地址子信号输出至第三译码器,将所述第 k2个列地址子信号作为所述 第 k2个列地址子信号的反相信号输出至第三译码器; 1 1^ 1 3, l k2 m3, l ^ n3^ m3 , m3是所述第1^个第三交换器所属列译码器的列地址子信号的总 个数。
5、 根据权利要求 1所述的非易失存储器, 其特征在于, 所述随机数发 生器包括: 至少 位的线性反馈移位寄存器, 所述线性反馈移位寄存器的任 意两个比特位进行异或处理后得到的信号作为所述线性反馈移位寄存器的 移位输入信号;
所述 个第一交换器分别与所述线性反馈移位寄存器的一个比特位对 应, 将对应比特位作为所述随机数发生器发送的选择信号。
6、 根据权利要求 2所述的非易失存储器, 其特征在于, 所述随机数发 生器包括: 具有至少^个比特位的线性反馈移位寄存器,所述线性反馈移位 寄存器的任意两个比特位进行异或处理后得到的信号作为所述线性反馈移 位寄存器的移位输入信号; 是非易失存储器中包括的第一交换器以及第二 交换器的总个数;
每个所述第一交换器和每个所述第二交换器分别与所述线性反馈移位 寄存器的一个比特位对应, 将对应比特位作为所述随机数发生器发送的选择 信号。
7、 根据权利要求 3所述的非易失存储器, 其特征在于, 所述随机数发 生器包括: 具有至少 N2个比特位的线性反馈移位寄存器,所述线性反馈移位 寄存器的任意两个比特位进行异或处理后得到的信号作为所述线性反馈移 位寄存器的移位输入信号; N2是非易失存储器中包括的第一变换器和第三变 换器的总个数;
每个所述第一交换器和每个所述第三交换器分别与所述线性反馈移位 寄存器的一个比特位对应, 将对应比特位作为所述随机数发生器发送的选择 信号。
8、 根据权利要求 4所述的非易失存储器, 其特征在于, 所述随机数发 生器包括: 具有至少 N3个比特位的线性反馈移位寄存器,所述线性反馈移位 寄存器的任意两个比特位进行异或处理后得到的信号作为所述线性反馈移 位寄存器的移位输入信号; N3是非易失存储器中包括的第一变换器、 第二变 换器和第三变换器的总个数;
每个所述第一交换器、每个所述第二交换器和每个所述第三交换器分别 与所述线性反馈移位寄存器的一个比特位对应, 将对应比特位作为所述随机 数发生器发送的选择信号。
9、 一种非易失存储器, 所述非易失存储器包括至少一个存储体 bank, 每个所述 bank包括存储阵列、 存储阵列的行译码器和存储阵列的列译码器, 其特征在于, 还包括: 随机数发生器, 至少一个所述 bank还包括: 设置于行 译码器的第二信号生成器与第二译码器之间的 n2个第二交换器,一个第二交 换器对应行译码器的一个行地址子信号; 其中,
所述随机数发生器, 用于在非易失存储器上电时, 分别为各个第二交换 器随机生成选择信号, 将生成的选择信号发送至所述选择信号对应的第二交 换器;
每个 bank的第 ^个第二交换器, 用于接收所述第^个第二交换器对应 的第 j2个行地址子信号以及所述第 j2个行地址子信号的反相信号; 当接收到 的选择信号为第三信号时, 将所述第 j2个行地址子信号作为所述第 j2个行地 址子信号输出至第二译码器, 将所述第 j2个行地址子信号的反相信号作为所 述第 j2个行地址子信号的反相信号输出至第二译码器; 当接收到的选择信号 为第四信号时, 将所述第 j2个行地址子信号的反相信号作为所述第 j2个行地 址子信号输出至第二译码器, 将所述第 j2个行地址子信号作为所述第 j2个行 地址子信号的反相信号输出至第二译码器; Kji n^ l ^j2^ m2 , l ^ n2^ m2, m2是所述第^个第二交换器所属行译码器的行地址子信号的总个数。
10、 根据权利要求 9所述的非易失存储器, 其特征在于, 至少一个所述 bank还包括:设置于列译码器的第三信号生成器与第三译码器之间的 n3个第 三交换器, 一个第三交换器对应列译码器的一个列地址子信号; 其中,
所述随机数发生器还用于: 在非易失存储器上电时, 分别为各个第三交 换器随机生成选择信号, 将生成的选择信号发送至所述选择信号对应的第三 交换器;
每个 bank的第 个所述第三交换器,用于接收所述第 个第三交换器 对应的第 k2个列地址子信号以及所述第 k2个列地址子信号的反相信号; 当 接收到的选择信号为第五信号时, 将所述第 k2个列地址子信号作为所述第 k2个列地址子信号输出至第三译码器,将所述第 k2个列地址子信号的反相信 号作为所述第 k2个列地址子信号的反相信号输出至第三译码器; 当接收到的 选择信号为第六信号时,将所述第 k2个列地址子信号的反相信号作为所述第 k2个列地址子信号输出至第三译码器,将所述第 k2个列地址子信号作为所述 第 k2个列地址子信号的反相信号输出至第三译码器; 1 1^ 1 3, l k2 m3, l ^n3^ m3 , m3是所述第1^个第三交换器所属列译码器的列地址子信号的总 个数。
11、 根据权利要求 9所述的非易失存储器, 其特征在于, 所述随机数发 生器包括: 具有至少 N4个比特位的线性反馈移位寄存器, 所述线性反馈移 位寄存器的任意两个比特位进行异或处理后得到的信号作为所述线性反馈 移位寄存器的移位输入信号; N4为非易失存储器包括的第二交换器的总个 数;
每个所述第二交换器分别与所述线性反馈移位寄存器的一个比特位对 应, 将对应比特位作为所述随机数发生器发送的选择信号。
12、 根据权利要求 10所述的非易失存储器, 其特征在于, 所述随机数 发生器包括: 具有至少 N5个比特位的线性反馈移位寄存器,所述线性反馈移 位寄存器的任意两个比特位进行异或处理后得到的信号作为所述线性反馈 移位寄存器的移位输入信号; N5是非易失存储器包括的第二交换器和第三交 换器的总个数;
每个所述第二交换器和每个所述第三交换器分别与所述线性反馈移位 寄存器的一个比特位对应, 将对应比特位作为所述随机数发生器发送的选择 信号。
13、 一种非易失存储器, 所述非易失存储器包括至少一个存储体 bank, 每个所述 bank包括存储阵列、 存储阵列的行译码器和存储阵列的列译码器, 其特征在于, 还包括: 随机数发生器, 至少一个所述 bank还包括: 设置于列 译码器的第三信号生成器与第三译码器之间的 n3个第三交换器,一个第三交 换器对应列译码器的一个列地址子信号; 其中,
所述随机数发生器, 用于在非易失存储器上电时, 分别为各个第三交换 器随机生成选择信号, 将生成的选择信号发送至所述选择信号对应的第三交 换器;
每个 bank的第 个第三交换器,用于接收所述第 个第三交换器对应 的第 k2个列地址子信号以及所述第 k2个列地址子信号的反相信号; 当接收 到的选择信号为第五信号时, 将所述第 k2个列地址子信号作为所述第 k2个 列地址子信号输出至第三译码器,将所述第 k2个列地址子信号的反相信号作 为所述第 k2个列地址子信号的反相信号输出至第三译码器; 当接收到的选择 信号为第六信号时, 将所述第 k2个列地址子信号的反相信号作为所述第 k2 个列地址子信号输出至第三译码器,将所述第 k2个列地址子信号作为所述第 k2个列地址子信号的反相信号输出至第三译码器; 1 1^ 13, l k2 m3, 1 ^n3^m3, m3是所述第 个第三交换器所属列译码器的列地址子信号的总 个数。
14、 根据权利要求 13所述的非易失存储器, 其特征在于, 所述随机数 发生器包括: 具有至少 N6个比特位的线性反馈移位寄存器,所述线性反馈移 位寄存器的任意两个比特位进行异或处理后得到的信号作为所述线性反馈 移位寄存器的移位输入信号; N6为非易失存储器中包括第三选择器的总个 数;
每个所述第三交换器分别与所述线性反馈移位寄存器的一个比特位对 应, 将对应比特位作为所述随机数发生器发送的选择信号。
15、一种电子设备, 其特征在于, 包括权利要求 1至 14任一项所述的非 易失存储器。
PCT/CN2014/076595 2013-11-27 2014-04-30 非易失存储器及电子设备 WO2015078141A1 (zh)

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