WO2015074335A1 - 一种薄膜晶体管阵列基板及修补方法 - Google Patents

一种薄膜晶体管阵列基板及修补方法 Download PDF

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Publication number
WO2015074335A1
WO2015074335A1 PCT/CN2014/070838 CN2014070838W WO2015074335A1 WO 2015074335 A1 WO2015074335 A1 WO 2015074335A1 CN 2014070838 W CN2014070838 W CN 2014070838W WO 2015074335 A1 WO2015074335 A1 WO 2015074335A1
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Prior art keywords
electrode
pixel electrode
pixel
array substrate
sub
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English (en)
French (fr)
Inventor
衣志光
张骢泷
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/241,392 priority Critical patent/US20150137128A1/en
Publication of WO2015074335A1 publication Critical patent/WO2015074335A1/zh
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to liquid crystal display technology, and more particularly to a thin film transistor array substrate and a repairing method for a large-sized liquid crystal display panel. Background technique
  • the thin film transistor liquid crystal display panel is usually composed of a thin film transistor array substrate, a color filter substrate, and a liquid crystal layer.
  • a plurality of pixel units (Pixel) are arranged in an array on the thin film transistor array substrate, each pixel unit includes at least one thin film transistor, and a pixel electrode (Pixel Electrode) corresponding to the thin film transistor, and the thin film transistor is used as a thin film transistor
  • the switching element that starts the operation of the pixel unit is connected to the scan line (Scan Line) and the data line (Data Line), and the voltage of the data signal is loaded on the corresponding pixel electrode under the driving of the scan signal, thereby realizing the display of the image information.
  • a partial region of the pixel electrode is overlaid on the common line of the scan line or the substrate, and the overlapped portion is used as the storage capacitor Cst for stabilizing the voltage of the data signal loaded on the pixel electrode, thereby maintaining the picture. Display quality.
  • an upper electrode is disposed between each pixel electrode and its corresponding common electrode wiring.
  • a first dielectric layer is disposed between the upper electrode and the corresponding common electrode wiring to maintain isolation.
  • a second dielectric layer is disposed between the upper electrode and the corresponding pixel electrode, and the second layer is disposed. The dielectric layer opens a contact window at a corresponding position, and the upper electrode and the corresponding pixel electrode are electrically connected by the contact window.
  • the storage capacitor may leak or even fail, which may cause the pixel unit to display abnormality and affect the display quality of the screen.
  • the problem of partial repair of the thin film transistor array substrate in which the above problems occur is brought about.
  • the commonly used repair method is to cut off the electrical connection around the tantalum capacitor, so that the pixel unit where the tantalum capacitor is located fails and becomes a dark point. This repair method is quite cumbersome for a large-size thin film transistor liquid crystal display panel which is gradually becoming the mainstream in the market.
  • each pixel unit is configured with at least three thin film transistors. It is used to adjust the voltage difference between the main pixel electrode I (Main Pixel) and the sub-pixel electrode II (Sub Pixel) to improve the apparent role bias.
  • main pixel electrode I Main Pixel
  • sub-pixel electrode II Sub Pixel
  • the present invention provides a thin film transistor array substrate and a repairing method, and the pixel unit repaired according to the method can continue to work, and has little influence on the image quality of the image.
  • the present invention provides a method for repairing a thin film transistor array substrate, the array substrate comprising: a substrate;
  • each of the pixel units comprising: a main pixel electrode and a sub-pixel electrode , as well as
  • a charge sharing unit electrically connected to the main pixel electrode and the sub-pixel electrode, and including a charge capacitance for generating a voltage difference between the main pixel electrode and the sub-pixel electrode;
  • the repair method includes the following steps:
  • each pixel unit of the array substrate is electrically connected to two scan lines and one data line, wherein:
  • the main pixel electrode and the sub-pixel electrode are configured to receive the same voltage by respectively receiving data signals on the data line under the driving of the first scanning line scanning signal;
  • the charge sharing unit is configured to change a voltage of the sub-pixel electrode under a driving of a second scan line scan signal to cause a difference from a voltage of the main pixel electrode.
  • a laser may be used to fuse a line connecting the upper or lower electrode of the tantalum capacitor to the periphery thereof.
  • the upper electrode is a transparent conductive layer.
  • the upper electrode and the common electrode wiring are connected.
  • the lower electrode and the data line are formed by the same mask.
  • the invention also provides a thin film transistor array substrate, comprising:
  • each of the pixel units comprising: a main pixel electrode and a sub-pixel electrode , as well as
  • a charge sharing unit electrically connected to the main pixel electrode and the sub-pixel electrode, and including a charge capacitance for causing a voltage difference between the main pixel electrode and the sub-pixel electrode, when the charge capacitance is a tantalum capacitor,
  • the upper or lower electrode is disconnected from the surrounding line and electrically insulated.
  • each pixel unit of the array substrate is electrically connected to two scan lines and one data line, wherein:
  • the main pixel electrode and the sub-pixel electrode are configured to respectively receive data signals on the data line under the driving of the first scan line scan signal to have the same voltage;
  • the charge sharing unit is configured to change a voltage of the sub-pixel electrode under a driving of the second scanning line scan signal to cause a difference from a voltage of the main pixel electrode.
  • the above charge sharing unit includes:
  • the thin film transistor has a gate electrically connected to the second scan line, a drain electrically connected to the sub-pixel electrode, and a source coupled to the common electrode line to form the charge capacitor.
  • the source of the thin film transistor of the charge sharing unit may also be coupled to the main pixel electrode to form another charge capacitor.
  • the upper electrode may be a transparent conductive layer.
  • the upper electrode and the common electrode wiring are connected.
  • the lower electrode and the data line may be formed by the same reticle.
  • the repairing method provided by the invention can prevent the storage capacitor from being generated due to the hole of the particle or the dielectric layer. The situation of leakage is highly practical.
  • the repairing method provided by the invention is simple and quick to operate, and has little influence on the display effect.
  • the thin film transistor array substrate provided by the present invention can be fabricated in the same process as the drain and source of the thin film transistor and the data line during the fabrication process, and belongs to the second metal layer.
  • the upper electrode of the charge and capacitance can be formed in the same process as the common electrode wiring, and belongs to the first metal layer (M1), so that the manufacturing cost is low.
  • FIG. 1 is a schematic diagram of a conventional thin film transistor array substrate repairing method in the prior art
  • FIG. 2 is an equivalent circuit diagram of a 2G1D pixel unit structure on a liquid crystal display panel array substrate in the prior art
  • FIG. 3 is a schematic diagram of an embodiment of a method for repairing a thin film transistor array substrate provided by the present invention. Specific form
  • FIG. 2 it is an equivalent circuit diagram of a pixel unit disposed on a large-size liquid crystal display panel array substrate. Due to the charge sharing technique, the pixel electrode of the pixel unit is divided into a main pixel electrode I region and a sub-pixel electrode II region, and a charge sharing unit Sharing. among them:
  • the main pixel electrode I region includes a thin film transistor ⁇ , the gate of the thin film transistor ⁇ is electrically connected to the scan line Scan1, the source is electrically connected to the data line Data, the drain is electrically connected to the main pixel electrode I region; and the main pixel electrode I region
  • the electrically connected upper electrode (not shown in FIG. 2) and the corresponding common electrode wiring Com are shaped The storage capacitor Cstl and the liquid crystal capacitor Clcl.
  • the sub-pixel electrode II region includes a thin film transistor T2, the gate of the thin film transistor T2 is electrically connected to the scan line Scan1, the source is electrically connected to the data line Data, and the drain is electrically connected to the sub-pixel electrode II region; and the sub-pixel electrode II region A storage capacitor Cst2 and a liquid crystal capacitor Clc2 are formed between the electrically connected upper electrode (not shown in FIG. 2) and the corresponding common electrode wiring Com.
  • the charge sharing unit SHAR includes a thin film transistor T3.
  • the gate of the thin film transistor T3 is electrically connected to the scan line S C an2 , the drain is electrically connected to the pixel electrode II region, and the source is electrically connected to the main electrode of the main pixel electrode I.
  • a first charge capacitance Ccs1 is formed therebetween, and a second charge capacitance Ccs2 is formed between the source and the corresponding common electrode line Com.
  • the basic principle of the charge sharing technique is: First, when the scan signal is transmitted from the scan line Scan1, the drain and the source of the thin film transistor ⁇ and the thin film transistor T2 are turned on, so that the voltages of the main pixel electrode I region and the sub-pixel electrode region II are The data signal transmitted from the data line Data reaches the same potential by the data signal; then when the scan line S C an2 transmits the scan signal, the drain and the source of the thin film transistor ⁇ and the thin film transistor T2 are turned off, and the thin film transistor T3 is leaked.
  • the pole and the source are turned on, causing the charge on the sub-pixel electrode II region to be transferred to the common electrode wiring Com through the second charge capacitor Ccs2, causing a voltage difference between the voltage of the sub-pixel electrode II region and the voltage of the main pixel electrode I region. Further, the liquid crystal of the sub-pixel electrode II region and the liquid crystal of the main pixel electrode I region are deflected at different deflection angles, thereby achieving the technical effect of multi-domain display compensating for the large-view character bias.
  • the storage capacitor may leak.
  • the pixel unit displays an abnormality, which results in poor display quality. At this point, you need to patch the pixel unit where the exception occurred.
  • the thin film transistor ⁇ in the pixel unit and the data line Data are electrically connected by using a laser, and the thin film transistor ⁇ is electrically connected to the main pixel electrode I, and the thin film transistor T2 and the data line Data are Electrically connected, the thin film transistor T2 is electrically connected to the sub-pixel electrode II region, the electrical connection between the thin film transistor T3 and the sub-pixel electrode II region is cut off, and the upper electrode electrically connected to the main pixel electrode I region by using a laser, The upper electrodes electrically connected to the sub-pixel electrode II region are respectively welded to the corresponding common electrode wires.
  • the entire process steps are cumbersome, time consuming and energy consuming, and the sub-pixel electrode II area, which would otherwise work properly, is also affected and becomes a dark spot.
  • the skilled person of the present invention has made some improvements to the above-mentioned conventional repairing method based on the rich experience and professional knowledge accumulated in the design and manufacture of the liquid crystal panel, so that it is more practical.
  • the second charge capacitor Ccs2 in the above pixel unit leaks due to particles or holes.
  • the present invention proposes a new repairing method, that is, a repairing method of removing only the second charge capacitance Ccs2.
  • the entire pixel unit can still work normally, but it can not effectively solve the problem of large-view character bias, but it has little effect on the display function of the whole pixel unit, and it is difficult for the human eye to distinguish the change of the display effect before and after.
  • This repair method is different from the traditional repair method. The repair process is quicker and easier, and the pixel unit can still display images after the repair, which has great improvement in implementation methods and technical effects, and has wide application value. .
  • the lower electrode of the second charge capacitor Ccs2 is the source of each thin film transistor.
  • the drain electrode and the data line are formed together, and belong to the second metal layer (M2).
  • the upper electrode of the second charge capacitor Ccs2 is formed together with the common electrode wiring, and belongs to the first metal layer (M1). Therefore, the second charge capacitor Ccs2 can be a metal-insulating-metal structure formed by a metal line extending from the source of the thin film transistor T3 and a metal line extending from the common electrode line Com. Therefore, the present embodiment can adopt the following two types. The method removes the failed second charge capacitor Ccs2:
  • the metal wire connected between the upper electrode of the second charge capacitor Ccs2 and the common electrode wiring Com is disconnected by a laser (as shown in Figs. 2 and 3).
  • a pixel cell structure employing charge sharing techniques can have many variations, not limited to a configuration consisting of three thin film transistors.
  • the embodiments of the present invention have been described above, the described embodiments are merely for the purpose of understanding the invention and are not intended to limit the invention. Any modification and variation of the form and details of the invention may be made by those skilled in the art without departing from the spirit and scope of the invention. It is still subject to the scope defined by the appended claims.

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Abstract

一种薄膜晶体管阵列基板及修补方法，该阵列基板包括基板；多条共用电极配线配置于基板上；多条扫描线和数据线交错配置在基板上以形成多个像素区域；多个像素单元配置于像素区域内，每个像素单元包括主像素电极T1和次像素电极T2，以及电性连接主像素电极T1和次像素电极T2的电荷分享单元T3；其中，电荷分享单元T3包括用于使主像素电极T1与次像素电极T2产生电压差的电荷电容Ccs2。当电荷电容Ccs2为瑕疵电容时，将其上电极或下电极与其周围连接的线路断开。该修补方法不同于以往传统的修补手段，修补过程简单快捷，且修补之后像素单元仍然可以正常工作，只是不能有效解决大视角色偏问题，但是对整个像素单元的显示功能影响不大。

Description

一种薄膜晶体管阵列基板及修补旅
技术领域
本发明涉及液晶显示技术， 特别是关于一种大尺寸液晶显示面板的薄膜晶体 管阵列基板及修补方法。 背景技术
薄膜晶体管液晶显示面板 （TFT LCD ) 以其卓越的性能已经成为当前市场的 主流产品。 薄膜晶体管液晶显示面板通常由薄膜晶体管阵列基板、 彩色滤光片基 板和液晶层组成。 其中， 薄膜晶体管阵列基板上以阵列的形式排布有多个像素单 元 （Pixel ), 每一个像素单元至少包括一个薄膜晶体管， 以及与薄膜晶体管对应 配置的像素电极 （Pixel Electrode ) ,, 薄膜晶体管作为启动像素单元工作的开关 元件， 与扫描线 （Scan Line ) 和数据线 （Data Line ) 连接， 在扫描信号的驱动 下， 将数据信号的电压加载在对应的像素电极上， 从而实现图像信息的显示。 此 外， 像素电极的部分区域会覆盖在扫描线或基板的共用电极配线 （Common Line ) 上， 重叠的部分即作为存储电容 Cst， 用于稳定加载在像素电极的数据信号的电 压， 从而保持画面显示品质。 在目前主流的薄膜晶体管阵列基板制程中， 在每一 个像素电极与其对应的共用电极配线之间还会配置一上电极。 该上电极与对应的 共用电极配线之间配置有一第一介电层， 以保持性隔绝， 同时， 该上电极与对应 的像素电极之间也配置一第二介电层， 而此第二介电层会在对应的位置开设接触 窗， 藉由该接触窗使上电极与对应的像素电极实现电性连接。 当有粒子 (Particle ) 因为制程中的缺陷或者其他因素落入存储电容的介电层时， 会导致 存储电容漏电甚至失效，进而导致像素单元显示异常， 影响画面显示品质。 由此， 就引出了对出现上述问题的薄膜晶体管阵列基板进行局部修补的问题。 目前常用 的修补方法是切断瑕疵电容周围的电性连接， 使瑕疵电容所在的像素单元失效， 成为一个暗点。 这种修补方法对于目前逐渐成为市场主流的大尺寸薄膜晶体管液 晶显示面板而言， 颇为繁琐。 这是因为， 大尺寸液晶显示面板为解决大视角色偏 问题多采用一种电荷分享技术， 即，每一个像素单元配置有至少三个薄膜晶体管， 用于调节主像素电极 I区 （Main Pixel ) 和次像素电极 II区 （Sub Pixel ) 之间 的电压差异， 来改善视角色偏。 当有粒子落入存储电容的介电层时， 需要将存储 电容与像素电极之间的电性连接全部切断， 以及将存储电容的两极熔接， 使瑕疵 电容所在的像素单元失效， 成为暗点。 这种传统的修补方法在操作时步骤繁琐， 需要至少四次熔接和五次切断 （如图 1 所示）， 耗时耗能， 而且由于像素单元完 全失效， 成为暗点， 因此会影响画面成像品质。 为此， 亟需一种更加简便合理的 方法， 以取代上述传统的修补方法。 本发明的发明人正是基于从事液晶显示面板 设计制造的实务经验和相关的专业知识， 经过多次反复的实验研究， 得出一种更 加简单合理的修补方法， 根据该方法修补的像素单元能够继续工作， 对显示效果 影响较小。 发明内容
针对上述问题， 本发明提供了一种薄膜晶体管阵列基板及修补方法， 根据该 方法修补的像素单元能够继续工作， 对画面成像品质影响较小。
本发明提供一种薄膜晶体管阵列基板的修补方法， 所述阵列基板包括： 基板；
多条共用电极配线， 配置于所述基板上；
多条扫描线和数据线， 交错配置在所述基板上以形成多个像素区域； 多个像素单元， 配置于所述像素区域内， 每个所述像素单元包括： 主像素电极和次像素电极， 以及
电荷分享单元， 其电性连接所述主像素电极和次像素电极， 并包括用于使所 述主像素电极与次像素电极产生电压差的电荷电容；
当所述电荷电容为瑕疵电容时， 所述修补方法包括以下步骤：
将瑕疵电容的上电极或下电极与其周围连接的线路断开， 以形成电性绝缘。 根据本发明的实施例， 上述阵列基板的每一个像素单元电性连接两条扫描线 和一条数据线， 其中：
所述主像素电极和次像素电极， 配置以在第一条扫描线扫描信号的驱动下分 别接收数据线上的数据信号而具有相同的电压；
所述电荷分享单元， 配置以在第二条扫描线扫描信号的驱动下改变所述次像 素电极的电压， 使其与所述主像素电极的电压产生差异。 根据本发明的实施例， 可以利用激光将瑕疵电容的上电极或下电极与其周围 连接的线路熔断。
根据本发明的实施例， 上电极为透明导电层。
进一步地， 上电极和所述共用电极配线连接。
此外， 下电极和所述的数据线通过同一道光罩形成。
本发明还提供一种薄膜晶体管阵列基板， 其中包括：
基板；
多条共用电极配线， 配置于所述基板上；
多条扫描线和数据线， 交错配置在所述基板上以形成多个像素区域； 多个像素单元， 配置于所述像素区域内， 每个所述像素单元包括： 主像素电极和次像素电极， 以及
电荷分享单元， 其电性连接所述主像素电极和次像素电极， 并包括用于使所 述主像素电极与次像素电极产生电压差的电荷电容， 当所述电荷电容为瑕疵电容 时， 其上电极或下电极与其周围连接的线路断开而电性绝缘。
根据本发明的实施例， 上述阵列基板的每一个像素单元电性连接两条扫描线 和一条数据线， 其中：
所述主像素电极和次像素电极， 配置以在所述第一条扫描线扫描信号的驱动 下分别接收所述数据线上的数据信号而具有相同的电压；
所述电荷分享单元， 配置以在所述第二条扫描线扫描信号的驱动下改变所述 次像素电极的电压， 使其与所述主像素电极的电压产生差异。
具体地， 上述电荷分享单元包括：
薄膜晶体管， 其栅极电性连接所述第二条扫描线， 漏极电性连接所述次像素 电极， 源极与所述共用电极配线耦合形成所述电荷电容。
此外， 所述电荷分享单元的薄膜晶体管的源极还可以与所述主像素电极耦合 形成另一个电荷电容。
此外， 所述上电极可以为透明导电层。
进一步地， 上电极和所述共用电极配线连接。
此外， 所述下电极和所述的数据线可以通过同一道光罩形成。
本发明与现有技术相比具有以下明显的优点和有益效果：
1、 本发明提供的修补方法可以避免存储电容因为粒子或者介电层破洞而发 生泄漏的情形， 实用性高。
2、 本发明提供的修补方法操作简单快捷， 对显示效果影响较小。
3、 本发明提供的薄膜电晶体阵列基板， 在其制作过程中电荷电容的下电极 可以与薄膜晶体管的漏极和源极， 以及数据线同一工序制成， 同属于第二金属层
(M2 ), 电荷电容的上电极可以与共用电极配线同一工序一并形成， 同属于第一 金属层 （Ml )， 因此制造成本较低。 附图说明
图 1是现有技术中常用的薄膜晶体管阵列基板修补方法的示意图； 图 2是现有技术中液晶显示面板阵列基板上一种 2G1D像素单元结构的等效 电路图；
图 3是本发明提供的薄膜晶体管阵列基板修补方法的一个实施例的示意图。 具体实 式
为了进一步说明本发明的目的、 技术方案和技术效果， 下面参照现有技术中 大尺寸液晶显示面板薄膜晶体管阵列基板及其上排布的 2G1D像素单元结构 （像 素单元与两条扫描线和一条数据线电性连接） 的等效电路图， 详细地介绍本发明 提供的修补方法的工作原理及实施方式， 以及与现有技术相比更好的技术效果。 需要说明的是， 虽然本发明是针对 2G1D像素单元结构进行说明， 但是不应局限 于此。 不同厂商设计的像素单元其结构不尽相同， 会有多种变形， 例如还存在一 种 1G2D像素单元结构 （像素单元与一条扫描线和两条数据线电性连接）， 因此任 何本发明所属技术领域内的技术人员， 在不脱离本发明所揭露的精神的前提下， 在技术方案实施的形式上和细节上做出任何的修改与变化均在本发明要求保护 的范围内。
如图 2所示， 是布置在大尺寸液晶显示面板阵列基板上的像素单元的等效电 路图。 由于采用电荷分享技术， 该像素单元的像素电极分为主像素电极 I区和次 像素电极 II区， 以及电荷分享单元 Sharing。 其中：
主像素电极 I区包括薄膜晶体管 Π， 该薄膜晶体管 Π的栅极电性连接扫描 线 Scanl， 源极电性连接数据线 Data, 漏极电性连接主像素电极 I区； 与主像素 电极 I区电性连接的上电极 （图 2中未示出） 与对应的共用电极配线 Com之间形 成存储电容 Cstl以及液晶电容 Clcl。
次像素电极 II区包括薄膜晶体管 T2，该薄膜晶体管 Τ2的栅极电性连接扫描 线 Scanl , 源极电性连接数据线 Data, 漏极电性连接次像素电极 II 区； 与次像 素电极 II区电性连接的上电极 （图 2中未示出） 与对应的共用电极配线 Com之 间形成存储电容 Cst2以及液晶电容 Clc2。
电荷分享单元 Sharing包括薄膜晶体管 T3， 该薄膜晶体管 Τ3的栅极电性连 接扫描线 SCan2， 漏极电性连接像素电极 II区， 源极与主像素电极 I区电性连接 的上电极之间形成第一电荷电容 Ccsl，同时源极还与对应的共用电极配线 Com之 间形成第二电荷电容 Ccs2。
电荷分享技术的基本原理是： 首先当扫描线 Scanl传来扫描信号时， 薄膜晶 体管 Π和薄膜晶体管 T2的漏极和源极导通，使主像素电极 I区和次像素电极 II 区的电压在数据线 Data传来的数据信号的作用下达到相同的电位； 然后当扫描 线 SCan2传来扫描信号时， 薄膜晶体管 Π和薄膜晶体管 T2的漏极和源极截止， 同时薄膜晶体管 T3的漏极和源极导通， 致使次像素电极 II区上的电荷通过第二 电荷电容 Ccs2向共用电极配线 Com转移， 使次像素电极 II区的电压与主像素电 极 I区的电压产生电压差， 进而使次像素电极 II区的液晶与主像素电极 I区的 液晶以不同的偏转角度进行偏转， 达到多畴显示补偿大视角色偏的技术效果。
如背景技术所介绍， 当有粒子落入存储电容的介电层， 又或者存储电容的介 电层出现破洞时， 存储电容会发生泄漏 （leakage) 现象。 如此一来， 将会导致 像素单元显示异常， 进而使得画面显示品质不佳。 此时， 需要对出现异常的像素 单元进行修补。 就目前的修补手段而言， 需要利用激光将该像素单元中薄膜晶体 管 Π与数据线 Data的电性连接， 薄膜晶体管 Π与主像素电极 I区的电性连接， 薄膜晶体管 T2与数据线 Data的电性连接， 薄膜晶体管 T2与次像素电极 II区的 电性连接， 薄膜晶体管 T3与次像素电极 II区的电性连接切断， 以及利用激光将 与主像素电极 I 区电性连接的上电极、 与次像素电极 II 区电性连接的上电极分 别与对应的共用电极配线熔接。 整个过程步骤繁琐， 耗时耗能， 而且原本可以正 常工作的次像素电极 II区也会受到影响， 变成了暗点。
针对于此， 本发明的技术人员基于从事液晶面板设计制造多年积累的丰富经 验和专业知识， 对上述传统的修补方法做了一定的改进， 使其更具有实用性。
如针对上述像素单元中的第二电荷电容 Ccs2 因为粒子或者破洞而出现漏电 或者失效的情况， 本发明提出了一种新的修补方法， 即只需去除第二电荷电容 Ccs2的修补方法。根据上文描述的电荷分享技术的工作原理， 在去除第二电荷电 容 Ccs2后，当扫描线 SCan2传来扫描信号时，薄膜晶体管 T3的漏极和源极导通， 只有第一电荷电容 Ccs l 参与工作， 整个像素单元仍然能够正常工作， 只是不能 有效解决大视角色偏问题， 但是对整个像素单元的显示功能影响不大， 人眼很难 分辨前后显示效果的变化。 这种修补方法不同于以往传统的修补手段， 修补过程 更加快捷简便， 而且修补之后像素单元仍然能够显示图像， 无论在实施方法上还 是在技术效果上皆有较大的改进， 具有广泛的应用价值。
仍然以背景技术中图 1所示的实施例为例， 在采用了电荷分享技术的大尺寸 液晶显示面板阵列基板的制作过程中， 第二电荷电容 Ccs2 的下电极是与各薄膜 晶体管的源极、 漏极， 以及数据线一并形成， 同属于第二金属层 （M2 )， 第二电 荷电容 Ccs2的上电极是与共用电极配线一并形成， 同属于第一金属层 （Ml )。 因 此第二电荷电容 Ccs2可以是由薄膜晶体管 T3的源极延伸出来的金属线与由共用 电极配线 Com延伸出来的金属线形成的金属 -绝缘 -金属结构， 所以本实施例可以 采用以下两种方法去除失效的第二电荷电容 Ccs2 :
利用激光将连接于第二电荷电容 Ccs2下电极与薄膜晶体管 T3源极之间的金 属线断开； 或者
利用激光将连接于第二电荷电容 Ccs2上电极与共用电极配线 Com之间的金 属线断开 （如图 2和图 3中所示）。
以上所述， 仅是本发明的较佳实施例而已。 例如， 采用电荷分享技术的像素 单元结构可以有很多种变化形式， 不仅限于由三个薄膜晶体管组成的结构形式。 虽然本发明所披露的实施方式如上， 但所述的内容只是为了便于理解本发明而采 用的实施方式， 并非用以限定本发明。 任何本发明所属技术领域内的技术人员， 在不脱离本发明所揭露的精神和范围的前提下， 可以在实施的形式上及细节上作 任何的修改与变化， 但本发明的专利保护范围， 仍须以所附的权利要求书所界定 的范围为准。

Claims

权利要求书
1、 一种薄膜晶体管阵列基板的修补方法， 所述阵列基板包括：
基板；
多条共用电极配线， 配置于所述基板上；
多条扫描线和数据线， 交错配置在所述基板上以形成多个像素区域； 多个像素单元， 配置于所述像素区域内， 每个所述像素单元包括： 主像素电极和次像素电极， 以及
电荷分享单元， 其电性连接所述主像素电极和次像素电极， 并包括用于使所 述主像素电极与次像素电极产生电压差的电荷电容；
当所述电荷电容为瑕疵电容时， 所述修补方法包括以下步骤：
将瑕疵电容的上电极或下电极与其周围连接的线路断开， 以形成电性绝缘。
2、 如权利要求 1所述的修补方法， 其中：
所述阵列基板的每一个像素单元电性连接两条扫描线和一条数据线， 其中： 所述主像素电极和次像素电极， 配置以在第一条扫描线扫描信号的驱动下分 别接收数据线上的数据信号而具有相同的电压；
所述电荷分享单元， 配置以在第二条扫描线扫描信号的驱动下改变所述次像 素电极的电压， 使其与所述主像素电极的电压产生差异。
3、 如权利要求 1所述的修补方法， 其中：
利用激光将瑕疵电容的上电极或下电极与其周围连接的线路熔断。
4、 如权利要求 2所述的修补方法， 其中：
利用激光将瑕疵电容的上电极或下电极与其周围连接的线路熔断。
5、 如权利要求 1所述的修补方法， 其中：
所述上电极为透明导电层。
6、 如权利要求 2所述的修补方法， 其中：
所述上电极为透明导电层。
7、 如权利要求 5所述的修补方法， 其中：
所述上电极和所述共用电极配线连接。
8、 如权利要求 6所述的修补方法， 其中：
所述上电极和所述共用电极配线连接。
9、 如权利要求 1所述的修补方法， 其中： 所述下电极和所述的数据线通过同一道光罩形成。
10、 如权利要求 2所述的修补方法， 其中：
所述下电极和所述的数据线通过同一道光罩形成。
11、 一种薄膜晶体管阵列基板， 其中包括：
基板；
多条共用电极配线， 配置于所述基板上；
多条扫描线和数据线， 交错配置在所述基板上以形成多个像素区域； 多个像素单元， 配置于所述像素区域内， 每个所述像素单元包括： 主像素电极和次像素电极， 以及
电荷分享单元， 其电性连接所述主像素电极和次像素电极， 并包括用于使所 述主像素电极与次像素电极产生电压差的电荷电容， 当所述电荷电容为瑕疵电容 时， 其上电极或下电极与其周围连接的线路断开而电性绝缘。
12、 如权利要求 11 所述的阵列基板， 所述阵列基板的每一个像素单元电性 连接两条扫描线和一条数据线， 其中：
所述主像素电极和次像素电极， 配置以在所述第一条扫描线扫描信号的驱动 下分别接收所述数据线上的数据信号而具有相同的电压；
所述电荷分享单元， 配置以在所述第二条扫描线扫描信号的驱动下改变所述 次像素电极的电压， 使其与所述主像素电极的电压产生差异。
13、 如权利要求 12所述的阵列基板， 其中：
所述电荷分享单元包括薄膜晶体管， 其栅极电性连接所述第二条扫描线， 漏 极电性连接所述次像素电极， 源极与所述共用电极配线耦合形成所述电荷电容。
14、 如权利要求 13所述的阵列基板， 其中：
所述电荷分享单元的薄膜晶体管的源极还与所述主像素电极耦合形成另一 个电荷电容。
15、 如权利要求 11所述的阵列基板， 其中：
所述上电极为透明导电层。
16、 如权利要求 12所述的阵列基板， 其中：
所述上电极为透明导电层。
17、 如权利要求 11所述的阵列基板， 其中：
所述上电极和所述共用电极配线连接。
18、 如权利要求 12所述的阵列基板， 其中： 所述上电极和所述共用电极配线连接。
19、 如权利要求 11所述的阵列基板， 其中： 所述下电极和所述的数据线通过同一道光罩形成。
20、 如权利要求 12所述的阵列基板， 其中： 所述下电极和所述的数据线通过同一道光罩形成。
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