WO2015046073A1 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
WO2015046073A1
WO2015046073A1 PCT/JP2014/074899 JP2014074899W WO2015046073A1 WO 2015046073 A1 WO2015046073 A1 WO 2015046073A1 JP 2014074899 W JP2014074899 W JP 2014074899W WO 2015046073 A1 WO2015046073 A1 WO 2015046073A1
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Prior art keywords
sheet
resin composition
shaped resin
chip
meth
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PCT/JP2014/074899
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English (en)
French (fr)
Inventor
博行 花園
尚英 高本
章洋 福井
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日東電工株式会社
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Application filed by 日東電工株式会社 filed Critical 日東電工株式会社
Priority to KR1020167006511A priority Critical patent/KR20160055806A/ko
Priority to US15/024,552 priority patent/US20160233184A1/en
Publication of WO2015046073A1 publication Critical patent/WO2015046073A1/ja

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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device.
  • the surface mount type suitable for high-density mounting is the mainstream of the semiconductor package instead of the conventional pin insertion type.
  • the lead is soldered directly to a printed circuit board or the like.
  • the entire package is heated and mounted by infrared reflow, vapor phase reflow, solder dipping, or the like.
  • the space between the semiconductor element and the substrate is filled with a sealing resin in order to protect the surface of the semiconductor element and ensure the connection reliability between the semiconductor element and the substrate.
  • Filling the space between the semiconductor element and the substrate with the sealing resin is also referred to as underfill.
  • a sealing resin for underfill a liquid sealing resin is widely used, but it is difficult to adjust an injection position and an injection amount with a liquid sealing resin.
  • Patent Document 1 a technique for filling a space between a semiconductor element and a substrate using a sheet-shaped resin composition has been proposed (see, for example, Patent Document 1).
  • Patent Document 1 a wafer is attached to a sheet-shaped resin composition, and then the wafer with the sheet-shaped resin composition attached is diced to form a chip, and then the surface of the sheet-shaped resin composition is a substrate. It is disclosed that the electrical connection between the substrate and the chip is obtained and the interface between the chip and the substrate is sealed by thermosetting the sheet-shaped resin composition.
  • the electrical connection between the substrate and the chip is performed, for example, by electrically connecting the electrodes formed on the substrate and the bumps formed on the chip.
  • bubbles voids
  • a void may bite into the concavo-convex portion caused by the bump formed on the wafer.
  • the present inventors diligently studied a method for manufacturing a semiconductor device using the sheet-shaped resin composition.
  • the electrical connection between the substrate and the chip and the curing of the sheet-shaped resin composition are performed at the same time by one heating. It was determined that the void expanded and then the sheet-shaped resin composition was cured in this state. Therefore, it was found out that a large void was in a state of being bitten. The presence of large voids causes various problems such as a decrease in reliability, and therefore it is desirable that the generation be suppressed.
  • the present invention has been made in view of the above-described problems, and the object thereof is to suppress the expansion of voids even when the voids are caught between the sheet-shaped resin composition and the adherend.
  • An object of the present invention is to provide a method for manufacturing a semiconductor device.
  • the present invention is a method of manufacturing a semiconductor device, Preparing a chip with a sheet-shaped resin composition in which the sheet-shaped resin composition is attached to a semiconductor chip; and Step B for preparing an adherend; A process C for attaching the chip with the sheet-shaped resin composition to the adherend with the sheet-shaped resin composition as a bonding surface; After the step C, the step D of heating and semi-curing the sheet-shaped resin composition, After the step D, the sheet-like resin composition is heated and cured at a higher temperature than the heating in the step D, and the step E is included.
  • a sheet-shaped resin composition is heated in a state where a chip with a sheet-shaped resin composition is bonded to an adherend with the sheet-shaped resin composition as a bonding surface. And semi-cured (step D). Accordingly, the viscosity of the sheet-shaped resin composition is higher than that before semi-curing. Thereafter, the sheet-shaped resin composition is cured by heating at a temperature higher than that in the process D (process E). Since the sheet-shaped resin composition has already been semi-cured at the stage of Step E, even if a void is caught between the sheet-shaped resin composition and the adherend, the expansion of the void is suppressed. ing. Therefore, the generation of large voids that cause various problems can be suppressed.
  • the sheet-shaped resin composition preferably has a thermosetting rate of 10% or more when heated at 200 ° C. for 10 seconds.
  • the sheet-shaped resin composition has a thermosetting rate of 10% or more when heated at 200 ° C. for 10 seconds, the viscosity of the sheet-shaped resin composition after Step D is increased to some extent. Become. As a result, void expansion can be further suppressed.
  • thermosetting rate is a value obtained from reaction heat obtained by differential scanning calorimetry (DSC), assuming that the state before heating is 0% and the state of complete thermosetting is 100%. More details will be described later.
  • the adherend may have unevenness of 3 ⁇ m or more and 100 ⁇ m or less on the surface side to which the sheet-shaped resin composition is bonded.
  • the adherend When the adherend has irregularities of 3 ⁇ m or more and 100 ⁇ m or less, bubbles are easily caught between the sheet-shaped resin composition. However, as described above, after the step D, the viscosity of the sheet-shaped resin composition is increased. Therefore, even when using an adherend having irregularities of 3 ⁇ m or more and 100 ⁇ m or less, in which bubbles tend to bite, the expansion of voids is suppressed, so the generation of large voids that cause various problems is suppressed. can do.
  • the semiconductor chip may have irregularities of 3 ⁇ m or more and 100 ⁇ m or less on the surface side to which the sheet-shaped resin composition is bonded.
  • the semiconductor chip When the semiconductor chip has concavities and convexities of 3 ⁇ m or more and 100 ⁇ m or less, bubbles are likely to be caught between the sheet-shaped resin composition. However, as described above, after the step D, the viscosity of the sheet-shaped resin composition is increased. Therefore, even when a semiconductor chip having an unevenness of 3 ⁇ m or more and 100 ⁇ m or less in which air bubbles are easily caught is used, the expansion of voids is suppressed, so that the generation of large voids that cause various problems is suppressed. be able to.
  • a method for manufacturing a semiconductor device includes: Preparing a chip with a sheet-shaped resin composition in which the sheet-shaped resin composition is attached to a semiconductor chip; and Step B for preparing an adherend; A process C for attaching the chip with the sheet-shaped resin composition to the adherend with the sheet-shaped resin composition as a bonding surface; After the step C, the step D of heating and semi-curing the sheet-shaped resin composition, After the step D, a step E of heating and curing the sheet-shaped resin composition at a higher temperature than the heating in the step D is included.
  • the manufacturing method of the semiconductor device is as follows. Preparing a chip with a sheet-shaped resin composition in which a sheet-shaped resin composition is attached to a bump-forming surface of a semiconductor chip; and Step B for preparing a mounting substrate on which electrodes are formed; The sheet-shaped resin composition-attached chip is attached to the mounting substrate with the sheet-shaped resin composition as a bonding surface, and the bumps formed on the semiconductor chip and the mounting substrate are formed.
  • Step C for making the electrodes face each other; After the step C, the step D of heating and semi-curing the sheet-shaped resin composition, After the step D, at least a step E of heating at a higher temperature than the heating in the step D, bonding the bumps and the electrodes, and curing the sheet-like composition is included.
  • Step A a chip 40 with a sheet-shaped resin composition is prepared (step A).
  • a specific method for preparing the chip 40 with sheet-shaped resin composition will be described later with reference to FIGS.
  • the chip 40 with the sheet-shaped resin composition includes the semiconductor chip 22 on which the bumps 18 are formed, and the sheet-shaped resin composition 10 attached to the bump forming surface 22a of the semiconductor chip 22.
  • the bumps 18 are embedded in the sheet-shaped resin composition 10, and the bump forming surface 22 a of the semiconductor chip 22 is attached to the sheet-shaped resin composition 10.
  • the sheet-shaped resin composition 10 has a function of sealing a gap between the semiconductor chip 22 and the mounting substrate 50 when the semiconductor chip 22 is mounted on the mounting substrate 50 (see FIG. 2).
  • the sheet-shaped resin composition 10 preferably has a thermosetting rate of 10% or more after heating at 200 ° C. for 10 seconds, and more preferably 13% or more. If the sheet-shaped resin composition 10 has a thermosetting rate of 10% or more when heated at 200 ° C. for 10 seconds, the viscosity of the sheet-shaped resin composition 10 after the step D is increased to some extent. Become. As a result, void expansion can be further suppressed.
  • thermosetting rate is obtained by measuring the calorific value using differential scanning calorimetry (DSC). Specifically, first, a sheet-shaped resin composition that has not been heat-cured is prepared, and the temperature is set to 350 ° C. (the thermosetting reaction is assumed to be completely completed from ⁇ 10 ° C. under a temperature rising rate of 10 ° C./min. The amount of heat generated when the temperature is raised to (the temperature of reaction of the uncured sample) is measured. Moreover, the sample which heated the sheet-shaped resin composition before thermosetting at 200 degreeC for 10 second is created. Next, when the sample heated at 200 ° C. for 10 seconds was heated from ⁇ 10 ° C. to 350 ° C.
  • DSC differential scanning calorimetry
  • thermosetting reaction calorie of the sample heated at 200 ° C. for 10 seconds is measured. Thereafter, the thermosetting rate is obtained by the following formula (3).
  • the calorific value is determined using the area surrounded by the straight line connecting the two points of the rising temperature of the exothermic peak and the reaction end temperature measured with a differential scanning calorimeter and the peak.
  • Thermal curing rate [ ⁇ (reaction heat amount of uncured sample) ⁇ (reaction heat amount of sample heated at 200 ° C. for 10 seconds) ⁇ / (reaction heat amount of uncured sample)] ⁇ 100 (%)
  • the sheet-like resin composition 10 preferably has a minimum melt viscosity at less than 200 ° C. within a range of 100 Pa ⁇ s to 5000 Pa ⁇ s, more preferably within a range of 300 Pa ⁇ s to 4000 Pa ⁇ s, More preferably in the range of s to 2000 Pa ⁇ s.
  • the minimum melt viscosity at less than 200 ° C. of the sheet-shaped resin composition 10 is in the range of 100 Pa ⁇ s to 5000 Pa ⁇ s
  • the bump 18 formed on the semiconductor chip 22 and the mounting substrate 50 are formed in the step C.
  • the formed electrode 52 can be opposed to the sheet-shaped resin composition 10 while being easily embedded.
  • the minimum melt viscosity at less than 200 ° C. of the sheet-shaped resin composition 10 refers to the minimum melt viscosity at less than 200 ° C. before thermosetting.
  • the minimum melt viscosity at less than 200 ° C. of the sheet-shaped resin composition 10 can be controlled by selecting the constituent material of the sheet-shaped resin composition 10. In particular, it can be controlled by selecting a thermoplastic resin. Specifically, for example, when a low molecular weight resin is used as the thermoplastic resin, the minimum melt viscosity at less than 200 ° C. can be reduced. For example, when a high molecular weight resin is used, the minimum melt viscosity at less than 200 ° C. Can be increased.
  • Examples of the sheet-like resin composition 10 include a combination of a thermoplastic resin and a thermosetting resin.
  • a thermosetting resin alone can also be used.
  • thermoplastic resin examples include natural rubber, butyl rubber, isoprene rubber, chloroprene rubber, ethylene-vinyl acetate copolymer, ethylene-acrylic acid copolymer, ethylene-acrylic acid ester copolymer, polybutadiene resin, polycarbonate resin, heat Examples thereof include plastic polyimide resins, polyamide resins such as 6-nylon and 6,6-nylon, phenoxy resins, acrylic resins, saturated polyester resins such as PET and PBT, polyamideimide resins, and fluorine resins. These thermoplastic resins can be used alone or in combination of two or more. Among these thermoplastic resins, an acrylic resin that has few ionic impurities and high heat resistance and can ensure the reliability of the semiconductor chip is particularly preferable.
  • the acrylic resin is not particularly limited, and includes one or more esters of acrylic acid or methacrylic acid ester having a linear or branched alkyl group having 30 or less carbon atoms, particularly 4 to 18 carbon atoms.
  • Examples include polymers as components.
  • the alkyl group include methyl group, ethyl group, propyl group, isopropyl group, n-butyl group, t-butyl group, isobutyl group, amyl group, isoamyl group, hexyl group, heptyl group, cyclohexyl group, 2 -Ethylhexyl group, octyl group, isooctyl group, nonyl group, isononyl group, decyl group, isodecyl group, undecyl group, lauryl group, tridecyl group, tetradecyl group, stearyl group, octadecyl group,
  • the other monomer forming the polymer is not particularly limited, and examples thereof include acrylic acid, methacrylic acid, carboxyethyl acrylate, carboxypentyl acrylate, itaconic acid, maleic acid, fumaric acid, and crotonic acid.
  • Carboxyl group-containing monomers maleic anhydride or acid anhydride monomers such as itaconic anhydride, 2-hydroxyethyl (meth) acrylate, 2-hydroxypropyl (meth) acrylate, 4-methacrylic acid 4- Hydroxybutyl, 6-hydroxyhexyl (meth) acrylate, 8-hydroxyoctyl (meth) acrylate, 10-hydroxydecyl (meth) acrylate, 12-hydroxylauryl (meth) acrylate or (4-hydroxymethylcyclohexyl) -Methyl Hydroxyl group-containing monomers such as acrylate, styrene sulfonic acid, allyl sulfonic acid, 2- (meth) acrylamide-2-methylpropane sulfonic acid, (meth) acrylamide propane sulfonic acid, sulfopropyl (meth) acrylate or (meth) Examples thereof include sulfonic acid group-containing monomers such as
  • the content of the thermoplastic resin with respect to the entire sheet-shaped resin composition 10 is preferably 3% by weight or more, and more preferably 4% by weight or more. When it is 4% by weight or more, good flexibility is obtained. On the other hand, the content of the thermoplastic resin in the resin component is preferably 15% by weight or less, more preferably 12% by weight or less, and still more preferably 8% by weight or less. Good thermal reliability is acquired as it is 8 weight% or less.
  • thermoplastic resins acrylic resin is preferable in order to make the viscosity of the sheet-shaped resin composition 10 before semi-curing low.
  • thermosetting resin examples include phenol resin, amino resin, unsaturated polyester resin, epoxy resin, polyurethane resin, silicone resin, and thermosetting polyimide resin. These resins can be used alone or in combination of two or more. In particular, an epoxy resin containing a small amount of ionic impurities that corrode the semiconductor chip is preferable. Moreover, as a hardening
  • the epoxy resin is not particularly limited as long as it is generally used as an adhesive composition, for example, bisphenol A type, bisphenol F type, bisphenol S type, brominated bisphenol A type, hydrogenated bisphenol A type, bisphenol AF type.
  • novolac type epoxy resins novolac type epoxy resins, biphenyl type epoxy resins, trishydroxyphenylmethane type resins or tetraphenylolethane type epoxy resins are particularly preferred. This is because these epoxy resins are rich in reactivity with a phenol resin as a curing agent and are excellent in heat resistance and the like.
  • the phenol resin acts as a curing agent for the epoxy resin.
  • a phenol novolac resin, a phenol aralkyl resin, a cresol novolac resin, a tert-butylphenol novolac resin, a novolak type phenol resin such as a nonylphenol novolac resin examples include resol-type phenolic resins and polyoxystyrenes such as polyparaoxystyrene. These can be used alone or in combination of two or more. Of these phenol resins, phenol novolac resins and phenol aralkyl resins are particularly preferred. This is because the sealing reliability can be improved.
  • the compounding ratio of the epoxy resin and the phenol resin is preferably such that, for example, the hydroxyl group in the phenol resin is 0.5 to 2.0 equivalents per equivalent of the epoxy group in the epoxy resin component. More preferred is 0.8 to 1.2 equivalents. That is, if the blending ratio of both is out of the above range, sufficient curing reaction does not proceed and the properties of the cured epoxy resin are likely to deteriorate.
  • the content of the thermosetting resin with respect to the entire sheet-shaped resin composition 10 is preferably 10% by weight or more, more preferably 12% by weight or more, and further preferably 15% by weight or more. When it is 10% or more, good flexibility is obtained.
  • the content of the thermosetting resin in the resin component is preferably 30% by weight or less, more preferably 25% by weight or less, and further preferably 20% by weight or less. When the content is 20% by weight or less, the tackiness of the sheet is suppressed and the handleability is improved.
  • thermosetting acceleration catalyst for epoxy resin and phenol resin is not particularly limited, and can be appropriately selected from known thermosetting acceleration catalysts.
  • stimulation catalyst can be used individually or in combination of 2 or more types.
  • thermosetting acceleration catalyst for example, an amine-based curing accelerator, a phosphorus-based curing accelerator, an imidazole-based curing accelerator, a boron-based curing accelerator, a phosphorus-boron-based curing accelerator, or the like can be used.
  • the content of the thermosetting acceleration catalyst is preferably 0.7 parts by weight or more, more preferably 2.4 parts by weight or more, with respect to 100 parts by weight of the thermosetting resin. More preferably, it is at least part. When it is 4.8 parts by weight or more, the sheet-shaped resin composition 10 can be easily semi-cured in the semi-curing step.
  • the content of the thermosetting acceleration catalyst is preferably 24 parts by weight or less. The preservability of a thermosetting resin can be improved as it is 24 weight part or less.
  • the sheet-like resin composition 10 can be appropriately mixed with an inorganic filler.
  • the blending of the inorganic filler makes it possible to impart conductivity, improve thermal conductivity, adjust the storage elastic modulus, and the like.
  • the inorganic filler examples include silica, clay, gypsum, calcium carbonate, barium sulfate, alumina, beryllium oxide, silicon carbide, silicon nitride, and other ceramics, aluminum, copper, silver, gold, nickel, chromium, lead. And various inorganic powders made of metals such as tin, zinc, palladium, solder, or alloys, and other carbons. These can be used alone or in combination of two or more. Among these, silica, particularly fused silica is preferably used.
  • the average particle size of the inorganic filler is preferably in the range of 0.01 to 30 ⁇ m, and more preferably in the range of 0.05 to 10 ⁇ m. In the present invention, inorganic fillers having different average particle sizes may be used in combination.
  • the average particle size is a value determined by a photometric particle size distribution meter (manufactured by HORIBA, apparatus name: LA-910).
  • the blending amount of the inorganic filler is preferably set to 100 to 1400 parts by weight with respect to 100 parts by weight of the organic resin component. Particularly preferred is 230 to 900 parts by weight.
  • the blending amount of the inorganic filler is 100 parts by weight or more, heat resistance and strength are improved.
  • liquidity is securable by setting it as 1400 weight part or less. Thereby, it can prevent that adhesiveness and embedding fall.
  • additives can be appropriately added to the sheet-shaped resin composition 10 as necessary.
  • other additives include flame retardants, silane coupling agents, ion trapping agents, pigments such as carbon black, and the like.
  • flame retardant include antimony trioxide, antimony pentoxide, brominated epoxy resin, and the like. These can be used alone or in combination of two or more.
  • silane coupling agent include ⁇ - (3,4-epoxycyclohexyl) ethyltrimethoxysilane, ⁇ -glycidoxypropyltrimethoxysilane, ⁇ -glycidoxypropylmethyldiethoxysilane, and the like.
  • ion trapping agent examples include hydrotalcites and bismuth hydroxide. These can be used alone or in combination of two or more.
  • An organic acid can also be added for the purpose of removing the oxide film of the solder during mounting.
  • the thickness (total thickness in the case of a multilayer) of the sheet-shaped resin composition 10 is not particularly limited, it is preferably 5 ⁇ m or more and 500 ⁇ m or less in consideration of the strength and fillability of the cured resin. Note that the thickness of the sheet-shaped resin composition 10 can be appropriately set in consideration of the width of the gap between the chip 22 and the mounting substrate 50.
  • the sheet-shaped resin composition 10 is produced as follows, for example. First, a resin composition solution that is a material for forming the sheet-shaped resin composition 10 is prepared. As described above, the resin composition solution contains the resin composition, filler, and other various additives.
  • the resin composition solution is applied on the base separator so as to have a predetermined thickness to form a coating film, and then the coating film is dried under predetermined conditions to form the sheet-shaped resin composition 10.
  • a coating method For example, roll coating, screen coating, gravure coating, etc. are mentioned.
  • drying conditions for example, a drying temperature of 70 to 160 ° C. and a drying time of 1 to 5 minutes are performed.
  • the thickness of the semiconductor chip 22 is not particularly limited, but can be set as appropriate within a range of 10 to 1000 ⁇ m, for example.
  • the height of the bump 18 formed on the semiconductor chip 22 is not particularly limited, but a bump of 3 ⁇ m or more and 100 ⁇ m or less can be used.
  • the height of the bump 18 is 3 ⁇ m or more and 100 ⁇ m or less, that is, when the semiconductor chip 22 has unevenness of 3 ⁇ m or more and 100 ⁇ m or less, bubbles are easily caught between the sheet-like resin composition 10.
  • the viscosity of the sheet-shaped resin composition 10 has increased. Therefore, even when the semiconductor chip 22 having irregularities of 3 ⁇ m or more and 100 ⁇ m or less in which air bubbles are easily caught is used, since the expansion of the voids is suppressed, the generation of large voids causing various problems is suppressed. can do.
  • the constituent material of the bump 18 is not particularly limited, but is preferably solder, Sn—Pb, Pb—Sn—Sb, Sn—Sb, Sn—Pb—Bi, Bi—Sn, Sn—Cu. , Sn—Pb—Cu, Sn—In, Sn—Ag, Sn—Pb—Ag, and Pb—Ag solders.
  • a mounting substrate 50 having an electrode 52 formed on the surface 50a is prepared (step B).
  • the mounting substrate 50 various substrates such as a lead frame and a circuit substrate (such as a wiring circuit substrate) can be used.
  • the material of such a substrate is not particularly limited, and examples thereof include a ceramic substrate and a plastic substrate.
  • the plastic substrate include an epoxy substrate, a bismaleimide triazine substrate, and a polyimide substrate.
  • a semiconductor wafer can be used as the mounting substrate 50.
  • the height of the electrode 52 formed on the mounting substrate 50 is not particularly limited, and a height of 3 ⁇ m or more and 100 ⁇ m or less can be used.
  • the height of the electrode 52 is 3 ⁇ m or more and 100 ⁇ m or less, that is, when the mounting substrate 50 has unevenness of 3 ⁇ m or more and 100 ⁇ m or less, bubbles are easily caught between the sheet-like resin composition 10.
  • the viscosity of the sheet-shaped resin composition 10 has increased. Therefore, even when the mounting substrate 50 having irregularities of 3 ⁇ m or more and 100 ⁇ m or less in which bubbles are easily caught, the expansion of the voids is suppressed, so that large voids that cause various problems are generated. Can be suppressed.
  • Step C a chip 40 with a sheet-shaped resin composition is bonded to a mounting substrate 50 with the sheet-shaped resin composition 10 as a bonding surface.
  • the bumps 18 formed on the chip 22 are opposed to the electrodes 52 formed on the mounting substrate 50 (step C).
  • the sheet-shaped resin composition 10 of the chip-shaped resin composition-attached chip 40 is arranged to face the mounting substrate 50, and then a flip-chip bonder is used to insert the chip with the sheet-shaped resin composition. Apply pressure from 40 side. Thereby, the bump 18 and the electrode 52 are opposed to each other while being embedded in the sheet-shaped resin composition 10.
  • the temperature at the time of bonding is preferably 100 to 200 ° C., more preferably 150 to 190 ° C. However, the temperature is preferably lower than the melting point of the solder. Further, the pressure at the time of bonding is preferably 0.01 to 10 MPa, more preferably 0.1 to 1 MPa. When the bonding temperature is 150 ° C. or higher, the viscosity of the sheet-shaped resin composition 10 is lowered, and the unevenness can be filled without a gap. Moreover, bonding becomes possible, suppressing the hardening reaction of the sheet-like resin composition 10 as the temperature of bonding is 200 degrees C or less. At this time, when the minimum melt viscosity at less than 200 ° C.
  • the of the sheet-shaped resin composition 10 is in the range of 100 Pa ⁇ s to 5000 Pa ⁇ s, the bump 18 formed on the semiconductor chip 22 and the mounting substrate 50 are formed.
  • the electrode 52 can be opposed to the sheet-shaped resin composition 10 while being easily embedded.
  • Step D the sheet-shaped resin composition 10 is heated and semi-cured (step D).
  • the heating temperature in the step D is preferably 100 to 230 ° C., more preferably 150 to 210 ° C.
  • the heating temperature in the step D is preferably lower than the melting point of the solder.
  • the heating time is preferably in the range of 1 to 300 seconds, and more preferably in the range of 3 to 120 seconds. At this time, when the thermal curing rate after heating the sheet-shaped resin composition 10 at 200 ° C. for 10 seconds is 10% or more, the viscosity of the sheet-shaped resin composition 10 after the step D is increased to some extent. It will be. As a result, void expansion can be further suppressed.
  • Step E [Step of bonding the bump and the electrode and curing the sheet-like composition]
  • heating is performed at a higher temperature than the heating in the step D, and as shown in FIG. 4, the bumps 18 and the electrodes 52 are joined, and the sheet-like composition 10 is cured (step E).
  • FIG. 4 shows a state in which the bump 18 is composed of solder, and the bump 18 and the electrode 52 are joined (electrically connected) by melting the bump 18.
  • the heating temperature at this time is preferably 180 to 400 ° C., and more preferably 200 to 300 ° C.
  • the heating time is preferably in the range of 1 to 300 seconds, and more preferably in the range of 3 to 120 seconds.
  • the semiconductor device 60 is obtained.
  • the sheet 40 with the sheet-shaped resin composition-attached chip 40 is attached to the mounting substrate 50 with the sheet-shaped resin composition 10 being bonded.
  • the resin-like resin composition 10 is heated and semi-cured (step D). Accordingly, the viscosity of the sheet-shaped resin composition 10 is higher than that before semi-curing. Then, it heats at higher temperature than the heating in the process D, and the sheet-like resin composition 10 is hardened (process E). Since the sheet-shaped resin composition 10 has already been semi-cured at the stage of the process E, even if the void is caught between the sheet-shaped resin composition 10 and the mounting substrate 50, the expansion of the void is caused. It is suppressed. Therefore, the generation of large voids that cause various problems can be suppressed.
  • the sheet-shaped resin composition of this embodiment can be used integrally with a back surface grinding tape or a dicing tape. Thereby, a semiconductor device can be manufactured efficiently.
  • 5 to 11 are schematic cross-sectional views for explaining an example of a method for preparing a chip with sheet-shaped resin composition.
  • the tape-integrated sheet-like resin composition for backside grinding includes a backside grinding tape and the above-described sheet-like resin composition.
  • FIG. 5 is a schematic cross-sectional view of the back-grinding tape-integrated sheet-shaped resin composition 100.
  • the back-grinding tape-integrated sheet-shaped resin composition 100 includes a back-grinding tape 12 and a sheet-shaped resin composition 10.
  • the back grinding tape 12 includes a substrate 12a and an adhesive layer 12b, and the adhesive layer 12b is provided on the substrate 12a.
  • the sheet-like resin composition 10 is provided on the pressure-sensitive adhesive layer 12b.
  • the sheet-shaped resin composition 10 does not have to be laminated on the entire surface of the back surface grinding tape 12 as shown in FIG. 5, and has a size sufficient for bonding to the semiconductor wafer 16 (see FIG. 6). What is necessary is just to be provided.
  • the back grinding tape 12 includes a base material 12a and an adhesive layer 12b laminated on the base material 12a.
  • the base material 12a is a strength matrix of the back-grinding tape-integrated sheet-shaped resin composition 100.
  • polyolefins such as low density polyethylene, linear polyethylene, medium density polyethylene, high density polyethylene, ultra low density polyethylene, random copolymer polypropylene, block copolymer polypropylene, homopolyprolene, polybutene, polymethylpentene, ethylene-acetic acid Vinyl copolymer, ionomer resin, ethylene- (meth) acrylic acid copolymer, ethylene- (meth) acrylic acid ester (random, alternating) copolymer, ethylene-butene copolymer, ethylene-hexene copolymer, Polyester such as polyurethane, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyetheretherketone, polyimide, polyetherimide, polyamide, wholly aromatic polyamide, polyphenyls Fuido, aramid (paper), glass, glass
  • the base material 12a can be appropriately selected from the same type or different types, and can be used by blending several types as necessary. Conventional surface treatment can be applied to the surface of the substrate 12a. In order to impart antistatic ability to the base material 12a, a conductive material vapor deposition layer having a thickness of about 30 to 500 mm and made of metal, alloy, oxides thereof, or the like is provided on the base material 12a. it can.
  • the substrate 12a may be a single layer or two or more layers.
  • the thickness of the substrate 12a can be determined as appropriate and is generally about 5 ⁇ m to 200 ⁇ m, preferably 35 ⁇ m to 120 ⁇ m.
  • the base material 12a may contain various additives (for example, a colorant, a filler, a plasticizer, an anti-aging agent, an antioxidant, a surfactant, a flame retardant, etc.).
  • additives for example, a colorant, a filler, a plasticizer, an anti-aging agent, an antioxidant, a surfactant, a flame retardant, etc.
  • the pressure-sensitive adhesive used for forming the pressure-sensitive adhesive layer 12b is not particularly limited as long as it can hold the semiconductor wafer during back surface grinding of the semiconductor wafer and can be peeled from the semiconductor wafer after back surface grinding.
  • a general pressure-sensitive adhesive such as an acrylic pressure-sensitive adhesive or a rubber-based pressure-sensitive adhesive can be used.
  • the pressure-sensitive adhesive is an acrylic pressure-sensitive adhesive based on an acrylic polymer from the standpoint of cleanability of semiconductor components such as semiconductor wafers and glass with organic solvents such as ultrapure water and alcohol. Is preferred.
  • acrylic polymer examples include those using acrylic acid ester as a main monomer component.
  • acrylic esters include (meth) acrylic acid alkyl esters (for example, methyl ester, ethyl ester, propyl ester, isopropyl ester, butyl ester, isobutyl ester, s-butyl ester, t-butyl ester, pentyl ester, Isopentyl ester, hexyl ester, heptyl ester, octyl ester, 2-ethylhexyl ester, isooctyl ester, nonyl ester, decyl ester, isodecyl ester, undecyl ester, dodecyl ester, tridecyl ester, tetradecyl ester, hexadecyl ester , Octadecyl esters, eicosyl esters, etc., alkyl
  • the acrylic polymer includes units corresponding to the other monomer components copolymerizable with the (meth) acrylic acid alkyl ester or cycloalkyl ester, if necessary, for the purpose of modifying cohesive force, heat resistance, and the like. You may go out.
  • Such monomer components include carboxyl group-containing monomers such as acrylic acid, methacrylic acid, carboxyethyl (meth) acrylate, carboxypentyl (meth) acrylate, itaconic acid, maleic acid, fumaric acid, and crotonic acid; maleic anhydride Acid anhydride monomers such as itaconic anhydride; 2-hydroxyethyl (meth) acrylate, 2-hydroxypropyl (meth) acrylate, 4-hydroxybutyl (meth) acrylate, 6-hydroxyhexyl (meth) acrylate Hydroxyl group-containing monomers such as 8-hydroxyoctyl (meth) acrylate, 10-hydroxydecyl (meth) acrylate, 12-hydroxylauryl (meth) acrylate, (4-hydroxymethylcyclohexyl) methyl (meth) acrylate;
  • the Sulfonic acid groups such as lensulfonic acid, allylsulfonic acid, 2- (meth)
  • a polyfunctional monomer or the like can be included as a monomer component for copolymerization as necessary.
  • polyfunctional monomers include hexanediol di (meth) acrylate, (poly) ethylene glycol di (meth) acrylate, (poly) propylene glycol di (meth) acrylate, neopentyl glycol di (meth) acrylate, Pentaerythritol di (meth) acrylate, trimethylolpropane tri (meth) acrylate, pentaerythritol tri (meth) acrylate, dipentaerythritol hexa (meth) acrylate, epoxy (meth) acrylate, polyester (meth) acrylate, urethane (meth) Examples include acrylates. These polyfunctional monomers can also be used alone or in combination of two or more. The amount of the polyfunctional monomer used is preferably 30% by weight
  • the acrylic polymer can be obtained by subjecting a single monomer or a mixture of two or more monomers to polymerization.
  • the polymerization can be carried out by any method such as solution polymerization, emulsion polymerization, bulk polymerization, suspension polymerization and the like. From the viewpoint of preventing contamination of a clean adherend, it is preferable that the content of the low molecular weight substance is small. From this point, the number average molecular weight of the acrylic polymer is preferably 300,000 or more, more preferably about 400,000 to 3 million.
  • an external cross-linking agent can be appropriately employed for the pressure-sensitive adhesive in order to increase the number average molecular weight of an acrylic polymer as a base polymer.
  • the external crosslinking method include a method in which a so-called crosslinking agent such as a polyisocyanate compound, an epoxy compound, an aziridine compound, or a melamine crosslinking agent is added and reacted.
  • a so-called crosslinking agent such as a polyisocyanate compound, an epoxy compound, an aziridine compound, or a melamine crosslinking agent is added and reacted.
  • the amount used is appropriately determined depending on the balance with the base polymer to be cross-linked, and further depending on the intended use as an adhesive. Generally, about 5 parts by weight or less, more preferably 0.1 to 5 parts by weight, is preferably added to 100 parts by weight of the base polymer.
  • additives such as various conventionally known tackifiers and anti-aging agents may be used for the pressure-sensitive adhesive, if necessary
  • the pressure-sensitive adhesive layer 12b can be formed of a radiation curable pressure-sensitive adhesive.
  • the radiation curable pressure-sensitive adhesive can increase the degree of cross-linking by irradiation with radiation such as ultraviolet rays, and can easily reduce its adhesive strength, and can be easily picked up. Examples of radiation include X-rays, ultraviolet rays, electron beams, ⁇ rays, ⁇ rays, and neutron rays.
  • radiation curable pressure-sensitive adhesive those having a radiation curable functional group such as a carbon-carbon double bond and exhibiting adhesiveness can be used without particular limitation.
  • radiation curable adhesives include additive radiation curable adhesives in which radiation curable monomer components and oligomer components are blended with general pressure sensitive adhesives such as the above acrylic adhesives and rubber adhesives. An agent can be illustrated.
  • Examples of the radiation curable monomer component to be blended include urethane oligomer, urethane (meth) acrylate, trimethylolpropane tri (meth) acrylate, tetramethylolmethane tetra (meth) acrylate, pentaerythritol tri (meth) acrylate, and pentaerythritol.
  • Examples thereof include stall tetra (meth) acrylate, dipentaerystol monohydroxypenta (meth) acrylate, dipentaerythritol hexa (meth) acrylate, 1,4-butanediol di (meth) acrylate and the like.
  • the radiation curable oligomer component examples include urethane, polyether, polyester, polycarbonate, and polybutadiene oligomers, and those having a weight average molecular weight in the range of about 100 to 30000 are suitable.
  • the compounding amount of the radiation curable monomer component or oligomer component can be appropriately determined in such an amount that the adhesive force of the pressure-sensitive adhesive layer can be reduced depending on the type of the pressure-sensitive adhesive layer. In general, the amount is, for example, about 5 to 500 parts by weight, preferably about 40 to 150 parts by weight with respect to 100 parts by weight of a base polymer such as an acrylic polymer constituting the pressure-sensitive adhesive.
  • the radiation curable pressure-sensitive adhesive has a carbon-carbon double bond as a base polymer in the polymer side chain or main chain or at the main chain terminal.
  • Intrinsic radiation curable adhesives using Intrinsic radiation-curable pressure-sensitive adhesives do not need to contain oligomer components, which are low-molecular components, or do not contain many, so the oligomer components do not move through the adhesive over time and are stable. This is preferable because an adhesive layer having a layered structure can be formed.
  • the base polymer having a carbon-carbon double bond those having a carbon-carbon double bond and having adhesiveness can be used without particular limitation.
  • an acrylic polymer having a basic skeleton is preferable.
  • the basic skeleton of the acrylic polymer include the acrylic polymers exemplified above.
  • the method for introducing the carbon-carbon double bond into the acrylic polymer is not particularly limited, and various methods can be adopted.
  • the carbon-carbon double bond can be easily introduced into the polymer side chain for easy molecular design.
  • a compound having a functional group capable of reacting with the functional group and a carbon-carbon double bond is converted into a radiation-curable carbon-carbon double bond. Examples of the method include condensation or addition reaction while maintaining the above.
  • combinations of these functional groups include carboxylic acid groups and epoxy groups, carboxylic acid groups and aziridyl groups, hydroxyl groups and isocyanate groups.
  • a combination of a hydroxyl group and an isocyanate group is preferable because of easy tracking of the reaction.
  • the functional group may be on either side of the acrylic polymer and the above compound as long as the acrylic polymer having the carbon-carbon double bond is generated by the combination of these functional groups. In the above preferred combination, it is preferable that the acrylic polymer has a hydroxyl group and the compound has an isocyanate group.
  • examples of the isocyanate compound having a carbon-carbon double bond include methacryloyl isocyanate, 2-methacryloyloxyethyl isocyanate, m-isopropenyl- ⁇ , ⁇ -dimethylbenzyl isocyanate, and the like.
  • acrylic polymer those obtained by copolymerizing the above-exemplified hydroxy group-containing monomers, ether compounds of 2-hydroxyethyl vinyl ether, 4-hydroxybutyl vinyl ether, diethylene glycol monovinyl ether, or the like are used.
  • a base polymer having a carbon-carbon double bond can be used alone, but the radiation-curable monomer does not deteriorate the characteristics.
  • Components and oligomer components can also be blended.
  • the radiation-curable oligomer component is usually in the range of 30 parts by weight, preferably in the range of 0 to 10 parts by weight, based on 100 parts by weight of the base polymer.
  • the radiation curable pressure-sensitive adhesive preferably contains a photopolymerization initiator when cured by ultraviolet rays or the like.
  • the photopolymerization initiator include 4- (2-hydroxyethoxy) phenyl (2-hydroxy-2-propyl) ketone, ⁇ -hydroxy- ⁇ , ⁇ ′-dimethylacetophenone, 2-methyl-2-hydroxypropio ⁇ -ketol compounds such as phenone and 1-hydroxycyclohexyl phenyl ketone; methoxyacetophenone, 2,2-dimethoxy-2-phenylacetophenone, 2,2-diethoxyacetophenone, 2-methyl-1- [4- ( Acetophenone compounds such as methylthio) -phenyl] -2-morpholinopropane-1; benzoin ether compounds such as benzoin ethyl ether, benzoin isopropyl ether and anisoin methyl ether; ketal compounds such as benzyldimethyl ketal; 2-naphthal
  • oxygen air
  • examples thereof include a method of coating the surface of the pressure-sensitive adhesive layer 12b with a separator, and a method of irradiating radiation such as ultraviolet rays in a nitrogen gas atmosphere.
  • the pressure-sensitive adhesive layer 12b has various additives (for example, colorants, thickeners, extenders, fillers, tackifiers, plasticizers, anti-aging agents, antioxidants, surfactants, cross-linking agents, etc. ) May be included.
  • additives for example, colorants, thickeners, extenders, fillers, tackifiers, plasticizers, anti-aging agents, antioxidants, surfactants, cross-linking agents, etc.
  • the thickness of the pressure-sensitive adhesive layer 12b is not particularly limited, it is preferably about 1 to 50 ⁇ m from the viewpoint of preventing chipping of the chip cut surface and compatibility of fixing and holding the sheet-shaped resin composition 10.
  • the thickness is preferably 2 to 30 ⁇ m, more preferably 5 to 25 ⁇ m.
  • the back-grinding tape-integrated sheet-like resin composition 100 can be produced, for example, by separately producing the back-grinding tape 12 and the sheet-like resin composition 10 and finally bonding them together.
  • FIG. 6 to 11 are diagrams showing each step of the method for preparing the chip 40 with sheet-shaped resin composition using the tape-integrated sheet-shaped resin composition 100 for back grinding.
  • the method for preparing the chip with the sheet-shaped resin composition is that the bump-formed surface 22a of the semiconductor wafer 16 on which the bumps 18 are formed and the sheet-shaped resin composition 100 of the tape-integrated sheet-shaped resin composition 100 for back grinding.
  • a plurality of bumps 18 are formed on the bump forming surface 22a of the semiconductor wafer 16 (see FIG. 6).
  • the height of the bump 18 is determined according to the application, and is generally about 15 to 100 ⁇ m. Of course, the height of each bump 18 in the semiconductor wafer 16 may be the same or different.
  • the height X ( ⁇ m) of the bump 18 formed on the surface of the semiconductor wafer 16 and the thickness Y ( ⁇ m) of the sheet-shaped resin composition 10 satisfy the relationship of 0.5 ⁇ Y / X ⁇ 2. . More preferably, 0.5 ⁇ Y / X ⁇ 1.5, and still more preferably 0.8 ⁇ Y / X ⁇ 1.3.
  • the height X ( ⁇ m) of the bump 18 and the thickness Y ( ⁇ m) of the sheet-shaped resin composition 10 satisfy the above relationship, the space between the semiconductor chip 22 and the mounting substrate 50 is sufficiently filled.
  • the sheet-like resin composition 10 can be prevented from excessively protruding from the space, and contamination of the semiconductor chip 22 by the sheet-like resin composition 10 can be prevented.
  • the heights of the bumps 18 are different, the height of the highest bump 18 is used as a reference.
  • the separator arbitrarily provided on the sheet-shaped resin composition 10 of the tape-integrated sheet-shaped resin composition 100 for back grinding is appropriately peeled to form bumps 18 of the semiconductor wafer 16 as shown in FIG.
  • the formed bump forming surface 22a and the sheet-shaped resin composition 10 are opposed to each other, and the sheet-shaped resin composition 10 and the semiconductor wafer 16 are bonded (mounting).
  • the method of bonding is not particularly limited, but a method by pressure bonding is preferable.
  • the pressure for pressure bonding is preferably 0.1 MPa or more, more preferably 0.2 MPa or more. When the pressure is 0.1 MPa or more, the unevenness of the bump forming surface 22a of the semiconductor wafer 16 can be embedded satisfactorily.
  • the upper limit of the pressure for pressure bonding is not particularly limited, but is preferably 1 MPa or less, more preferably 0.5 MPa or less.
  • the bonding temperature is preferably 40 ° C. or higher, more preferably 60 ° C. or higher. When the temperature is 40 ° C. or higher, the viscosity of the sheet-shaped resin composition 10 is reduced, and the unevenness of the semiconductor wafer 16 can be filled without a gap. Further, the bonding temperature is preferably 100 ° C. or lower, more preferably 80 ° C. or lower. When the temperature is 100 ° C. or lower, bonding can be performed while suppressing the curing reaction of the sheet-shaped resin composition 10.
  • Bonding is preferably performed under reduced pressure, for example, 1000 Pa or less, preferably 500 Pa or less.
  • a minimum is not specifically limited, For example, it is 1 Pa or more.
  • the surface (that is, the back surface) 16b opposite to the bump forming surface 22a of the semiconductor wafer 16 is ground (see FIG. 7).
  • the thin processing machine used for the back surface grinding of the semiconductor wafer 16 is not particularly limited, and examples thereof include a grinding machine (back grinder) and a polishing pad. Further, the back surface grinding may be performed by a chemical method such as etching. The back surface grinding is performed until the semiconductor wafer 16 has a desired thickness (for example, 10 to 800 ⁇ m).
  • the dicing tape 11 is attached to the back surface 16b of the semiconductor wafer 16 (see FIG. 8).
  • the dicing tape 11 has a structure in which an adhesive layer 11b is laminated on a substrate 11a.
  • the base material 11a and the pressure-sensitive adhesive layer 11b can be suitably produced by using the components and the manufacturing methods shown in the paragraphs of the base material 12a and the pressure-sensitive adhesive layer 12b of the back grinding tape 12.
  • the pressure sensitive adhesive layer 12b When the back surface grinding tape 12 is peeled off, if the pressure sensitive adhesive layer 12b has radiation curability, the pressure sensitive adhesive layer 12b is irradiated with radiation to harden the pressure sensitive adhesive layer 12b, so that peeling can be easily performed. Can do.
  • the radiation dose may be set as appropriate in consideration of the type of radiation used and the degree of curing of the pressure-sensitive adhesive layer.
  • the semiconductor wafer 40 and the sheet-shaped resin composition 10 are diced to form the diced semiconductor chip 40 with the sheet-shaped resin composition.
  • Dicing is performed according to a conventional method from the bump forming surface 22a on which the sheet-shaped resin composition 10 of the semiconductor wafer 16 is bonded.
  • a cutting method called full cut that cuts up to the dicing tape 11 can be adopted. It does not specifically limit as a dicing apparatus used at this process, A conventionally well-known thing can be used.
  • the expansion can be performed using a conventionally known expanding apparatus.
  • the semiconductor chip 40 with a sheet-shaped resin composition is peeled from the dicing tape 11 (the semiconductor chip 40 with a sheet-shaped resin composition is picked up).
  • the pickup method is not particularly limited, and various conventionally known methods can be employed.
  • the adhesive layer 11b of the dicing tape 11 is an ultraviolet curable type
  • the pickup is performed after the adhesive layer 11b is irradiated with ultraviolet rays.
  • the adhesive force with respect to the semiconductor chip 22 of the adhesive layer 11b falls, and peeling of the semiconductor chip 22 becomes easy.
  • the preparation method of the semiconductor chip with a sheet-shaped resin composition according to the present invention is not limited to the method using the tape-integrated sheet-shaped resin composition for back grinding.
  • the dicing tape-integrated sheet-shaped resin composition includes a dicing tape and a sheet-shaped resin composition.
  • the dicing tape includes a base material and an adhesive layer, and the adhesive layer is provided on the base material.
  • the sheet-shaped resin composition is provided on the pressure-sensitive adhesive layer.
  • the dicing tape can employ the same configuration as the back grinding tape described above.
  • the method for preparing the chip with sheet-shaped resin composition is a method of bonding a bump forming surface on which a bump of a semiconductor wafer is formed and a sheet-shaped resin composition of a dicing tape-integrated sheet-shaped resin composition.
  • a method for preparing a chip with a sheet-shaped resin composition using a single sheet-shaped resin composition is, for example, a process of bonding a bump-formed surface on which a bump of a semiconductor wafer is formed and a sheet-shaped resin composition.
  • a bonding process a process of bonding a back surface grinding tape to the surface opposite to the semiconductor wafer bonding surface of the sheet-shaped resin composition, a grinding process of grinding the back surface of the semiconductor wafer, and a dicing tape applied to the back surface of the semiconductor wafer Wafer fixing step, peeling step for peeling back surface grinding tape, dicing step for dicing semiconductor wafer to form semiconductor chip with sheet resin composition, and pickup for peeling semiconductor chip with sheet resin composition from dicing tape Process.
  • the method for preparing a chip with a sheet-shaped resin composition has a bump formed on a semiconductor wafer.
  • a dicing step of forming a semiconductor chip with a resin composition and a pickup step of peeling the semiconductor chip with a sheet-like resin composition from a dicing tape are included.
  • the semiconductor chip according to the present invention does not have to be formed with unevenness (for example, unevenness of 3 ⁇ m or more) due to bumps or the like on the surface side to which the sheet-shaped resin composition is bonded.
  • the adherend of the present invention may not have irregularities (for example, irregularities of 3 ⁇ m or more) formed by electrodes or the like on the surface side to which the sheet-shaped resin composition is bonded.
  • Step D step of heating and semi-curing the sheet-shaped resin composition
  • Step E after Step D, the sheet is heated at a higher temperature than the heating in Step D.
  • the step of heating and curing the resin-like resin composition suppresses the expansion of voids. Therefore, even in such a case, generation of large voids that cause various problems can be suppressed.
  • the manufacturing method of the semiconductor device is: Preparing a chip with a sheet-shaped resin composition in which a sheet-shaped resin composition as a die-bonding film is attached to a non-circuit-forming surface of a semiconductor chip (the surface opposite to the circuit-forming surface); Step B for preparing a mounting substrate such as a lead frame; A step C of attaching the chip with the sheet-shaped resin composition to the mounting substrate with the sheet-shaped resin composition as a bonding surface; and After the step C, the step D of heating and semi-curing the sheet-shaped resin composition, After the step D, at least a step E of heating and curing the sheet-shaped composition at a higher temperature than the heating in the step D is included.
  • Thermosetting catalyst Imidazole catalyst (trade name “2PHZ-PW”, manufactured by Shikoku Kasei Co., Ltd.)
  • thermosetting rate was measured as follows using a differential scanning calorimeter manufactured by T.A. Instrument Co., Ltd., product name “Q2000”. First, the temperature of the sheet-shaped resin composition A that has not been heat-cured is increased from ⁇ 10 ° C. to 350 ° C. (a temperature at which the thermosetting reaction is assumed to be completely completed) at a temperature increase rate of 10 ° C./min. The amount of heat generated when heated (the amount of reaction heat of the uncured sample) was measured. Also, a sample was prepared by heating the sheet-shaped resin composition A at 200 ° C. for 10 seconds.
  • thermosetting rate [ ⁇ (reaction heat amount of uncured sample) ⁇ (reaction heat amount of sample heated at 200 ° C. for 10 seconds) ⁇ / (reaction heat amount of uncured sample)] ⁇ 100 (%)
  • the calorific value is determined using the area surrounded by the straight line connecting the two points of the rising temperature of the exothermic peak and the reaction end temperature measured with a differential scanning calorimeter and the peak. The results are shown in Table 1.
  • a sheet-shaped resin composition A having a thickness of 40 ⁇ m was attached to a test vehicle manufactured by Waltz Co., Ltd. (a wafer having a thickness of 725 ⁇ m on which bumps having a height of 40 ⁇ m were formed).
  • the pasting conditions were a temperature of 60 ° C. and a pasting pressure of 0.5 Mpa under a vacuum degree of 100 Pa. As a result, a sample A having a form as shown in FIG. 1 was obtained.
  • Example 1 Next, a mounting substrate having an electrode (electrode height: 15 ⁇ m) was attached to Sample A.
  • a flip chip bonder (FC3000W) manufactured by Toray Engineering Co., Ltd. was used, and the pasting conditions were a load: 0.5 Mpa, held at 200 ° C. for 10 seconds, and then held at 260 ° C. for 10 seconds. Then, it grind
  • Example 1 As in Example 1, a mounting substrate having an electrode (electrode height: 15 ⁇ m) was attached to Sample A. For the pasting, a flip chip bonder (FC3000W) manufactured by Toray Engineering Co., Ltd. was used, and the pasting conditions were a load: 0.5 Mpa and held at 260 ° C. for 10 seconds. Then, it grind

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Abstract

　半導体チップにシート状樹脂組成物が貼り付けられたシート状樹脂組成物付きチップを準備する工程Ａと、被着体を準備する工程Ｂと、被着体に、シート状樹脂組成物付きチップを、シート状樹脂組成物を貼り合わせ面にして貼り付ける工程Ｃと、工程Ｃの後に、シート状樹脂組成物を加熱して半硬化させる工程Ｄと、工程Ｄの後に、工程Ｄにおける加熱よりも高温でシート状樹脂組成物を加熱して硬化させる工程Ｅとを含む半導体装置の製造方法。

Description

半導体装置の製造方法
　本発明は、半導体装置の製造方法に関する。
　電子機器の小型・薄型化による高密度実装の要求が、近年、急激に増加している。このため、半導体パッケージは、従来のピン挿入型に代わり、高密度実装に適した表面実装型が主流になっている。この表面実装型は、リードをプリント基板等に直接はんだ付けする。加熱方法としては、赤外線リフローやベーパーフェーズリフロー、はんだディップなどにより、パッケージ全体を加熱して実装される。
　表面実装後には、半導体素子表面の保護や半導体素子と基板との間の接続信頼性を確保するために、半導体素子と基板との間の空間に封止樹脂の充填が行われている。半導体素子と基板との間の空間への封止樹脂の充填は、アンダーフィルとも称されている。アンダーフィル用の封止樹脂としては、液状の封止樹脂が広く用いられているものの、液状の封止樹脂では注入位置や注入量の調節が困難である。そこで、シート状樹脂組成物を用いて半導体素子と基板との間の空間を充填する技術が提案されている（例えば、特許文献１参照）。
　特許文献１には、シート状樹脂組成物にウェハを付着させ、次いで、シート状樹脂組成物の付着したままのウェハをダイシングしてチップを形成し、その後、シート状樹脂組成物の面を基板に実装し、基板とチップとの電気接続を得るとともに、シート状樹脂組成物を熱硬化させて、チップと基板との界面を封止することが開示されている。
特許第４４３８９７３号
　基板とチップとの電気接続は、例えば、基板に形成された電極とチップに形成されたバンプとを電気的に接続することにより行なわれる。シート状樹脂組成物と基板とを貼り合わせる際には、基板に形成された電極に起因する凹凸部分に気泡（ボイド）が噛み込む場合がある。また、シート状樹脂組成物とウエハとを貼り合わせる際にも、ウエハに形成されたバンプに起因する凹凸部分にボイドが噛み込む場合がある。
　本発明者らは、上記シート状樹脂組成物を使用した半導体装置の製造方法について鋭意検討した。その結果、上述した従来の半導体装置の製造方法では、一度の加熱で、基板とチップとの電気接続と、シート状樹脂組成物の硬化とを同時に行なっているため、加熱により凹凸部分に噛み込んだボイドが膨張し、その後、この状態でシート状樹脂組成物が硬化することを突き止めた。そのため、大きなボイドが噛み込んだ状態となることを突き止めた。大きなボイドの存在は、信頼性の低下等、種々の不具合の原因となることから、発生が抑制されていることが望まれる。
　また、電極やバンプに限らず、一般的に凹凸部分には気泡が噛み込み易いことから、種々の被着体にシート状樹脂組成物を貼り合わせる際には、仮に凹凸部分に気泡が噛み込んだとしてもこの気泡を膨張させないことが望まれる。
　本発明は上述した課題に鑑みてなされたものであり、その目的は、シート状樹脂組成物と被着体との間にボイドが噛み込んだとしても、ボイドの膨張を抑制することが可能な半導体装置の製造方法を提供することにある。
　本願発明者等は、下記の構成を採用することにより、前記の課題を解決できることを見出して本発明を完成させるに至った。
　すなわち、本発明は、半導体装置の製造方法であって、
　半導体チップにシート状樹脂組成物が貼り付けられたシート状樹脂組成物付きチップを準備する工程Ａと、
　被着体を準備する工程Ｂと、
　前記被着体に、前記シート状樹脂組成物付きチップを、前記シート状樹脂組成物を貼り合わせ面にして貼り付ける工程Ｃと、
　前記工程Ｃの後に、前記シート状樹脂組成物を加熱して半硬化させる工程Ｄと、
　前記工程Ｄの後に、前記工程Ｄにおける加熱よりも高温で前記シート状樹脂組成物を加熱して硬化させる工程Ｅとを含むことを特徴とする。
　本発明に係る半導体装置の製造方法によれば、被着体に、シート状樹脂組成物付きチップを、シート状樹脂組成物を貼り合わせ面にして貼り付けた状態でシート状樹脂組成物を加熱して半硬化させる（工程Ｄ）。従って、シート状樹脂組成物は半硬化前よりも粘度が上昇する。その後、前記工程Ｄにおける加熱よりも高温で加熱し、前記シート状樹脂組成物を硬化させる（工程Ｅ）。前記工程Ｅの段階では、すでにシート状樹脂組成物は半硬化しているため、仮にシート状樹脂組成物と被着体との間にボイドが噛み込んでいたとしても、ボイドの膨張は抑制されている。従って、種々の不具合の原因となる大きなボイドの発生を抑制することができる。
　前記構成において、前記シート状樹脂組成物は、２００℃で１０秒間加熱した際の熱硬化率が１０％以上であることが好ましい。
　前記シート状樹脂組成物の２００℃で１０秒間加熱した際の熱硬化率が１０％以上であると、前記工程Ｄの後の前記シート状樹脂組成物は、ある程度粘度が上昇していることとなる。その結果、よりボイドの膨張を抑制することができる。
　前記熱硬化率は、加熱前の状態を０％、完全に熱硬化した状態を１００％とし、示差走査熱量測定（ＤＳＣ）により得られる反応熱から求めた値である。より詳しくは後に説明する。
　前記構成において、前記被着体は、前記シート状樹脂組成物が貼り合わせられる面側に、３μｍ以上１００μｍ以下の凹凸を有していても構わない。
　前記被着体が３μｍ以上１００μｍ以下の凹凸を有する場合、シート状樹脂組成物との間に気泡が噛み込み易い。しかしながら、上述の通り、前記工程Ｄの後は、前記シート状樹脂組成物の粘度は、上昇している。従って、気泡が噛み込み易い３μｍ以上１００μｍ以下の凹凸を有する被着体を用いた場合であっても、ボイドの膨張が抑制されているため、種々の不具合の原因となる大きなボイドの発生を抑制することができる。
　前記構成において、前記半導体チップは、前記シート状樹脂組成物が貼り合わせられる面側に、３μｍ以上１００μｍ以下の凹凸を有していても構わない。
　前記半導体チップが３μｍ以上１００μｍ以下の凹凸を有する場合、シート状樹脂組成物との間に気泡が噛み込み易い。しかしながら、上述の通り、前記工程Ｄの後は、前記シート状樹脂組成物の粘度は、上昇している。従って、気泡が噛み込み易い３μｍ以上１００μｍ以下の凹凸を有する半導体チップを用いた場合であっても、ボイドの膨張が抑制されているため、種々の不具合の原因となる大きなボイドの発生を抑制することができる。
　本発明によれば、シート状樹脂組成物と被着体との間にボイドが噛み込んだとしても、ボイドの膨張を抑制することが可能な半導体装置の製造方法を提供することが可能となる。
本発明の一実施形態に係る半導体装置の製造方法を説明するための断面模式図である。 本発明の一実施形態に係る半導体装置の製造方法を説明するための断面模式図である。 本発明の一実施形態に係る半導体装置の製造方法を説明するための断面模式図である。 本発明の一実施形態に係る半導体装置の製造方法を説明するための断面模式図である。 シート状樹脂組成物付チップの準備方法の一例を説明するための断面模式図である。 シート状樹脂組成物付チップの準備方法の一例を説明するための断面模式図である。 シート状樹脂組成物付チップの準備方法の一例を説明するための断面模式図である。 シート状樹脂組成物付チップの準備方法の一例を説明するための断面模式図である。 シート状樹脂組成物付チップの準備方法の一例を説明するための断面模式図である。 シート状樹脂組成物付チップの準備方法の一例を説明するための断面模式図である。 シート状樹脂組成物付チップの準備方法の一例を説明するための断面模式図
　以下、本発明の実施形態について、図面を参照しつつ説明する。
　本発明に係る半導体装置の製造方法は、
　半導体チップにシート状樹脂組成物が貼り付けられたシート状樹脂組成物付きチップを準備する工程Ａと、
　被着体を準備する工程Ｂと、
　前記被着体に、前記シート状樹脂組成物付きチップを、前記シート状樹脂組成物を貼り合わせ面にして貼り付ける工程Ｃと、
　前記工程Ｃの後に、前記シート状樹脂組成物を加熱して半硬化させる工程Ｄと、
　前記工程Ｄの後に、前記工程Ｄにおける加熱よりも高温で前記シート状樹脂組成物を加熱して硬化させる工程Ｅとを含む。
　以下では、本発明に係る一実施形態として、まず、半導体チップにバンプが形成されているとともに、被着体としての搭載用基板に電極が形成されている場合について説明する。
　すなわち、本実施形態に係る半導体装置の製造方法は、
　半導体チップのバンプ形成面にシート状樹脂組成物が貼り付けられたシート状樹脂組成物付きチップを準備する工程Ａと、
　電極が形成された実装用基板を準備する工程Ｂと、
　前記実装用基板に、前記シート状樹脂組成物付きチップを、前記シート状樹脂組成物を貼り合わせ面にして貼り付けて、前記半導体チップに形成された前記バンプと前記実装用基板に形成された電極とを対向させる工程Ｃと、
　前記工程Ｃの後に、前記シート状樹脂組成物を加熱して半硬化させる工程Ｄと、
　前記工程Ｄの後に、前記工程Ｄにおける加熱よりも高温で加熱し、前記バンプと前記電極とを接合するとともに、前記シート状組成物を硬化させる工程Ｅとを少なくとも含む。
　［シート状樹脂組成物付きチップを準備する工程］
　図１～図４は、本発明の一実施形態に係る半導体装置の製造方法を説明するための断面模式図である。
　本実施形態に係る半導体装置の製造方法においては、まず、図１に示すように、シート状樹脂組成物付きチップ４０を準備する（工程Ａ）。なお、シート状樹脂組成物付チップ４０の具体的な準備方法については、後に図５～図１１を参照しながら説明することとする。
　シート状樹脂組成物付きチップ４０は、バンプ１８が形成された半導体チップ２２と、半導体チップ２２のバンプ形成面２２ａに貼り付けられたシート状樹脂組成物１０とを有する。シート状樹脂組成物付きチップ４０では、バンプ１８がシート状樹脂組成物１０に埋め込まれるとともに、半導体チップ２２のバンプ形成面２２ａがシート状樹脂組成物１０に貼り付けられている。
　（シート状樹脂組成物）
　シート状樹脂組成物１０は、半導体チップ２２を実装用基板５０（図２参照）に実装する際に、半導体チップ２２と実装用基板５０との間隙を封止する機能を有する。
　シート状樹脂組成物１０は、２００℃で１０秒間加熱した後の熱硬化率が１０％以上であることが好ましく、１３％以上であることがより好ましい。シート状樹脂組成物１０の２００℃で１０秒間加熱した際の熱硬化率が１０％以上であると、前記工程Ｄの後のシート状樹脂組成物１０は、ある程度粘度が上昇していることとなる。その結果、よりボイドの膨張を抑制することができる。
　熱硬化率は、示差走査熱量測定（ＤＳＣ）を用い、発熱量を測定して求める。具体的には、まず、熱硬化させていないシート状樹脂組成物を作成し、－１０℃から昇温速度１０℃／分の条件で、３５０℃（熱硬化反応が完全に完了したと想定される温度）まで昇温した際の発熱量（未硬化サンプルの反応熱量）を測定する。また、熱硬化前のシート状樹脂組成物を、２００℃で１０秒間加熱したサンプルを作成する。
　次に、２００℃で１０秒間加熱したサンプルについて、－１０℃から昇温速度１０℃／分の条件で、３５０℃（熱硬化反応が完全に完了したと想定される温度）まで昇温した際の発熱量（２００℃で１０秒間加熱したサンプルの反応熱量）を測定する。その後、以下の式（３）により熱硬化率を得る。なお、発熱量は、示差走査熱量計にて測定される発熱ピークの立ち上がり温度と反応終了温度の２点を結んだ直線とピークで囲まれる面積を用いて求める。
　式（３）：
熱硬化率＝［｛（未硬化サンプルの反応熱量）－（２００℃で１０秒間加熱したサンプルの反応熱量）｝／（未硬化サンプルの反応熱量）］×１００（％）
　シート状樹脂組成物１０は、２００℃未満における最低溶融粘度が１００Ｐａ・ｓ～５０００Ｐａ・ｓの範囲内にあることが好ましく、３００Ｐａ・ｓ～４０００Ｐａ・ｓの範囲内にあることがより好ましく、５００Ｐａ・ｓ～２０００Ｐａ・ｓの範囲内にあることがさらに好ましい。シート状樹脂組成物１０の２００℃未満における最低溶融粘度が１００Ｐａ・ｓ～５０００Ｐａ・ｓの範囲内にあると、前記工程Ｃにおいて、半導体チップ２２に形成されたバンプ１８と実装用基板５０に形成された電極５２とを容易にシート状樹脂組成物１０に埋め込みながら、対向させることができる。
　シート状樹脂組成物１０の２００℃未満における最低溶融粘度とは、熱硬化前の２００℃未満における最低溶融粘度をいう。
　シート状樹脂組成物１０の２００℃未満における最低溶融粘度は、シート状樹脂組成物１０の構成材料の選択によりコントロールすることができる。特に、熱可塑性樹脂の選択によりコントロールすることができる。具体的に、熱可塑性樹脂として、例えば、低分子量のものを使用すると、２００℃未満における最低溶融粘度を小さくすることができ、例えば、高分子量のものを使用すると、２００℃未満における最低溶融粘度を大きくすることができる。
　シート状樹脂組成物１０としては、熱可塑性樹脂と熱硬化性樹脂とを併用したものが挙げられる。また、熱硬化性樹脂単独でも使用可能である。
　前記熱可塑性樹脂としては、天然ゴム、ブチルゴム、イソプレンゴム、クロロプレンゴム、エチレン－酢酸ビニル共重合体、エチレン－アクリル酸共重合体、エチレン－アクリル酸エステル共重合体、ポリブタジエン樹脂、ポリカーボネート樹脂、熱可塑性ポリイミド樹脂、６－ナイロンや６，６－ナイロン等のポリアミド樹脂、フェノキシ樹脂、アクリル樹脂、ＰＥＴやＰＢＴ等の飽和ポリエステル樹脂、ポリアミドイミド樹脂、フッ素樹脂等が挙げられる。これらの熱可塑性樹脂は単独で、又は２種以上を併用して用いることができる。これらの熱可塑性樹脂のうち、イオン性不純物が少なく耐熱性が高く、半導体チップの信頼性を確保できるアクリル樹脂が特に好ましい。
　前記アクリル樹脂としては、特に限定されるものではなく、炭素数３０以下、特に炭素数４～１８の直鎖若しくは分岐のアルキル基を有するアクリル酸又はメタクリル酸のエステルの１種又は２種以上を成分とする重合体等が挙げられる。前記アルキル基としては、例えばメチル基、エチル基、プロピル基、イソプロピル基、ｎ－ブチル基、ｔ－ブチル基、イソブチル基、アミル基、イソアミル基、へキシル基、へプチル基、シクロヘキシル基、２－エチルヘキシル基、オクチル基、イソオクチル基、ノニル基、イソノニル基、デシル基、イソデシル基、ウンデシル基、ラウリル基、トリデシル基、テトラデシル基、ステアリル基、オクタデシル基、又はドデシル基等が挙げられる。
　また、前記重合体を形成する他のモノマーとしては、特に限定されるものではなく、例えばアクリル酸、メタクリル酸、カルボキシエチルアクリレート、カルボキシペンチルアクリレート、イタコン酸、マレイン酸、フマール酸若しくはクロトン酸等の様なカルボキシル基含有モノマー、無水マレイン酸若しくは無水イタコン酸等の様な酸無水物モノマー、（メタ）アクリル酸２－ヒドロキシエチル、（メタ）アクリル酸２－ヒドロキシプロピル、（メタ）アクリル酸４－ヒドロキシブチル、（メタ）アクリル酸６－ヒドロキシヘキシル、（メタ）アクリル酸８－ヒドロキシオクチル、（メタ）アクリル酸１０－ヒドロキシデシル、（メタ）アクリル酸１２－ヒドロキシラウリル若しくは（４－ヒドロキシメチルシクロヘキシル）－メチルアクリレート等の様なヒドロキシル基含有モノマー、スチレンスルホン酸、アリルスルホン酸、２－（メタ）アクリルアミド－２－メチルプロパンスルホン酸、（メタ）アクリルアミドプロパンスルホン酸、スルホプロピル（メタ）アクリレート若しくは（メタ）アクリロイルオキシナフタレンスルホン酸等の様なスルホン酸基含有モノマー、又は２－ヒドロキシエチルアクリロイルホスフェート等の様な燐酸基含有モノマーが挙げられる。
　シート状樹脂組成物１０全体に対する熱可塑性樹脂の含有量は、好ましくは３重量％以上であり、より好ましくは４重量％以上である。４重量％以上であると、良好な可とう性が得られる。一方、樹脂成分中の熱可塑性樹脂の含有量は、好ましくは１５重量％以下であり、より好ましくは１２重量％以下であり、さらに好ましくは８重量％以下である。８重量％以下であると、良好な熱的信頼性が得られる。
　前記熱可塑性樹脂の中でも、半硬化前のシート状樹脂組成物１０の粘度を低粘度とするために、アクリル樹脂が好ましい。
　前記熱硬化性樹脂としては、フェノール樹脂、アミノ樹脂、不飽和ポリエステル樹脂、エポキシ樹脂、ポリウレタン樹脂、シリコーン樹脂、又は熱硬化性ポリイミド樹脂等が挙げられる。これらの樹脂は、単独で又は２種以上を併用して用いることができる。特に、半導体チップを腐食させるイオン性不純物等の含有が少ないエポキシ樹脂が好ましい。また、エポキシ樹脂の硬化剤としてはフェノール樹脂が好ましい。
　前記エポキシ樹脂は、接着剤組成物として一般に用いられるものであれば特に限定は無く、例えばビスフェノールＡ型、ビスフェノールＦ型、ビスフェノールＳ型、臭素化ビスフェノールＡ型、水添ビスフェノールＡ型、ビスフェノールＡＦ型、ビフェニル型、ナフタレン型、フルオンレン型、フェノールノボラック型、オルソクレゾールノボラック型、トリスヒドロキシフェニルメタン型、テトラフェニロールエタン型等の二官能エポキシ樹脂や多官能エポキシ樹脂、又はヒダントイン型、トリスグリシジルイソシアヌレート型若しくはグリシジルアミン型等のエポキシ樹脂が用いられる。これらは単独で、又は２種以上を併用して用いることができる。これらのエポキシ樹脂のうちノボラック型エポキシ樹脂、ビフェニル型エポキシ樹脂、トリスヒドロキシフェニルメタン型樹脂又はテトラフェニロールエタン型エポキシ樹脂が特に好ましい。これらのエポキシ樹脂は、硬化剤としてのフェノール樹脂との反応性に富み、耐熱性等に優れるからである。
　さらに、前記フェノール樹脂は、前記エポキシ樹脂の硬化剤として作用するものであり、例えば、フェノールノボラック樹脂、フェノールアラルキル樹脂、クレゾールノボラック樹脂、ｔｅｒｔ－ブチルフェノールノボラック樹脂、ノニルフェノールノボラック樹脂等のノボラック型フェノール樹脂、レゾール型フェノール樹脂、ポリパラオキシスチレン等のポリオキシスチレン等が挙げられる。これらは単独で、又は２種以上を併用して用いることができる。これらのフェノール樹脂のうちフェノールノボラック樹脂、フェノールアラルキル樹脂が特に好ましい。封止信頼性を向上させることができるからである。
　前記エポキシ樹脂とフェノール樹脂の配合割合は、例えば、前記エポキシ樹脂成分中のエポキシ基１当量当たりフェノール樹脂中の水酸基が０．５～２．０当量になるように配合することが好適である。より好適なのは、０．８～１．２当量である。すなわち、両者の配合割合が前記範囲を外れると、十分な硬化反応が進まず、エポキシ樹脂硬化物の特性が劣化し易くなるからである。
　シート状樹脂組成物１０全体に対する熱硬化性樹脂の含有量は、１０重量％以上であることが好ましく、１２重量％以上であることがより好ましく、１５重量％以上であることがさらに好ましい。１０％以上であると、良好な可とう性が得られる。一方、樹脂成分中の熱硬化性樹脂の含有量は、３０重量％以下であることが好ましく、２５重量％以下であることがより好ましく、２０重量％以下であることがさらに好ましい。２０重量％以下であると、シートのタックが抑制され取扱い性が向上する。
　エポキシ樹脂とフェノール樹脂の熱硬化促進触媒としては、特に制限されず、公知の熱硬化促進触媒の中から適宜選択して用いることができる。熱硬化促進触媒は単独で又は２種以上を組み合わせて用いることができる。熱硬化促進触媒としては、例えば、アミン系硬化促進剤、リン系硬化促進剤、イミダゾール系硬化促進剤、ホウ素系硬化促進剤、リン－ホウ素系硬化促進剤などを用いることができる。
　前記熱硬化促進触媒の含有量は、熱硬化性樹脂１００重量部に対して、０．７重量部以上であることが好ましく、２．４重量部以上であることがより好ましく、４．８重量部以上であることがさらに好ましい。４．８重量部以上であると、半硬化工程において容易にシート状樹脂組成物１０を半硬化させることができる。また、熱硬化促進触媒の含有量は、好ましくは２４重量部以下である。２４重量部以下であると、熱硬化性樹脂の保存性を向上させることができる。
　また、シート状樹脂組成物１０には、無機充填剤を適宜配合することができる。無機充填剤の配合は、導電性の付与や熱伝導性の向上、貯蔵弾性率の調節等を可能にする。
　前記無機充填剤としては、例えば、シリカ、クレー、石膏、炭酸カルシウム、硫酸バリウム、酸化アルミナ、酸化ベリリウム、炭化珪素、窒化珪素等のセラミック類、アルミニウム、銅、銀、金、ニッケル、クロム、鉛、錫、亜鉛、パラジウム、半田等の金属、又は合金類、その他カーボン等からなる種々の無機粉末が挙げられる。これらは、単独で又は２種以上を併用して用いることができる。なかでも、シリカ、特に溶融シリカが好適に用いられる。
　無機充填剤の平均粒径は、０．０１～３０μｍの範囲内であることが好ましく、０．０５～１０μｍの範囲内であることがより好ましい。なお、本発明においては、平均粒径が相互に異なる無機充填剤同士を組み合わせて使用してもよい。また、平均粒径は、光度式の粒度分布計（ＨＯＲＩＢＡ製、装置名；ＬＡ－９１０）により求めた値である。
　前記無機充填剤の配合量は、有機樹脂成分１００重量部に対し１００～１４００重量部に設定することが好ましい。特に好ましくは２３０～９００重量部である。無機充填剤の配合量を１００重量部以上にすると、耐熱性や強度が向上する。また、１４００重量部以下とすることにより、流動性が確保できる。これにより、接着性や埋め込み性が低下することを防止できる。
　なお、シート状樹脂組成物１０には、前記無機充填剤以外に、必要に応じて他の添加剤を適宜に配合することができる。他の添加剤としては、例えば難燃剤、シランカップリング剤、イオントラップ剤、カーボンブラック等の顔料等が挙げられる。前記難燃剤としては、例えば、三酸化アンチモン、五酸化アンチモン、臭素化エポキシ樹脂等が挙げられる。これらは、単独で、又は２種以上を併用して用いることができる。前記シランカップリング剤としては、例えば、β－（３、４－エポキシシクロヘキシル）エチルトリメトキシシラン、γ－グリシドキシプロピルトリメトキシシラン、γ－グリシドキシプロピルメチルジエトキシシラン等が挙げられる。これらの化合物は、単独で又は２種以上を併用して用いることができる。前記イオントラップ剤としては、例えばハイドロタルサイト類、水酸化ビスマス等が挙げられる。これらは、単独で又は２種以上を併用して用いることができる。また、実装時に半田の酸化膜を除去することを目的として、有機酸を添加することもできる。
　シート状樹脂組成物１０の厚さ（複層の場合は、総厚）は特に限定されないものの、硬化後の樹脂の強度や充填性を考慮すると５μｍ以上５００μｍ以下が好ましい。なお、シート状樹脂組成物１０の厚さは、チップ２２と実装用基板５０との間隙の幅を考慮して適宜設定することができる。
　シート状樹脂組成物１０は、例えば、次の通りにして作製される。まず、シート状樹脂組成物１０の形成材料である樹脂組成物溶液を作製する。当該樹脂組成物溶液には、前述の通り、前記樹脂組成物やフィラー、その他各種の添加剤等が配合されている。
　次に、樹脂組成物溶液を基材セパレータ上に所定厚みとなる様に塗布して塗布膜を形成した後、該塗布膜を所定条件下で乾燥させ、シート状樹脂組成物１０を形成する。塗布方法としては特に限定されず、例えば、ロール塗工、スクリーン塗工、グラビア塗工等が挙げられる。また、乾燥条件としては、例えば乾燥温度７０～１６０℃、乾燥時間１～５分間の範囲内で行われる。
　半導体チップ２２の厚さとしては、特に限定されないが、例えば、１０～１０００μｍの範囲内で適宜設定することができる。
　半導体チップ２２に形成されているバンプ１８の高さとしては、特に限定されないが、３μｍ以上１００μｍ以下のものを用いることができる。バンプ１８の高さが３μｍ以上１００μｍ以下の場合、すなわち、半導体チップ２２が３μｍ以上１００μｍ以下の凹凸を有する場合、シート状樹脂組成物１０との間に気泡が噛み込み易い。しかしながら、前記工程Ｄの後は、シート状樹脂組成物１０の粘度は、上昇している。従って、気泡が噛み込み易い３μｍ以上１００μｍ以下の凹凸を有する半導体チップ２２を用いた場合であっても、ボイドの膨張が抑制されているため、種々の不具合の原因となる大きなボイドの発生を抑制することができる。
　バンプ１８の構成材料としては、特に限定されないが、ハンダが好ましく、Ｓｎ－Ｐｂ系、Ｐｂ－Ｓｎ－Ｓｂ系、Ｓｎ－Ｓｂ系、Ｓｎ－Ｐｂ－Ｂｉ系、Ｂｉ－Ｓｎ系、Ｓｎ－Ｃｕ系、Ｓｎ－Ｐｂ－Ｃｕ系、Ｓｎ－Ｉｎ系、Ｓｎ－Ａｇ系、Ｓｎ－Ｐｂ－Ａｇ系、Ｐｂ－Ａｇ系のハンダを挙げることができる。
　［実装用基板を準備する工程］
　また、図２に示すように、表面５０ａに電極５２が形成された実装用基板５０を準備する（工程Ｂ）。
　実装用基板５０としては、リードフレームや回路基板（配線回路基板など）等の各種基板を用いることができる。このような基板の材質としては、特に限定されるものではないが、セラミック基板や、プラスチック基板が挙げられる。プラスチック基板としては、例えば、エポキシ基板、ビスマレイミドトリアジン基板、ポリイミド基板等が挙げられる。
また、実装用基板５０として半導体ウエハを用いることもできる。
　実装用基板５０に形成されている電極５２の高さとしては、特に限定されないが、３μｍ以上１００μｍ以下のものを用いることができる。電極５２の高さが３μｍ以上１００μｍ以下の場合、すなわち、搭載用基板５０が３μｍ以上１００μｍ以下の凹凸を有する場合、シート状樹脂組成物１０との間に気泡が噛み込み易い。しかしながら、前記工程Ｄの後は、シート状樹脂組成物１０の粘度は、上昇している。従って、気泡が噛み込み易い３μｍ以上１００μｍ以下の凹凸を有する搭載用基板５０を用いた場合であっても、ボイドの膨張が抑制されているため、種々の不具合の原因となる大きなボイドの発生を抑制することができる。
　［半導体チップに形成されたバンプと実装用基板に形成された電極とを対向させる工程］
　前記工程Ａ及び前記工程Ｂの後、図３に示すように、実装用基板５０に、シート状樹脂組成物付きチップ４０を、シート状樹脂組成物１０を貼り合わせ面にして貼り付けて、半導体チップ２２に形成されたバンプ１８と実装用基板５０に形成された電極５２とを対向させる（工程Ｃ）。具体的には、まず、シート状樹脂組成物付きチップ４０のシート状樹脂組成物１０を実装用基板５０に対向させて配置し、次に、フリップチップボンダーを用い、シート状樹脂組成物付きチップ４０側から圧力を加える。これにより、バンプ１８と電極５２とは、シート状樹脂組成物１０に埋め込まれながら、対向される。貼り合わせ時の温度は、１００～２００℃が好ましく、より好ましくは１５０～１９０℃である。ただし、ハンダの融点よりも低い温度であることが好ましい。また、貼り合わせ時の圧力は０．０１～１０ＭＰａが好ましく、より好ましくは０．１～１ＭＰａである。
　貼り合わせの温度が１５０℃以上であると、シート状樹脂組成物１０の粘度が低下し、凹凸を空隙なく充填できる。また、貼り合わせの温度が、２００℃以下であると、シート状樹脂組成物１０の硬化反応を抑制したまま貼り合わせが可能となる。
　この際、シート状樹脂組成物１０の２００℃未満における最低溶融粘度が１００Ｐａ・ｓ～５０００Ｐａ・ｓの範囲内にあると、半導体チップ２２に形成されたバンプ１８と実装用基板５０に形成された電極５２とを容易にシート状樹脂組成物１０に埋め込みながら、対向させることができる。
　［シート状樹脂組成物を半硬化させる工程］
　前記工程Ｃの後、シート状樹脂組成物１０を加熱して半硬化させる（工程Ｄ）。前記工程Ｄにおける加熱温度は、１００～２３０℃であることが好ましく、１５０～２１０℃であることがより好ましい。前記工程Ｄにおける加熱温度は、ハンダの融点よりも低い温度であることが好ましい。また、加熱時間は、１～３００秒の範囲内であることが好ましく、３～１２０秒の範囲内であることがより好ましい。
　この際、シート状樹脂組成物１０の２００℃で１０秒間加熱した後の熱硬化率が１０％以上であると、工程Ｄの後のシート状樹脂組成物１０は、ある程度粘度が上昇していることとなる。その結果、よりボイドの膨張を抑制することができる。
　［バンプと電極とを接合するとともに、シート状組成物を硬化させる工程］
　前記工程Ｄの後、前記工程Ｄにおける加熱よりも高温で加熱し、図４に示すように、バンプ１８と電極５２とを接合するとともに、シート状組成物１０を硬化させる（工程Ｅ）。図４では、バンプ１８がハンダで構成され、バンプ１８が溶融することによりバンプ１８と電極５２とが接合（電気的に接続）されている様子を示している。
　この際の加熱温度は、１８０～４００℃であることが好ましく、２００～３００℃であることがより好ましい。また、加熱時間は、１～３００秒の範囲内であることが好ましく、３～１２０秒の範囲内であることがより好ましい。
　以上により、半導体装置６０が得られる。
　以上、本実施形態に係る半導体装置の製造方法によれば、搭載用基板５０に、シート状樹脂組成物付きチップ４０を、シート状樹脂組成物１０を貼り合わせ面にして貼り付けた状態でシート状樹脂組成物１０を加熱して半硬化させる（工程Ｄ）。従って、シート状樹脂組成物１０は半硬化前よりも粘度が上昇する。その後、工程Ｄにおける加熱よりも高温で加熱し、シート状樹脂組成物１０を硬化させる（工程Ｅ）。工程Ｅの段階では、すでにシート状樹脂組成物１０は半硬化しているため、仮にシート状樹脂組成物１０と搭載用基板５０との間にボイドが噛み込んでいたとしても、ボイドの膨張は抑制されている。従って、種々の不具合の原因となる大きなボイドの発生を抑制することができる。
　次に、シート状樹脂組成物付チップの具体的な準備方法について、図５～図１１を参照しながら説明する。
　本実施形態のシート状樹脂組成物は、裏面研削用テープ又はダイシングテープと一体化して使用できる。これにより、半導体装置を効率よく製造できる。図５～図１１は、シート状樹脂組成物付チップの準備方法の一例を説明するための断面模式図である。
　［裏面研削用テープ一体型シート状樹脂組成物］
　本実施形態に係る裏面研削用テープ一体型シート状樹脂組成物は、裏面研削用テープと、前述のシート状樹脂組成物とを備える。
　図５は、裏面研削用テープ一体型シート状樹脂組成物１００の断面模式図である。図５に示すように、裏面研削用テープ一体型シート状樹脂組成物１００は、裏面研削用テープ１２と、シート状樹脂組成物１０とを備える。裏面研削用テープ１２は、基材１２ａ及び粘着剤層１２ｂを備え、粘着剤層１２ｂは基材１２ａ上に設けられている。シート状樹脂組成物１０は粘着剤層１２ｂ上に設けられている。
　なお、シート状樹脂組成物１０は、図５に示したように裏面研削用テープ１２の全面に積層されていなくてもよく、半導体ウェハ１６（図６参照）との貼り合わせに十分なサイズで設けられていればよい。
　（裏面研削用テープ）
　裏面研削用テープ１２は、基材１２ａと、基材１２ａ上に積層された粘着剤層１２ｂとを備えている。
　上記基材１２ａは裏面研削用テープ一体型シート状樹脂組成物１００の強度母体となるものである。例えば、低密度ポリエチレン、直鎖状ポリエチレン、中密度ポリエチレン、高密度ポリエチレン、超低密度ポリエチレン、ランダム共重合ポリプロピレン、ブロック共重合ポリプロピレン、ホモポリプロレン、ポリブテン、ポリメチルペンテンなどのポリオレフィン、エチレン－酢酸ビニル共重合体、アイオノマー樹脂、エチレン－（メタ）アクリル酸共重合体、エチレン－（メタ）アクリル酸エステル（ランダム、交互）共重合体、エチレン－ブテン共重合体、エチレン－ヘキセン共重合体、ポリウレタン、ポリエチレンテレフタレート、ポリエチレンナフタレートなどのポリエステル、ポリカーボネート、ポリイミド、ポリエーテルエーテルケトン、ポリイミド、ポリエーテルイミド、ポリアミド、全芳香族ポリアミド、ポリフェニルスルフイド、アラミド（紙）、ガラス、ガラスクロス、フッ素樹脂、ポリ塩化ビニル、ポリ塩化ビニリデン、セルロース系樹脂、シリコーン樹脂、金属（箔）、紙などが挙げられる。粘着剤層１２ｂが紫外線硬化型である場合、基材１２ａは紫外線に対し透過性を有するものが好ましい。
　上記基材１２ａは、同種又は異種のものを適宜に選択して使用することができ、必要に応じて数種をブレンドしたものを用いることができる。基材１２ａの表面には、慣用の表面処理を施すことができる。基材１２ａには、帯電防止能を付与するため、上記の基材１２ａ上に金属、合金、これらの酸化物などからなる厚さが３０～５００Å程度の導電性物質の蒸着層を設けることができる。基材１２ａは単層又は２種以上の複層でもよい。
　基材１２ａの厚さは適宜に決定でき、一般的には５μｍ以上２００μｍ以下程度であり、好ましくは３５μｍ以上１２０μｍ以下である。
　なお、基材１２ａには、各種添加剤（例えば、着色剤、充填剤、可塑剤、老化防止剤、酸化防止剤、界面活性剤、難燃剤など）が含まれていてもよい。
　粘着剤層１２ｂの形成に用いる粘着剤は、半導体ウェハの裏面研削時に半導体ウェハを保持でき、裏面研削後に半導体ウェハから剥離できるものであれば特に制限されない。例えば、アクリル系粘着剤、ゴム系粘着剤などの一般的な感圧性接着剤を用いることができる。上記感圧性接着剤としては、半導体ウェハやガラスなどの汚染をきらう電子部品の超純水やアルコールなどの有機溶剤による清浄洗浄性などの点から、アクリル系ポリマーをベースポリマーとするアクリル系粘着剤が好ましい。
　上記アクリル系ポリマーとしては、アクリル酸エステルを主モノマー成分として用いたものが挙げられる。上記アクリル酸エステルとしては、例えば、（メタ）アクリル酸アルキルエステル（例えば、メチルエステル、エチルエステル、プロピルエステル、イソプロピルエステル、ブチルエステル、イソブチルエステル、ｓ－ブチルエステル、ｔ－ブチルエステル、ペンチルエステル、イソペンチルエステル、ヘキシルエステル、ヘプチルエステル、オクチルエステル、２－エチルヘキシルエステル、イソオクチルエステル、ノニルエステル、デシルエステル、イソデシルエステル、ウンデシルエステル、ドデシルエステル、トリデシルエステル、テトラデシルエステル、ヘキサデシルエステル、オクタデシルエステル、エイコシルエステルなどのアルキル基の炭素数１～３０、特に炭素数４～１８の直鎖状又は分岐鎖状のアルキルエステルなど）及び（メタ）アクリル酸シクロアルキルエステル（例えば、シクロペンチルエステル、シクロヘキシルエステルなど）の１種又は２種以上を単量体成分として用いたアクリル系ポリマーなどが挙げられる。なお、（メタ）アクリル酸エステルとはアクリル酸エステル及び／又はメタクリル酸エステルをいい、本発明の（メタ）とは全て同様の意味である。
　上記アクリル系ポリマーは、凝集力、耐熱性などの改質を目的として、必要に応じ、上記（メタ）アクリル酸アルキルエステル又はシクロアルキルエステルと共重合可能な他のモノマー成分に対応する単位を含んでいてもよい。このようなモノマー成分として、例えば、アクリル酸、メタクリル酸、カルボキシエチル（メタ）アクリレート、カルボキシペンチル（メタ）アクリレート、イタコン酸、マレイン酸、フマル酸、クロトン酸などのカルボキシル基含有モノマー；無水マレイン酸、無水イタコン酸などの酸無水物モノマー；（メタ）アクリル酸２－ヒドロキシエチル、（メタ）アクリル酸２－ヒドロキシプロピル、（メタ）アクリル酸４－ヒドロキシブチル、（メタ）アクリル酸６－ヒドロキシヘキシル、（メタ）アクリル酸８－ヒドロキシオクチル、（メタ）アクリル酸１０－ヒドロキシデシル、（メタ）アクリル酸１２－ヒドロキシラウリル、（４－ヒドロキシメチルシクロヘキシル）メチル（メタ）アクリレートなどのヒドロキシル基含有モノマー；スチレンスルホン酸、アリルスルホン酸、２－（メタ）アクリルアミド－２－メチルプロパンスルホン酸、（メタ）アクリルアミドプロパンスルホン酸、スルホプロピル（メタ）アクリレート、（メタ）アクリロイルオキシナフタレンスルホン酸などのスルホン酸基含有モノマー；２－ヒドロキシエチルアクリロイルホスフェートなどのリン酸基含有モノマー；アクリルアミド、アクリロニトリルなどがあげられる。これら共重合可能なモノマー成分は、１種又は２種以上使用できる。これら共重合可能なモノマーの使用量は、全モノマー成分の４０重量％以下が好ましい。
　さらに、上記アクリル系ポリマーは、架橋させるため、多官能性モノマーなども、必要に応じて共重合用モノマー成分として含むことができる。このような多官能性モノマーとして、例えば、ヘキサンジオールジ（メタ）アクリレート、（ポリ）エチレングリコールジ（メタ）アクリレート、（ポリ）プロピレングリコールジ（メタ）アクリレート、ネオペンチルグリコールジ（メタ）アクリレート、ペンタエリスリトールジ（メタ）アクリレート、トリメチロールプロパントリ（メタ）アクリレート、ペンタエリスリトールトリ（メタ）アクリレート、ジペンタエリスリトールヘキサ（メタ）アクリレート、エポキシ（メタ）アクリレート、ポリエステル（メタ）アクリレート、ウレタン（メタ）アクリレートなどがあげられる。これらの多官能性モノマーも１種又は２種以上用いることができる。多官能性モノマーの使用量は、粘着特性などの点から、全モノマー成分の３０重量％以下が好ましい。
　上記アクリル系ポリマーは、単一モノマー又は２種以上のモノマー混合物を重合に付すことにより得られる。重合は、溶液重合、乳化重合、塊状重合、懸濁重合などの何れの方式で行うこともできる。清浄な被着体への汚染防止などの点から、低分子量物質の含有量が小さいのが好ましい。この点から、アクリル系ポリマーの数平均分子量は、好ましくは３０万以上、さらに好ましくは４０万～３００万程度である。
　また、上記粘着剤には、ベースポリマーであるアクリル系ポリマーなどの数平均分子量を高めるため、外部架橋剤を適宜に採用することもできる。外部架橋方法の具体的手段としては、ポリイソシアネート化合物、エポキシ化合物、アジリジン化合物、メラミン系架橋剤などのいわゆる架橋剤を添加し反応させる方法があげられる。外部架橋剤を使用する場合、その使用量は、架橋すべきベースポリマーとのバランスにより、さらには、粘着剤としての使用用途によって適宜決定される。一般的には、上記ベースポリマー１００重量部に対して、５重量部程度以下、さらには０．１～５重量部配合するのが好ましい。さらに、粘着剤には、必要により、上記成分のほかに、従来公知の各種の粘着付与剤、老化防止剤などの添加剤を用いてもよい。
　粘着剤層１２ｂは放射線硬化型粘着剤により形成することができる。放射線硬化型粘着剤は、紫外線などの放射線の照射により架橋度を増大させてその粘着力を容易に低下させることができ、ピックアップを容易に行うことができる。放射線としては、Ｘ線、紫外線、電子線、α線、β線、中性子線などが挙げられる。
　放射線硬化型粘着剤は、炭素－炭素二重結合などの放射線硬化性の官能基を有し、かつ粘着性を示すものを特に制限なく使用することができる。放射線硬化型粘着剤としては、例えば、上記アクリル系粘着剤、ゴム系粘着剤などの一般的な感圧性粘着剤に、放射線硬化性のモノマー成分やオリゴマー成分を配合した添加型の放射線硬化性粘着剤を例示できる。
　配合する放射線硬化性のモノマー成分としては、例えば、ウレタンオリゴマー、ウレタン（メタ）アクリレート、トリメチロールプロパントリ（メタ）アクリレート、テトラメチロールメタンテトラ（メタ）アクリレート、ペンタエリスリトールトリ（メタ）アクリレート、ペンタエリストールテトラ（メタ）アクリレート、ジペンタエリストールモノヒドロキシペンタ（メタ）アクリレート、ジペンタエリスリトールヘキサ（メタ）アクリレート、１，４－ブタンジオールジ（メタ）アクリレートなどがあげられる。また放射線硬化性のオリゴマー成分はウレタン系、ポリエーテル系、ポリエステル系、ポリカーボネート系、ポリブタジエン系など種々のオリゴマーがあげられ、その重量平均分子量が１００～３００００程度の範囲のものが適当である。放射線硬化性のモノマー成分やオリゴマー成分の配合量は、上記粘着剤層の種類に応じて、粘着剤層の粘着力を低下できる量を、適宜に決定することができる。一般的には、粘着剤を構成するアクリル系ポリマーなどのベースポリマー１００重量部に対して、例えば５～５００重量部、好ましくは４０～１５０重量部程度である。
　また、放射線硬化型粘着剤としては、上記説明した添加型の放射線硬化性粘着剤のほかに、ベースポリマーとして、炭素－炭素二重結合をポリマー側鎖または主鎖中もしくは主鎖末端に有するものを用いた内在型の放射線硬化性粘着剤があげられる。内在型の放射線硬化性粘着剤は、低分子成分であるオリゴマー成分などを含有する必要がなく、または多くは含まないため、経時的にオリゴマー成分などが粘着剤在中を移動することなく、安定した層構造の粘着剤層を形成することができるため好ましい。
　上記炭素－炭素二重結合を有するベースポリマーは、炭素－炭素二重結合を有し、かつ粘着性を有するものを特に制限なく使用できる。このようなベースポリマーとしては、アクリル系ポリマーを基本骨格とするものが好ましい。アクリル系ポリマーの基本骨格としては、上記例示したアクリル系ポリマーがあげられる。
　上記アクリル系ポリマーへの炭素－炭素二重結合の導入法は特に制限されず、様々な方法を採用できるが、炭素－炭素二重結合はポリマー側鎖に導入するのが分子設計が容易である。例えば、予め、アクリル系ポリマーに官能基を有するモノマーを共重合した後、この官能基と反応しうる官能基および炭素－炭素二重結合を有する化合物を、炭素－炭素二重結合の放射線硬化性を維持したまま縮合または付加反応させる方法があげられる。
　これら官能基の組合せの例としては、カルボン酸基とエポキシ基、カルボン酸基とアジリジル基、ヒドロキシル基とイソシアネート基などがあげられる。これら官能基の組合せのなかでも反応追跡の容易さから、ヒドロキシル基とイソシアネート基との組合せが好適である。また、これら官能基の組み合わせにより、上記炭素－炭素二重結合を有するアクリル系ポリマーを生成するような組合せであれば、官能基はアクリル系ポリマーと上記化合物のいずれの側にあってもよいが、上記の好ましい組み合わせでは、アクリル系ポリマーがヒドロキシル基を有し、上記化合物がイソシアネート基を有する場合が好適である。この場合、炭素－炭素二重結合を有するイソシアネート化合物としては、例えば、メタクリロイルイソシアネート、２－メタクリロイルオキシエチルイソシアネート、ｍ－イソプロペニル－α，α－ジメチルベンジルイソシアネートなどがあげられる。また、アクリル系ポリマーとしては、上記例示のヒドロキシ基含有モノマーや２－ヒドロキシエチルビニルエーテル、４－ヒドロキシブチルビニルエーテル、ジエチレングルコールモノビニルエーテルのエーテル系化合物などを共重合したものが用いられる。
　上記内在型の放射線硬化性粘着剤は、上記炭素－炭素二重結合を有するベースポリマー（特にアクリル系ポリマー）を単独で使用することができるが、特性を悪化させない程度に上記放射線硬化性のモノマー成分やオリゴマー成分を配合することもできる。放射線硬化性のオリゴマー成分などは、通常ベースポリマー１００重量部に対して３０重量部の範囲内であり、好ましくは０～１０重量部の範囲である。
　上記放射線硬化型粘着剤には、紫外線などにより硬化させる場合には光重合開始剤を含有させることが好ましい。光重合開始剤としては、例えば、４－（２－ヒドロキシエトキシ）フェニル（２－ヒドロキシ－２－プロピル）ケトン、α－ヒドロキシ－α，α´－ジメチルアセトフェノン、２－メチル－２－ヒドロキシプロピオフェノン、１－ヒドロキシシクロヘキシルフェニルケトンなどのα－ケトール系化合物；メトキシアセトフェノン、２，２－ジメトキシ－２－フェニルアセトフエノン、２，２－ジエトキシアセトフェノン、２－メチル－１－［４－（メチルチオ）－フェニル］－２－モルホリノプロパン－１などのアセトフェノン系化合物；ベンゾインエチルエーテル、ベンゾインイソプロピルエーテル、アニソインメチルエーテルなどのベンゾインエーテル系化合物；ベンジルジメチルケタールなどのケタール系化合物；２－ナフタレンスルホニルクロリドなどの芳香族スルホニルクロリド系化合物；１－フェノン－１，１―プロパンジオン－２－（ｏ－エトキシカルボニル）オキシムなどの光活性オキシム系化合物；ベンゾフェノン、ベンゾイル安息香酸、３，３′－ジメチル－４－メトキシベンゾフェノンなどのベンゾフェノン系化合物；チオキサンソン、２－クロロチオキサンソン、２－メチルチオキサンソン、２，４－ジメチルチオキサンソン、イソプロピルチオキサンソン、２，４－ジクロロチオキサンソン、２，４－ジエチルチオキサンソン、２，４－ジイソプロピルチオキサンソンなどのチオキサンソン系化合物；カンファーキノン；ハロゲン化ケトン；アシルホスフィノキシド；アシルホスフォナートなどがあげられる。光重合開始剤の配合量は、粘着剤を構成するアクリル系ポリマーなどのベースポリマー１００重量部に対して、例えば０．０５～２０重量部程度である。
　なお、放射線照射の際に、酸素による硬化阻害が起こる場合は、放射線硬化型の粘着剤層１２ｂの表面よりなんらかの方法で酸素（空気）を遮断するのが望ましい。例えば、上記粘着剤層１２ｂの表面をセパレータで被覆する方法や、窒素ガス雰囲気中で紫外線などの放射線の照射を行う方法などが挙げられる。
　なお、粘着剤層１２ｂには、各種添加剤（例えば、着色剤、増粘剤、増量剤、充填剤、粘着付与剤、可塑剤、老化防止剤、酸化防止剤、界面活性剤、架橋剤など）が含まれていてもよい。
　粘着剤層１２ｂの厚さは特に限定されないが、チップ切断面の欠け防止、シート状樹脂組成物１０の固定保持の両立性などの観点から１～５０μｍ程度であるのが好ましい。好ましくは２～３０μｍ、さらには好ましくは５～２５μｍである。
　（裏面研削用テープ一体型シート状樹脂組成物の製造方法）
　裏面研削用テープ一体型シート状樹脂組成物１００は、例えば裏面研削用テープ１２及びシート状樹脂組成物１０を別々に作製しておき、最後にこれらを貼り合わせることにより作成することができる。
　（シート状樹脂組成物付チップの準備方法）
　次に、シート状樹脂組成物付チップの準備方法について説明する。図６～図１１は、裏面研削用テープ一体型シート状樹脂組成物１００を用いるシート状樹脂組成物付チップ４０準備方法の各工程を示す図である。
　具体的には、当該シート状樹脂組成物付チップの準備方法は、半導体ウェハ１６のバンプ１８が形成されたバンプ形成面２２ａと裏面研削用テープ一体型シート状樹脂組成物１００のシート状樹脂組成物１０とを貼り合わせる貼合せ工程、半導体ウェハ１６の裏面１６ｂを研削する研削工程、半導体ウェハ１６の裏面１６ｂにダイシングテープ１１を貼りつけるウェハ固定工程、裏面研削用テープ１２を剥離する剥離工程、半導体ウェハ１６をダイシングしてシート状樹脂組成物付き半導体チップ４０を形成するダイシング工程、及びシート状樹脂組成物付き半導体チップ４０をダイシングテープ１１から剥離するピックアップ工程を含む。
　＜貼合せ工程＞
　貼合せ工程では、半導体ウェハ１６のバンプ１８が形成されたバンプ形成面２２ａと裏面研削用テープ一体型シート状樹脂組成物１００のシート状樹脂組成物１０とを貼り合わせる（図６参照）。
　半導体ウェハ１６のバンプ形成面２２ａには、複数のバンプ１８が形成されている（図６参照）。バンプ１８の高さは用途に応じて定められ、一般的には１５～１００μｍ程度である。もちろん、半導体ウェハ１６における個々のバンプ１８の高さは同一でも異なっていてもよい。
　半導体ウェハ１６表面に形成されたバンプ１８の高さＸ（μｍ）とシート状樹脂組成物１０の厚さＹ（μｍ）とが、０．５≦Ｙ／Ｘ≦２の関係を満たすことが好ましい。より好ましくは、０．５≦Ｙ／Ｘ≦１．５であり、さらに好ましくは、０．８≦Ｙ／Ｘ≦１．３である。
　バンプ１８の高さＸ（μｍ）とシート状樹脂組成物１０の厚さＹ（μｍ）とが上記関係を満たすことにより、半導体チップ２２と実装用基板５０との間の空間を十分に充填することができると共に、当該空間からのシート状樹脂組成物１０の過剰のはみ出しを防止することができ、シート状樹脂組成物１０による半導体チップ２２の汚染などを防止することができる。なお、各バンプ１８の高さが異なる場合は、最も高いバンプ１８の高さを基準とする。
　まず、裏面研削用テープ一体型シート状樹脂組成物１００のシート状樹脂組成物１０上に任意に設けられたセパレータを適宜に剥離し、図６に示すように、半導体ウェハ１６のバンプ１８が形成されたバンプ形成面２２ａとシート状樹脂組成物１０とを対向させ、シート状樹脂組成物１０と半導体ウェハ１６とを貼り合わせる（マウント）。
　貼り合わせの方法は特に限定されないが、圧着による方法が好ましい。圧着の圧力は、好ましくは０．１ＭＰａ以上、より好ましくは０．２ＭＰａ以上である。０．１ＭＰａ以上であると、半導体ウェハ１６のバンプ形成面２２ａの凹凸を良好に埋め込むことができる。また、圧着の圧力の上限は特に限定されないが、好ましくは１ＭＰａ以下、より好ましくは０．５ＭＰａ以下である。
　貼り合わせの温度は、好ましくは４０℃以上であり、より好ましくは６０℃以上である。４０℃以上であると、シート状樹脂組成物１０の粘度が低下し、半導体ウェハ１６の凹凸を空隙なく充填できる。また、貼り合わせの温度は、好ましくは１００℃以下であり、より好ましくは８０℃以下である。１００℃以下であると、シート状樹脂組成物１０の硬化反応を抑制したまま貼り合わせが可能となる。
　貼り合わせは、減圧下で行うことが好ましく、例えば、１０００Ｐａ以下、好ましくは５００Ｐａ以下である。下限は特に限定されず、例えば、１Ｐａ以上である。
　＜研削工程＞
　研削工程では、半導体ウェハ１６のバンプ形成面２２ａとは反対側の面（すなわち、裏面）１６ｂを研削する（図７参照）。半導体ウェハ１６の裏面研削に用いる薄型加工機としては特に限定されず、例えば研削機（バックグラインダー）、研磨パッドなどを例示できる。また、エッチングなどの化学的方法にて裏面研削を行ってもよい。裏面研削は、半導体ウェハ１６が所望の厚さ（例えば、１０～８００μｍ）になるまで行われる。
　＜ウェハ固定工程＞
　研削工程後、半導体ウェハ１６の裏面１６ｂにダイシングテープ１１を貼りつける（図８参照）。なお、ダイシングテープ１１は、基材１１ａ上に粘着剤層１１ｂが積層された構造を有する。基材１１ａ及び粘着剤層１１ｂとしては、裏面研削用テープ１２の基材１２ａ及び粘着剤層１２ｂの項で示した成分及び製法を用いて好適に作製することができる。
　＜剥離工程＞
　次いで、裏面研削用テープ１２を剥離する（図９参照）。これにより、シート状樹脂組成物１０が露出した状態となる。
　裏面研削用テープ１２を剥離する際、粘着剤層１２ｂが放射線硬化性を有する場合には、粘着剤層１２ｂに放射線を照射して粘着剤層１２ｂを硬化させることで、剥離を容易に行うことができる。放射線の照射量は、用いる放射線の種類や粘着剤層の硬化度などを考慮して適宜設定すればよい。
　＜ダイシング工程＞
　ダイシング工程では、図１０に示すように半導体ウェハ１６及びシート状樹脂組成物１０をダイシングしてダイシングされたシート状樹脂組成物付き半導体チップ４０を形成する。ダイシングは、半導体ウェハ１６のシート状樹脂組成物１０を貼り合わせたバンプ形成面２２ａから常法に従い行われる。例えば、ダイシングテープ１１まで切込みを行うフルカットと呼ばれる切断方式などを採用できる。本工程で用いるダイシング装置としては特に限定されず、従来公知のものを用いることができる。
　なお、ダイシング工程に続いてダイシングテープ１１のエキスパンドを行う場合、該エキスパンドは従来公知のエキスパンド装置を用いて行うことができる。
　＜ピックアップ工程＞
　図１１に示すように、シート状樹脂組成物付き半導体チップ４０をダイシングテープ１１から剥離する（シート状樹脂組成物付き半導体チップ４０をピックアップする）。ピックアップの方法としては特に限定されず、従来公知の種々の方法を採用できる。
　ここでピックアップは、ダイシングテープ１１の粘着剤層１１ｂが紫外線硬化型の場合、粘着剤層１１ｂに紫外線を照射した後に行う。これにより、粘着剤層１１ｂの半導体チップ２２に対する粘着力が低下し、半導体チップ２２の剥離が容易になる。
　以上により、シート状樹脂組成物付き半導体チップ４０の準備が完了する。
　また、本発明に係るシート状樹脂組成物付き半導体チップの準備方法は、裏面研削用テープ一体型シート状樹脂組成物を用いる方法に限定されない。
　例えば、ダイシングテープ一体型シート状樹脂組成物を用いて準備してもよい。ダイシングテープ一体型シート状樹脂組成物は、ダイシングテープと、シート状樹脂組成物とを備える。ダイシングテープは、基材及び粘着剤層を備え、粘着剤層は基材上に設けられている。シート状樹脂組成物は粘着剤層上に設けられている。ダイシングテープは、上述した裏面研削用テープと同様の構成を採用することができる。
　具体的に、当該シート状樹脂組成物付チップの準備方法は、半導体ウェハのバンプが形成されたバンプ形成面とダイシングテープ一体型シート状樹脂組成物のシート状樹脂組成物とを貼り合わせる貼合せ工程、半導体ウェハをダイシングしてシート状樹脂組成物付き半導体チップを形成するダイシング工程、及びシート状樹脂組成物付き半導体チップをダイシングテープから剥離するピックアップ工程を含む。
　また、本発明に係るシート状樹脂組成物付き半導体チップの準備方法は、単体のシート状樹脂組成物を用いて準備してもよい。
　具体的に、単体のシート状樹脂組成物を用いたシート状樹脂組成物付チップの準備方法は、例えば、半導体ウェハのバンプが形成されたバンプ形成面とシート状樹脂組成物とを貼り合わせる貼合せ工程、シート状樹脂組成物の半導体ウエハ貼り合わせ面とは反対側の面に裏面研削用テープを貼り合わせる工程、半導体ウェハの裏面を研削する研削工程、半導体ウェハの裏面にダイシングテープを貼りつけるウェハ固定工程、裏面研削用テープを剥離する剥離工程、半導体ウェハをダイシングしてシート状樹脂組成物付き半導体チップを形成するダイシング工程、及びシート状樹脂組成物付き半導体チップをダイシングテープから剥離するピックアップ工程を含む。
また、単体のシート状樹脂組成物を用いたシート状樹脂組成物付チップの準備方法の他の例としては、当該シート状樹脂組成物付チップの準備方法は、半導体ウェハのバンプが形成されたバンプ形成面とシート状樹脂組成物とを貼り合わせる貼合せ工程、シート状樹脂組成物の半導体ウエハ貼り合わせ面とは反対側の面にダイシングテープを貼り合わせる工程、半導体ウェハをダイシングしてシート状樹脂組成物付き半導体チップを形成するダイシング工程、及びシート状樹脂組成物付き半導体チップをダイシングテープから剥離するピックアップ工程を含む。
　上述した実施形態では、半導体チップにバンプが形成されているとともに、被着体としての搭載用基板に電極が形成されている場合について説明した。しかしながら、本発明に係る半導体チップは、シート状樹脂組成物が貼り合わせられる面側に、バンプ等による凹凸（例えば、３μｍ以上の凹凸）が形成されていなくてもよい。また、本発明の被着体は、シート状樹脂組成物が貼り合わせられる面側に、電極等による凹凸（例えば、３μｍ以上の凹凸）が形成されていなくてもよい。３μｍ未満の凹凸がある場合や凹凸がない場合にもシート状樹脂組成物と被着体との間にボイド（例えば、微小なボイド）が噛み込む場合はある。しかしながら、このような場合であっても、工程Ｄ（シート状樹脂組成物を加熱して半硬化させる工程）と、工程Ｅ（前記工程Ｄの後に、前記工程Ｄにおける加熱よりも高温で前記シート状樹脂組成物を加熱して硬化させる工程）とを行なうため、ボイドの膨張は抑制されている。従って、このような場合においても種々の不具合の原因となる大きなボイドの発生を抑制することができる。
　半導体チップのシート状樹脂組成物が貼り合わせられる面側に凹凸が形成されておらず、被着体のシート状樹脂組成物が貼り合わせられる面側に凹凸が形成されていない場合の具体例としては、シート状樹脂組成物をダイボンドフィルムとして使用する例が挙げられる。
　すなわち、この場合の半導体装置の製造方法は、
　半導体チップの非回路形成面（回路形成面とは反対側の面）にダイボンドフィルムとしてのシート状樹脂組成物が貼り付けられたシート状樹脂組成物付きチップを準備する工程Ａと、
　リードフレーム等の実装用基板を準備する工程Ｂと、
　前記実装用基板に、前記シート状樹脂組成物付きチップを、前記シート状樹脂組成物を貼り合わせ面にして貼り付ける工程Ｃと、
　前記工程Ｃの後に、前記シート状樹脂組成物を加熱して半硬化させる工程Ｄと、
　前記工程Ｄの後に、前記工程Ｄにおける加熱よりも高温で前記シート状組成物を加熱して硬化させる工程Ｅとを少なくとも含む。
　以下に、この発明の好適な実施例を例示的に詳しく説明する。但し、この実施例に記載されている材料や配合量などは、特に限定的な記載がない限りは、この発明の範囲をそれらのみに限定する趣旨のものではない。
　＜シート状樹脂組成物の作製＞
　以下の成分を表１に示す割合でメチルエチルケトンに溶解して、固形分濃度が２５．４～６０．６重量％となる接着剤組成物の溶液を調製した。
　アクリルポリマー：アクリル酸エチル－メチルメタクリレートを主成分とするアクリル酸エステル系ポリマー（商品名「パラクロンＷ－１９７ＣＭ」、根上工業株式会社製）
　エポキシ樹脂１：商品名「エピコート１００４」、ＪＥＲ株式会社製
　エポキシ樹脂２：商品名「エピコート８２８」、ＪＥＲ株式会社製
　フェノール樹脂：商品名「ミレックスＸＬＣ－４Ｌ」、三井化学株式会社製
　無機充填剤：球状シリカ（商品名「ＳＯ－２５Ｒ」、株式会社アドマテックス製）
　熱硬化促進触媒：イミダゾール触媒（商品名「２ＰＨＺ－ＰＷ」、四国化成株式会社製）
　この接着剤組成物の溶液を、剥離ライナ（セパレータ）としてシリコーン離型処理した厚さが５０μｍのポリエチレンテレフタレートフィルムからなる離型処理フィルム上に塗布した後、１３０℃で２分間乾燥させることにより、厚さ３５μｍのシート状樹脂組成物Ａを作製した。
　［２００℃未満における最低溶融粘度の測定］
　回転式粘度計ＨＡＡＫＥ　Ｒｏｔｏ　Ｖｉｓｃｏ　１（サーモフィッシャーサイエンティフィック社製）を用いてシート状樹脂組成物Ａを測定したときの８０℃～２００℃における溶融粘度の最低値を最低溶融粘度とした。測定条件は、昇温速度１０℃／ｍｉｎ、せん断速度５（１／ｓ）とした。結果を表１に示す。
　（２００℃で１０秒間加熱した後の熱硬化率の測定）
　ティー・エイ・インスツルメント社製の示差走査熱量計、製品名「Ｑ２０００」を用いて、以下のようにして、熱硬化率を測定した。
　まず、熱硬化処理をしていないシート状樹脂組成物Ａを－１０℃から昇温速度１０℃／分の条件で、３５０℃（熱硬化反応が完全に完了したと想定される温度）まで昇温した際の発熱量（未硬化サンプルの反応熱量）を測定した。
　また、シート状樹脂組成物Ａを２００℃で１０秒間加熱したサンプルを準備し、－１０℃から昇温速度１０℃／分の条件で、３５０℃（熱硬化反応が完全に完了したと想定される温度）まで昇温した際の発熱量（２００℃で１０秒間加熱したサンプルの反応熱量）を測定した。その後、以下の式（３）により熱硬化率を得た。
　式（３）：
熱硬化率＝［｛（未硬化サンプルの反応熱量）－（２００℃で１０秒間加熱したサンプルの反応熱量）｝／（未硬化サンプルの反応熱量）］×１００（％）
　なお、発熱量は、示差走査熱量計にて測定される発熱ピークの立ち上がり温度と反応終了温度の２点を結んだ直線とピークで囲まれる面積を用いて求める。
　結果を表１に示す。
Figure JPOXMLDOC01-appb-T000001
 
　（ボイド評価）
　（株）ウォルツ社のテストビークル（厚さ７２５μｍのウエハに、高さ４０μｍのバンプが形成されたもの）に、厚さ４０μｍのシート状樹脂組成物Ａを貼り付けた。貼付条件は、真空度：１００Ｐａの条件下において、温度：６０℃、貼り付け圧力：０．５Ｍｐａとした。これにより図１に示すような形態のサンプルＡを得た。
　（実施例１）
　次に、このサンプルＡに電極を有する実装用基板（電極の高さ：１５μｍ）を貼り付けた。貼り付けには、東レエンジニアリング社のフリップチップボンダー（ＦＣ３０００Ｗ）を用い、貼付条件は、荷重：０．５Ｍｐａの条件で、２００℃で１０秒間保持した後、２６０℃で１０秒保持した。その後、実装用基板面に対して平行に研削しバンプ近辺を観察した。
　（比較例１）
　実施例１と同様に、サンプルＡに電極を有する実装用基板（電極の高さ：１５μｍ）を貼り付けた。貼り付けには、東レエンジニアリング社のフリップチップボンダー（ＦＣ３０００Ｗ）を用い、貼付条件は、荷重：０．５Ｍｐａの条件で、２６０℃で１０秒保持した。その後、実装用基板面に対して平行に研削しバンプ近辺を観察した。
　ボイドの発生が抑制されていることが確認できた場合を〇、ボイドの発生が抑制されていることが確認できない場合を×として評価した。結果を表２に示す。
Figure JPOXMLDOC01-appb-T000002
１０　シート状樹脂組成物
１８　バンプ
２２　半導体チップ
２２ａ　バンプ形成面
４０　シート状樹脂組成物付きチップ
５０　実装用基板
５２　電極
６０　半導体装置
 

Claims (4)

  1. 　半導体チップにシート状樹脂組成物が貼り付けられたシート状樹脂組成物付きチップを準備する工程Ａと、
    　被着体を準備する工程Ｂと、
    　前記被着体に、前記シート状樹脂組成物付きチップを、前記シート状樹脂組成物を貼り合わせ面にして貼り付ける工程Ｃと、
    　前記工程Ｃの後に、前記シート状樹脂組成物を加熱して半硬化させる工程Ｄと、
    　前記工程Ｄの後に、前記工程Ｄにおける加熱よりも高温で前記シート状樹脂組成物を加熱して硬化させる工程Ｅとを含むことを特徴とする半導体装置の製造方法。
  2. 　前記シート状樹脂組成物は、２００℃で１０秒間加熱した際の熱硬化率が１０％以上であることを特徴とする請求項１に記載の半導体装置の製造方法。
  3. 　前記被着体は、前記シート状樹脂組成物が貼り合わせられる面側に、３μｍ以上１００μｍ以下の凹凸を有することを特徴とする請求項１又は２に記載の半導体装置の製造方法。
  4. 　前記半導体チップは、前記シート状樹脂組成物が貼り合わせられる面側に、３μｍ以上１００μｍ以下の凹凸を有することを特徴とする請求項１～３のいずれか１に記載の半導体装置の製造方法。
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Publication number Priority date Publication date Assignee Title
TW463336B (en) * 1997-11-19 2001-11-11 Matsushita Electric Ind Co Ltd Method for planarizing circuit board and method for manufacturing semiconductor device
JP4663184B2 (ja) * 2001-09-26 2011-03-30 パナソニック株式会社 半導体装置の製造方法
US20050205981A1 (en) * 2004-03-18 2005-09-22 Kabushiki Kaisha Toshiba Stacked electronic part
ATE510306T1 (de) * 2005-02-18 2011-06-15 Clean Venture 21 Corp Matrixanordnung sphärischer solarzellen und ihr herstellungsverfahren
US8212370B2 (en) * 2006-10-04 2012-07-03 Hitachi Chemical Company, Ltd. Resin paste for die bonding, containing a polyurethaneimide resin and thermosetting resin method for manufacturing semiconductor device, and semiconductor device, using the resin paste
JP5395360B2 (ja) * 2008-02-25 2014-01-22 新光電気工業株式会社 電子部品内蔵基板の製造方法
JP6208411B2 (ja) * 2012-06-15 2017-10-04 新光電気工業株式会社 配線基板及びその製造方法
JP5870198B2 (ja) * 2012-09-14 2016-02-24 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001332520A (ja) * 2000-05-23 2001-11-30 Amkor Technology Inc シート状樹脂組成物及びそれを用いた半導体装置の製造方法
JP2007157758A (ja) * 2005-11-30 2007-06-21 Sumitomo Bakelite Co Ltd 半導体用接着フィルム及びこれを用いた半導体装置

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