WO2015039388A1 - 阵列基板的制作方法 - Google Patents
阵列基板的制作方法 Download PDFInfo
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- WO2015039388A1 WO2015039388A1 PCT/CN2013/088837 CN2013088837W WO2015039388A1 WO 2015039388 A1 WO2015039388 A1 WO 2015039388A1 CN 2013088837 W CN2013088837 W CN 2013088837W WO 2015039388 A1 WO2015039388 A1 WO 2015039388A1
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- insulating layer
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- 239000000758 substrate Substances 0.000 title claims abstract description 88
- 238000000034 method Methods 0.000 title claims abstract description 56
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 88
- 229910052751 metal Inorganic materials 0.000 claims description 39
- 239000002184 metal Substances 0.000 claims description 39
- 238000005530 etching Methods 0.000 claims description 23
- -1 phosphorus ions Chemical class 0.000 claims description 9
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- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 239000003292 glue Substances 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 description 30
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 15
- 229920005591 polysilicon Polymers 0.000 description 11
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- 238000010586 diagram Methods 0.000 description 7
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- 238000000151 deposition Methods 0.000 description 5
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- 229910052782 aluminium Inorganic materials 0.000 description 3
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- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 239000012495 reaction gas Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- 238000002207 thermal evaporation Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 238000002425 crystallisation Methods 0.000 description 2
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- 238000001459 lithography Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
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- 239000004065 semiconductor Substances 0.000 description 2
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- 239000010409 thin film Substances 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
Definitions
- Embodiments of the present invention relate to a method of fabricating an array substrate. Background technique
- the planar structure of the low temperature polysilicon array substrate is shown in Figure la, and its cross-sectional view is shown in Figure lb.
- the manufacturing process of the low-temperature polysilicon array substrate in the prior art comprises: depositing a shielding layer film on the substrate, forming a pattern of the shielding layer 201 by one patterning process; depositing a buffer insulating layer and an amorphous silicon layer on the substrate on which the shielding layer is formed;
- the polysilicon process crystallizes the amorphous silicon into polycrystalline silicon; the active layer pattern is formed by one patterning process; the gate insulating layer is formed on the substrate on which the active layer is formed; and the gate is formed on the substrate on which the gate insulating layer is formed, wherein
- a PMOS (Positive Channel-Metal-Oxide-Semiconductor) gate in the driving region is fabricated by a patterning process, followed by boron ion (B) implantation, and a display region and a driving region are formed by one patterning process.
- NMOS Native Channel-Metal-Oxide-Semiconductor
- PMOS phosphorus
- An intermediate insulating layer on the substrate forming a via for connecting the source/drain electrode layer and the active layer by one patterning process
- the via hole penetrates through the intermediate insulating layer; and a via hole for connecting the shielding layer and the source/drain electrode layer is formed by one patterning process, the via hole penetrating through the intermediate insulating layer and the gate insulating layer;
- a source/drain metal film is deposited on a substrate having a via for connecting the source/drain electrode layer and the active layer, and a via for connecting the shield layer and the source/drain electrode layer, and the source/drain electrode layer is formed by one patterning process.
- the via for connecting the source/drain electrode layer and the active layer and the via for connecting the shield layer and the source/drain electrode layer are realized by two patterning processes, and the process is complicated. However, if the same patterning process is applied to the above two vias for the barreling process, the via depth for connecting the source and drain electrode layers and the active layer is used for connecting the shield layer and the source and drain electrode layers. The hole depth is different, and the required etching time is also different, so that the via hole for connecting the source/drain electrode layer and the active layer is excessively etched, and the via etching for connecting the shield layer and the source/drain electrode layer is performed. Did not do well. Summary of the invention
- Embodiments of the present invention provide a method of fabricating an array substrate, which is capable of ensuring the quality of etching while performing a barreling process.
- One aspect of the present invention provides a method of fabricating an array substrate, including:
- Step 1 sequentially forming a shielding layer, a buffer insulating layer, an active layer, a gate insulating layer, and an NMOS gate in the display region and the driving region on the substrate, and then implanting phosphorus ions into the active layer;
- Step 2 forming a PMOS gate in the driving region on the substrate formed with the shielding layer, the buffer insulating layer, the active layer, the gate insulating layer, and the NMOS gate in the display region and the driving region, the NMOS gate and the PMOS
- the gate is in the same layer and simultaneously forms a first via in the common electrode connection region, the first via is used to connect the shielding layer and the source/drain electrode layer, and then implant boron ions into the active layer;
- Step 3 forming an intermediate insulating layer on the substrate on which the first via hole in the PMOS gate and the common electrode connection region in the driving region is formed, and forming the second via hole and the display region and the driving region in the common electrode connection region a third via hole, the second via hole having the same position as the first via hole for connecting a shield layer and a source/drain electrode layer, wherein the third via hole is used for connecting the active layer and the source/drain electrodes Floor;
- Step 4 Form a source/drain electrode layer on the substrate on which the intermediate insulating layer, the second via hole in the common electrode connection region, and the display via region and the third via hole in the driving region are formed.
- the step 1 may include: sequentially forming a shielding layer, a buffer insulating layer, an active layer, and a gate insulating layer on the substrate; forming a shielding layer, a buffer insulating layer, an active layer, and a gate insulating layer Depositing a gate metal film on the substrate, coating a photoresist on the gate metal film; exposing the photoresist, the remaining area of the photoresist corresponding to the pattern and the PMOS region of the NMOS gate in the display region and the driving region, lithography
- the removal area of the glue corresponds to other areas where the gate metal film is not required to be retained;
- the gate metal film of the photoresist removal region is etched to form an NMOS gate in the display region and the driving region, and the photoresist of the photoresist remaining region is stripped.
- the step 2 may include: coating a photoresist on a substrate formed with a shielding layer, a buffer insulating layer, an active layer, a gate insulating layer, and an NMOS gate in the display region and the driving region; Exposing the photoresist, the remaining area of the photoresist corresponding to the pattern of the NMOS gate and the PMOS gate in the driving region, the entire display area and the area other than the pattern of the first via in the common electrode connection region, lithography
- the removed area of the glue corresponds to the pattern of the first via and other areas where the gate metal film is not required to be left; the gate metal film of the photoresist removal area is etched to form the PMOS gate in the driving region, and the photoresist is etched away
- the gate insulating layer and the buffer insulating layer of the region are removed to form a first via hole in the common electrode connection region.
- the etching the off the gate insulating layer of the photoresist removal region and the buffer insulating layer to form the first via in the common electrode connection region comprises: etching away the entire gate insulation of the photoresist removal region Layer and all buffer insulating layers to form a first via in the common electrode connection region; or etching away all of the gate insulating layer and a portion of the buffer insulating layer of the photoresist removal region to form a first of the common electrode connection regions Through hole.
- the step 3 may include: forming an intermediate insulating layer on the substrate on which the first via hole in the PMOS gate and the common electrode connection region in the driving region is formed, and coating on the intermediate insulating layer Photoresist; exposing the photoresist, the removed area of the photoresist corresponds to the pattern of the second via and the third via, and the remaining area of the photoresist corresponds to other areas that do not need to remove the intermediate insulating layer; The intermediate insulating layer of the photoresist removal region and a portion of the buffer insulating layer are formed to form a second via hole, and the intermediate insulating layer and the gate insulating layer of the photoresist removal region are etched away to form a third via hole, and the photoresist is stripped. Retain the area of the photoresist.
- the step 3 may include: forming an intermediate insulating layer on the substrate formed with the first via in the PMOS gate and the common electrode connection region in the driving region, and coating the intermediate insulating layer with a photoresist; Exposing the photoresist, the removed region of the photoresist corresponds to the pattern of the second via and the third via, and the remaining area of the photoresist corresponds to other regions that do not need to remove the intermediate insulating layer; The intermediate insulating layer of the region forms a second via hole while etching away the intermediate insulating layer and the gate insulating layer of the photoresist removal region to form a third via hole, and stripping the photoresist of the photoresist remaining region.
- the etching of the NMOS gate pattern in the display region and the driving region may be performed by wet etching.
- the etching of the pattern in the driving region PMOS gate pattern and the common electrode connection region may be dry etching.
- the second via hole and the third via hole are simultaneously fabricated by one patterning process, and one of the second via hole and the third via hole does not appear.
- the eclipse is excessive and the other is not etched. This saves one patterning process while ensuring the quality of the etch.
- Figure la is a plan view of a prior art array substrate
- Figure lb is a cross-sectional view of the array substrate A1-A1 in Figure la;
- FIG. 2 is a schematic view of the array substrate after the first patterning process according to an embodiment of the present invention
- FIG. 3 is a schematic diagram of a second patterning process of an array substrate according to an embodiment of the present invention.
- FIG. 4 is a schematic diagram of a third patterning process of an array substrate according to an embodiment of the present invention.
- FIG. 5 is a schematic diagram of a fourth patterning process of an array substrate according to an embodiment of the present invention.
- FIG. 6 is a schematic diagram of a fifth patterning process of an array substrate according to an embodiment of the present invention.
- FIG. 7 is a schematic diagram of a sixth patterning process of an array substrate according to an embodiment of the present invention. detailed description
- FIGS. 2 to 7 are schematic diagrams showing respective steps of a method of fabricating an array substrate according to an embodiment of the invention, each of which shows a cross-sectional structure of three regions, which are respectively a driving region, a display region, and a common electrode connection. region.
- the method for fabricating the array substrate provided by the embodiment of the present invention can be as follows. Row.
- a shielding layer 201, a buffer insulating layer 301, and an amorphous silicon layer are sequentially formed on a substrate (for example, a glass substrate, a quartz substrate, a plastic substrate, or the like), and the amorphous silicon is crystallized into polycrystalline silicon through a polysilicon process, and is actively produced by one patterning process.
- the layer patterns 302, 303, the gate insulating layer 401, and the NMOS gate 402 in the display region and the driving region (the NMOS gate in the driving region are not shown in the drawing), and then implant phosphorus ions (P) into the active layer.
- a PMOS gate 501 in the driving region is formed on the substrate on which the shield layer 201, the buffer insulating layer 301, the active layers 302 and 303, the gate insulating layer 401, and the NMOS gate 402 in the display region and the driving region are formed.
- the NMOS gate and the PMOS gate are in the same layer, and simultaneously form a first via 502 in the common electrode connection region, the first via 502 is used to connect the shielding layer 201 and the source/drain electrode layer 701, and then Boron ions (B) are implanted into the active layer.
- a source/drain electrode layer 701 is formed on the substrate on which the intermediate insulating layer 601, the second via hole 602 in the common electrode connection region, and the third via 603 in the display region and the driving region are formed.
- the method for fabricating the array substrate makes the first via hole in the common electrode connection region while fabricating the PMOS gate in the driving region, and then forms the PMOS gate and the first in the driving region.
- An intermediate insulating layer is formed on the via substrate, and then a second via for connecting the source/drain electrode layer and the shielding layer and a third via for connecting the source/drain electrode layer and the active layer are formed, and the second via is formed
- the position is the same as the position of the first via.
- the intermediate insulating layer forms a pit at the pattern of the first via hole in the common electrode connection region, and the second via hole for connecting the shield layer and the source/drain electrode layer due to the existence of the pit
- the depth becomes smaller to the extent substantially the same as the depth of the third via for connecting the active layer and the source-drain electrode layer.
- the second via hole and the third via hole can be simultaneously fabricated by one patterning process, and one of the second via hole and the third via hole is not overetched, and the other is etched. Not in place. This saves one patterning process while ensuring the quality of the etch.
- the structure S of the embodiment of the present invention may include processes such as photoresist coating, masking, exposure, development, and etching.
- Step 11 is to form a shield layer 201 on the substrate 1.
- FIG. 2 is a schematic view of the array substrate after the first patterning process of the embodiment.
- a masking metal film is deposited on the substrate 1 (e.g., a glass substrate or a quartz substrate) by sputtering or thermal evaporation.
- the shielding metal film a metal such as Cr, W, Ti, Ta, Mo, Al, Cu or the like and a metal thereof may be used, and the shielding metal film may also be composed of a plurality of metal thin films.
- a photoresist is coated on the shielding metal film, and the shielding metal film is etched by a first patterning process using a common mask to form a pattern of the shielding layer 201 on the substrate 1.
- the shielding layer is connected to the common electrode and functions as a common electrode, and the shielding layer forms an additional storage capacitor with the active layer to compensate for the reduction of the storage capacitance itself.
- a shielding layer is also formed in the common electrode connection region around the array substrate, and the shielding layer is disposed in the same layer as the shielding layer in the display region.
- Step 12 forming active layers 302, 303 on the substrate on which the shield layer 201 is formed.
- FIG. 3 is a schematic view of the array substrate after the second patterning process of the embodiment.
- a buffer insulating film is continuously deposited by a plasma enhanced chemical vapor deposition method to form a buffer insulating layer 301.
- the buffer insulating layer film may be an oxide, a nitride or an oxynitride, and the corresponding reaction gas may be a mixed gas of SiH 4 , N 2 0, NH 3 , N 2 , or may be SiH 2 Cl 2 , N 2 0, A mixed gas of NH 3 and N 2 .
- amorphous silicon is deposited on the substrate on which the buffer insulating layer 301 is formed, and amorphous silicon is crystallized into polycrystalline silicon by a polysilicon process, and then the polycrystalline silicon layer is doped to form doped polysilicon.
- the etching is performed by the second patterning process to form a polysilicon pattern, which is an active layer.
- the active layer includes a driving region active layer 302 and a display region active layer 303.
- the polysilicon process is, for example, a metal induced amorphous silicon crystallization method, a lateral metal induced amorphous silicon crystallization method, or the like.
- Step 13 An NMOS gate 402 in the display region and the driving region is formed on the substrate on which the active layers 302, 303 are formed.
- a gate insulating film is continuously deposited by a plasma enhanced chemical vapor deposition method to form a gate insulating layer 401 as shown in FIG.
- the gate insulating film may be an oxide, a nitride or an oxynitride, and the corresponding reaction gas may be a mixed gas of Si, N 2 0, NH 3 , N 2 or SiH 2 Cl 2 , N 2 0, NH 3 , N. 2 mixed gas.
- sputtering or thermal evaporation is performed on the substrate on which the gate insulating layer 401 is formed.
- the method is to deposit a gate metal film, and a metal such as Cr, W, Ti, Ta, Mo, Al, Cu or the like can be selected for the gate metal thin waist.
- Coating a photoresist on the gate metal film exposing the photoresist using a common mask, the remaining area of the photoresist corresponding to the pattern and the PMOS region of the NMOS gate 402 in the display region and the driving region, and the removal of the photoresist The region corresponds to other regions where the gate metal film is not required to be retained; the gate metal film of the photoresist removal region is etched away to form the NMOS gate 402 in the display region and the driving region. At this time, the gate metal film in the common electrode connection region is also etched away. Phosphorus ions (P) are then implanted into the polysilicon layer to form an NMOS switch, and the photoresist is removed.
- Phosphorus ions P
- Step 14 A first via 502 in the PMOS gate 501 and the common electrode connection region in the driving region is formed on the substrate on which the NMOS gate 402 in the display region and the driving region is formed.
- FIG. 5 is a schematic view of the array substrate after the fourth patterning process of the embodiment. Coating a photoresist on the substrate on which the NMOS gate 402 in the display region and the driving region is formed; exposing the photoresist using a common mask, the remaining region of the photoresist corresponding to the NMOS gate pattern in the driving region and The pattern of the PMOS gate 501, the entire display area, and the area other than the pattern of the first via 502 in the common electrode connection region, the removed region of the photoresist corresponds to the pattern of the first via 502 and the gate metal film does not need to be retained.
- Etching the gate insulating layer 401 and the buffer insulating layer 301 of the photoresist removal region to form the first via 502 in the common electrode connection region may specifically include: etching away all the gate insulating layer 401 of the photoresist removal region and All of the buffer insulating layer 301 is formed to form the first via hole 502 in the common electrode connection region; or the entire gate insulating layer 401 and the partial buffer insulating layer 301 of the photoresist removal region are etched away to form a common electrode connection region The first via 502.
- the thickness of the gate insulating layer is very thin, the buffer insulating layer 3000A, the gate insulating layer 1200A, the gate metal 2200A, and the gate electrode is finished, the gate insulating layer is finished, and most of the buffer insulating layer is also finished. . That is, the first via may extend to the shield layer 201 or may not extend to the shield layer 201.
- Step 15 forming a second via 602 and a display area in the common electrode connection region on the substrate on which the PMOS gate 501 in the driving region and the first via 502 in the common electrode connection region are formed a third via 603 in the domain and the driving region, the second via being the same as the first via for connecting the shield layer and the source/drain electrode layer, the third via being used for connection active Layer and source/drain electrode layer;
- FIG. 6 is a schematic view of the array substrate after the fifth patterning process of the embodiment.
- the intermediate insulating layer film is continuously deposited by a plasma enhanced chemical vapor deposition method to form an intermediate insulating layer 601.
- the intermediate insulating layer film may be selected from an oxide, a nitride or an oxynitride, and the corresponding reaction gas may be a mixed gas of SiH 4 , N 2 0, NH 3 , N 2 or SiH 2 Cl 2 , N 2 0, NH 3 , A mixed gas of N 2 .
- a photoresist is coated on the substrate on which the intermediate insulating layer 601 is formed; the photoresist is exposed using a common mask, and the removed regions of the photoresist correspond to the patterns of the second via 602 and the third via 603.
- the remaining area of the photoresist corresponds to other areas where the intermediate insulating layer film is not required to be removed; the intermediate insulating layer 601 of the photoresist removing area, the partial buffer insulating layer 301 is etched away or only the intermediate insulating layer 601 is etched to form the second Via 602, in summary, second via 602 is etched to reach shield layer 201.
- the intermediate insulating layer 601 and the gate insulating layer 401 of the photoresist removal region are simultaneously etched away to form a third via hole 603, and the photoresist of the photoresist remaining region is peeled off.
- the second via 602 and the third via 603 can be formed by one patterning process, and the second via is not made.
- One of the via 602 and the third via 603 is etched excessively while the other is not etched.
- Step 16 forming a source/drain electrode layer 701 on the substrate having the intermediate insulating layer 601, the second via hole 602 in the common electrode connection region, and the third via hole 603 in the display region and the driving region;
- a schematic diagram of the array substrate after the sixth patterning process Depositing a source/drain metal film by sputtering or thermal evaporation on a substrate formed with an intermediate insulating layer 601, a second via 602 in the common electrode connection region, and a third via 603 in the display region and the driving region, the source Metals such as Cr, W, Ti, Ta, Mo, Al, Cu, and alloys thereof may be used as the metal thin film.
- a photoresist is applied, exposed and developed, and etching is performed to form a source/drain electrode layer 701.
- the etching of the NMOS pattern in the display region and the driving region is, for example, wet etching. Since the etched objects involved in the display area are all metal, wet etching can meet the requirements.
- the etching in the driving region PMOS gate pattern and the common electrode connection region is, for example, dry etching.
- Engraving of the PMOS gate pattern and the common electrode connection region of the driving region The etching is performed simultaneously, and the etching of the common electrode connection region further includes etching of the non-metal, so the etching of the two regions is preferably dry etching.
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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US14/366,925 US9240353B2 (en) | 2013-09-18 | 2013-12-09 | Method for manufacturing array substrate by forming common electrode connecting NMOS in display area and PMOS in drive area |
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US9520421B1 (en) * | 2015-06-29 | 2016-12-13 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Method for manufacturing LTPS TFT substrate and LTPS TFT substrate |
KR102395997B1 (ko) * | 2015-09-30 | 2022-05-10 | 삼성전자주식회사 | 자기 저항 메모리 소자 및 그 제조 방법 |
CN105789115A (zh) | 2016-04-26 | 2016-07-20 | 京东方科技集团股份有限公司 | 过孔的制作方法、阵列基板及其制作方法、显示装置 |
CN109616418B (zh) * | 2018-12-06 | 2021-11-09 | 合肥鑫晟光电科技有限公司 | 薄膜晶体管、显示基板及其制作方法、显示装置 |
CN109887880B (zh) * | 2019-01-04 | 2021-04-27 | 长江存储科技有限责任公司 | 一种半导体连接结构及其制作方法 |
CN111640766B (zh) * | 2020-06-22 | 2023-12-12 | 武汉华星光电技术有限公司 | 一种阵列基板及其制作方法 |
CN111897168A (zh) | 2020-08-21 | 2020-11-06 | 京东方科技集团股份有限公司 | 阵列基板及其制备方法、显示装置 |
CN113161372B (zh) * | 2021-03-04 | 2024-04-02 | 合肥维信诺科技有限公司 | 半导体器件及其制备方法、阵列基板 |
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CN103489786A (zh) | 2014-01-01 |
US9240353B2 (en) | 2016-01-19 |
CN103489786B (zh) | 2015-11-25 |
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