WO2015039388A1 - Method for manufacturing an array substrate - Google Patents

Method for manufacturing an array substrate Download PDF

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Publication number
WO2015039388A1
WO2015039388A1 PCT/CN2013/088837 CN2013088837W WO2015039388A1 WO 2015039388 A1 WO2015039388 A1 WO 2015039388A1 CN 2013088837 W CN2013088837 W CN 2013088837W WO 2015039388 A1 WO2015039388 A1 WO 2015039388A1
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Prior art keywords
area
insulating layer
photoresist
gate
via hole
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PCT/CN2013/088837
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French (fr)
Chinese (zh)
Inventor
杨玉清
朴承翊
李炳天
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/366,925 priority Critical patent/US9240353B2/en
Publication of WO2015039388A1 publication Critical patent/WO2015039388A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate

Definitions

  • Embodiments of the present invention relate to a method of fabricating an array substrate. Background technique
  • the planar structure of the low temperature polysilicon array substrate is shown in Figure la, and its cross-sectional view is shown in Figure lb.
  • the manufacturing process of the low-temperature polysilicon array substrate in the prior art comprises: depositing a shielding layer film on the substrate, forming a pattern of the shielding layer 201 by one patterning process; depositing a buffer insulating layer and an amorphous silicon layer on the substrate on which the shielding layer is formed;
  • the polysilicon process crystallizes the amorphous silicon into polycrystalline silicon; the active layer pattern is formed by one patterning process; the gate insulating layer is formed on the substrate on which the active layer is formed; and the gate is formed on the substrate on which the gate insulating layer is formed, wherein
  • a PMOS (Positive Channel-Metal-Oxide-Semiconductor) gate in the driving region is fabricated by a patterning process, followed by boron ion (B) implantation, and a display region and a driving region are formed by one patterning process.
  • NMOS Native Channel-Metal-Oxide-Semiconductor
  • PMOS phosphorus
  • An intermediate insulating layer on the substrate forming a via for connecting the source/drain electrode layer and the active layer by one patterning process
  • the via hole penetrates through the intermediate insulating layer; and a via hole for connecting the shielding layer and the source/drain electrode layer is formed by one patterning process, the via hole penetrating through the intermediate insulating layer and the gate insulating layer;
  • a source/drain metal film is deposited on a substrate having a via for connecting the source/drain electrode layer and the active layer, and a via for connecting the shield layer and the source/drain electrode layer, and the source/drain electrode layer is formed by one patterning process.
  • the via for connecting the source/drain electrode layer and the active layer and the via for connecting the shield layer and the source/drain electrode layer are realized by two patterning processes, and the process is complicated. However, if the same patterning process is applied to the above two vias for the barreling process, the via depth for connecting the source and drain electrode layers and the active layer is used for connecting the shield layer and the source and drain electrode layers. The hole depth is different, and the required etching time is also different, so that the via hole for connecting the source/drain electrode layer and the active layer is excessively etched, and the via etching for connecting the shield layer and the source/drain electrode layer is performed. Did not do well. Summary of the invention
  • Embodiments of the present invention provide a method of fabricating an array substrate, which is capable of ensuring the quality of etching while performing a barreling process.
  • One aspect of the present invention provides a method of fabricating an array substrate, including:
  • Step 1 sequentially forming a shielding layer, a buffer insulating layer, an active layer, a gate insulating layer, and an NMOS gate in the display region and the driving region on the substrate, and then implanting phosphorus ions into the active layer;
  • Step 2 forming a PMOS gate in the driving region on the substrate formed with the shielding layer, the buffer insulating layer, the active layer, the gate insulating layer, and the NMOS gate in the display region and the driving region, the NMOS gate and the PMOS
  • the gate is in the same layer and simultaneously forms a first via in the common electrode connection region, the first via is used to connect the shielding layer and the source/drain electrode layer, and then implant boron ions into the active layer;
  • Step 3 forming an intermediate insulating layer on the substrate on which the first via hole in the PMOS gate and the common electrode connection region in the driving region is formed, and forming the second via hole and the display region and the driving region in the common electrode connection region a third via hole, the second via hole having the same position as the first via hole for connecting a shield layer and a source/drain electrode layer, wherein the third via hole is used for connecting the active layer and the source/drain electrodes Floor;
  • Step 4 Form a source/drain electrode layer on the substrate on which the intermediate insulating layer, the second via hole in the common electrode connection region, and the display via region and the third via hole in the driving region are formed.
  • the step 1 may include: sequentially forming a shielding layer, a buffer insulating layer, an active layer, and a gate insulating layer on the substrate; forming a shielding layer, a buffer insulating layer, an active layer, and a gate insulating layer Depositing a gate metal film on the substrate, coating a photoresist on the gate metal film; exposing the photoresist, the remaining area of the photoresist corresponding to the pattern and the PMOS region of the NMOS gate in the display region and the driving region, lithography
  • the removal area of the glue corresponds to other areas where the gate metal film is not required to be retained;
  • the gate metal film of the photoresist removal region is etched to form an NMOS gate in the display region and the driving region, and the photoresist of the photoresist remaining region is stripped.
  • the step 2 may include: coating a photoresist on a substrate formed with a shielding layer, a buffer insulating layer, an active layer, a gate insulating layer, and an NMOS gate in the display region and the driving region; Exposing the photoresist, the remaining area of the photoresist corresponding to the pattern of the NMOS gate and the PMOS gate in the driving region, the entire display area and the area other than the pattern of the first via in the common electrode connection region, lithography
  • the removed area of the glue corresponds to the pattern of the first via and other areas where the gate metal film is not required to be left; the gate metal film of the photoresist removal area is etched to form the PMOS gate in the driving region, and the photoresist is etched away
  • the gate insulating layer and the buffer insulating layer of the region are removed to form a first via hole in the common electrode connection region.
  • the etching the off the gate insulating layer of the photoresist removal region and the buffer insulating layer to form the first via in the common electrode connection region comprises: etching away the entire gate insulation of the photoresist removal region Layer and all buffer insulating layers to form a first via in the common electrode connection region; or etching away all of the gate insulating layer and a portion of the buffer insulating layer of the photoresist removal region to form a first of the common electrode connection regions Through hole.
  • the step 3 may include: forming an intermediate insulating layer on the substrate on which the first via hole in the PMOS gate and the common electrode connection region in the driving region is formed, and coating on the intermediate insulating layer Photoresist; exposing the photoresist, the removed area of the photoresist corresponds to the pattern of the second via and the third via, and the remaining area of the photoresist corresponds to other areas that do not need to remove the intermediate insulating layer; The intermediate insulating layer of the photoresist removal region and a portion of the buffer insulating layer are formed to form a second via hole, and the intermediate insulating layer and the gate insulating layer of the photoresist removal region are etched away to form a third via hole, and the photoresist is stripped. Retain the area of the photoresist.
  • the step 3 may include: forming an intermediate insulating layer on the substrate formed with the first via in the PMOS gate and the common electrode connection region in the driving region, and coating the intermediate insulating layer with a photoresist; Exposing the photoresist, the removed region of the photoresist corresponds to the pattern of the second via and the third via, and the remaining area of the photoresist corresponds to other regions that do not need to remove the intermediate insulating layer; The intermediate insulating layer of the region forms a second via hole while etching away the intermediate insulating layer and the gate insulating layer of the photoresist removal region to form a third via hole, and stripping the photoresist of the photoresist remaining region.
  • the etching of the NMOS gate pattern in the display region and the driving region may be performed by wet etching.
  • the etching of the pattern in the driving region PMOS gate pattern and the common electrode connection region may be dry etching.
  • the second via hole and the third via hole are simultaneously fabricated by one patterning process, and one of the second via hole and the third via hole does not appear.
  • the eclipse is excessive and the other is not etched. This saves one patterning process while ensuring the quality of the etch.
  • Figure la is a plan view of a prior art array substrate
  • Figure lb is a cross-sectional view of the array substrate A1-A1 in Figure la;
  • FIG. 2 is a schematic view of the array substrate after the first patterning process according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a second patterning process of an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a third patterning process of an array substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a fourth patterning process of an array substrate according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a fifth patterning process of an array substrate according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a sixth patterning process of an array substrate according to an embodiment of the present invention. detailed description
  • FIGS. 2 to 7 are schematic diagrams showing respective steps of a method of fabricating an array substrate according to an embodiment of the invention, each of which shows a cross-sectional structure of three regions, which are respectively a driving region, a display region, and a common electrode connection. region.
  • the method for fabricating the array substrate provided by the embodiment of the present invention can be as follows. Row.
  • a shielding layer 201, a buffer insulating layer 301, and an amorphous silicon layer are sequentially formed on a substrate (for example, a glass substrate, a quartz substrate, a plastic substrate, or the like), and the amorphous silicon is crystallized into polycrystalline silicon through a polysilicon process, and is actively produced by one patterning process.
  • the layer patterns 302, 303, the gate insulating layer 401, and the NMOS gate 402 in the display region and the driving region (the NMOS gate in the driving region are not shown in the drawing), and then implant phosphorus ions (P) into the active layer.
  • a PMOS gate 501 in the driving region is formed on the substrate on which the shield layer 201, the buffer insulating layer 301, the active layers 302 and 303, the gate insulating layer 401, and the NMOS gate 402 in the display region and the driving region are formed.
  • the NMOS gate and the PMOS gate are in the same layer, and simultaneously form a first via 502 in the common electrode connection region, the first via 502 is used to connect the shielding layer 201 and the source/drain electrode layer 701, and then Boron ions (B) are implanted into the active layer.
  • a source/drain electrode layer 701 is formed on the substrate on which the intermediate insulating layer 601, the second via hole 602 in the common electrode connection region, and the third via 603 in the display region and the driving region are formed.
  • the method for fabricating the array substrate makes the first via hole in the common electrode connection region while fabricating the PMOS gate in the driving region, and then forms the PMOS gate and the first in the driving region.
  • An intermediate insulating layer is formed on the via substrate, and then a second via for connecting the source/drain electrode layer and the shielding layer and a third via for connecting the source/drain electrode layer and the active layer are formed, and the second via is formed
  • the position is the same as the position of the first via.
  • the intermediate insulating layer forms a pit at the pattern of the first via hole in the common electrode connection region, and the second via hole for connecting the shield layer and the source/drain electrode layer due to the existence of the pit
  • the depth becomes smaller to the extent substantially the same as the depth of the third via for connecting the active layer and the source-drain electrode layer.
  • the second via hole and the third via hole can be simultaneously fabricated by one patterning process, and one of the second via hole and the third via hole is not overetched, and the other is etched. Not in place. This saves one patterning process while ensuring the quality of the etch.
  • the structure S of the embodiment of the present invention may include processes such as photoresist coating, masking, exposure, development, and etching.
  • Step 11 is to form a shield layer 201 on the substrate 1.
  • FIG. 2 is a schematic view of the array substrate after the first patterning process of the embodiment.
  • a masking metal film is deposited on the substrate 1 (e.g., a glass substrate or a quartz substrate) by sputtering or thermal evaporation.
  • the shielding metal film a metal such as Cr, W, Ti, Ta, Mo, Al, Cu or the like and a metal thereof may be used, and the shielding metal film may also be composed of a plurality of metal thin films.
  • a photoresist is coated on the shielding metal film, and the shielding metal film is etched by a first patterning process using a common mask to form a pattern of the shielding layer 201 on the substrate 1.
  • the shielding layer is connected to the common electrode and functions as a common electrode, and the shielding layer forms an additional storage capacitor with the active layer to compensate for the reduction of the storage capacitance itself.
  • a shielding layer is also formed in the common electrode connection region around the array substrate, and the shielding layer is disposed in the same layer as the shielding layer in the display region.
  • Step 12 forming active layers 302, 303 on the substrate on which the shield layer 201 is formed.
  • FIG. 3 is a schematic view of the array substrate after the second patterning process of the embodiment.
  • a buffer insulating film is continuously deposited by a plasma enhanced chemical vapor deposition method to form a buffer insulating layer 301.
  • the buffer insulating layer film may be an oxide, a nitride or an oxynitride, and the corresponding reaction gas may be a mixed gas of SiH 4 , N 2 0, NH 3 , N 2 , or may be SiH 2 Cl 2 , N 2 0, A mixed gas of NH 3 and N 2 .
  • amorphous silicon is deposited on the substrate on which the buffer insulating layer 301 is formed, and amorphous silicon is crystallized into polycrystalline silicon by a polysilicon process, and then the polycrystalline silicon layer is doped to form doped polysilicon.
  • the etching is performed by the second patterning process to form a polysilicon pattern, which is an active layer.
  • the active layer includes a driving region active layer 302 and a display region active layer 303.
  • the polysilicon process is, for example, a metal induced amorphous silicon crystallization method, a lateral metal induced amorphous silicon crystallization method, or the like.
  • Step 13 An NMOS gate 402 in the display region and the driving region is formed on the substrate on which the active layers 302, 303 are formed.
  • a gate insulating film is continuously deposited by a plasma enhanced chemical vapor deposition method to form a gate insulating layer 401 as shown in FIG.
  • the gate insulating film may be an oxide, a nitride or an oxynitride, and the corresponding reaction gas may be a mixed gas of Si, N 2 0, NH 3 , N 2 or SiH 2 Cl 2 , N 2 0, NH 3 , N. 2 mixed gas.
  • sputtering or thermal evaporation is performed on the substrate on which the gate insulating layer 401 is formed.
  • the method is to deposit a gate metal film, and a metal such as Cr, W, Ti, Ta, Mo, Al, Cu or the like can be selected for the gate metal thin waist.
  • Coating a photoresist on the gate metal film exposing the photoresist using a common mask, the remaining area of the photoresist corresponding to the pattern and the PMOS region of the NMOS gate 402 in the display region and the driving region, and the removal of the photoresist The region corresponds to other regions where the gate metal film is not required to be retained; the gate metal film of the photoresist removal region is etched away to form the NMOS gate 402 in the display region and the driving region. At this time, the gate metal film in the common electrode connection region is also etched away. Phosphorus ions (P) are then implanted into the polysilicon layer to form an NMOS switch, and the photoresist is removed.
  • Phosphorus ions P
  • Step 14 A first via 502 in the PMOS gate 501 and the common electrode connection region in the driving region is formed on the substrate on which the NMOS gate 402 in the display region and the driving region is formed.
  • FIG. 5 is a schematic view of the array substrate after the fourth patterning process of the embodiment. Coating a photoresist on the substrate on which the NMOS gate 402 in the display region and the driving region is formed; exposing the photoresist using a common mask, the remaining region of the photoresist corresponding to the NMOS gate pattern in the driving region and The pattern of the PMOS gate 501, the entire display area, and the area other than the pattern of the first via 502 in the common electrode connection region, the removed region of the photoresist corresponds to the pattern of the first via 502 and the gate metal film does not need to be retained.
  • Etching the gate insulating layer 401 and the buffer insulating layer 301 of the photoresist removal region to form the first via 502 in the common electrode connection region may specifically include: etching away all the gate insulating layer 401 of the photoresist removal region and All of the buffer insulating layer 301 is formed to form the first via hole 502 in the common electrode connection region; or the entire gate insulating layer 401 and the partial buffer insulating layer 301 of the photoresist removal region are etched away to form a common electrode connection region The first via 502.
  • the thickness of the gate insulating layer is very thin, the buffer insulating layer 3000A, the gate insulating layer 1200A, the gate metal 2200A, and the gate electrode is finished, the gate insulating layer is finished, and most of the buffer insulating layer is also finished. . That is, the first via may extend to the shield layer 201 or may not extend to the shield layer 201.
  • Step 15 forming a second via 602 and a display area in the common electrode connection region on the substrate on which the PMOS gate 501 in the driving region and the first via 502 in the common electrode connection region are formed a third via 603 in the domain and the driving region, the second via being the same as the first via for connecting the shield layer and the source/drain electrode layer, the third via being used for connection active Layer and source/drain electrode layer;
  • FIG. 6 is a schematic view of the array substrate after the fifth patterning process of the embodiment.
  • the intermediate insulating layer film is continuously deposited by a plasma enhanced chemical vapor deposition method to form an intermediate insulating layer 601.
  • the intermediate insulating layer film may be selected from an oxide, a nitride or an oxynitride, and the corresponding reaction gas may be a mixed gas of SiH 4 , N 2 0, NH 3 , N 2 or SiH 2 Cl 2 , N 2 0, NH 3 , A mixed gas of N 2 .
  • a photoresist is coated on the substrate on which the intermediate insulating layer 601 is formed; the photoresist is exposed using a common mask, and the removed regions of the photoresist correspond to the patterns of the second via 602 and the third via 603.
  • the remaining area of the photoresist corresponds to other areas where the intermediate insulating layer film is not required to be removed; the intermediate insulating layer 601 of the photoresist removing area, the partial buffer insulating layer 301 is etched away or only the intermediate insulating layer 601 is etched to form the second Via 602, in summary, second via 602 is etched to reach shield layer 201.
  • the intermediate insulating layer 601 and the gate insulating layer 401 of the photoresist removal region are simultaneously etched away to form a third via hole 603, and the photoresist of the photoresist remaining region is peeled off.
  • the second via 602 and the third via 603 can be formed by one patterning process, and the second via is not made.
  • One of the via 602 and the third via 603 is etched excessively while the other is not etched.
  • Step 16 forming a source/drain electrode layer 701 on the substrate having the intermediate insulating layer 601, the second via hole 602 in the common electrode connection region, and the third via hole 603 in the display region and the driving region;
  • a schematic diagram of the array substrate after the sixth patterning process Depositing a source/drain metal film by sputtering or thermal evaporation on a substrate formed with an intermediate insulating layer 601, a second via 602 in the common electrode connection region, and a third via 603 in the display region and the driving region, the source Metals such as Cr, W, Ti, Ta, Mo, Al, Cu, and alloys thereof may be used as the metal thin film.
  • a photoresist is applied, exposed and developed, and etching is performed to form a source/drain electrode layer 701.
  • the etching of the NMOS pattern in the display region and the driving region is, for example, wet etching. Since the etched objects involved in the display area are all metal, wet etching can meet the requirements.
  • the etching in the driving region PMOS gate pattern and the common electrode connection region is, for example, dry etching.
  • Engraving of the PMOS gate pattern and the common electrode connection region of the driving region The etching is performed simultaneously, and the etching of the common electrode connection region further includes etching of the non-metal, so the etching of the two regions is preferably dry etching.

Abstract

A method for manufacturing an array substrate, comprising: sequentially forming on a substrate (1) a shielding layer (201), a buffer insulating layer (301), an active layer (302, 303), a gate insulating layer (401), and an NMOS gate (402) in the display area and the drive area; forming on the substrate (1) a PMOS gate (501) in the drive area, the NMOS gate (402) and the PMOS gate (501) being on the same layer and at the same time forming a first via (502) in the common electrode connection area, the first via (502) being used for connecting the shielding layer (201) and the source/drain electrode layer (701); forming on the substrate (1) an intermediate insulating layer (601), and forming a second via (602) in the common electrode connection area and a third via (603) in the display area and the drive area, the position of the second via (602) being the same as the position of the first via (502), the first and second vias being used for connecting the shielding layer (201) and the source/drain electrode layer (701), and the third via (603) being used for connecting the active layer (302, 303) and the source/drain electrode layer (701); forming the source/drain electrode layer (701) on the substrate (1).

Description

阵列基板的制作方法 技术领域  Array substrate manufacturing method
本发明的实施例涉及一种阵列基板的制作方法。 背景技术  Embodiments of the present invention relate to a method of fabricating an array substrate. Background technique
随着低温多晶硅技术的发展，高 PPI ( Pixel Per Inch,每英寸的像素数目） 的产品逐渐成为了主流。 高 PPI产品的缺点是存储电容面积的减少， 因此需 要额外增加存储电容以补偿本身存储电容面积的减少。 相应的对策大多是在 阵列基板的最下层增加屏蔽层， 屏蔽层与公共电极连接。 这样， 增加屏蔽层 和有源层之间的存储电容， 以补偿本身存储电容的减少。  With the development of low-temperature polysilicon technology, products with high PPI (Pixel Per Inch, number of pixels per inch) have gradually become mainstream. The disadvantage of high PPI products is the reduction in the area of the storage capacitor, so additional storage capacitors are needed to compensate for the reduction in the area of the storage capacitor itself. The corresponding countermeasures are mostly to add a shielding layer at the lowermost layer of the array substrate, and the shielding layer is connected to the common electrode. In this way, the storage capacitance between the shield layer and the active layer is increased to compensate for the reduction in its own storage capacitance.
低温多晶硅阵列基板的平面结构如图 la所示， 其截面图如图 lb所示。 图 lb中示出了 3个区域的截面结构图，该 3个区域从左到右依次为公共电极 连接区域、 显示区域以及驱动区域。  The planar structure of the low temperature polysilicon array substrate is shown in Figure la, and its cross-sectional view is shown in Figure lb. A cross-sectional structural view of three regions, which are a common electrode connection region, a display region, and a driving region, from left to right, are shown in FIG.
现有技术中低温多晶硅阵列基板的制作工艺包括： 在基板上沉积屏蔽层 薄膜， 经一次构图工艺制作屏蔽层 201 图案； 在形成有屏蔽层的基板上沉积 緩沖绝缘层、 非晶硅层； 经过多晶硅工艺将非晶硅结晶化为多晶硅； 经一次 构图工艺制作有源层图案； 在形成有有源层的基板上制作栅绝缘层； 在形成 有栅绝缘层的基板上制作栅极， 其中， 经一次构图工艺制作驱动区域中的 PMOS ( Positive channel-Metal-Oxide-Semiconductor, P型金属氧化物半导体 ) 栅极， 然后进行硼离子（B )注入， 再经一次构图工艺制作显示区域及驱动 区域中的 NMOS ( Negative channel-Metal-Oxide-Semiconductor, N型金属氧 化物半导体）栅极， 然后进行磷离子（P )注入， PMOS栅极与 NMOS栅极 位于同一层； 之后， 在形成有 NMOS栅极的基板上制作中间绝缘层； 经一次 构图工艺制作用于连接源漏电极层和有源层的过孔， 所述过孔贯穿所述中间 绝缘层； 再经一次构图工艺制作用于连接屏蔽层和源漏电极层的过孔， 所述 过孔贯穿所述中间绝缘层和栅绝缘层； 然后在形成有用于连接源漏电极层和 有源层的过孔以及用于连接屏蔽层和源漏电极层的过孔的基板上沉积源漏金 属薄膜， 并经一次构图工艺制作源漏电极层。 用于连接源漏电极层和有源层的 ϋ孔和用于连接屏蔽层和源漏电极层的 过孔通过两次构图工艺实现， 工艺较为冗杂。 但是， 如果为了筒化工艺而对 上述两种过孔应用同一次构图工艺形成， 由于用于连接源漏电极层和有源层 的过孔深度与用于连接屏蔽层和源漏电极层的过孔深度不同， 所需的刻蚀时 间也不同， 因此会导致用于连接源漏电极层和有源层的过孔刻蚀过度， 而用 于连接屏蔽层和源漏电极层的过孔刻蚀不到位。 发明内容 The manufacturing process of the low-temperature polysilicon array substrate in the prior art comprises: depositing a shielding layer film on the substrate, forming a pattern of the shielding layer 201 by one patterning process; depositing a buffer insulating layer and an amorphous silicon layer on the substrate on which the shielding layer is formed; The polysilicon process crystallizes the amorphous silicon into polycrystalline silicon; the active layer pattern is formed by one patterning process; the gate insulating layer is formed on the substrate on which the active layer is formed; and the gate is formed on the substrate on which the gate insulating layer is formed, wherein A PMOS (Positive Channel-Metal-Oxide-Semiconductor) gate in the driving region is fabricated by a patterning process, followed by boron ion (B) implantation, and a display region and a driving region are formed by one patterning process. The NMOS (Negative Channel-Metal-Oxide-Semiconductor) gate is then implanted with phosphorus (P), and the PMOS gate is in the same layer as the NMOS gate. Thereafter, an NMOS gate is formed. Making an intermediate insulating layer on the substrate; forming a via for connecting the source/drain electrode layer and the active layer by one patterning process The via hole penetrates through the intermediate insulating layer; and a via hole for connecting the shielding layer and the source/drain electrode layer is formed by one patterning process, the via hole penetrating through the intermediate insulating layer and the gate insulating layer; A source/drain metal film is deposited on a substrate having a via for connecting the source/drain electrode layer and the active layer, and a via for connecting the shield layer and the source/drain electrode layer, and the source/drain electrode layer is formed by one patterning process. The via for connecting the source/drain electrode layer and the active layer and the via for connecting the shield layer and the source/drain electrode layer are realized by two patterning processes, and the process is complicated. However, if the same patterning process is applied to the above two vias for the barreling process, the via depth for connecting the source and drain electrode layers and the active layer is used for connecting the shield layer and the source and drain electrode layers. The hole depth is different, and the required etching time is also different, so that the via hole for connecting the source/drain electrode layer and the active layer is excessively etched, and the via etching for connecting the shield layer and the source/drain electrode layer is performed. Did not do well. Summary of the invention
本发明的实施例提供了一种阵列基板的制作方法， 能够在筒化制作工艺 的同时保证刻蚀的质量。  Embodiments of the present invention provide a method of fabricating an array substrate, which is capable of ensuring the quality of etching while performing a barreling process.
本发明的一个方面提供了一种阵列基板的制作方法， 包括：  One aspect of the present invention provides a method of fabricating an array substrate, including:
步骤 1、 在基板上依次形成屏蔽层、 緩沖绝缘层、 有源层、 栅绝缘层和 显示区域及驱动区域中的 NMOS栅极， 然后将磷离子注入有源层；  Step 1. sequentially forming a shielding layer, a buffer insulating layer, an active layer, a gate insulating layer, and an NMOS gate in the display region and the driving region on the substrate, and then implanting phosphorus ions into the active layer;
步骤 2、 在形成有屏蔽层、 緩沖绝缘层、 有源层、 栅绝缘层和显示区域 及驱动区域中的 NMOS栅极的基板上形成驱动区域中的 PMOS栅极， 所述 NMOS栅极和 PMOS栅极在同一层，并同时形成公共电极连接区域中的第一 过孔， 所述第一过孔用于连接屏蔽层和源漏电极层， 然后将硼离子注入有源 层；  Step 2, forming a PMOS gate in the driving region on the substrate formed with the shielding layer, the buffer insulating layer, the active layer, the gate insulating layer, and the NMOS gate in the display region and the driving region, the NMOS gate and the PMOS The gate is in the same layer and simultaneously forms a first via in the common electrode connection region, the first via is used to connect the shielding layer and the source/drain electrode layer, and then implant boron ions into the active layer;
步骤 3、 在形成有驱动区域中的 PMOS栅极和公共电极连接区域中的第 一过孔的基板上形成中间绝缘层， 并形成公共电极连接区域中的第二过孔和 显示区域及驱动区域中的第三过孔， 所述第二过孔与所述第一过孔的位置相 同用于连接屏蔽层和源漏电极层， 所述第三过孔用于连接有源层和源漏电极 层；  Step 3, forming an intermediate insulating layer on the substrate on which the first via hole in the PMOS gate and the common electrode connection region in the driving region is formed, and forming the second via hole and the display region and the driving region in the common electrode connection region a third via hole, the second via hole having the same position as the first via hole for connecting a shield layer and a source/drain electrode layer, wherein the third via hole is used for connecting the active layer and the source/drain electrodes Floor;
步骤 4、 在形成有中间绝缘层、 公共电极连接区域中的第二过孔和显示 区域及驱动区域中的第三过孔的基板上形成源漏电极层。  Step 4. Form a source/drain electrode layer on the substrate on which the intermediate insulating layer, the second via hole in the common electrode connection region, and the display via region and the third via hole in the driving region are formed.
例如， 该方法中， 所述步骤 1可以包括： 在基板上依次形成屏蔽层、 緩 沖绝缘层、 有源层和栅绝缘层； 在形成有屏蔽层、 緩沖绝缘层、 有源层和栅 绝缘层的基板上沉积栅金属薄膜， 在栅金属薄膜上涂覆光刻胶； 对光刻胶进 行曝光，光刻胶的保留区域对应显示区域及驱动区域中 NMOS栅极的图形和 PMOS区域， 光刻胶的去除区域对应不需要保留栅金属薄膜的其他区域； 刻 蚀掉光刻胶去除区域的栅金属薄膜形成显示区域及驱动区域中的 NMOS栅 极， 并剥离光刻胶保留区域的光刻胶。 For example, in the method, the step 1 may include: sequentially forming a shielding layer, a buffer insulating layer, an active layer, and a gate insulating layer on the substrate; forming a shielding layer, a buffer insulating layer, an active layer, and a gate insulating layer Depositing a gate metal film on the substrate, coating a photoresist on the gate metal film; exposing the photoresist, the remaining area of the photoresist corresponding to the pattern and the PMOS region of the NMOS gate in the display region and the driving region, lithography The removal area of the glue corresponds to other areas where the gate metal film is not required to be retained; The gate metal film of the photoresist removal region is etched to form an NMOS gate in the display region and the driving region, and the photoresist of the photoresist remaining region is stripped.
例如， 该方法中， 所述步骤 2可以包括： 在形成有屏蔽层、緩沖绝缘层、 有源层、栅绝缘层和显示区域及驱动区域中的 NMOS栅极的基板上涂覆光刻 胶； 对光刻胶进行曝光， 光刻胶的保留区域对应驱动区域中的 NMOS栅极和 PMOS栅极的图形、 全部显示区域和公共电极连接区域中第一过孔的图形之 外的区域， 光刻胶的去除区域对应第一过孔的图形以及不需要保留栅金属薄 膜的其他区域； 刻蚀掉光刻胶去除区域的栅金属薄膜形成驱动区域中的 PMOS栅极， 同时刻蚀掉光刻胶去除区域的栅绝缘层和緩沖绝缘层以形成公 共电极连接区域中的第一过孔。  For example, in the method, the step 2 may include: coating a photoresist on a substrate formed with a shielding layer, a buffer insulating layer, an active layer, a gate insulating layer, and an NMOS gate in the display region and the driving region; Exposing the photoresist, the remaining area of the photoresist corresponding to the pattern of the NMOS gate and the PMOS gate in the driving region, the entire display area and the area other than the pattern of the first via in the common electrode connection region, lithography The removed area of the glue corresponds to the pattern of the first via and other areas where the gate metal film is not required to be left; the gate metal film of the photoresist removal area is etched to form the PMOS gate in the driving region, and the photoresist is etched away The gate insulating layer and the buffer insulating layer of the region are removed to form a first via hole in the common electrode connection region.
例如， 该方法中， 所述刻蚀掉光刻胶去除区域的栅绝缘层和緩沖绝缘层 以形成公共电极连接区域中的第一过孔包括： 刻蚀掉光刻胶去除区域的全部 栅绝缘层和全部緩沖绝缘层， 以形成公共电极连接区域中的第一过孔； 或刻 蚀掉光刻胶去除区域的全部栅绝缘层和部分緩沖绝缘层， 以形成公共电极连 接区域中的第一过孔。  For example, in the method, the etching the off the gate insulating layer of the photoresist removal region and the buffer insulating layer to form the first via in the common electrode connection region comprises: etching away the entire gate insulation of the photoresist removal region Layer and all buffer insulating layers to form a first via in the common electrode connection region; or etching away all of the gate insulating layer and a portion of the buffer insulating layer of the photoresist removal region to form a first of the common electrode connection regions Through hole.
例如， 该方法中， 所述步骤 3可以包括： 在形成有驱动区域中的 PMOS 栅极和公共电极连接区域中的第一过孔的基板上形成中间绝缘层， 并在中间 绝缘层上涂覆光刻胶； 对光刻胶进行曝光， 光刻胶的去除区域对应第二过孔 和第三过孔的图形， 光刻胶的保留区域对应不需要去除中间绝缘层的其他区 域；刻蚀掉光刻胶去除区域的中间绝缘层、部分緩沖绝缘层以形成第二过孔， 同时刻蚀掉光刻胶去除区域的中间绝缘层和栅绝缘层以形成第三过孔， 并剥 离光刻胶保留区域的光刻胶。  For example, in the method, the step 3 may include: forming an intermediate insulating layer on the substrate on which the first via hole in the PMOS gate and the common electrode connection region in the driving region is formed, and coating on the intermediate insulating layer Photoresist; exposing the photoresist, the removed area of the photoresist corresponds to the pattern of the second via and the third via, and the remaining area of the photoresist corresponds to other areas that do not need to remove the intermediate insulating layer; The intermediate insulating layer of the photoresist removal region and a portion of the buffer insulating layer are formed to form a second via hole, and the intermediate insulating layer and the gate insulating layer of the photoresist removal region are etched away to form a third via hole, and the photoresist is stripped. Retain the area of the photoresist.
或者， 所述步骤 3可以包括： 在形成有驱动区域中的 PMOS栅极和公共 电极连接区域中的第一过孔的基板上形成中间绝缘层， 并在中间绝缘层上涂 覆光刻胶； 对光刻胶进行曝光， 光刻胶的去除区域对应第二过孔和第三过孔 的图形， 光刻胶的保留区域对应不需要去除中间绝缘层的其他区域； 刻蚀掉 光刻胶去除区域的中间绝缘层以形成第二过孔， 同时刻蚀掉光刻胶去除区域 的中间绝缘层和栅绝缘层以形成第三过孔，并剥离光刻胶保留区域的光刻胶。  Alternatively, the step 3 may include: forming an intermediate insulating layer on the substrate formed with the first via in the PMOS gate and the common electrode connection region in the driving region, and coating the intermediate insulating layer with a photoresist; Exposing the photoresist, the removed region of the photoresist corresponds to the pattern of the second via and the third via, and the remaining area of the photoresist corresponds to other regions that do not need to remove the intermediate insulating layer; The intermediate insulating layer of the region forms a second via hole while etching away the intermediate insulating layer and the gate insulating layer of the photoresist removal region to form a third via hole, and stripping the photoresist of the photoresist remaining region.
例如，该方法中，对显示区域及驱动区域中 NMOS栅极图形的刻蚀可以 采用湿法刻蚀。 例如， 该方法中， 对驱动区域 PMOS栅极图形及公共电极连接区域中图 形的刻蚀可以采用干法刻蚀。 For example, in the method, the etching of the NMOS gate pattern in the display region and the driving region may be performed by wet etching. For example, in the method, the etching of the pattern in the driving region PMOS gate pattern and the common electrode connection region may be dry etching.
本发明实施例提供的阵列基板的制作方法， 通过一次构图工艺， 对该第 二过孔和第三过孔同时进行制作， 而不会出现第二过孔和第三过孔中的一者 刻蚀过度， 而另一者刻蚀不到位的情况。 这样既节省了一次构图工艺， 同时 还能保证刻蚀的质量。 附图说明  In the method for fabricating the array substrate provided by the embodiment of the present invention, the second via hole and the third via hole are simultaneously fabricated by one patterning process, and one of the second via hole and the third via hole does not appear. The eclipse is excessive and the other is not etched. This saves one patterning process while ensuring the quality of the etch. DRAWINGS
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。  In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, rather than to the present invention. limit.
图 la为现有技术中阵列基板的平面结构图；  Figure la is a plan view of a prior art array substrate;
图 lb为图 la中阵列基板 A1-A1向的截面图；  Figure lb is a cross-sectional view of the array substrate A1-A1 in Figure la;
图 2为本发明实施例阵列基板第一次构图工艺后的示意图；  2 is a schematic view of the array substrate after the first patterning process according to an embodiment of the present invention;
图 3为本发明实施例阵列基板第二次构图工艺后的示意图；  3 is a schematic diagram of a second patterning process of an array substrate according to an embodiment of the present invention;
图 4为本发明实施例阵列基板第三次构图工艺后的示意图；  4 is a schematic diagram of a third patterning process of an array substrate according to an embodiment of the present invention;
图 5为本发明实施例阵列基板第四次构图工艺后的示意图；  FIG. 5 is a schematic diagram of a fourth patterning process of an array substrate according to an embodiment of the present invention; FIG.
图 6为本发明实施例阵列基板第五次构图工艺后的示意图；  6 is a schematic diagram of a fifth patterning process of an array substrate according to an embodiment of the present invention;
图 7为本发明实施例阵列基板第六次构图工艺后的示意图。 具体实施方式  FIG. 7 is a schematic diagram of a sixth patterning process of an array substrate according to an embodiment of the present invention. detailed description
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。  The technical solutions of the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings of the embodiments of the present invention. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.
图 2至 7为根据本发明实施例的阵列基板的制作方法的各个步骤的示意 图， 各图中示出了 3个区域的截面结构， 该 3个区域分别为驱动区域、 显示 区域以及公共电极连接区域。  2 to 7 are schematic diagrams showing respective steps of a method of fabricating an array substrate according to an embodiment of the invention, each of which shows a cross-sectional structure of three regions, which are respectively a driving region, a display region, and a common electrode connection. region.
如图 2至 7所示， 本发明的实施例提供的阵列基板的制作方法可如下进 行。 As shown in FIG. 2 to FIG. 7 , the method for fabricating the array substrate provided by the embodiment of the present invention can be as follows. Row.
在基板（例如玻璃基板、石英基板或塑料基板等）上依次形成屏蔽层 201、 緩沖绝缘层 301、 非晶硅层， 经过多晶硅工艺将非晶硅结晶化为多晶硅， 经 一次构图工艺制作有源层图案 302、 303、 栅绝缘层 401和显示区域及驱动区 域中的 NMOS栅极 402 (驱动区域中的 NMOS栅极在图中未示出）， 然后将 磷离子（P )注入有源层。  A shielding layer 201, a buffer insulating layer 301, and an amorphous silicon layer are sequentially formed on a substrate (for example, a glass substrate, a quartz substrate, a plastic substrate, or the like), and the amorphous silicon is crystallized into polycrystalline silicon through a polysilicon process, and is actively produced by one patterning process. The layer patterns 302, 303, the gate insulating layer 401, and the NMOS gate 402 in the display region and the driving region (the NMOS gate in the driving region are not shown in the drawing), and then implant phosphorus ions (P) into the active layer.
在形成有屏蔽层 201、緩沖绝缘层 301、有源层 302、 303、栅绝缘层 401 和显示区域及驱动区域中的 NMOS 栅极 402 的基板上形成驱动区域中的 PMOS栅极 501。所述 NMOS栅极和 PMOS栅极在同一层， 并同时形成公共 电极连接区域中的第一过孔 502, 所述第一过孔 502用于连接屏蔽层 201和 源漏电极层 701 , 然后将硼离子（B )注入有源层。  A PMOS gate 501 in the driving region is formed on the substrate on which the shield layer 201, the buffer insulating layer 301, the active layers 302 and 303, the gate insulating layer 401, and the NMOS gate 402 in the display region and the driving region are formed. The NMOS gate and the PMOS gate are in the same layer, and simultaneously form a first via 502 in the common electrode connection region, the first via 502 is used to connect the shielding layer 201 and the source/drain electrode layer 701, and then Boron ions (B) are implanted into the active layer.
在形成有驱动区域中的 PMOS栅极 501和公共电极连接区域中的第一过 孔 502的基板上形成中间绝缘层 601 , 并形成公共电极连接区域中的第二过 孔 602和显示区域及驱动区域中的第三过孔 603 , 所述第二过孔 603与所述 第一过孔 502的位置相同用于连接屏蔽层 201和源漏电极层 701 , 所述第三 过孔 603用于连接有源层 302、 303和源漏电极层 701。  Forming an intermediate insulating layer 601 on the substrate formed with the PMOS gate 501 in the driving region and the first via 502 in the common electrode connection region, and forming the second via 602 and the display region and driving in the common electrode connection region a third via 603 in the region, the second via 603 is the same as the first via 502 for connecting the shield layer 201 and the source/drain electrode layer 701, and the third via 603 is used for connection The active layers 302, 303 and the source and drain electrode layers 701.
在形成有中间绝缘层 601、 公共电极连接区域中的第二过孔 602和显示 区域及驱动区域中的第三过孔 603的基板上形成源漏电极层 701。  A source/drain electrode layer 701 is formed on the substrate on which the intermediate insulating layer 601, the second via hole 602 in the common electrode connection region, and the third via 603 in the display region and the driving region are formed.
本发明的实施例提供的阵列基板的制作方法通过在制作驱动区域中 PMOS栅极的同时， 制作公共电极连接区域中的第一过孔， 然后在形成有驱 动区域中的 PMOS栅极和第一过孔的基板上制作中间绝缘层，之后制作用于 连接源漏电极层和屏蔽层的第二过孔和用于连接源漏电极层和有源层的第三 过孔， 且第二过孔的位置与第一过孔的位置相同。 此时中间绝缘层在公共电 极连接区域中的第一过孔的图形处会形成一个凹坑， 由于此凹坑的存在， 用 于连接屏蔽层和源漏电极层的所述第二过孔的深度变小， 而达到与用于连接 有源层和源漏电极层的所述第三过孔的深度大致相同的程度。 此时可以通过 一次构图工艺， 对该第二过孔和第三过孔同时进行制作， 而不会出现第二过 孔和第三过孔中的一者刻蚀过度， 而另一者刻蚀不到位的情况。 这样既节省 了一次构图工艺， 同时还能保证刻蚀的质量。  The method for fabricating the array substrate provided by the embodiment of the present invention makes the first via hole in the common electrode connection region while fabricating the PMOS gate in the driving region, and then forms the PMOS gate and the first in the driving region. An intermediate insulating layer is formed on the via substrate, and then a second via for connecting the source/drain electrode layer and the shielding layer and a third via for connecting the source/drain electrode layer and the active layer are formed, and the second via is formed The position is the same as the position of the first via. At this time, the intermediate insulating layer forms a pit at the pattern of the first via hole in the common electrode connection region, and the second via hole for connecting the shield layer and the source/drain electrode layer due to the existence of the pit The depth becomes smaller to the extent substantially the same as the depth of the third via for connecting the active layer and the source-drain electrode layer. At this time, the second via hole and the third via hole can be simultaneously fabricated by one patterning process, and one of the second via hole and the third via hole is not overetched, and the other is etched. Not in place. This saves one patterning process while ensuring the quality of the etch.
下面将结合具体的例子来说明本发明实施例中阵列基板的制造工艺。 在 以下说明中， 本发明实施例所称的构囝工 S可以包括光刻胶涂覆、 掩膜、 曝 光、 显影以及刻蚀等工艺。 The manufacturing process of the array substrate in the embodiment of the present invention will be described below with reference to specific examples. In In the following description, the structure S of the embodiment of the present invention may include processes such as photoresist coating, masking, exposure, development, and etching.
步骤 11 , 在基板 1上形成屏蔽层 201。  Step 11 is to form a shield layer 201 on the substrate 1.
图 2为本实施例的阵列基板第一次构图工艺后的示意图。 首先， 采用溅 射或热蒸发的方法在基板 1 (如玻璃基板或石英基板）上沉积一层屏蔽金属 薄膜。 屏蔽金属薄膜可以使用 Cr、 W、 Ti、 Ta、 Mo、 Al、 Cu等金属及其合 金， 屏蔽金属薄膜也可以由多层金属薄膜组成。 然后在屏蔽金属薄膜上涂覆 光刻胶， 采用普通掩模板， 通过第一次构图工艺对屏蔽金属薄膜进行刻蚀， 在基板 1 上形成屏蔽层 201的图形。 所述屏蔽层与公共电极相连， 可以起到 公共电极的作用， 所述屏蔽层与有源层形成附加存储电容， 以补偿本身存储 电容的减少。 在该显示区域的第一次构图工艺中， 在所述阵列基板周边的公 共电极连接区域内也形成有屏蔽层， 且该屏蔽层与显示区域内的屏蔽层同层 设置。  FIG. 2 is a schematic view of the array substrate after the first patterning process of the embodiment. First, a masking metal film is deposited on the substrate 1 (e.g., a glass substrate or a quartz substrate) by sputtering or thermal evaporation. As the shielding metal film, a metal such as Cr, W, Ti, Ta, Mo, Al, Cu or the like and a metal thereof may be used, and the shielding metal film may also be composed of a plurality of metal thin films. Then, a photoresist is coated on the shielding metal film, and the shielding metal film is etched by a first patterning process using a common mask to form a pattern of the shielding layer 201 on the substrate 1. The shielding layer is connected to the common electrode and functions as a common electrode, and the shielding layer forms an additional storage capacitor with the active layer to compensate for the reduction of the storage capacitance itself. In the first patterning process of the display region, a shielding layer is also formed in the common electrode connection region around the array substrate, and the shielding layer is disposed in the same layer as the shielding layer in the display region.
步骤 12, 在形成有屏蔽层 201的基板上形成有源层 302、 303。  Step 12, forming active layers 302, 303 on the substrate on which the shield layer 201 is formed.
图 3为本实施例的阵列基板第二次构图工艺后的示意图。 首先， 通过等 离子体增强化学气相沉积方法连续沉积緩沖绝缘层薄膜、 形成緩沖绝缘层 301。緩沖绝缘层薄膜可以选用氧化物、 氮化物或者氮氧化合物， 对应的反应 气体可以为 SiH4、 N20、 NH3、 N2 的混合气体， 或可以为 SiH2Cl2、 N20、 NH3、 N2 的混合气体。之后，在形成有緩沖绝缘层 301的基板上沉积非晶硅， 并通过多晶硅工艺将非晶硅结晶化为多晶硅， 之后对该多晶硅层进行掺杂以 形成掺杂多晶硅。 通过第二次构图工艺进行刻蚀， 形成多晶硅图案， 即为有 源层。 该有源层包括驱动区域有源层 302和显示区域有源层 303。 该多晶硅 工艺例如为金属诱导非晶硅晶化法、 横向金属诱导非晶硅晶化法等。 FIG. 3 is a schematic view of the array substrate after the second patterning process of the embodiment. First, a buffer insulating film is continuously deposited by a plasma enhanced chemical vapor deposition method to form a buffer insulating layer 301. The buffer insulating layer film may be an oxide, a nitride or an oxynitride, and the corresponding reaction gas may be a mixed gas of SiH 4 , N 2 0, NH 3 , N 2 , or may be SiH 2 Cl 2 , N 2 0, A mixed gas of NH 3 and N 2 . Thereafter, amorphous silicon is deposited on the substrate on which the buffer insulating layer 301 is formed, and amorphous silicon is crystallized into polycrystalline silicon by a polysilicon process, and then the polycrystalline silicon layer is doped to form doped polysilicon. The etching is performed by the second patterning process to form a polysilicon pattern, which is an active layer. The active layer includes a driving region active layer 302 and a display region active layer 303. The polysilicon process is, for example, a metal induced amorphous silicon crystallization method, a lateral metal induced amorphous silicon crystallization method, or the like.
步骤 13, 在形成有有源层 302、 303的基板上形成显示区域及驱动区域 中的 NMOS栅极 402。  Step 13. An NMOS gate 402 in the display region and the driving region is formed on the substrate on which the active layers 302, 303 are formed.
图 4为本实施例的阵列基板第三次构图工艺后的示意图。 首先， 通过等 离子体增强化学气相沉积方法连续沉积栅绝缘层薄膜、 形成如图 4所示的栅 绝缘层 401。 栅绝缘层薄膜可以选用氧化物、 氮化物或者氮氧化合物， 对应 的反应气体可以为 Si 、 N20、 NH3、 N2 的混合气体或 SiH2Cl2、 N20、 NH3、 N2 的混合气体。 之后， 在形成有栅绝缘层 401 的基板上通过溅射或热蒸发 的方法沉积栅金属薄膜， 栅金属薄腰可以选用 Cr、 W、 Ti、 Ta、 Mo、 Al、 Cu 等金属及其合金。 在栅金属薄膜上涂覆光刻胶； 使用普通掩模板对光刻 胶进行曝光， 光刻胶的保留区域对应显示区域及驱动区域中 NMOS栅 极 402的图形和 PMOS区域， 光刻胶的去除区域对应不需要保留栅金 属薄膜的其他区域； 刻蚀掉光刻胶去除区域的栅金属薄膜形成显示区 域及驱动区域中的 NMOS栅极 402。且此时，公共电极连接区域中的栅金 属薄膜也被刻蚀掉了。 然后将磷离子（P )注入多晶硅层， 形成 NMOS开关， 去掉光刻胶。 4 is a schematic view of the array substrate after the third patterning process of the embodiment. First, a gate insulating film is continuously deposited by a plasma enhanced chemical vapor deposition method to form a gate insulating layer 401 as shown in FIG. The gate insulating film may be an oxide, a nitride or an oxynitride, and the corresponding reaction gas may be a mixed gas of Si, N 2 0, NH 3 , N 2 or SiH 2 Cl 2 , N 2 0, NH 3 , N. 2 mixed gas. Thereafter, sputtering or thermal evaporation is performed on the substrate on which the gate insulating layer 401 is formed. The method is to deposit a gate metal film, and a metal such as Cr, W, Ti, Ta, Mo, Al, Cu or the like can be selected for the gate metal thin waist. Coating a photoresist on the gate metal film; exposing the photoresist using a common mask, the remaining area of the photoresist corresponding to the pattern and the PMOS region of the NMOS gate 402 in the display region and the driving region, and the removal of the photoresist The region corresponds to other regions where the gate metal film is not required to be retained; the gate metal film of the photoresist removal region is etched away to form the NMOS gate 402 in the display region and the driving region. At this time, the gate metal film in the common electrode connection region is also etched away. Phosphorus ions (P) are then implanted into the polysilicon layer to form an NMOS switch, and the photoresist is removed.
步骤 14, 在形成有显示区域及驱动区域中的 NMOS栅极 402的基板上 形成驱动区域中 PMOS栅极 501和公共电极连接区域中的第一过孔 502。  Step 14. A first via 502 in the PMOS gate 501 and the common electrode connection region in the driving region is formed on the substrate on which the NMOS gate 402 in the display region and the driving region is formed.
图 5为本实施例的阵列基板第四次构图工艺后的示意图。 在形成有显示 区域及驱动区域中的 NMOS栅极 402的基板上涂覆光刻胶；使用普通掩模板 对光刻胶进行曝光， 光刻胶的保留区域对应驱动区域中的 NMOS栅极 图形和 PMOS栅极 501 的图形、 全部显示区域和公共电极连接区域中 第一过孔 502的图形之外的区域，光刻胶的去除区域对应第一过孔 502 的图形以及不需要保留栅金属薄膜的其他区域； 刻蚀掉光刻胶去除区 域的栅金属薄膜形成驱动区域中的 PMOS栅极 501 ,同时刻蚀掉光刻胶 去除区域的栅绝缘层 401和緩沖绝缘层 301 以形成公共电极连接区域中 的第一过孔 502, 然后将硼离子（B )注入多晶硅层， 形成 PMOS开关， 去 掉光刻胶。  FIG. 5 is a schematic view of the array substrate after the fourth patterning process of the embodiment. Coating a photoresist on the substrate on which the NMOS gate 402 in the display region and the driving region is formed; exposing the photoresist using a common mask, the remaining region of the photoresist corresponding to the NMOS gate pattern in the driving region and The pattern of the PMOS gate 501, the entire display area, and the area other than the pattern of the first via 502 in the common electrode connection region, the removed region of the photoresist corresponds to the pattern of the first via 502 and the gate metal film does not need to be retained. Other regions; etching the gate metal film of the photoresist removal region to form the PMOS gate 501 in the driving region, while etching away the gate insulating layer 401 and the buffer insulating layer 301 of the photoresist removal region to form a common electrode connection region The first via 502 is then implanted with boron ions (B) into the polysilicon layer to form a PMOS switch, and the photoresist is removed.
刻蚀掉光刻胶去除区域的栅绝缘层 401和緩沖绝缘层 301 以形成 公共电极连接区域中的第一过孔 502具体可以包括： 刻蚀掉光刻胶去除区 域的全部栅绝缘层 401和全部緩沖绝缘层 301 , 以形成公共电极连接区 域中的第一过孔 502; 或刻蚀掉光刻胶去除区域的全部栅绝缘层 401 和 部分緩沖绝缘层 301 , 以形成公共电极连接区域中的第一过孔 502。 通常， 栅极绝缘层的厚度非常薄， 緩沖绝缘层 3000A左右， 栅极绝缘层 1200A, 栅 极金属 2200A ,栅极刻完，则栅极绝缘层刻完，大部分緩沖绝缘层也被刻完。 即， 第一过孔可以延伸至屏蔽层 201 , 或者也可以并未延伸至屏蔽层 201。  Etching the gate insulating layer 401 and the buffer insulating layer 301 of the photoresist removal region to form the first via 502 in the common electrode connection region may specifically include: etching away all the gate insulating layer 401 of the photoresist removal region and All of the buffer insulating layer 301 is formed to form the first via hole 502 in the common electrode connection region; or the entire gate insulating layer 401 and the partial buffer insulating layer 301 of the photoresist removal region are etched away to form a common electrode connection region The first via 502. Generally, the thickness of the gate insulating layer is very thin, the buffer insulating layer 3000A, the gate insulating layer 1200A, the gate metal 2200A, and the gate electrode is finished, the gate insulating layer is finished, and most of the buffer insulating layer is also finished. . That is, the first via may extend to the shield layer 201 or may not extend to the shield layer 201.
步骤 15,在形成有驱动区域中的 PMOS栅极 501和公共电极连接区域中 的第一过孔 502的基板上形成公共电极连接区域中的第二过孔 602和显示区 域及驱动区域中的第三过孔 603, 所迷第二过孔与所述第一过孔的位置相同 用于连接屏蔽层和源漏电极层，所述第三过孔用于连接有源层和源漏电极层； 图 6为本实施例的阵列基板第五次构图工艺后的示意图。 通过等离子体 增强化学气相沉积方法连续沉积中间绝缘层薄膜、 形成中间绝缘层 601。 中 间绝缘层薄膜可以选用氧化物、 氮化物或者氮氧化合物， 对应的反应气体可 以为 SiH4、 N20、 NH3、 N2 的混合气体或 SiH2Cl2、 N20、 NH3、 N2 的混合 气体。 之后， 在形成有中间绝缘层 601的基板上涂覆光刻胶； 使用普通掩模 板对光刻胶进行曝光， 光刻胶的去除区域对应第二过孔 602 和第三过 孔 603 的图形， 光刻胶的保留区域对应不需要去除中间绝缘层薄膜的 其他区域； 刻蚀掉光刻胶去除区域的中间绝缘层 601、部分緩沖绝缘层 301或者只刻蚀掉中间绝缘层 601以形成第二过孔 602, 总之， 要将第 二过孔 602刻蚀至达到屏蔽层 201。同时刻蚀掉光刻胶去除区域的中间 绝缘层 601和栅绝缘层 401以形成第三过孔 603 ,并剥离光刻胶保留区 域的光刻胶。 Step 15, forming a second via 602 and a display area in the common electrode connection region on the substrate on which the PMOS gate 501 in the driving region and the first via 502 in the common electrode connection region are formed a third via 603 in the domain and the driving region, the second via being the same as the first via for connecting the shield layer and the source/drain electrode layer, the third via being used for connection active Layer and source/drain electrode layer; FIG. 6 is a schematic view of the array substrate after the fifth patterning process of the embodiment. The intermediate insulating layer film is continuously deposited by a plasma enhanced chemical vapor deposition method to form an intermediate insulating layer 601. The intermediate insulating layer film may be selected from an oxide, a nitride or an oxynitride, and the corresponding reaction gas may be a mixed gas of SiH 4 , N 2 0, NH 3 , N 2 or SiH 2 Cl 2 , N 2 0, NH 3 , A mixed gas of N 2 . Thereafter, a photoresist is coated on the substrate on which the intermediate insulating layer 601 is formed; the photoresist is exposed using a common mask, and the removed regions of the photoresist correspond to the patterns of the second via 602 and the third via 603. The remaining area of the photoresist corresponds to other areas where the intermediate insulating layer film is not required to be removed; the intermediate insulating layer 601 of the photoresist removing area, the partial buffer insulating layer 301 is etched away or only the intermediate insulating layer 601 is etched to form the second Via 602, in summary, second via 602 is etched to reach shield layer 201. The intermediate insulating layer 601 and the gate insulating layer 401 of the photoresist removal region are simultaneously etched away to form a third via hole 603, and the photoresist of the photoresist remaining region is peeled off.
由于此时第二过孔 602和第三过孔 603的深度差异很小， 或甚至 没有差异， 因此第二过孔 602和第三过孔 603可以通过一次构图工艺 形成， 并且不会使第二过孔 602和第三过孔 603 中的一者刻蚀过度， 而另一者刻蚀不到位。  Since the difference in depth between the second via 602 and the third via 603 is small at this time, or even no difference, the second via 602 and the third via 603 can be formed by one patterning process, and the second via is not made. One of the via 602 and the third via 603 is etched excessively while the other is not etched.
步骤 16,在形成有中间绝缘层 601、公共电极连接区域中的第二过孔 602 和显示区域及驱动区域中的第三过孔 603的基板上形成源漏电极层 701; 图 7为本实施例的阵列基板第六次构图工艺后的示意图。 在形成有中间 绝缘层 601、 公共电极连接区域中的第二过孔 602和显示区域及驱动区域中 的第三过孔 603的基板上通过溅射或热蒸发的方法沉积源漏金属薄膜， 源漏 金属薄膜可以选用 Cr、 W、 Ti、 Ta、 Mo、 Al、 Cu 等金属及其合金。 在沉积 完源漏金属薄膜后，涂覆光刻胶，曝光显影并进行刻蚀，形成源漏电极层 701。  Step 16, forming a source/drain electrode layer 701 on the substrate having the intermediate insulating layer 601, the second via hole 602 in the common electrode connection region, and the third via hole 603 in the display region and the driving region; A schematic diagram of the array substrate after the sixth patterning process. Depositing a source/drain metal film by sputtering or thermal evaporation on a substrate formed with an intermediate insulating layer 601, a second via 602 in the common electrode connection region, and a third via 603 in the display region and the driving region, the source Metals such as Cr, W, Ti, Ta, Mo, Al, Cu, and alloys thereof may be used as the metal thin film. After depositing the source/drain metal film, a photoresist is applied, exposed and developed, and etching is performed to form a source/drain electrode layer 701.
在以上各步骤中，对显示区域及驱动区域中 NMOS图形的刻蚀例如采用 湿法刻蚀。 由于显示区域所涉及到的被刻蚀物均为金属， 用湿法刻蚀即可满 足要求。  In the above steps, the etching of the NMOS pattern in the display region and the driving region is, for example, wet etching. Since the etched objects involved in the display area are all metal, wet etching can meet the requirements.
在以上各步骤中，对驱动区域 PMOS栅极图形及公共电极连接区域中的 刻蚀例如采用干法刻蚀。驱动区域 PMOS栅极图形和公共电极连接区域的刻 蚀同时进行， 而公共电极连接区域的刻蚀还包括对非金属的刻蚀， 因此该两 个区域的刻蚀优选采用干法刻蚀。 In the above steps, the etching in the driving region PMOS gate pattern and the common electrode connection region is, for example, dry etching. Engraving of the PMOS gate pattern and the common electrode connection region of the driving region The etching is performed simultaneously, and the etching of the common electrode connection region further includes etching of the non-metal, so the etching of the two regions is preferably dry etching.
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。  The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

权利要氷书 Rights demand ice book
1、 一种阵列基板的制作方法， 包括： 1. A method for manufacturing an array substrate, including:
在基板上依次形成屏蔽层、 緩沖绝缘层、 有源层、 栅绝缘层和显示区域 及驱动区域中的 NMOS栅极， 然后将磷离子注入有源层； A shielding layer, a buffer insulating layer, an active layer, a gate insulating layer, and an NMOS gate in the display area and driving area are sequentially formed on the substrate, and then phosphorus ions are implanted into the active layer;
在所述栅绝缘层上形成驱动区域中的 PMOS栅极， 所述 NMOS栅极和 PMOS栅极在同一层， 并同时形成公共电极连接区域中的第一过孔， 所述第 一过孔用于连接所述屏蔽层和将形成的源漏电极层， 然后将硼离子注入所述 有源层； A PMOS gate in the driving area is formed on the gate insulating layer. The NMOS gate and the PMOS gate are on the same layer, and a first via hole in the common electrode connection area is formed at the same time. The first via hole is To connect the shielding layer and the source and drain electrode layers to be formed, and then implant boron ions into the active layer;
在所述基板上形成中间绝缘层， 并形成公共电极连接区域中的第二过孔 和显示区域及驱动区域中的第三过孔， 所述第二过孔与所述第一过孔的位置 相同用于连接所述屏蔽层和所述源漏电极层， 所述第三过孔用于连接所述有 源层和所述源漏电极层； An intermediate insulating layer is formed on the substrate, and a second via hole in the common electrode connection area and a third via hole in the display area and the driving area are formed. The positions of the second via hole and the first via hole are The same is used to connect the shielding layer and the source and drain electrode layers, and the third via hole is used to connect the active layer and the source and drain electrode layers;
在所述基板上形成所述源漏电极层， 所述源漏电极层通过所述第二过孔 与所述第三过孔连接所述屏蔽层和所述有缘层。 The source and drain electrode layers are formed on the substrate, and the source and drain electrode layers are connected to the shielding layer and the edge layer through the second via hole and the third via hole.
2、根据权利要求 1所述的阵列基板的制作方法， 其中，在基板上依次形 成屏蔽层、 緩沖绝缘层、 有源层和栅绝缘层之后， 在所述基板上沉积栅金属 薄膜， 在栅金属薄膜上涂覆光刻胶； 2. The manufacturing method of an array substrate according to claim 1, wherein after sequentially forming a shielding layer, a buffer insulating layer, an active layer and a gate insulating layer on the substrate, a gate metal film is deposited on the substrate, and the gate metal film is deposited on the substrate. Coating the metal film with photoresist;
对光刻胶进行曝光， 光刻胶的保留区域对应显示区域及驱动区域中 NMOS栅极的图形以及 PMOS区域，光刻胶的去除区域对应不需要保留栅金 属薄膜的其他区域； Expose the photoresist. The retained area of the photoresist corresponds to the pattern of the NMOS gate and the PMOS area in the display area and driving area. The removed area of the photoresist corresponds to other areas where the gate metal film does not need to be retained;
刻蚀掉光刻胶去除区域的栅金属薄膜形成显示区域及驱动区域中的 NMOS栅极， 并剥离光刻胶保留区域的光刻胶。 The gate metal film in the photoresist removal area is etched away to form the NMOS gate electrode in the display area and driving area, and the photoresist in the photoresist remaining area is peeled off.
3、根据权利要求 2所述的阵列基板的制作方法，其中，在形成有屏蔽层、 緩沖绝缘层、有源层、栅绝缘层和显示区域及驱动区域中的 NMOS栅极的基 板上涂覆光刻胶； 3. The method of manufacturing an array substrate according to claim 2, wherein the substrate is coated with a shielding layer, a buffer insulating layer, an active layer, a gate insulating layer and an NMOS gate in the display area and the driving area. Photoresist;
对光刻胶进行曝光，光刻胶的保留区域对应驱动区域中的 NMOS栅极和 PMOS栅极的图形、 全部显示区域和公共电极连接区域中第一过孔的图形之 外的区域， 光刻胶的去除区域对应第一过孔的图形以及不需要保留栅金属薄 膜的其他区域； 刻蚀掉光刻胶去除区域的栅金属溥腰形成驱动区域中的 PMOS栅极， 同 时刻蚀掉光刻胶去除区域的栅绝缘层和緩沖绝缘层以形成公共电极连接区域 中的第一过孔， 并剥离光刻胶保留区域的光刻胶。 Expose the photoresist. The reserved area of the photoresist corresponds to the pattern of the NMOS gate and PMOS gate in the driving area, the entire display area and the area other than the pattern of the first via hole in the common electrode connection area. Photolithography The removed area of the glue corresponds to the pattern of the first via hole and other areas where the gate metal film does not need to be retained; The gate metal strip in the photoresist removal area is etched away to form the PMOS gate electrode in the driving area. At the same time, the gate insulating layer and buffer insulating layer in the photoresist removal area are etched away to form the first pass in the common electrode connection area. holes, and strip the photoresist from the photoresist-retained areas.
4、根据权利要求 3所述的阵列基板的制作方法， 其中， 刻蚀掉光刻胶去 除区域的栅绝缘层和緩沖绝缘层以形成公共电极连接区域中的第一过孔包 括： 4. The method for manufacturing an array substrate according to claim 3, wherein etching away the gate insulating layer and the buffer insulating layer in the photoresist removal area to form the first via hole in the common electrode connection area includes:
刻蚀掉光刻胶去除区域的全部栅绝缘层和全部緩沖绝缘层， 以形成公共 电极连接区域中的第一过孔； 或 Etch away all the gate insulating layer and all the buffer insulating layer in the photoresist removal area to form the first via hole in the common electrode connection area; or
刻蚀掉光刻胶去除区域的全部栅绝缘层和部分緩沖绝缘层， 以形成公共 电极连接区域中的第一过孔。 Etch away all the gate insulating layer and part of the buffer insulating layer in the photoresist removal area to form a first via hole in the common electrode connection area.
5、 根据权利要求 1-4任一项所述的阵列基板的制作方法， 其中， 在形成 有驱动区域中的 PMOS栅极和公共电极连接区域中的第一过孔的基板上形成 中间绝缘层之后， 在中间绝缘层上涂覆光刻胶； 5. The manufacturing method of an array substrate according to any one of claims 1 to 4, wherein an intermediate insulating layer is formed on the substrate on which the PMOS gate in the driving area and the first via hole in the common electrode connection area are formed. Afterwards, apply photoresist on the intermediate insulating layer;
对光刻胶进行曝光，光刻胶的去除区域对应第二过孔和第三过孔的图形， 光刻胶的保留区域对应不需要去除中间绝缘层的其他区域； Expose the photoresist. The removed area of the photoresist corresponds to the pattern of the second via hole and the third via hole. The retained area of the photoresist corresponds to other areas where the intermediate insulating layer does not need to be removed;
刻蚀掉光刻胶去除区域的中间绝缘层、部分緩沖绝缘层以形成第二过孔， 同时刻蚀掉光刻胶去除区域的中间绝缘层和栅绝缘层以形成第三过孔， 并剥 离光刻胶保留区域的光刻胶。 The middle insulating layer and part of the buffer insulating layer in the photoresist removal area are etched away to form the second via hole. At the same time, the middle insulating layer and the gate insulating layer in the photoresist removal area are etched away to form the third via hole, and peeled off. Photoresist Retained areas of photoresist.
6、 根据权利要求 1-4任一项所述的阵列基板的制作方法， 其中， 在形成 有驱动区域中的 PMOS栅极和公共电极连接区域中的第一过孔的基板上形成 中间绝缘层之后， 并在中间绝缘层上涂覆光刻胶； 6. The manufacturing method of an array substrate according to any one of claims 1 to 4, wherein an intermediate insulating layer is formed on the substrate on which the PMOS gate in the driving area and the first via hole in the common electrode connection area are formed. After that, apply photoresist on the intermediate insulating layer;
对光刻胶进行曝光，光刻胶的去除区域对应第二过孔和第三过孔的图形， 光刻胶的保留区域对应不需要去除中间绝缘层的其他区域； Expose the photoresist. The removed area of the photoresist corresponds to the pattern of the second via hole and the third via hole. The retained area of the photoresist corresponds to other areas where the intermediate insulating layer does not need to be removed;
刻蚀掉光刻胶去除区域的中间绝缘层以形成第二过孔， 同时刻蚀掉光刻 胶去除区域的中间绝缘层和栅绝缘层以形成第三过孔， 并剥离光刻胶保留区 域的光刻胶。 The middle insulating layer in the photoresist removal area is etched away to form a second via hole. At the same time, the middle insulating layer and the gate insulating layer in the photoresist removal area are etched away to form a third via hole, and the photoresist remaining area is peeled off. of photoresist.
7、根据权利要求 6所述的制作阵列基板的方法， 其中，对显示区域及驱 动区域中的 NMOS栅极图形的刻蚀采用湿法刻蚀。 7. The method of manufacturing an array substrate according to claim 6, wherein wet etching is used to etch the NMOS gate pattern in the display area and the driving area.
8、根据权利要求 6所述的制作阵列基板的方法，其中，对驱动区域 PMOS 栅极图形及公共电极连接区域中图形的刻蚀采用干法刻蚀。 8. The method of manufacturing an array substrate according to claim 6, wherein dry etching is used to etch the PMOS gate pattern in the driving area and the pattern in the common electrode connection area.
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